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Various cosmetic and coding style fixes in CAR code (trivial).

Browse Source 
Also, whitespace fixes, consistency fixes, and drop some of the less
useful comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-09-30 23:15:36 +00:00
parent 1d36d6df7d
commit 4292684e1a
3 changed files with 289 additions and 262 deletions
Download Patch File Download Diff File Expand all files Collapse all files

234
src/cpu/amd/car/cache_as_ram.inc
View File

@ -18,76 +18,82 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
/* for CAR with FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
#define MSR_MCFG_BASE 0xC0010058
#define MSR_FAM10 0xC001102A
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define CPUID_MASK 0x0ff00f00
#define CPUID_VAL_FAM10_ROTATED 0x0f000010
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* Leave some space for global variable to pass to RAM stage. */
#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
/* For CAR with Fam10h. */
#define CacheSizeAPStack 0x400 /* 1K */
#define MSR_MCFG_BASE 0xC0010058
#define MSR_FAM10 0xC001102A
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define CPUID_MASK 0x0ff00f00
#define CPUID_VAL_FAM10_ROTATED 0x0f000010
/* /*
* XMM map: * XMM map:
* xmm1: cpu family * xmm1: CPU family
* xmm2: fam10 comparison value * xmm2: Fam10h comparison value
* xmm3: backup ebx * xmm3: Backup EBX
*/ */
/* Save the BIST result */ /* Save the BIST result. */
movl %eax, %ebp movl %eax, %ebp
/* for normal part %ebx already contain cpu_init_detected from fallback call */ /*
* For normal part %ebx already contain cpu_init_detected
* from fallback call.
*/
cache_as_ram_setup: cache_as_ram_setup:
post_code(0xa0) post_code(0xa0)
/* enable SSE */ /* Enable SSE. */
movl %cr4, %eax movl %cr4, %eax
orl $(3<<9), %eax orl $(3 << 9), %eax
movl %eax, %cr4 movl %eax, %cr4
/* figure out cpu family */ /* Figure out the CPU family. */
cvtsi2sd %ebx, %xmm3 cvtsi2sd %ebx, %xmm3
movl $0x01, %eax movl $0x01, %eax
cpuid cpuid
/* base family is bits 8..11, extended family is bits 20..27 */ /* Base family is bits 8..11, extended family is bits 20..27. */
andl $CPUID_MASK, %eax andl $CPUID_MASK, %eax
/* reorder bits for easier comparison by value */ /* Reorder bits for easier comparison by value. */
roll $0x10, %eax roll $0x10, %eax
cvtsi2sd %eax, %xmm1 cvtsi2sd %eax, %xmm1
movl $CPUID_VAL_FAM10_ROTATED, %eax movl $CPUID_VAL_FAM10_ROTATED, %eax
cvtsi2sd %eax, %xmm2 cvtsi2sd %eax, %xmm2
cvtsd2si %xmm3, %ebx cvtsd2si %xmm3, %ebx
/* check if cpu_init_detected */ /* Check if cpu_init_detected. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
andl $(1 << 11), %eax andl $(1 << 11), %eax
movl %eax, %ebx /* We store the status */ movl %eax, %ebx /* We store the status. */
jmp_if_k8(CAR_FAM10_out_post_errata) jmp_if_k8(CAR_FAM10_out_post_errata)
/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */ /*
* For GH, CAR need to set DRAM Base/Limit registers to direct that
/* Only BSP needed, for other nodes set during HT/memory init. */ * to node0.
/* So we need to check if it is BSP */ * Only BSP needed, for other nodes set during HT/memory init.
* So we need to check if it is BSP.
*/
movl $0x1b, %ecx movl $0x1b, %ecx
rdmsr rdmsr
bt $8, %eax /*BSC */ bt $8, %eax /* BSC */
jnc CAR_FAM10_out jnc CAR_FAM10_out
/* Enable RT tables on BSP */ /* Enable RT tables on BSP. */
movl $0x8000c06c, %eax movl $0x8000c06c, %eax
movw $0xcf8, %dx movw $0xcf8, %dx
outl %eax, %dx outl %eax, %dx
@ -96,7 +102,7 @@ cache_as_ram_setup:
btr $0, %eax btr $0, %eax
outl %eax, %dx outl %eax, %dx
/* Setup temporary DRAM map: [0,16M) bit 0-23 */ /* Setup temporary DRAM map: [0,16M) bit 0-23. */
movl $0x8000c144, %eax movl $0x8000c144, %eax
movw $0xcf8, %dx movw $0xcf8, %dx
outl %eax, %dx outl %eax, %dx
@ -113,8 +119,9 @@ cache_as_ram_setup:
CAR_FAM10_out: CAR_FAM10_out:
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. /*
* Re-enable it in after RAM is initialized and before CAR is disabled * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled.
*/ */
movl $MSR_FAM10, %ecx movl $MSR_FAM10, %ecx
rdmsr rdmsr
@ -122,23 +129,13 @@ CAR_FAM10_out:
wrmsr wrmsr
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
/* read-address has to be stored in the ecx register */
movl $MSR_FAM10, %ecx movl $MSR_FAM10, %ecx
/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
rdmsr rdmsr
bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
/* Set bit 35 to 1 in EAX:EDX */
bts $35-32, %edx
/* write back the modified register EDX:EAX to the MSR specified in ECX */
wrmsr wrmsr
/* Erratum 343 end */
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
/* Set MMIO Config space BAR */ /* Set MMIO Config space BAR. */
movl $MSR_MCFG_BASE, %ecx movl $MSR_MCFG_BASE, %ecx
rdmsr rdmsr
@ -152,7 +149,7 @@ CAR_FAM10_out:
CAR_FAM10_out_post_errata: CAR_FAM10_out_post_errata:
/* Set MtrrFixDramModEn for clear fixed mtrr */ /* Set MtrrFixDramModEn for clear fixed MTRR. */
enable_fixed_mtrr_dram_modify: enable_fixed_mtrr_dram_modify:
movl $SYSCFG_MSR, %ecx movl $SYSCFG_MSR, %ecx
rdmsr rdmsr
@ -160,7 +157,7 @@ enable_fixed_mtrr_dram_modify:
orl $SYSCFG_MSR_MtrrFixDramModEn, %eax orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
wrmsr wrmsr
/* Clear all MTRRs */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
@ -176,59 +173,63 @@ clear_fixed_var_mtrr:
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment. /*
* 0x06 is the WB IO type for a given 4k segment.
* 0x1e is the MEM IO type for a given 4k segment (K10 and above). * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
* segs is the number of 4k segments in the area of the particular * segs is the number of 4k segments in the area of the particular
* register we want to use for CAR. * register we want to use for CAR.
* reg is the register where the IO type should be stored. * reg is the register where the IO type should be stored.
*/ */
.macro extractmask segs, reg .macro extractmask segs, reg
.if \segs <= 0 .if \segs <= 0
/* The xorl here is superfluous because at the point of first execution /*
* The xorl here is superfluous because at the point of first execution
* of this macro, %eax and %edx are cleared. Later invocations of this * of this macro, %eax and %edx are cleared. Later invocations of this
* macro will have a monotonically increasing segs parameter. * macro will have a monotonically increasing segs parameter.
*/ */
xorl \reg, \reg xorl \reg, \reg
.else .else
jmp_if_k8(1f) jmp_if_k8(1f)
.if \segs == 1 .if \segs == 1
movl $0x1e000000, \reg /* WB MEM type */ movl $0x1e000000, \reg /* WB MEM type */
.elseif \segs == 2 .elseif \segs == 2
movl $0x1e1e0000, \reg /* WB MEM type */ movl $0x1e1e0000, \reg /* WB MEM type */
.elseif \segs == 3 .elseif \segs == 3
movl $0x1e1e1e00, \reg /* WB MEM type */ movl $0x1e1e1e00, \reg /* WB MEM type */
.elseif \segs >= 4 .elseif \segs >= 4
movl $0x1e1e1e1e, \reg /* WB MEM type */ movl $0x1e1e1e1e, \reg /* WB MEM type */
.endif .endif
jmp 2f jmp 2f
1: 1:
.if \segs == 1 .if \segs == 1
movl $0x06000000, \reg /* WB IO type */ movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2 .elseif \segs == 2
movl $0x06060000, \reg /* WB IO type */ movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3 .elseif \segs == 3
movl $0x06060600, \reg /* WB IO type */ movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4 .elseif \segs >= 4
movl $0x06060606, \reg /* WB IO type */ movl $0x06060606, \reg /* WB IO type */
.endif .endif
2: 2:
.endif /* if \segs <= 0 */ .endif /* if \segs <= 0 */
.endm .endm
/* size is the cache size in bytes we want to use for CAR. /*
* windowoffset is the 32k-aligned window into CAR size * size is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size.
*/ */
.macro simplemask carsize, windowoffset .macro simplemask carsize, windowoffset
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
extractmask gas_bug_workaround, %eax extractmask gas_bug_workaround, %eax
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
extractmask gas_bug_workaround, %edx extractmask gas_bug_workaround, %edx
/* Without the gas bug workaround, the entire macro would consist only of the /*
* two lines below. * Without the gas bug workaround, the entire macro would consist
extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax * only of the two lines below:
extractmask (((\carsize - \windowoffset) / 0x1000)), %edx * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
*/ * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
*/
.endm .endm
#if CacheSize > 0x10000 #if CacheSize > 0x10000
@ -242,18 +243,18 @@ clear_fixed_var_mtrr_out:
#endif #endif
#if CacheSize > 0x8000 #if CacheSize > 0x8000
/* enable caching for 32K-64K using fixed mtrr */ /* Enable caching for 32K-64K using fixed MTRR. */
movl $MTRRfix4K_C0000_MSR, %ecx movl $MTRRfix4K_C0000_MSR, %ecx
simplemask CacheSize, 0x8000 simplemask CacheSize, 0x8000
wrmsr wrmsr
#endif #endif
/* enable caching for 0-32K using fixed mtrr */ /* Enable caching for 0-32K using fixed MTRR. */
movl $MTRRfix4K_C8000_MSR, %ecx movl $MTRRfix4K_C8000_MSR, %ecx
simplemask CacheSize, 0 simplemask CacheSize, 0
wrmsr wrmsr
/* enable memory access for first MBs using top_mem */ /* Enable memory access for first MBs using top_mem. */
movl $TOP_MEM, %ecx movl $TOP_MEM, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
@ -267,13 +268,13 @@ clear_fixed_var_mtrr_out:
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif #endif
/* enable write base caching so we can do execute in place /* Enable write base caching so we can do execute in place (XIP)
* on the flash rom. * on the flash ROM.
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
@ -285,14 +286,13 @@ wbcache_post_fam10_setup:
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
movl $0x00000c00, %eax
wrmsr wrmsr
/* Enable the MTRRs and IORRs in SYSCFG */ /* Enable the MTRRs and IORRs in SYSCFG. */
movl $SYSCFG_MSR, %ecx movl $SYSCFG_MSR, %ecx
rdmsr rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
@ -300,35 +300,35 @@ wbcache_post_fam10_setup:
post_code(0xa1) post_code(0xa1)
/* enable cache */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
jmp_if_k8(fam10_end_part1) jmp_if_k8(fam10_end_part1)
/* So we need to check if it is BSP */ /* So we need to check if it is BSP. */
movl $0x1b, %ecx movl $0x1b, %ecx
rdmsr rdmsr
bt $8, %eax /*BSC */ bt $8, %eax /* BSC */
jnc CAR_FAM10_ap jnc CAR_FAM10_ap
fam10_end_part1: fam10_end_part1:
post_code(0xa2) post_code(0xa2)
/* Read the range with lodsl*/ /* Read the range with lodsl. */
cld cld
movl $CacheBase, %esi movl $CacheBase, %esi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range */ /* Clear the range. */
movl $CacheBase, %edi movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
/* set up the stack pointer */ /* Set up the stack pointer. */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp movl %eax, %esp
@ -336,42 +336,47 @@ fam10_end_part1:
jmp CAR_FAM10_ap_out jmp CAR_FAM10_ap_out
CAR_FAM10_ap: CAR_FAM10_ap:
/* need to set stack pointer for AP */ /*
/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/ * Need to set stack pointer for AP.
/* So need to get the NodeID and CoreID at first */ * It will be from:
/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */ * CacheBase + (CacheSize - GlobalVarSize) / 2
* - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
* So need to get the NodeID and CoreID at first.
* If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
* to reverse it.
*/
/* store our init detected */ /* Store our init detected. */
movl %ebx, %esi movl %ebx, %esi
/* get the coreid bits at first */ /* Get the coreid bits at first. */
movl $0x80000008, %eax movl $0x80000008, %eax
cpuid cpuid
shrl $12, %ecx shrl $12, %ecx
andl $0x0f, %ecx andl $0x0f, %ecx
movl %ecx, %edi movl %ecx, %edi
/* get the initial apic id */ /* Get the initial APIC ID. */
movl $1, %eax movl $1, %eax
cpuid cpuid
shrl $24, %ebx shrl $24, %ebx
/* get the nb cfg bit 54 */ /* Get the nb cfg bit 54. */
movl $0xc001001f, %ecx /* NB_CFG_MSR */ movl $0xc001001f, %ecx /* NB_CFG_MSR */
rdmsr rdmsr
movl %edi, %ecx /* CoreID bits */ movl %edi, %ecx /* CoreID bits */
bt $(54-32), %edx bt $(54-32), %edx
jc roll_cfg jc roll_cfg
rolb %cl, %bl rolb %cl, %bl
roll_cfg: roll_cfg:
/* calculate stack pointer */ /* Calculate stack pointer. */
movl $CacheSizeAPStack, %eax movl $CacheSizeAPStack, %eax
mull %ebx mull %ebx
movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
subl %eax, %esp subl %eax, %esp
/* retrive init detected */ /* Retrive init detected. */
movl %esi, %ebx movl %esi, %ebx
post_code(0xa4) post_code(0xa4)
@ -380,35 +385,38 @@ CAR_FAM10_ap_out:
post_code(0xa5) post_code(0xa5)
/* disable SSE */ /* Disable SSE. */
movl %cr4, %eax movl %cr4, %eax
andl $~(3<<9), %eax andl $~(3 << 9), %eax
movl %eax, %cr4 movl %eax, %cr4
/* Restore the BIST result */ /* Restore the BIST result. */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set EBP? No need. */
movl %esp, %ebp movl %esp, %ebp
pushl %ebx /* init detected */ pushl %ebx /* Init detected. */
pushl %eax /* bist */ pushl %eax /* BIST */
call cache_as_ram_main call cache_as_ram_main
/* We will not go back */ /* We will not go back. */
post_code(0xaf) /* Should never see this postcode */ post_code(0xaf) /* Should never see this POST code. */
fixed_mtrr_msr: fixed_mtrr_msr:
.long 0x250, 0x258, 0x259 .long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A .long 0x268, 0x269, 0x26A
.long 0x26B, 0x26C, 0x26D .long 0x26B, 0x26C, 0x26D
.long 0x26E, 0x26F .long 0x26E, 0x26F
var_mtrr_msr: var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203 .long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207 .long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B .long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F .long 0x20C, 0x20D, 0x20E, 0x20F
var_iorr_msr: var_iorr_msr:
.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
mem_top: mem_top:
.long 0xC001001A, 0xC001001D .long 0xC001001A, 0xC001001D
.long 0x000 /* NULL, end of table */ .long 0x000 /* NULL, end of table */

145
src/cpu/intel/car/cache_as_ram.inc
View File

@ -21,18 +21,18 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h> #include <cpu/x86/lapic_def.h>
/* Save the BIST result */ #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* Save the BIST result. */
movl %eax, %ebp movl %eax, %ebp
CacheAsRam: CacheAsRam:
// Check whether the processor has HT capability /* Check whether the processor has HT capability. */
movl $01, %eax movl $01, %eax
cpuid cpuid
btl $28, %edx btl $28, %edx
@ -41,20 +41,26 @@ CacheAsRam:
cmpb $01, %bh cmpb $01, %bh
jbe NotHtProcessor jbe NotHtProcessor
// It is a HT processor; Send SIPI to the other logical processor /*
// within this processor so that the CAR related common system * It is a HT processor. Send SIPI to the other logical processor
// registers are programmed accordingly. * within this processor so that the CAR related common system
* registers are programmed accordingly.
*/
// Use some register that is common to both logical processors /*
// as semaphore. Refer Appendix B, Vol.3 * Use some register that is common to both logical processors
* as semaphore. Refer Appendix B, Vol.3.
*/
xorl %eax, %eax xorl %eax, %eax
xorl %edx, %edx xorl %edx, %edx
movl $MTRRfix64K_00000_MSR, %ecx movl $MTRRfix64K_00000_MSR, %ecx
wrmsr wrmsr
// Figure out the logical AP's APIC ID; the following logic will /*
// work only for processors with 2 threads. * Figure out the logical AP's APIC ID; the following logic will
// Refer to Vol 3. Table 7-1 for details about this logic * work only for processors with 2 threads.
* Refer to Vol 3. Table 7-1 for details about this logic.
*/
movl $0xFEE00020, %esi movl $0xFEE00020, %esi
movl (%esi), %ebx movl (%esi), %ebx
andl $0xFF000000, %ebx andl $0xFF000000, %ebx
@ -66,17 +72,19 @@ CacheAsRam:
LogicalAP0: LogicalAP0:
orb $0x01, %bl orb $0x01, %bl
Send_SIPI: Send_SIPI:
bswapl %ebx // ebx - logical AP's APIC ID bswapl %ebx /* EBX - logical AP's APIC ID. */
// Fill up the IPI command registers in the Local APIC mapped to /*
// default address and issue SIPI to the other logical processor * Fill up the IPI command registers in the Local APIC mapped to
// within this processor die. * default address and issue SIPI to the other logical processor
* within this processor die.
*/
Retry_SIPI: Retry_SIPI:
movl %ebx, %eax movl %ebx, %eax
movl $0xFEE00310, %esi movl $0xFEE00310, %esi
movl %eax, (%esi) movl %eax, (%esi)
// SIPI vector - F900:0000 /* SIPI vector - F900:0000 */
movl $0x000006F9, %eax movl $0x000006F9, %eax
movl $0xFEE00300, %esi movl $0xFEE00300, %esi
movl %eax, (%esi) movl %eax, (%esi)
@ -91,7 +99,7 @@ SIPI_Delay:
andl $0x00001000, %eax andl $0x00001000, %eax
jnz Retry_SIPI jnz Retry_SIPI
// Wait for the Logical AP to complete initialization /* Wait for the Logical AP to complete initialization. */
LogicalAP_SIPINotdone: LogicalAP_SIPINotdone:
movl $MTRRfix64K_00000_MSR, %ecx movl $MTRRfix64K_00000_MSR, %ecx
rdmsr rdmsr
@ -99,14 +107,13 @@ LogicalAP_SIPINotdone:
jz LogicalAP_SIPINotdone jz LogicalAP_SIPINotdone
NotHtProcessor: NotHtProcessor:
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
movl $0x00000c00, %eax
wrmsr wrmsr
/* Clear all MTRRs */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
@ -126,6 +133,7 @@ fixed_mtrr_msr:
.long 0x268, 0x269, 0x26A .long 0x268, 0x269, 0x26A
.long 0x26B, 0x26C, 0x26D .long 0x26B, 0x26C, 0x26D
.long 0x26E, 0x26F .long 0x26E, 0x26F
var_mtrr_msr: var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203 .long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207 .long 0x204, 0x205, 0x206, 0x207
@ -135,14 +143,16 @@ var_mtrr_msr:
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment. /*
* 0x06 is the WB IO type for a given 4k segment.
* segs is the number of 4k segments in the area of the particular * segs is the number of 4k segments in the area of the particular
* register we want to use for CAR. * register we want to use for CAR.
* reg is the register where the IO type should be stored. * reg is the register where the IO type should be stored.
*/ */
.macro extractmask segs, reg .macro extractmask segs, reg
.if \segs <= 0 .if \segs <= 0
/* The xorl here is superfluous because at the point of first execution /*
* The xorl here is superfluous because at the point of first execution
* of this macro, %eax and %edx are cleared. Later invocations of this * of this macro, %eax and %edx are cleared. Later invocations of this
* macro will have a monotonically increasing segs parameter. * macro will have a monotonically increasing segs parameter.
*/ */
@ -158,19 +168,21 @@ clear_fixed_var_mtrr_out:
.endif .endif
.endm .endm
/* size is the cache size in bytes we want to use for CAR. /*
* windowoffset is the 32k-aligned window into CAR size * size is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size.
*/ */
.macro simplemask carsize, windowoffset .macro simplemask carsize, windowoffset
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
extractmask gas_bug_workaround, %eax extractmask gas_bug_workaround, %eax
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
extractmask gas_bug_workaround, %edx extractmask gas_bug_workaround, %edx
/* Without the gas bug workaround, the entire macro would consist only of the /*
* two lines below. * Without the gas bug workaround, the entire macro would consist
extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax * only of the two lines below:
extractmask (((\carsize - \windowoffset) / 0x1000)), %edx * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
*/ * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
*/
.endm .endm
#if CacheSize > 0x10000 #if CacheSize > 0x10000
@ -184,13 +196,13 @@ clear_fixed_var_mtrr_out:
#endif #endif
#if CacheSize > 0x8000 #if CacheSize > 0x8000
/* enable caching for 32K-64K using fixed mtrr */ /* Enable caching for 32K-64K using fixed MTRR. */
movl $MTRRfix4K_C0000_MSR, %ecx movl $MTRRfix4K_C0000_MSR, %ecx
simplemask CacheSize, 0x8000 simplemask CacheSize, 0x8000
wrmsr wrmsr
#endif #endif
/* enable caching for 0-32K using fixed mtrr */ /* Enable caching for 0-32K using fixed MTRR. */
movl $MTRRfix4K_C8000_MSR, %ecx movl $MTRRfix4K_C8000_MSR, %ecx
simplemask CacheSize, 0 simplemask CacheSize, 0
wrmsr wrmsr
@ -203,8 +215,9 @@ clear_fixed_var_mtrr_out:
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif #endif
/* enable write base caching so we can do execute in place /*
* on the flash rom. * Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
@ -218,27 +231,27 @@ clear_fixed_var_mtrr_out:
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl*/ /* Read the range with lodsl. */
movl $CacheBase, %esi movl $CacheBase, %esi
cld cld
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range */ /* Clear the range. */
movl $CacheBase, %edi movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
#if 0 #if 0
/* check the cache as ram */ /* Check the cache as ram. */
movl $CacheBase, %esi movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx movl $(CacheSize >> 2), %ecx
.xin1: .xin1:
movl %esi, %eax movl %esi, %eax
movl %eax, (%esi) movl %eax, (%esi)
@ -249,29 +262,30 @@ clear_fixed_var_mtrr_out:
.xout1: .xout1:
movl $CacheBase, %esi movl $CacheBase, %esi
// movl $(CacheSize>>2), %ecx // movl $(CacheSize >> 2), %ecx
movl $4, %ecx movl $4, %ecx
.xin1x: .xin1x:
movl %esi, %eax movl %esi, %eax
movl $0x4000, %edx movl $0x4000, %edx
movb %ah, %al movb %ah, %al
.testx1: .testx1:
outb %al, $0x80 outb %al, $0x80
decl %edx decl %edx
jnz .testx1 jnz .testx1
movl (%esi), %eax movl (%esi), %eax
cmpb 0xff, %al cmpb 0xff, %al
je .xin2 /* dont show */ je .xin2 /* Don't show. */
movl $0x4000, %edx movl $0x4000, %edx
.testx2: .testx2:
outb %al, $0x80 outb %al, $0x80
decl %edx decl %edx
jnz .testx2 jnz .testx2
.xin2: decl %ecx .xin2:
decl %ecx
je .xout1x je .xout1x
add $4, %esi add $4, %esi
jmp .xin1x jmp .xin1x
@ -281,21 +295,22 @@ clear_fixed_var_mtrr_out:
movl $(CacheBase + CacheSize - 4), %eax movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp movl %eax, %esp
lout: lout:
/* Restore the BIST result */ /* Restore the BIST result. */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set EBP? No need. */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* BIST */
call main call main
/* We don't need cache as ram for now on */ /* We don't need CAR for now on. */
/* disable cache */
/* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(0x1<<30),%eax orl $(1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
/* clear sth */ /* Clear sth. */
movl $MTRRfix4K_C8000_MSR, %ecx movl $MTRRfix4K_C8000_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
xorl %eax, %eax xorl %eax, %eax
@ -306,25 +321,25 @@ lout:
wrmsr wrmsr
#endif #endif
/* Set the default memory type and disable fixed /*
* and enable variable MTRRs * Set the default memory type and disable fixed
* and enable variable MTRRs.
*/ */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Disable Fixed MTRRs */ movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
movl $0x00000800, %eax
wrmsr wrmsr
/* enable cache */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff,%eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
/* clear boot_complete flag */ /* Clear boot_complete flag. */
xorl %ebp, %ebp xorl %ebp, %ebp
__main: __main:
post_code(0x11) post_code(0x11)
cld /* clear direction flag */ cld /* Clear direction flag. */
movl %ebp, %esi movl %ebp, %esi

172
src/cpu/via/car/cache_as_ram.inc
View File

@ -25,31 +25,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
/* Save the BIST result */ #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
/* Save the BIST result. */
movl %eax, %ebp movl %eax, %ebp
CacheAsRam: CacheAsRam:
/* disable cache */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(0x1<<30),%eax orl $(1 << 30), %eax
movl %eax,%cr0 movl %eax, %cr0
invd invd
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */
movl $0x00000c00, %eax
wrmsr wrmsr
/* Clear all MTRRs */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
@ -80,13 +79,13 @@ var_mtrr_msr:
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(0), %ecx movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CacheBase|MTRR_TYPE_WRBACK),%eax movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(0), %ecx movl $MTRRphysMask_MSR(0), %ecx
/* This assumes we never access addresses above 2^36 in CAR. */ /* This assumes we never access addresses above 2^36 in CAR. */
movl $0x0000000f,%edx movl $0x0000000f, %edx
movl $(~(CacheSize-1)|0x800),%eax movl $(~(CacheSize - 1) | 0x800), %eax
wrmsr wrmsr
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
@ -95,13 +94,14 @@ clear_fixed_var_mtrr_out:
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif #endif
/* enable write base caching so we can do execute in place /*
* on the flash rom. * Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
@ -111,39 +111,41 @@ clear_fixed_var_mtrr_out:
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */
movl $0x00000800, %eax
wrmsr wrmsr
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl*/ /* Read the range with lodsl. */
cld cld
movl $CacheBase, %esi movl $CacheBase, %esi
movl %esi, %edi movl %esi, %edi
movl $(CacheSize>>2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
movl $CacheBase, %esi movl $CacheBase, %esi
movl %esi, %edi movl %esi, %edi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
/* 0x5c5c5c5c is a memory test pattern. /*
* TODO: Check if everything works with the zero pattern as well. */ * 0x5c5c5c5c is a memory test pattern.
/*xorl %eax, %eax*/ * TODO: Check if everything works with the zero pattern as well.
xorl $0x5c5c5c5c,%eax */
/* xorl %eax, %eax */
xorl $0x5c5c5c5c, %eax
rep stosl rep stosl
#ifdef CARTEST #ifdef CARTEST
movl REAL_XIP_ROM_BASE, %esi movl REAL_XIP_ROM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
rep lodsl rep lodsl
#endif #endif
/* The key point of this CAR code is C7 cache does not turn into /*
* The key point of this CAR code is C7 cache does not turn into
* "no fill" mode, which is not compatible with general CAR code. * "no fill" mode, which is not compatible with general CAR code.
*/ */
@ -155,27 +157,27 @@ testok:
post_code(0x40) post_code(0x40)
xorl %edx, %edx xorl %edx, %edx
xorl %eax, %eax xorl %eax, %eax
movl $0x5c5c,%edx movl $0x5c5c, %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
popl %esi popl %esi
popl %esi popl %esi
popl %eax popl %eax
popl %eax popl %eax
popl %eax popl %eax
cmpl %edx,%eax cmpl %edx, %eax
jne stackerr jne stackerr
#endif #endif
/* Restore the BIST result */ /* Restore the BIST result. */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set EBP? No need. */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* BIST */
call main call main
/* /*
@ -184,94 +186,96 @@ testok:
* want to go back. * want to go back.
*/ */
/* We don't need cache as ram for now on */ /* We don't need CAR for now on. */
/* disable cache */
movl %cr0, %eax
orl $(0x1<<30),%eax
movl %eax, %cr0
/* Disable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
/* Set the default memory type and disable fixed and enable variable MTRRs */ /*
movl $MTRRdefType_MSR, %ecx * Set the default memory type and disable fixed and enable
xorl %edx, %edx * variable MTRRs.
*/
/* Enable Variable and Disable Fixed MTRRs */ movl $MTRRdefType_MSR, %ecx
movl $0x00000800, %eax xorl %edx, %edx
movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */
wrmsr wrmsr
/* enable caching for first 1M using variable mtrr */ /* Enable caching for first 1M using variable MTRR. */
movl $MTRRphysBase_MSR(0), %ecx movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0 | 6), %eax movl $(0 | 6), %eax
//movl $(0 | MTRR_TYPE_WRBACK), %eax // movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; /*
* Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
* If 1M cacheable, then when S3 resume, there is stange color on * If 1M cacheable, then when S3 resume, there is stange color on
* screen for 2 sec. suppose problem of a0000-dfffff and cache. * screen for 2 sec. Suppose problem of a0000-dfffff and cache.
* And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
*/ */
movl $MTRRphysMask_MSR(0), %ecx movl $MTRRphysMask_MSR(0), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $0x0000000f, %edx /* AMD 40 bit 0xff */
movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax movl $((~((0 + 0x80000) - 1)) | 0x800), %eax
wrmsr wrmsr
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0x80000 | 6), %eax movl $(0x80000 | 6), %eax
orl $(0 | 6), %eax orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $0x0000000f, %edx /* AMD 40 bit 0xff */
movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax movl $((~((0 + 0x20000) - 1)) | 0x800), %eax
wrmsr wrmsr
movl $MTRRphysBase_MSR(2), %ecx movl $MTRRphysBase_MSR(2), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0xc0000 | 6), %eax movl $(0xc0000 | 6), %eax
orl $(0 | 6), %eax orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(2), %ecx movl $MTRRphysMask_MSR(2), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $0x0000000f, %edx /* AMD 40 bit 0xff */
movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
wrmsr wrmsr
/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(3), %ecx movl $MTRRphysBase_MSR(3), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE,%eax movl $REAL_XIP_ROM_BASE,%eax
orl $(0 | 6), %eax orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(3), %ecx movl $MTRRphysMask_MSR(3), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $CONFIG_XIP_ROM_SIZE,%eax movl $CONFIG_XIP_ROM_SIZE, %eax
decl %eax decl %eax
notl %eax notl %eax
orl $(0 | 0x800), %eax orl $(0 | 0x800), %eax
wrmsr wrmsr
/* enable cache */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff,%eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
invd invd
/* clear boot_complete flag */ /* Clear boot_complete flag. */
xorl %ebp, %ebp xorl %ebp, %ebp
__main: __main:
post_code(0x11) post_code(0x11)
cld /* clear direction flag */ cld /* Clear direction flag. */
movl %ebp, %esi movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp movl %esp, %ebp
pushl %esi pushl %esi
call copy_and_run call copy_and_run
.Lhlt: .Lhlt:
post_code(0xee) post_code(0xee)