soc/amd/*/i2c: drop unused mainboard_i2c_override
No mainboard in the current tree implements mainboard_i2c_override. In a follow-up commit the i2c_pad_control struct is introduced to be able to make more parameters controllable by devicetree settings in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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		@@ -33,8 +33,6 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
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}
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#endif
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__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
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void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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{
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	const struct soc_amd_cezanne_config *config = config_of_soc();
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@@ -57,8 +55,6 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
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		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
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	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
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	mainboard_i2c_override(bus, &pad_ctrl);
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	misc_write32(misc_reg, pad_ctrl);
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}
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@@ -147,7 +147,4 @@ void fch_final(void *chip_info);
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void enable_aoac_devices(void);
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void wait_for_aoac_enabled(unsigned int dev);
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/* Allow the board to change the default I2C pad configuration */
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void mainboard_i2c_override(int bus, uint32_t *pad_settings);
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#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */
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@@ -38,8 +38,6 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
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}
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#endif
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__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
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void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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{
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	uint32_t pad_ctrl;
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@@ -59,7 +57,6 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
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	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
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	mainboard_i2c_override(bus, &pad_ctrl);
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	misc_write32(misc_reg, pad_ctrl);
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}
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@@ -136,7 +136,4 @@ void fch_final(void *chip_info);
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void enable_aoac_devices(void);
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void wait_for_aoac_enabled(unsigned int dev);
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/* Allow the board to change the default I2C pad configuration */
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void mainboard_i2c_override(int bus, uint32_t *pad_settings);
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#endif /* AMD_PICASSO_SOUTHBRIDGE_H */
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@@ -35,8 +35,6 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
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}
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#endif
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__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
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void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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{
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	const struct soc_amd_sabrina_config *config = config_of_soc();
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@@ -59,8 +57,6 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
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		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
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	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
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	mainboard_i2c_override(bus, &pad_ctrl);
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	misc_write32(misc_reg, pad_ctrl);
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}
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@@ -151,7 +151,4 @@ void fch_final(void *chip_info);
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void enable_aoac_devices(void);
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void wait_for_aoac_enabled(unsigned int dev);
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/* Allow the board to change the default I2C pad configuration */
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void mainboard_i2c_override(int bus, uint32_t *pad_settings);
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#endif /* AMD_SABRINA_SOUTHBRIDGE_H */
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