fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/fsp_baytrail/nvm.c

@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <console/console.h>
+#include <string.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <baytrail/nvm.h>
+
+/* This module assumes the flash is memory mapped just below 4GiB in the
+ * address space for reading. Also this module assumes an area it erased
+ * when all bytes read as all 0xff's. */
+
+static struct spi_flash *flash;
+
+static int nvm_init(void)
+{
+	if (flash != NULL)
+		return 0;
+
+	spi_init();
+	flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!flash) {
+		printk(BIOS_DEBUG, "Could not find SPI device\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Convert memory mapped pointer to flash offset. */
+static inline uint32_t to_flash_offset(void *p)
+{
+#ifndef CONFIG_ROM_SIZE
+#error CONFIG_ROM_SIZE must be set.
+#endif
+	return CONFIG_ROM_SIZE + (uintptr_t)p;
+}
+
+int nvm_is_erased(const void *start, size_t size)
+{
+	const uint8_t *cur = start;
+	const uint8_t erased_value = 0xff;
+
+	while (size > 0) {
+		if (*cur != erased_value)
+			return 0;
+		cur++;
+		size--;
+	}
+	return 1;
+}
+
+int nvm_erase(void *start, size_t size)
+{
+	if (nvm_init() < 0)
+		return -1;
+	flash->erase(flash, to_flash_offset(start), size);
+	return 0;
+}
+
+/* Write data to NVM. Returns 0 on success < 0 on error.  */
+int nvm_write(void *start, const void *data, size_t size)
+{
+	if (nvm_init() < 0)
+		return -1;
+	flash->write(flash, to_flash_offset(start), size, data);
+	return 0;
+}