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Remove CACHE_ROM.

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With the recent improvement 3d6ffe76f8,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Vladimir Serbinenko
2014-02-05 19:46:45 +01:00
parent 20f83d5656
commit 4337020b95
16 changed files with 0 additions and 163 deletions
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3
src/cpu/intel/haswell/haswell_init.c
View File

@@ -789,9 +789,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
/* Restore the default SMM region. */
restore_default_smm_area(smm_save_area);
/* Enable ROM caching if option was selected. */
x86_mtrr_enable_rom_caching();
}
static struct device_operations cpu_dev_ops = {

15
src/cpu/intel/haswell/mp_init.c
View File

@@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel)
printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n");
}
/* The mtrr code sets up ROM caching on the BSP, but not the others. However,
* the boot loader payload disables this. In order for Linux not to complain
* ensure the caching is disabled for the APs before going to sleep. */
static void cleanup_rom_caching(void)
{
x86_mtrr_disable_rom_caching();
}
/* By the time APs call ap_init() caching has been setup, and microcode has
* been loaded. */
static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr)
@@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr)
/* After SMM relocation a 2nd microcode load is required. */
intel_microcode_load_unlocked(microcode_ptr);
/* The MTRR resources are core scoped. Therefore, there is no need
* to do the same work twice. Additionally, this check keeps the
* ROM cache enabled on the BSP since its hyperthread sibling won't
* call cleanup_rom_caching(). */
if ((lapicid() & 1) == 0)
cleanup_rom_caching();
/* FIXME(adurbin): park CPUs properly -- preferably somewhere in a
* reserved part of memory that the OS cannot get to. */
stop_this_cpu();