sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/apollolake: Fix whitespace issues

Browse Source 
Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14368
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This commit is contained in:
Martin Roth
2016-04-14 16:41:11 -06:00
parent 59493717ad
commit 433e8d272d
7 changed files with 194 additions and 195 deletions
Download Patch File Download Diff File Expand all files Collapse all files

96
src/soc/intel/apollolake/acpi/lpss.asl
View File

@@ -17,100 +17,100 @@
scope (\_SB.PCI0) { scope (\_SB.PCI0) {
/* LPIO1 PWM */ /* LPIO1 PWM */
Device(PWM) { Device(PWM) {
Name (_ADR, 0x001A0000) Name (_ADR, 0x001A0000)
Name (_DDN, "Intel(R) PWM Controller") Name (_DDN, "Intel(R) PWM Controller")
} }
/* LPIO1 HS-UART #1 */ /* LPIO1 HS-UART #1 */
Device(URT1) { Device(URT1) {
Name (_ADR, 0x00180000) Name (_ADR, 0x00180000)
Name (_DDN, "Intel(R) HS-UART Controller #1") Name (_DDN, "Intel(R) HS-UART Controller #1")
} }
/* LPIO1 HS-UART #2 */ /* LPIO1 HS-UART #2 */
Device(URT2) { Device(URT2) {
Name (_ADR, 0x00180001) Name (_ADR, 0x00180001)
Name (_DDN, "Intel(R) HS-UART Controller #2") Name (_DDN, "Intel(R) HS-UART Controller #2")
} }
/* LPIO1 HS-UART #3 */ /* LPIO1 HS-UART #3 */
Device(URT3) { Device(URT3) {
Name (_ADR, 0x00180002) Name (_ADR, 0x00180002)
Name (_DDN, "Intel(R) HS-UART Controller #3") Name (_DDN, "Intel(R) HS-UART Controller #3")
} }
/* LPIO1 HS-UART #4 */ /* LPIO1 HS-UART #4 */
Device(URT4) { Device(URT4) {
Name (_ADR, 0x00180003) Name (_ADR, 0x00180003)
Name (_DDN, "Intel(R) HS-UART Controller #4") Name (_DDN, "Intel(R) HS-UART Controller #4")
} }
/* LPIO1 SPI */ /* LPIO1 SPI */
Device(SPI1) { Device(SPI1) {
Name (_ADR, 0x00190000) Name (_ADR, 0x00190000)
Name (_DDN, "Intel(R) SPI Controller #1") Name (_DDN, "Intel(R) SPI Controller #1")
} }
/* LPIO1 SPI #2 */ /* LPIO1 SPI #2 */
Device(SPI2) { Device(SPI2) {
Name (_ADR, 0x00190001) Name (_ADR, 0x00190001)
Name (_DDN, "Intel(R) SPI Controller #2") Name (_DDN, "Intel(R) SPI Controller #2")
} }
/* LPIO1 SPI #3 */ /* LPIO1 SPI #3 */
Device(SPI3) { Device(SPI3) {
Name (_ADR, 0x00190002) Name (_ADR, 0x00190002)
Name (_DDN, "Intel(R) SPI Controller #3") Name (_DDN, "Intel(R) SPI Controller #3")
} }
/* LPIO2 I2C #0 */ /* LPIO2 I2C #0 */
Device(I2C0) { Device(I2C0) {
Name (_ADR, 0x00160000) Name (_ADR, 0x00160000)
Name (_DDN, "Intel(R) I2C Controller #0") Name (_DDN, "Intel(R) I2C Controller #0")
} }
/* LPIO2 I2C #1 */ /* LPIO2 I2C #1 */
Device(I2C1) { Device(I2C1) {
Name (_ADR, 0x00160001) Name (_ADR, 0x00160001)
Name (_DDN, "Intel(R) I2C Controller #1") Name (_DDN, "Intel(R) I2C Controller #1")
} }
/* LPIO2 I2C #2 */ /* LPIO2 I2C #2 */
Device(I2C2) { Device(I2C2) {
Name (_ADR, 0x00160002) Name (_ADR, 0x00160002)
Name (_DDN, "Intel(R) I2C Controller #2") Name (_DDN, "Intel(R) I2C Controller #2")
} }
/* LPIO2 I2C #3 */ /* LPIO2 I2C #3 */
Device(I2C3) { Device(I2C3) {
Name (_ADR, 0x00160003) Name (_ADR, 0x00160003)
Name (_DDN, "Intel(R) I2C Controller #3") Name (_DDN, "Intel(R) I2C Controller #3")
} }
/* LPIO2 I2C #4 */ /* LPIO2 I2C #4 */
Device(I2C4) { Device(I2C4) {
Name (_ADR, 0x00170000) Name (_ADR, 0x00170000)
Name (_DDN, "Intel(R) I2C Controller #4") Name (_DDN, "Intel(R) I2C Controller #4")
} }
/* LPIO2 I2C #5 */ /* LPIO2 I2C #5 */
Device(I2C5) { Device(I2C5) {
Name (_ADR, 0x00170001) Name (_ADR, 0x00170001)
Name (_DDN, "Intel(R) I2C Controller #5") Name (_DDN, "Intel(R) I2C Controller #5")
} }
/* LPIO2 I2C #6 */ /* LPIO2 I2C #6 */
Device(I2C6) { Device(I2C6) {
Name (_ADR, 0x00170002) Name (_ADR, 0x00170002)
Name (_DDN, "Intel(R) I2C Controller #6") Name (_DDN, "Intel(R) I2C Controller #6")
} }
/* LPIO2 I2C #7 */ /* LPIO2 I2C #7 */
Device(I2C7) { Device(I2C7) {
Name (_ADR, 0x00170003) Name (_ADR, 0x00170003)
Name (_DDN, "Intel(R) I2C Controller #7") Name (_DDN, "Intel(R) I2C Controller #7")
} }
} }

11
src/soc/intel/apollolake/acpi/northbridge.asl
View File

@@ -81,11 +81,11 @@ Device (MCHC)
NonCacheable, ReadWrite, NonCacheable, ReadWrite,
0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x00000000, 0x10000, 0x1ffff, 0x00000000,
0x10000,,, PM02) 0x10000,,, PM02)
}) })
/* Current Resource Settings */ /* Current Resource Settings */
Method (_CRS, 0, Serialized) Method (_CRS, 0, Serialized)
{ {
/* Find PCI resource area in MCRS */ /* Find PCI resource area in MCRS */
CreateDwordField (MCRS, ^PM01._MIN, PMIN) CreateDwordField (MCRS, ^PM01._MIN, PMIN)
@@ -119,6 +119,7 @@ Method (_CRS, 0, Serialized)
CreateQwordField (MCRS, ^PM02._LEN, MLEN) CreateQwordField (MCRS, ^PM02._LEN, MLEN)
Store (^TUUD, Local0) Store (^TUUD, Local0)
If (LLessEqual (Local0, 0x1000000000)) If (LLessEqual (Local0, 0x1000000000))
{ {
Store (0, MMIN) Store (0, MMIN)
@@ -127,5 +128,5 @@ Method (_CRS, 0, Serialized)
Subtract (Add (MMIN, MLEN), 1, MMAX) Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) Return (MCRS)
} }
} }

3
src/soc/intel/apollolake/acpi/pci_irqs.asl
View File

@@ -59,6 +59,5 @@ Method(_PRT)
Package(){0x001CFFFF, 0, 0, EMMC_INT}, Package(){0x001CFFFF, 0, 0, EMMC_INT},
Package(){0x001EFFFF, 0, 0, SDIO_INT}, Package(){0x001EFFFF, 0, 0, SDIO_INT},
Package(){0x001FFFFF, 1, 0, SMBUS_INT}, Package(){0x001FFFFF, 1, 0, SMBUS_INT},
} })
)
} }

1
src/soc/intel/apollolake/acpi/soc_int.asl
View File

@@ -53,5 +53,4 @@
#define EMMC_INT 39 #define EMMC_INT 39
#define SDIO_INT 42 #define SDIO_INT 42
#endif /* _SOC_INT_DEFINE_ASL_ */ #endif /* _SOC_INT_DEFINE_ASL_ */