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sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs

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The desktop 9 series PCHs should be the same as the 8 series PCHs.

Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Angel Pons
2022-10-07 00:36:00 +02:00
committed by Lean Sheng Tan
parent 05df1084ed
commit 434d7d4582
8 changed files with 46 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
src/include/device/pci_ids.h
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@@ -2835,6 +2835,11 @@
#define PCI_DID_INTEL_LPT_C224 0x8c54 #define PCI_DID_INTEL_LPT_C224 0x8c54
#define PCI_DID_INTEL_LPT_C226 0x8c56 #define PCI_DID_INTEL_LPT_C226 0x8c56
#define PCI_DID_INTEL_LPT_H81 0x8c5c #define PCI_DID_INTEL_LPT_H81 0x8c5c
#define PCI_DID_INTEL_LPT_MOBILE_SAMPLE_9 0x8cc1
#define PCI_DID_INTEL_LPT_DESKTOP_SAMPLE_9 0x8cc2
#define PCI_DID_INTEL_LPT_HM97 0x8cc3
#define PCI_DID_INTEL_LPT_Z97 0x8cc4
#define PCI_DID_INTEL_LPT_H97 0x8cc6
#define PCI_DID_INTEL_LPT_LP_SAMPLE 0x9c41 #define PCI_DID_INTEL_LPT_LP_SAMPLE 0x9c41
#define PCI_DID_INTEL_LPT_LP_PREMIUM 0x9c43 #define PCI_DID_INTEL_LPT_LP_PREMIUM 0x9c43
#define PCI_DID_INTEL_LPT_LP_MAINSTREAM 0x9c45 #define PCI_DID_INTEL_LPT_LP_MAINSTREAM 0x9c45
@@ -3475,6 +3480,18 @@
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07 #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09 #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_9 0x8c80
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI_9 0x8c82
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1_9 0x8c84
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM_9 0x8c86
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45_9 0x8c88
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2_9 0x8c0e
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_9 0x8c81
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI_9 0x8c83
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1_9 0x8c85
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM_9 0x8c87
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45_9 0x8c89
#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2_9 0x8c8f
#define PCI_DID_INTEL_LPT_LP_SATA_AHCI 0x9c03 #define PCI_DID_INTEL_LPT_LP_SATA_AHCI 0x9c03
#define PCI_DID_INTEL_LPT_LP_SATA_RAID_1 0x9c05 #define PCI_DID_INTEL_LPT_LP_SATA_RAID_1 0x9c05
#define PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07 #define PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07
@@ -4114,6 +4131,7 @@
/* Intel SMBUS device Ids */ /* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
#define PCI_DID_INTEL_LPT_H_SMBUS_9 0x8ca2
#define PCI_DID_INTEL_LPT_LP_SMBUS 0x9c22 #define PCI_DID_INTEL_LPT_LP_SMBUS 0x9c22
#define PCI_DID_INTEL_WPT_LP_SMBUS 0x9ca2 #define PCI_DID_INTEL_WPT_LP_SMBUS 0x9ca2
#define PCI_DID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DID_INTEL_APL_SMBUS 0x5ad4
@@ -4141,10 +4159,13 @@
/* Intel EHCI device IDs */ /* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
#define PCI_DID_INTEL_LPT_H_EHCI_2 0x8c2d #define PCI_DID_INTEL_LPT_H_EHCI_2 0x8c2d
#define PCI_DID_INTEL_LPT_H_EHCI_1_9 0x8ca6
#define PCI_DID_INTEL_LPT_H_EHCI_2_9 0x8cad
#define PCI_DID_INTEL_LPT_LP_EHCI 0x9c26 #define PCI_DID_INTEL_LPT_LP_EHCI 0x9c26
/* Intel XHCI device Ids */ /* Intel XHCI device Ids */
#define PCI_DID_INTEL_LPT_H_XHCI 0x8c31 #define PCI_DID_INTEL_LPT_H_XHCI 0x8c31
#define PCI_DID_INTEL_LPT_H_XHCI_9 0x8cb1
#define PCI_DID_INTEL_LPT_LP_XHCI 0x9c31 #define PCI_DID_INTEL_LPT_LP_XHCI 0x9c31
#define PCI_DID_INTEL_APL_XHCI 0x5aa8 #define PCI_DID_INTEL_APL_XHCI 0x5aa8
#define PCI_DID_INTEL_GLK_XHCI 0x31a8 #define PCI_DID_INTEL_GLK_XHCI 0x31a8
@@ -4215,6 +4236,7 @@
/* Intel AUDIO device Ids */ /* Intel AUDIO device Ids */
#define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20
#define PCI_DID_INTEL_LPT_H_AUDIO_9 0x8ca0
#define PCI_DID_INTEL_LPT_LP_AUDIO 0x9c20 #define PCI_DID_INTEL_LPT_LP_AUDIO 0x9c20
#define PCI_DID_INTEL_APL_AUDIO 0x5a98 #define PCI_DID_INTEL_APL_AUDIO 0x5a98
#define PCI_DID_INTEL_GLK_AUDIO 0x3198 #define PCI_DID_INTEL_GLK_AUDIO 0x3198
@@ -4262,6 +4284,7 @@
/* Intel HECI/ME device Ids */ /* Intel HECI/ME device Ids */
#define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a
#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba
#define PCI_DID_INTEL_LPT_LP_MEI 0x9c3a #define PCI_DID_INTEL_LPT_LP_MEI 0x9c3a
#define PCI_DID_INTEL_APL_CSE0 0x5a9a #define PCI_DID_INTEL_APL_CSE0 0x5a9a
#define PCI_DID_INTEL_GLK_CSE0 0x319a #define PCI_DID_INTEL_GLK_CSE0 0x319a

1
src/southbridge/intel/lynxpoint/azalia.c
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@@ -122,6 +122,7 @@ static struct device_operations azalia_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_H_AUDIO, PCI_DID_INTEL_LPT_H_AUDIO,
PCI_DID_INTEL_LPT_H_AUDIO_9,
PCI_DID_INTEL_LPT_LP_AUDIO, PCI_DID_INTEL_LPT_LP_AUDIO,
0 0
}; };

5
src/southbridge/intel/lynxpoint/lpc.c
View File

@@ -834,6 +834,11 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_LP_PREMIUM, PCI_DID_INTEL_LPT_LP_PREMIUM,
PCI_DID_INTEL_LPT_LP_MAINSTREAM, PCI_DID_INTEL_LPT_LP_MAINSTREAM,
PCI_DID_INTEL_LPT_LP_VALUE, PCI_DID_INTEL_LPT_LP_VALUE,
PCI_DID_INTEL_LPT_MOBILE_SAMPLE_9,
PCI_DID_INTEL_LPT_DESKTOP_SAMPLE_9,
PCI_DID_INTEL_LPT_HM97,
PCI_DID_INTEL_LPT_Z97,
PCI_DID_INTEL_LPT_H97,
0 0
}; };

1
src/southbridge/intel/lynxpoint/me.c
View File

@@ -923,6 +923,7 @@ static struct device_operations device_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_H_MEI, PCI_DID_INTEL_LPT_H_MEI,
PCI_DID_INTEL_LPT_H_MEI_9,
PCI_DID_INTEL_LPT_LP_MEI, PCI_DID_INTEL_LPT_LP_MEI,
0 0
}; };

12
src/southbridge/intel/lynxpoint/sata.c
View File

@@ -231,6 +231,18 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM, PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45, PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2, PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_9,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI_9,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1_9,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM_9,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45_9,
PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45_9,
PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2_9,
PCI_DID_INTEL_LPT_LP_SATA_AHCI, PCI_DID_INTEL_LPT_LP_SATA_AHCI,
PCI_DID_INTEL_LPT_LP_SATA_RAID_1, PCI_DID_INTEL_LPT_LP_SATA_RAID_1,
PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM, PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM,

1
src/southbridge/intel/lynxpoint/smbus.c
View File

@@ -35,6 +35,7 @@ static struct device_operations smbus_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_H_SMBUS, PCI_DID_INTEL_LPT_H_SMBUS,
PCI_DID_INTEL_LPT_H_SMBUS_9,
PCI_DID_INTEL_LPT_LP_SMBUS, PCI_DID_INTEL_LPT_LP_SMBUS,
PCI_DID_INTEL_WPT_LP_SMBUS, PCI_DID_INTEL_WPT_LP_SMBUS,
0 0

2
src/southbridge/intel/lynxpoint/usb_ehci.c
View File

@@ -173,6 +173,8 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_LP_EHCI, PCI_DID_INTEL_LPT_LP_EHCI,
PCI_DID_INTEL_LPT_H_EHCI_1, PCI_DID_INTEL_LPT_H_EHCI_1,
PCI_DID_INTEL_LPT_H_EHCI_2, PCI_DID_INTEL_LPT_H_EHCI_2,
PCI_DID_INTEL_LPT_H_EHCI_1_9,
PCI_DID_INTEL_LPT_H_EHCI_2_9,
0 0
}; };

1
src/southbridge/intel/lynxpoint/usb_xhci.c
View File

@@ -343,6 +343,7 @@ static struct device_operations usb_xhci_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LPT_H_XHCI, PCI_DID_INTEL_LPT_H_XHCI,
PCI_DID_INTEL_LPT_H_XHCI_9,
PCI_DID_INTEL_LPT_LP_XHCI, PCI_DID_INTEL_LPT_LP_XHCI,
0 0
}; };