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arch/arm: Add armv7-r configuration

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This change adds armv7-r support for all stages.

armv7-r is an ARM processor based on the Cortex-R series.

Currently, there is support for armv7-a and armv7-m and
armv7-a files has been modfied to accommodate armv7-r by
adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants
to src/include/rules.h.

armv7-r exceptions support will added in a later time.

Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15335
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Hakim Giydan
2016-09-08 10:13:59 -07:00
committed by Martin Roth
parent 06868f8154
commit 43e5b576b9
6 changed files with 98 additions and 4 deletions
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12
src/arch/arm/armv7/cpu.S
View File

@@ -31,6 +31,7 @@
*/
#include <arch/asm.h>
#include <rules.h>
/*
* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
@@ -126,6 +127,7 @@ ENTRY(arm_init_caches)
/* Flush and invalidate dcache in ascending order */
bl dcache_invalidate_all
#if ENV_ARMV7_A
/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
and r4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
mcr p15, 0, r4, c1, c0, 0
@@ -133,6 +135,16 @@ ENTRY(arm_init_caches)
/* Invalidate icache and TLB for good measure */
mcr p15, 0, r0, c7, c5, 0
mcr p15, 0, r0, c8, c7, 0
#endif
#if ENV_ARMV7_R
/* Deactivate Alignment Check (1) and DCache (2) */
and r4, # ~(1 << 1) & ~(1 << 2)
mcr p15, 0, r4, c1, c0, 0
/* Invalidate icache for good measure */
mcr p15, 0, r0, c7, c5, 0
#endif
dsb
isb