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soc/intel/alderlake: Update UART0 GPIO as per latest schematics

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UART0_RX: C8 -> H10
UART0_TX: C9 -> H11

GPIO PIN Mode: NF1 -> NF2

Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
2020-11-22 15:16:12 +05:30
parent 8ed53ec8c0
commit 447233ce8c
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/uart.c
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@@ -21,8 +21,8 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
.console_index = 0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */
},
},
{