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soc/intel/skylake: Unify serial IRQ options

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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.

In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.

Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?

Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nico Huber
2019-02-23 19:24:51 +01:00
committed by Patrick Georgi
parent ff79341a80
commit 44e89af6e6
30 changed files with 22 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/skylake/Kconfig
View File

@@ -162,13 +162,6 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
config SMM_RESERVED_SIZE
hex
default 0x200000

6
src/soc/intel/skylake/chip.c
View File

@@ -22,6 +22,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/acpi.h>
@@ -190,8 +191,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->PmConfigPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod;
params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable;
params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
params->SerialIrqConfigSirqMode =
config->serirq_mode == SERIRQ_CONTINUOUS;
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;

9
src/soc/intel/skylake/chip.h
View File

@@ -24,6 +24,7 @@
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <stdint.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -428,13 +429,7 @@ struct soc_intel_skylake_config {
RESET_POWER_CYCLE_4S = 4,
} PmConfigPwrCycDur;
/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
u8 SerialIrqConfigSirqEnable;
enum {
SERIAL_IRQ_QUIET_MODE = 0,
SERIAL_IRQ_CONTINUOUS_MODE = 1,
} SerialIrqConfigSirqMode;
enum serirq_mode serirq_mode;
enum {
SERIAL_IRQ_FRAME_PULSE_4CLK = 0,

5
src/soc/intel/skylake/chip_fsp20.c
View File

@@ -26,6 +26,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
@@ -418,8 +419,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Indicate whether platform supports Voltage Margining */
params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
params->PchSirqMode = config->SerialIrqConfigSirqMode;
params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();

7
src/soc/intel/skylake/lpc.c
View File

@@ -109,6 +109,8 @@ static void clock_gate_8254(struct device *dev)
void lpc_soc_init(struct device *dev)
{
const config_t *const config = dev->chip_info;
/* Legacy initialization */
isa_dma_init();
reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
@@ -117,10 +119,7 @@ void lpc_soc_init(struct device *dev)
lpc_enable_pci_clk_cntl();
/* Set LPC Serial IRQ mode */
if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
else
lpc_set_serirq_mode(SERIRQ_QUIET);
lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
pch_enable_ioapic(dev);