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soc/intel/skylake: Unify serial IRQ options

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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.

In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.

Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?

Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nico Huber
2019-02-23 19:24:51 +01:00
committed by Patrick Georgi
parent ff79341a80
commit 44e89af6e6
30 changed files with 22 additions and 52 deletions
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7
src/soc/intel/skylake/lpc.c
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@@ -109,6 +109,8 @@ static void clock_gate_8254(struct device *dev)
void lpc_soc_init(struct device *dev)
{
const config_t *const config = dev->chip_info;
/* Legacy initialization */
isa_dma_init();
reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
@@ -117,10 +119,7 @@ void lpc_soc_init(struct device *dev)
lpc_enable_pci_clk_cntl();
/* Set LPC Serial IRQ mode */
if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
else
lpc_set_serirq_mode(SERIRQ_QUIET);
lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
pch_enable_ioapic(dev);