soc/intel/skylake: Unify serial IRQ options

We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.

In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.

Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?

Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/eve/devicetree.cb

@@ -46,7 +46,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -81,7 +81,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/glados/variants/asuka/devicetree.cb

@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "4"        # 4s
 	register "PmConfigSlpSusMinAssert" = "3"       # 4s

src/mainboard/google/glados/variants/caroline/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/glados/variants/cave/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/glados/variants/chell/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/glados/variants/glados/devicetree.cb

@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/glados/variants/lars/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "4"        # 4s
 	register "PmConfigSlpSusMinAssert" = "3"       # 4s

src/mainboard/google/glados/variants/sentry/devicetree.cb

@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "4"        # 4s
 	register "PmConfigSlpSusMinAssert" = "3"       # 4s

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -54,7 +54,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -56,7 +56,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -54,7 +54,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms

src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb

@@ -54,8 +54,6 @@ chip soc/intel/skylake
 	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
 	register "PmConfigSlpAMinAssert" = "0x03"
 
-	# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
-	register "SerialIrqConfigSirqEnable" = "0x01"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+

src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb

@@ -11,7 +11,7 @@ chip soc/intel/skylake
 	register "Heci3Enabled" = "0"
 	register "PmTimerDisabled" = "0"
 
-        register "SerialIrqConfigSirqMode" = "0x01"
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
 	# Enable PCIE slot
 	register "PcieRpEnable[5]" = "1"

src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb

@@ -10,7 +10,8 @@ chip soc/intel/skylake
 	register "ScsSdCardEnabled" = "0"
 	register "HeciEnabled" = "0"
 	register "PmTimerDisabled" = "0"
-	register "SerialIrqConfigSirqMode" = "0x01"
+
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -60,8 +60,6 @@ chip soc/intel/skylake
 	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
 	register "PmConfigSlpAMinAssert" = "0x03"
 
-	# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
-	register "SerialIrqConfigSirqEnable" = "0x01"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+

src/mainboard/intel/saddlebrook/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select INTEL_LPSS_UART_FOR_CONSOLE
-	select SERIRQ_CONTINUOUS_MODE
 	select SKYLAKE_SOC_PCH_H
 	select SOC_INTEL_SKYLAKE
 	select SUPERIO_NUVOTON_NCT6776

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -60,9 +60,7 @@ chip soc/intel/skylake
 	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
 	register "PmConfigSlpAMinAssert" = "0x03"
 
-	# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
-	register "SerialIrqConfigSirqEnable" = "0x01"
-	register "SerialIrqConfigSirqMode" = "0x01"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+

src/mainboard/purism/librem_skl/Kconfig

@@ -6,8 +6,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
 	select HAVE_ACPI_TABLES
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select SOC_INTEL_SKYLAKE
-	# Workaround for EC/KBC IRQ1
-	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_USES_FSP2_0
 	select SPD_READ_BY_WORD
 	select MAINBOARD_HAS_LPC_TPM

src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb

@@ -61,13 +61,15 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
 	register "PmTimerDisabled" = "0"
 
+	# EC/KBC requires continuous mode
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"
 	register "pirqc_routing" = "PCH_IRQ11"

src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb

@@ -61,13 +61,15 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "3"
-	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
 	register "PmTimerDisabled" = "0"
 
+	# EC/KBC requires continuous mode
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"
 	register "pirqc_routing" = "PCH_IRQ11"

src/soc/intel/skylake/Kconfig

@@ -162,13 +162,6 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config SERIRQ_CONTINUOUS_MODE
-	bool
-	default n
-	help
-	  If you set this option to y, the serial IRQ machine will be
-	  operated in continuous mode.
-
 config SMM_RESERVED_SIZE
 	hex
 	default 0x200000

src/soc/intel/skylake/chip.c

@@ -22,6 +22,7 @@
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/acpi.h>
@@ -190,8 +191,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PmConfigPwrBtnOverridePeriod =
 		config->PmConfigPwrBtnOverridePeriod;
 	params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
-	params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable;
+	params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
-	params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
+	params->SerialIrqConfigSirqMode =
+		config->serirq_mode == SERIRQ_CONTINUOUS;
 	params->SerialIrqConfigStartFramePulse =
 		config->SerialIrqConfigStartFramePulse;
 

src/soc/intel/skylake/chip.h

@@ -24,6 +24,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
 #include <stdint.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
@@ -428,13 +429,7 @@ struct soc_intel_skylake_config {
 		RESET_POWER_CYCLE_4S      = 4,
 	} PmConfigPwrCycDur;
 
-	/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
+	enum serirq_mode serirq_mode;
-	u8 SerialIrqConfigSirqEnable;
-
-	enum {
-		SERIAL_IRQ_QUIET_MODE      = 0,
-		SERIAL_IRQ_CONTINUOUS_MODE = 1,
-	} SerialIrqConfigSirqMode;
 
 	enum {
 		SERIAL_IRQ_FRAME_PULSE_4CLK = 0,

src/soc/intel/skylake/chip_fsp20.c

@@ -26,6 +26,7 @@
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
@@ -418,8 +419,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Indicate whether platform supports Voltage Margining */
 	params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
 
-	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
+	params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
-	params->PchSirqMode = config->SerialIrqConfigSirqMode;
+	params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
 
 	params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
 

src/soc/intel/skylake/lpc.c

@@ -109,6 +109,8 @@ static void clock_gate_8254(struct device *dev)
 
 void lpc_soc_init(struct device *dev)
 {
+	const config_t *const config = dev->chip_info;
+
 	/* Legacy initialization */
 	isa_dma_init();
 	reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
@@ -117,10 +119,7 @@ void lpc_soc_init(struct device *dev)
 	lpc_enable_pci_clk_cntl();
 
 	/* Set LPC Serial IRQ mode */
-	if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
+	lpc_set_serirq_mode(config->serirq_mode);
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
 
 	/* Interrupt configuration */
 	pch_enable_ioapic(dev);