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arch/x86: Remove NO_FIXED_XIP_ROM_SIZE

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The variable SETUP_XIP_CACHE provides us a working
alternative.

Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2020-05-25 08:52:07 +03:00
committed by Nico Huber
parent 49c44cdccb
commit 44ef38f703
12 changed files with 3 additions and 22 deletions
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1
src/cpu/amd/agesa/Kconfig
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@@ -16,7 +16,6 @@ config CPU_AMD_AGESA
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
select SSE2
if CPU_AMD_AGESA

1
src/cpu/amd/pi/Kconfig
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@@ -16,7 +16,6 @@ config CPU_AMD_PI
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
select SSE2
if CPU_AMD_PI

1
src/cpu/intel/haswell/Kconfig
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@@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_FIXED_XIP_ROM_SIZE
config SMM_TSEG_SIZE
hex

1
src/cpu/intel/model_2065x/Kconfig
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@@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
config SMM_TSEG_SIZE

1
src/cpu/intel/model_206ax/Kconfig
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@@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE
config SMM_TSEG_SIZE
hex

1
src/cpu/intel/socket_FCBGA559/Kconfig
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@@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS
select MMX
select SSE
select CPU_HAS_L2_ENABLE_MSR
select NO_FIXED_XIP_ROM_SIZE
config DCACHE_RAM_BASE
hex

10
src/cpu/x86/Kconfig
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@@ -60,16 +60,6 @@ config TSC_SYNC_MFENCE
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.
config NO_FIXED_XIP_ROM_SIZE
bool
default n
help
The XIP_ROM_SIZE Kconfig variable is used globally on x86
with the assumption that all chipsets utilize this value.
For the chipsets which do not use the variable it can lead
to unnecessary alignment constraints in cbfs for romstage.
Therefore, allow those chipsets a path to not be burdened.
config SETUP_XIP_CACHE
bool
depends on !NO_XIP_EARLY_STAGES