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add bug support for 2.1

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-04-06 20:45:10 +00:00
parent 69085400f1
commit 44f72eb3a3
2 changed files with 49 additions and 63 deletions
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110
src/cpu/amd/model_gx2/cpubug.c
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@@ -239,78 +239,64 @@ void bug118253(void){
void bug118339(void) void bug118339(void)
{ {
printk_err("This is OPTIONAL BIOS-ENABLED ... ignore for now\n"); /* per AMD, do this always */
#if 0 msr_t msr = {0,0};
PROC NEAR PUBLIC int msrnum;
pushad
mov cx, TOKEN_VGTEAR_118339_SWAPSIF_ENABLE /* Disable enable_actions in DIAGCTL while setting up GLCP */
NOSTACK bx, GetNVRAMValueBX wrmsr(MSR_GLCP + 0x005f, msr);
cmp ax, TVALUE_ENABLE
jne bug118339exit
;Disable enable_actions in DIAGCTL while setting up GLCP /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
mov ecx, MSR_GLCP + 005fh msrnum = MSR_GLCP + 0x042;
xor edx, edx /* msr.hi = 2d6b8000h */;
xor eax, eax msr.hi = 0x596b8000;
WRMSR msr.lo = 0x00000a00;
wrmsr(msrnum, msr);
; SET2M fires if VG pri is odd (3, not 2) and Ystate=0 /* SET3M fires if MBUS changed and VG pri is odd */
mov ecx, MSR_GLCP + 042h msrnum = MSR_GLCP + 0x043;
; mov edx, 2d6b8000h msr.hi = 0x596b8040;
mov edx, 596b8000h msr.lo = 0;
mov eax, 00000a00h wrmsr(msrnum, msr);
WRMSR
; SET3M fires if MBUS changed and VG pri is odd /* Put VG request data on lower diag bus */
mov ecx, MSR_GLCP + 043h msrnum = MSR_GLIU0 + 0x2005;
mov edx, 596b8040h msr.hi = 0;
xor eax, eax msr.lo = 0x80338041;
WRMSR wrmsr(msrnum, msr);
; Put VG request data on lower diag bus /* Increment Y state if SET3M if true */
mov ecx, MSR_GLIU0 + 2005h msrnum = MSR_GLCP + 0x074;
xor edx, edx msr.hi = 0;
mov eax, 80338041h msr.lo = 0x0000c000;
WRMSR wrmsr(msrnum, msr);
; Increment Y state if SET3M if true /* Set up MBUS action to PRI=3 read of MBIU */
mov ecx, MSR_GLCP + 074h msrnum = MSR_GLCP + 0x020;
xor edx, edx msr.hi = 0x0000d863;
mov eax, 0000c000h msr.lo = 0x20002000;
WRMSR wrmsr(msrnum, msr);
; Set up MBUS action to PRI=3 read of MBIU /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
mov ecx, MSR_GLCP + 020h msrnum = MSR_GLCP + 0x071;
mov edx, 0000d863h msr.hi = 0;
mov eax, 20002000h msr.lo = 0x00000c00;
WRMSR wrmsr(msrnum, msr);
; Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI /* Writing DIAGCTL */
mov ecx, MSR_GLCP + 071h msrnum = MSR_GLCP + 0x005f;
xor edx, edx msr.hi = 0;
mov eax, 00000c00h msr.lo = 0x80004000;
WRMSR wrmsr(msrnum, msr);
;Writing DIAGCTL /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
mov ecx, MSR_GLCP + 005fh /* As per Todd Roberts in PBz1094 and PBz1095 */
xor edx, edx /* Moved from CPUREG to CPUBUG per Tom Sylla */
mov eax, 80004000h msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
WRMSR msr = rdmsr(msrnum);
msr.hi |= 8; /* Bit 35 = MCP_IN */
wrmsr(msrnum, msr);
; Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
; As per Todd Roberts in PBz1094 and PBz1095
; Moved from CPUREG to CPUBUG per Tom Sylla
mov ecx, 04C000042h ; GLCP SETMCTL Register
rdmsr
or edx, 8 ; Bit 35 = MCP_IN
wrmsr
bug118339exit:
popad
ret
CPUbug118339 ENDP
#endif
} }

2
src/include/cpu/amd/gx2def.h
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@@ -74,7 +74,7 @@
#define GL1_FG 5 #define GL1_FG 5
#define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */ #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) #define MSR_MC (GL0_MC << 29)
#define MSR_GLIU1 (GL0_GLIU1 << 29) #define MSR_GLIU1 (GL0_GLIU1 << 29)
#define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/ #define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/