nb/intel/ironlake: Correct PCIEXBAR definition

This register resides within the SAD's config space, and is 64-bit.

Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/ironlake.h

@@ -55,6 +55,8 @@
 #define QPD0F1_PAM(x)		(0x40 + (x)) /* 0-6 */
 #define QPD0F1_SMRAM		0x4d	/* System Management RAM Control */
 
+#define SAD_PCIEXBAR		0x50
+
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */