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intel: Use CF9 reset (part 1)

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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Rudolph
2018-10-01 19:17:11 +02:00
committed by Patrick Georgi
parent 33fcaf91ff
commit 45022ae056
56 changed files with 44 additions and 547 deletions
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4
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
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@@ -19,12 +19,12 @@
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <device/device.h>
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <fspvpd.h>
#include <fspbootmode.h>
#include <reset.h>
#include "../chip.h"
#ifdef __PRE_RAM__
@@ -173,7 +173,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status,
*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
soft_reset();
system_reset();
}
romstage_main_continue(Status, HobListPtr);
}

4
src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
View File

@@ -18,11 +18,11 @@
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <device/device.h>
#include <southbridge_pci_devs.h>
#include <fsp_util.h>
#include "../chip.h"
#include <reset.h>
#ifdef __PRE_RAM__
@@ -97,7 +97,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status,
{
*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
hard_reset();
system_reset();
}
romstage_main_continue(Status, HobListPtr);
}