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intel: Use CF9 reset (part 1)

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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Rudolph
2018-10-01 19:17:11 +02:00
committed by Patrick Georgi
parent 33fcaf91ff
commit 45022ae056
56 changed files with 44 additions and 547 deletions
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2
src/soc/intel/baytrail/Kconfig
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@@ -17,7 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select SOUTHBRIDGE_INTEL_COMMON_RESET
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PCIEXP_ASPM

2
src/soc/intel/baytrail/Makefile.inc
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@@ -23,8 +23,6 @@ smm-y += iosf.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
romstage-y += reset.c
ramstage-y += reset.c
ramstage-y += cpu.c
romstage-y += pmutil.c
ramstage-y += pmutil.c

32
src/soc/intel/baytrail/include/soc/reset.h
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@@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BAYTRAIL_RESET_H_
#define _BAYTRAIL_RESET_H_
#include <reset.h>
/* Bay Trail has the following types of resets:
* - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
* - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
* - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
* - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
* - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but
* with ETR[20] set.
*/
void cold_reset(void);
void warm_reset(void);
#endif /* _BAYTRAIL_RESET_H_ */

43
src/soc/intel/baytrail/reset.c
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@@ -1,43 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <soc/pmc.h>
#include <soc/reset.h>
void cold_reset(void)
{
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
}
void warm_reset(void)
{
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_soft_reset(void)
{
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
}
void do_hard_reset(void)
{
/* Don't power cycle on hard_reset(). It's not really clear what the
* semantics should be for the meaning of hard_reset(). */
warm_reset();
}

12
src/soc/intel/baytrail/romstage/raminit.c
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@@ -18,6 +18,7 @@
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <halt.h>
@@ -26,18 +27,11 @@
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/reset.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <security/vboot/vboot_common.h>
static void reset_system(void)
{
warm_reset();
halt();
}
static void enable_smbus(void)
{
uint32_t reg;
@@ -134,7 +128,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
reset_system();
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
@@ -165,7 +159,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
reset_system();
system_reset();
#endif
}

1
src/soc/intel/baytrail/romstage/romstage.c
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@@ -36,7 +36,6 @@
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/reset.h>
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>