intel: Use CF9 reset (part 1)

Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/southbridge/intel/bd82x6x/Kconfig

@@ -29,7 +29,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG_OPTIONS
 	select HAVE_SMI_HANDLER
 	select USE_WATCHDOG_ON_BOOT

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 ramstage-y += me_status.c
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
@@ -39,7 +38,6 @@ ramstage-$(CONFIG_ELOG) += elog.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
 
 romstage-y += early_smbus.c me_status.c
-romstage-y += reset.c
 romstage-y += early_spi.c early_pch_common.c
 romstage-y += early_rcba.c
 

src/southbridge/intel/bd82x6x/reset.c

@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}

src/southbridge/intel/common/Kconfig

@@ -1,5 +1,10 @@
 config SOUTHBRIDGE_INTEL_COMMON
 	def_bool n
+	select SOUTHBRIDGE_INTEL_COMMON_RESET
+
+config SOUTHBRIDGE_INTEL_COMMON_RESET
+	bool
+	select HAVE_CF9_RESET
 
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
 	def_bool n

src/southbridge/intel/common/Makefile.inc

@@ -16,6 +16,12 @@
 # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
 subdirs-y += firmware
 
+verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
 romstage-y += pmbase.c

src/southbridge/intel/common/reset.c

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2004 Ronald G. Minnich
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -13,11 +11,10 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <cf9_reset.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
-	/* Try rebooting through port 0xcf9 */
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+	system_reset();
 }

src/southbridge/intel/fsp_bd82x6x/Kconfig

@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_SMI_HANDLER
 	select USE_WATCHDOG_ON_BOOT
 	select PCIEXP_ASPM

src/southbridge/intel/fsp_bd82x6x/Makefile.inc

@@ -23,7 +23,6 @@ ramstage-y += sata.c
 ramstage-y += me.c
 ramstage-y += me_8.x.c
 ramstage-y += me_status.c
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
@@ -37,7 +36,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 smm-$(CONFIG_USBDEBUG) += usb_debug.c
-romstage-y += reset.c
 romstage-y += early_spi.c
 
 CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x

src/southbridge/intel/fsp_bd82x6x/reset.c

@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}

src/southbridge/intel/fsp_i89xx/Kconfig

@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_SMI_HANDLER
 	select USE_WATCHDOG_ON_BOOT
 	select PCIEXP_ASPM

src/southbridge/intel/fsp_i89xx/Makefile.inc

@@ -22,7 +22,6 @@ ramstage-y += sata.c
 ramstage-y += me.c
 ramstage-y += me_8.x.c
 ramstage-y += me_status.c
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
@@ -35,7 +34,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 smm-$(CONFIG_USBDEBUG) += usb_debug.c
-romstage-y += reset.c
 romstage-y += early_spi.c
 romstage-y += romstage.c
 

src/southbridge/intel/fsp_i89xx/reset.c

@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}

src/southbridge/intel/fsp_i89xx/romstage.c

@@ -31,7 +31,7 @@
 #include <console/usb.h>
 #include <halt.h>
 #include <program_loading.h>
-#include <reset.h>
+#include <cf9_reset.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <northbridge/intel/fsp_sandybridge/northbridge.h>
 #include <northbridge/intel/fsp_sandybridge/raminit.h>
@@ -42,12 +42,6 @@
 #include "pch.h"
 #include "romstage.h"
 
-static inline void reset_system(void)
-{
-	hard_reset();
-	halt();
-}
-
 static void pch_enable_lpc(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
@@ -202,7 +196,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	cbmem_was_initted = !cbmem_recovery(0);
 
 	if (cbmem_was_initted) {
-		reset_system();
+		system_reset();
 	}
 
 	/* Save the HOB pointer in CBMEM to be used in ramstage. */

src/southbridge/intel/fsp_rangeley/Kconfig

@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT
 	select PCIEXP_ASPM

src/southbridge/intel/fsp_rangeley/Makefile.inc

@@ -19,13 +19,12 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
 ramstage-y += soc.c
 ramstage-y += lpc.c
 ramstage-y += sata.c
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 ramstage-y += spi.c
 ramstage-y += smbus.c
 ramstage-y += acpi.c
 
-romstage-y += early_usb.c early_smbus.c gpio.c reset.c early_spi.c early_init.c
+romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c
 romstage-y += romstage.c
 
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c

src/southbridge/intel/fsp_rangeley/reset.c

@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	hard_reset();
-}
-
-void do_hard_reset(void)
-{
-	outb(0x02, 0xcf9);
-	outb(0x06, 0xcf9);
-}

src/southbridge/intel/i82801dx/Kconfig

@@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801DX
 	bool
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG
 	select SOUTHBRIDGE_INTEL_COMMON

src/southbridge/intel/i82801dx/Makefile.inc

@@ -24,8 +24,6 @@ ramstage-y += lpc.c
 ramstage-y += usb.c
 ramstage-y += usb2.c
 
-ramstage-y += reset.c
-
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

src/southbridge/intel/i82801gx/Kconfig

@@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select SOUTHBRIDGE_INTEL_COMMON
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT
 	select HAVE_SMI_HANDLER

src/southbridge/intel/i82801gx/Makefile.inc

@@ -30,7 +30,6 @@ ramstage-y += usb_ehci.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c

src/southbridge/intel/i82801gx/reset.c

@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-#if 0
-void do_hard_reset(void)
-{
-	/* Try rebooting through port 0xcf9. */
-	outb((1 << 2) | (1 << 1), 0xcf9);
-}
-#endif
-
-void do_hard_reset(void)
-{
-	outb(0x02, 0xcf9);
-	outb(0x06, 0xcf9);
-}

src/southbridge/intel/i82801ix/Kconfig

@@ -21,7 +21,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select IOAPIC
 	select HAVE_USBDEBUG
-	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG_OPTIONS

src/southbridge/intel/i82801ix/Makefile.inc

@@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += ../i82801gx/reset.c
 ramstage-y += ../i82801gx/watchdog.c
 
 ifneq ($(CONFIG_SMM_TSEG),y)

src/southbridge/intel/i82801jx/Kconfig

@@ -22,7 +22,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select IOAPIC
 	select HAVE_USBDEBUG
-	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG_OPTIONS

src/southbridge/intel/i82801jx/Makefile.inc

@@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += ../i82801gx/reset.c
 ramstage-y += ../i82801gx/watchdog.c
 
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c

src/southbridge/intel/ibexpeak/Kconfig

@@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG
 	select HAVE_SMI_HANDLER
 	select USE_WATCHDOG_ON_BOOT

src/southbridge/intel/ibexpeak/Makefile.inc

@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 ramstage-y += ../bd82x6x/me_status.c
-ramstage-y += ../bd82x6x/reset.c
 ramstage-y += ../bd82x6x/watchdog.c
 
 ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
@@ -41,7 +40,6 @@ ramstage-y += smi.c
 smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
 
 romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
-romstage-y += ../bd82x6x/reset.c
 romstage-y += ../bd82x6x/early_rcba.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c

src/southbridge/intel/lynxpoint/Kconfig

@@ -25,7 +25,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select IOAPIC
-	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG_OPTIONS
 	select USE_WATCHDOG_ON_BOOT
 	select PCIEXP_ASPM

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -36,7 +36,6 @@ endif
 
 ramstage-y += rcba.c
 ramstage-y += me_status.c
-ramstage-y += reset.c
 ramstage-y += watchdog.c
 ramstage-y += acpi.c
 
@@ -47,7 +46,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
 
 romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
-romstage-y += reset.c early_spi.c rcba.c pmutil.c
+romstage-y += early_spi.c rcba.c pmutil.c
 
 ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
 romstage-y += lp_gpio.c
@@ -55,6 +54,4 @@ ramstage-y += lp_gpio.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
 endif
 
-postcar-y += reset.c
-
 endif

src/southbridge/intel/lynxpoint/reset.c

@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}