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soc/amd/common/acp: Move Audio Co-processor driver to common

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Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.

BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.

Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2021-04-23 11:42:19 -06:00
committed by Martin Roth
parent e5b85c3377
commit 4520aa2891
17 changed files with 75 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/picasso/Kconfig
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@@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_EM100_SUPPORT
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACP
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO

1
src/soc/amd/picasso/Makefile.inc
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@@ -43,7 +43,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
ramstage-y += gpio.c
ramstage-y += fch.c
ramstage-y += reset.c
ramstage-y += acp.c
ramstage-y += sata.c
ramstage-y += uart.c
ramstage-y += soc_util.c

67
src/soc/amd/picasso/acp.c
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@@ -1,67 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_device.h>
#include <acpi/acpigen.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
#include <soc/acp.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include <amdblocks/acpimmio.h>
#include <commonlib/helpers.h>
static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
{
clrsetbits32((void *)(bar + reg), clear, set);
}
static void init(struct device *dev)
{
const struct soc_amd_picasso_config *cfg;
struct resource *res;
uintptr_t bar;
/* Set the proper I2S_PIN_CONFIG state */
cfg = config_of_soc();
res = dev->resource_list;
if (!res || !res->base) {
printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
return;
}
bar = (uintptr_t)res->base;
acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_pin_cfg);
/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */
acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable);
acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable);
}
static const char *acp_acpi_name(const struct device *dev)
{
return "ACPD";
}
static struct device_operations acp_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = init,
.ops_pci = &pci_dev_ops_pci,
.scan_bus = scan_static_bus,
.acpi_name = acp_acpi_name,
.acpi_fill_ssdt = acpi_device_write_pci_dev,
};
static const struct pci_driver acp_driver __pci_driver = {
.ops = &acp_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_FAM17H_ACP,
};

15
src/soc/amd/picasso/chip.h
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@@ -105,19 +105,6 @@ struct soc_amd_picasso_config {
*/
u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
enum {
I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
I2S_PINS_I2S_TDM = 4,
I2S_PINS_UNCONF = 7, /* All pads will be input mode */
} acp_pin_cfg;
/* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
u8 acp_i2s_wake_enable;
/* Enable ACP PME (0 = disable, 1 = enable) */
u8 acp_pme_enable;
/* System config index */
uint8_t system_config;
@@ -270,8 +257,6 @@ struct soc_amd_picasso_config {
/* The array index is the general purpose PCIe clock output number. */
enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
bool acp_i2s_use_external_48mhz_osc;
/* eDP phy tuning settings */
uint16_t edp_phy_override;

6
src/soc/amd/picasso/fch.c
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@@ -90,12 +90,12 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
void sb_clk_output_48Mhz(void)
{
u32 ctrl;
const struct soc_amd_picasso_config *cfg;
cfg = config_of_soc();
const struct soc_amd_common_config *cfg = soc_get_common_config();
ctrl = misc_read32(MISC_CLK_CNTL1);
/* If used external clock source for I2S, disable the internal clock output */
if (cfg->acp_i2s_use_external_48mhz_osc && cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
if (cfg->acp_config.acp_i2s_use_external_48mhz_osc &&
cfg->acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM)
ctrl &= ~BP_X48M0_OUTPUT_EN;
else
ctrl |= BP_X48M0_OUTPUT_EN;

14
src/soc/amd/picasso/include/soc/acp.h
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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_PICASSO_ACP_H
#define AMD_PICASSO_ACP_H
/* Bus A D0F5 - Audio Processor */
#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */
#define PIN_CONFIG_MASK (7 << 0)
#define ACP_I2S_WAKE_EN 0x1414
#define WAKE_EN_MASK (1 << 0)
#define ACP_PME_EN 0x1418
#define PME_EN_MASK (1 << 0)
#endif /* AMD_PICASSO_ACP_H */