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soc/intel/xeon_sp: Move VPD based settings to mainboard codes

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Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Shuo Liu 2024-04-26 06:15:35 +08:00 committed by Lean Sheng Tan
parent a0aff6e159
commit 45a670d223
3 changed files with 33 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/intel/archercity_crb/romstage.c
View File

@ -35,16 +35,22 @@ static void mainboard_config_iio(FSPM_UPD *mupd)
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)
{ {
uint8_t val; /* Setup FSP log */
mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG,
/* Send FSP log message to SOL */ FSP_LOG_DEFAULT);
if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) if (mupd->FspmConfig.SerialIoUartDebugEnable) {
mupd->FspmConfig.SerialIoUartDebugEnable = val; mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range(
else { FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", /* If serialDebugMsgLvl less than 1, disable FSP memory train results */
FSP_LOG, FSP_LOG_DEFAULT); if (mupd->FspmConfig.serialDebugMsgLvl <= 1) {
mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n");
mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
} }
}
/* FSP Dfx PMIC Secure mode */
mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range(
FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2);
/* Set Rank Margin Tool to disable. */ /* Set Rank Margin Tool to disable. */
mupd->FspmConfig.EnableRMT = 0x0; mupd->FspmConfig.EnableRMT = 0x0;

24
src/mainboard/inventec/transformers/romstage.c
View File

@ -98,21 +98,27 @@ static void mainboard_config_iio(FSPM_UPD *mupd)
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)
{ {
uint8_t val;
/* Since it's the first IPMI command, it's better to run get BMC selftest result first */ /* Since it's the first IPMI command, it's better to run get BMC selftest result first */
if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
init_frb2_wdt(); init_frb2_wdt();
} }
/* Send FSP log message to SOL */ /* Setup FSP log */
if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG,
mupd->FspmConfig.SerialIoUartDebugEnable = val; FSP_LOG_DEFAULT);
else { if (mupd->FspmConfig.SerialIoUartDebugEnable) {
printk(BIOS_INFO, "Not able to get VPD %s, default set " mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range(
"SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; /* If serialDebugMsgLvl less than 1, disable FSP memory train results */
if (mupd->FspmConfig.serialDebugMsgLvl <= 1) {
printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n");
mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
} }
}
/* FSP Dfx PMIC Secure mode */
mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range(
FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2);
/* Set Rank Margin Tool to disable. */ /* Set Rank Margin Tool to disable. */
mupd->FspmConfig.EnableRMT = 0x0; mupd->FspmConfig.EnableRMT = 0x0;

70
src/soc/intel/xeon_sp/spr/romstage.c
View File

@ -34,71 +34,8 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
/* Default weak implementation */ /* Default weak implementation */
} }
/* static void config_upd(FSPM_UPD *mupd)
* Search from VPD_RW first then VPD_RO for UPD config variables,
* overwrites them from VPD if it's found.
*/
static void config_upd_from_vpd(FSPM_UPD *mupd)
{ {
uint8_t val;
int val_int;
/* Send FSP log message to SOL */
if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
mupd->FspmConfig.SerialIoUartDebugEnable = val;
else {
printk(BIOS_INFO,
"Not able to get VPD %s, default set "
"SerialIoUartDebugEnable to %d\n",
FSP_LOG, FSP_LOG_DEFAULT);
mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
}
if (mupd->FspmConfig.SerialIoUartDebugEnable) {
/* FSP memory debug log level */
if (vpd_get_int(FSP_MEM_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) {
if (val_int < 0 || val_int > 4) {
printk(BIOS_DEBUG,
"Invalid serialDebugMsgLvl value from VPD: "
"%d\n",
val_int);
val_int = FSP_MEM_LOG_LEVEL_DEFAULT;
}
printk(BIOS_DEBUG, "Setting serialDebugMsgLvl to %d\n", val_int);
mupd->FspmConfig.serialDebugMsgLvl = (uint8_t)val_int;
} else {
printk(BIOS_INFO,
"Not able to get VPD %s, default set "
"DebugPrintLevel to %d\n",
FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT);
mupd->FspmConfig.serialDebugMsgLvl = FSP_MEM_LOG_LEVEL_DEFAULT;
}
/* If serialDebugMsgLvl less than 1, disable FSP memory train results */
if (mupd->FspmConfig.serialDebugMsgLvl <= 1) {
printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n");
mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
}
}
/* FSP Dfx PMIC Secure mode */
if (vpd_get_int(FSP_PMIC_SECURE_MODE, VPD_RW_THEN_RO, &val_int)) {
if (val_int < 0 || val_int > 2) {
printk(BIOS_DEBUG,
"Invalid PMIC secure mode value from VPD: "
"%d\n",
val_int);
val_int = FSP_PMIC_SECURE_MODE_DEFAULT;
}
printk(BIOS_DEBUG, "Setting PMIC secure mode to %d\n", val_int);
mupd->FspmConfig.DfxPmicSecureMode = (uint8_t)val_int;
} else {
printk(BIOS_INFO,
"Not able to get VPD %s, default set "
"PMIC secure mode to %d\n",
FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT);
mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT;
}
int cxl_mode = get_cxl_mode(); int cxl_mode = get_cxl_mode();
if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM) if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM)
mupd->FspmConfig.DfxCxlType3LegacyEn = 1; mupd->FspmConfig.DfxCxlType3LegacyEn = 1;
@ -274,9 +211,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
printk(BIOS_DEBUG, "CPU is D stepping, setting package C state to C0/C1\n"); printk(BIOS_DEBUG, "CPU is D stepping, setting package C state to C0/C1\n");
mupd->FspmConfig.CpuPmPackageCState = 0; mupd->FspmConfig.CpuPmPackageCState = 0;
} }
/* Set some common UPDs from VPD, mainboard can still override them if needed */
if (CONFIG(VPD)) config_upd(mupd);
config_upd_from_vpd(mupd);
initialize_iio_upd(mupd); initialize_iio_upd(mupd);
mainboard_memory_init_params(mupd); mainboard_memory_init_params(mupd);