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soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller

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- Correctly detect device 17h as the MMC 4.5 controller
- Support detection of the "old" MMC controller at device 10h

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Mate Kukri
2020-07-03 14:44:49 +02:00
committed by Patrick Georgi
parent 355d1c9870
commit 45b51e0180
6 changed files with 37 additions and 24 deletions
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12
src/soc/intel/baytrail/southcluster.c
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@ -204,6 +204,9 @@ static void sc_disable_devfn(struct device *dev)
uint32_t mask2 = 0;
switch (dev->path.pci.devfn) {
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
mask |= MMC_DIS;
break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
mask |= SDIO_DIS;
break;
@ -221,8 +224,8 @@ static void sc_disable_devfn(struct device *dev)
case PCI_DEVFN(LPE_DEV, LPE_FUNC):
mask |= LPE_DIS;
break;
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
mask |= MMC_DIS;
case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
mask |= MMC45_DIS;
break;
case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
mask |= SIO_DMA1_DIS;
@ -362,13 +365,16 @@ static int place_device_in_d3hot(struct device *dev)
* Work around this by hard coding the offset.
*/
switch (dev->path.pci.devfn) {
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(SD_DEV, SD_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(MMC_DEV, MMC_FUNC):
case PCI_DEVFN(MMC45_DEV, MMC45_FUNC):
offset = 0x80;
break;
case PCI_DEVFN(LPE_DEV, LPE_FUNC):