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soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE

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In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to
programming PWRMBASE and enable BIT 2 after programming PWRMBASE
along with PCI_COMMAND_MEMORY (BIT 1).

Also perform below operations
1. Use pci_and_config16 instead of pci read and write
2. Use setbits32 instead of mmio read and write

Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
2020-08-05 13:30:30 +05:30
parent ad3dceae30
commit 45caf972ed
4 changed files with 16 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/cannonlake/bootblock/pch.c
View File

@@ -59,26 +59,20 @@ static uint32_t get_pmc_reg_base(void)
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
{ {
uint32_t reg32;
uint16_t reg16;
/* /*
* Assign Resources to PWRMBASE * Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register * Clear BIT 1-2 Command Register
*/ */
reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */ /* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ /* Enable Bus Master and MMIO Space */
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ /* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
} }
void bootblock_pch_early_init(void) void bootblock_pch_early_init(void)

14
src/soc/intel/icelake/bootblock/pch.c
View File

@@ -40,26 +40,20 @@
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
{ {
uint32_t reg32;
uint16_t reg16;
/* /*
* Assign Resources to PWRMBASE * Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register * Clear BIT 1-2 Command Register
*/ */
reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */ /* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ /* Enable Bus Master and MMIO Space */
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ /* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
} }
void bootblock_pch_early_init(void) void bootblock_pch_early_init(void)

14
src/soc/intel/jasperlake/bootblock/pch.c
View File

@@ -44,26 +44,20 @@
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
{ {
uint32_t reg32;
uint16_t reg16;
/* /*
* Assign Resources to PWRMBASE * Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register * Clear BIT 1-2 Command Register
*/ */
reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */ /* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ /* Enable Bus Master and MMIO Space */
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ /* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
} }
void bootblock_pch_early_init(void) void bootblock_pch_early_init(void)

14
src/soc/intel/tigerlake/bootblock/pch.c
View File

@@ -49,26 +49,20 @@
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
{ {
uint32_t reg32;
uint16_t reg16;
/* /*
* Assign Resources to PWRMBASE * Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register * Clear BIT 1-2 Command Register
*/ */
reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */ /* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ /* Enable Bus Master and MMIO Space */
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ /* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
} }
void bootblock_pch_early_init(void) void bootblock_pch_early_init(void)