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mb/*: Update SPD mapping for sandybridge boards

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Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.

Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.

Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Keith Hui
2023-07-22 12:49:05 -04:00
committed by Felix Held
parent 940fe080bf
commit 45e4ab4a66
112 changed files with 104 additions and 672 deletions
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src/mainboard/google/parrot/devicetree.cb
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@@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x000001d4"
register "gpu_pch_backlight" = "0x03aa0000"
register "spd_addresses" = "{0x50, 0, 0x52, 0}"
register "ec_present" = "1"
# FIXME: Native raminit requires reduced max clock
register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"