add cpureginit to romcc code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -69,11 +69,11 @@
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#define GL0_DF 6
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#define GL1_GLIU0 1
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#define GL1_GLCP 3
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#define GL1_GLCP 3
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#define GL1_PCI 4
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#define GL1_FG 5
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#define GL1_VIP 5
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#define GL1_AES 6
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#define GL1_VIP 5
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#define GL1_AES 6
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#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* To get on GeodeLink one bit has to be set */
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#define MSR_MC (GL0_MC << 29)
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