diff --git a/.gitignore b/.gitignore index ed667765fb..11a6173283 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,3 @@ -payloads/libpayload/install/ -payloads/nvramcui/build -payloads/nvramcui/libpayload junit.xml abuild*.xml .config @@ -11,46 +8,8 @@ defconfig .ccwrap build/ coreboot-builds/ -payloads/coreinfo/lpbuild/ -payloads/coreinfo/lp.config* -payloads/external/depthcharge/depthcharge/ -payloads/external/FILO/filo/ -payloads/external/GRUB2/grub2/ -payloads/external/LinuxBoot/linuxboot/ -payloads/external/SeaBIOS/seabios/ -payloads/external/tianocore/tianocore/ -payloads/external/tint/tint/ -payloads/external/U-Boot/u-boot/ -payloads/external/Memtest86Plus/memtest86plus/ -payloads/external/iPXE/ipxe/ -util/crossgcc/acpica-unix-*/ -util/crossgcc/binutils-*/ -util/crossgcc/build-*BINUTILS/ -util/crossgcc/build-*EXPAT/ -util/crossgcc/build-*GCC/ -util/crossgcc/build-*GDB/ -util/crossgcc/build-*GMP/ -util/crossgcc/build-*LIBELF/ -util/crossgcc/build-*MPC/ -util/crossgcc/build-*MPFR/ -util/crossgcc/build-*PYTHON/ -util/crossgcc/build-*LVM/ -util/crossgcc/build-*IASL/ -util/crossgcc/expat-*/ -util/crossgcc/gcc-*/ -util/crossgcc/gdb-*/ -util/crossgcc/gmp-*/ -util/crossgcc/libelf-*/ -util/crossgcc/mingwrt-*/ -util/crossgcc/mpc-*/ -util/crossgcc/mpfr-*/ -util/crossgcc/Python-*/ -util/crossgcc/*.src/ -util/crossgcc/tarballs/ -util/crossgcc/w32api-*/ -util/crossgcc/xgcc/ -util/crossgcc/xgcc-*/ -util/crossgcc/xgcc +coreboot-builds*/ + site-local *.\# @@ -59,13 +18,15 @@ site-local *.debug !Kconfig.debug *.elf +*.fd *.o *.o.d *.out *.pyc *.sw[po] /*.rom -coreboot-builds*/ +.test +.dependencies # Development friendly files tags @@ -75,61 +36,9 @@ tags xgcc/ tarballs/ -# -# KDE editors create lots of backup files whenever -# a file is edited, so just ignore them +# editor backup files, temporary files, IDE project files *~ *.kate-swp -# Ignore Kdevelop project file *.kdev4 -util/*/.dependencies -util/*/.test -util/amdfwtool/amdfwtool -util/archive/archive -util/bincfg/bincfg -util/board_status/board-status -util/bucts/bucts -util/cbfstool/cbfs-compression-tool -util/cbfstool/cbfstool -util/cbfstool/fmaptool -util/cbfstool/ifwitool -util/cbfstool/rmodtool -util/cbmem/.dependencies -util/cbmem/cbmem -util/dumpmmcr/dumpmmcr -util/ectool/ectool -util/futility/futility -util/genprof/genprof -util/getpir/getpir -util/ifdtool/ifdtool -util/intelmetool/intelmetool -util/inteltool/.dependencies -util/inteltool/inteltool -util/intelvbttool/intelvbttool -util/k8resdump/k8resdump -util/lbtdump/lbtdump -util/mptable/mptable -util/msrtool/Makefile -util/msrtool/Makefile.deps -util/msrtool/msrtool -util/nvramtool/.dependencies -util/nvramtool/nvramtool -util/optionlist/Options.wiki -util/pmh7tool/pmh7tool -util/runfw/googlesnow -util/superiotool/superiotool -util/vgabios/testbios -util/autoport/autoport -util/kbc1126/kbc1126_ec_dump -util/kbc1126/kbc1126_ec_insert - -Documentation/*.aux -Documentation/*.idx -Documentation/*.log -Documentation/*.toc -Documentation/*.out -Documentation/*.pdf -Documentation/_build - doxygen/* diff --git a/.gitmodules b/.gitmodules index 2a9c60f8bb..0ed79be37c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -51,3 +51,10 @@ url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty +[submodule "3rdparty/intel-sec-tools"] + path = 3rdparty/intel-sec-tools + url = ../9esec-security-tooling.git +[submodule "3rdparty/stm"] + path = 3rdparty/stm + url = ../STM + branch = stmpe diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 1ac6d42bf3..b12744905d 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 1ac6d42bf336af639ae849933cbb818e51b1ffd1 +Subproject commit b12744905dd20c77154db99a379543f61a3e3e7f diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index ace23683be..a4c979ade4 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit ace23683beb81354d6edbc61c087ab8c384d0631 +Subproject commit a4c979ade4438dfdd69c1b6e23b64e88eb648183 diff --git a/3rdparty/blobs b/3rdparty/blobs index bbe5d99780..a59fb6e389 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit bbe5d99780d2d085e92d9bae2c0f7b6787419d72 +Subproject commit a59fb6e3892f0629d43769a07ee7f1048a0ae1f8 diff --git a/3rdparty/fsp b/3rdparty/fsp index 2263d48a00..e7138bf115 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 2263d48a006d8653df1fc742c3f7d5ffd6b75d68 +Subproject commit e7138bf11508b8b82350bd17fb611b67c0c64e6b diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 33b7b2f381..0e4288f81f 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 33b7b2f3817e362111cd91910026ab8907f21710 +Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools new file mode 160000 index 0000000000..a86ff5d400 --- /dev/null +++ b/3rdparty/intel-sec-tools @@ -0,0 +1 @@ +Subproject commit a86ff5d400983d685d4389c07433452c7a503300 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf2680..bc0588e482 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit bc0588e482b1320d5739900b00a45033f5b587f4 diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 126fef6b99..6b7fe498eb 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 126fef6b996237403039aa603945fc4caa75c8d6 +Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 diff --git a/3rdparty/stm b/3rdparty/stm new file mode 160000 index 0000000000..1f3258261a --- /dev/null +++ b/3rdparty/stm @@ -0,0 +1 @@ +Subproject commit 1f3258261a4f4d6c60ec4447c7a03acf2509b984 diff --git a/3rdparty/vboot b/3rdparty/vboot index 68de90c7e2..48195e5878 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 68de90c7e2f4a27d3a76489199176d2ab8f56de1 +Subproject commit 48195e5878006ac2cf74cb7f02953ab06c68202d diff --git a/Documentation/.gitignore b/Documentation/.gitignore new file mode 100644 index 0000000000..a8f5d5f6fa --- /dev/null +++ b/Documentation/.gitignore @@ -0,0 +1,7 @@ +*.aux +*.idx +*.log +*.toc +*.out +*.pdf +_build diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index f5546d18d5..0e14115db8 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -5,18 +5,21 @@ This section contains documentation about coreboot on x86 architecture. * [x86 PAE support](pae.md) ## State of x86_64 support -At the moment there's no single board that supports x86_64 or to be exact -`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`. +At the moment there's only experimental x86_64 support. +The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support +*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*. -In order to add support for x86_64 the following assumptions are made: +In order to add support for x86_64 the following assumptions were made: * The CPU supports long mode * All memory returned by malloc must be below 4GiB in physical memory * All code that is to be run must be below 4GiB in physical memory * The high dword of pointers is always zero * The reference implementation is qemu * The CPU supports 1GiB hugepages +* x86 payloads are loaded below 4GiB in physical memory and are jumped + to in *protected mode* -## Assuptions for all stages using the reference implementation +## Assumptions for all stages using the reference implementation * 0-4GiB are identity mapped using 2MiB-pages as WB * Memory above 4GiB isn't accessible * page tables reside in memory mapped ROM @@ -37,18 +40,16 @@ The page tables contains the following structure: At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. -## Steps to add basic support for x86_64 -* Add x86_64 toolchain support - *DONE* -* Fix compilation errors - *DONE* -* Fix linker errors - *TODO* -* Add x86_64 rmodule support - *DONE* -* Add x86_64 exception handlers - *DONE* -* Setup page tables for long mode - *DONE* -* Add assembly code for long mode - *DONE* -* Add assembly code for SMM - *DONE* -* Add assembly code for postcar stage - *TODO* -* Add assembly code to return to protected mode - *TODO* -* Implement reference code for mainboard `emulation/qemu-q35` - *TODO* +## Basic x86_64 support +Basic support for x86_64 has been implemented for QEMU mainboard target. + +## Reference implementation +The reference implementation is +* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md) +* [QEMU Q35](../../mainboard/emulation/qemu-q35.md) + +## TODO +* Identity map memory above 4GiB in ramstage ## Future work @@ -64,3 +65,33 @@ At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +According to Intel x86_64 mode hasn't been validated in CAR environments. +Until now it could be verified on various Intel platforms and no issues have +been found. + +## Known bugs on KVM enabled qemu + +The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues +when using KVM mode on some machines. The workaround is to *not* place +page-tables in ROM, as done in +[CB:49228](https://review.coreboot.org/c/coreboot/+/49228). + +Here's a list of known issues: + +* After entering long mode, the FPU doesn't work anymore, including accessing + MMX registers. It works fine before entering long mode. It works fine when + switching back to protected mode. Other registers, like SSE registers, are + working fine. +* Reading from virtual memory, when the page tables are stored in ROM, causes + the MMU to abort the "page table walking" mechanism when the lower address + bits of the virtual address to be translated have a specific pattern. + Instead of loading the correct physical page, the one containing the + page tables in ROM will be loaded and used, which breaks code and data as + the page table doesn't contain the expected data. This in turn leads to + undefined behaviour whenever the 'wrong' address is being read. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU. +* Entering long mode crashes on AMD host platforms. diff --git a/Documentation/cbfstool/index.md b/Documentation/cbfstool/index.md new file mode 100644 index 0000000000..f99b612855 --- /dev/null +++ b/Documentation/cbfstool/index.md @@ -0,0 +1,5 @@ +# cbfstool + +Contents: + +* [Handling memory mapped boot media](mmap_windows.md) diff --git a/Documentation/cbfstool/mmap_windows.md b/Documentation/cbfstool/mmap_windows.md new file mode 100644 index 0000000000..66685f30e8 --- /dev/null +++ b/Documentation/cbfstool/mmap_windows.md @@ -0,0 +1,77 @@ +# cbfstool: Handling memory mapped boot media + +`cbfstool` is a utility used for managing coreboot file system (CBFS) +components in a ROM image. x86 platforms are special since they have +the SPI flash boot media memory mapped into host address space at +runtime. This requires `cbfstool` to deal with two separate address +spaces for any CBFS components that are eXecute-In-Place (XIP) - one +is the SPI flash address space and other is the host address space +where the SPI flash gets mapped. + +By default, all x86 platforms map a maximum of 16MiB of SPI flash at +the top of 4G in host address space. If the flash is greater than +16MiB, then only the top 16MiB of the flash is mapped in the host +address space. If the flash is smaller than 16MiB, then the entire SPI +flash is mapped at the top of 4G and the rest of the space remains +unused. + +In more recent platforms like Tiger Lake (TGL), it is possible to map +more than 16MiB of SPI flash. Since the host address space has legacy +fixed device addresses mapped below `4G - 16M`, the SPI flash is split +into separate windows when being mapped to the host address space. +Default decode window of maximum 16MiB size still lives just below the +4G boundary. The additional decode window is free to live in any +available MMIO space that the SoC chooses. + +Following diagram shows different combinations of SPI flash being +mapped into host address space when using multiple windows: + +![MMAP window combinations with different flash sizes][mmap_windows] + +*(a) SPI flash of size 16MiB (b) SPI flash smaller than 16MiB (c) SPI flash +of size (16MiB+ext window size) (d) SPI flash smaller than (16MiB+ext +window size)* + +The location of standard decode window is fixed in host address space +`(4G - 16M) to 4G`. However, the platform is free to choose where the +extended window lives in the host address space. Since `cbfstool` +needs to know the exact location of the extended window, it allows the +platform to pass in two parameters `ext-win-base` and `ext-win-size` +that provide the base and the size of the extended window in host +address space. + +`cbfstool` creates two memory map windows using the knowledge about the +standard decode window and the information passed in by the platform +about the extended decode window. These windows are useful in +converting addresses from one space to another (flash space and host +space) when dealing with XIP components. + +## Assumptions + +1. Top 16MiB is still decoded in the fixed decode window just below 4G + boundary. +1. Rest of the SPI flash below the top 16MiB is mapped at the top of + the extended window. Even though the platform might support a + larger extended window, the SPI flash part used by the mainboard + might not be large enough to be mapped in the entire window. In + such cases, the mapping is assumed to be in the top part of the + extended window with the bottom part remaining unused. + +## Example + +If the platform supports extended window and the SPI flash size is +greater, then `cbfstool` creates a mapping for the extended window as +well. + +``` +ext_win_base = 0xF8000000 +ext_win_size = 32 * MiB +ext_win_limit = ext_win_base + ext_win_size - 1 = 0xF9FFFFFF +``` + +If SPI flash is 32MiB, then top 16MiB is mapped from `0xFF000000 - +0xFFFFFFFF` whereas the bottom 16MiB is mapped from `0xF9000000 - +0xF9FFFFFF`. The extended window `0xF8000000 - 0xF8FFFFFF` remains +unused. + +[mmap_windows]: mmap_windows.svg diff --git a/Documentation/cbfstool/mmap_windows.svg b/Documentation/cbfstool/mmap_windows.svg new file mode 100644 index 0000000000..617c60e743 --- /dev/null +++ b/Documentation/cbfstool/mmap_windows.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Documentation/community/language_style.md b/Documentation/community/language_style.md new file mode 100644 index 0000000000..97f9601286 --- /dev/null +++ b/Documentation/community/language_style.md @@ -0,0 +1,136 @@ +# Language style + +Following our [Code of Conduct](code_of_conduct.md) the project aims to +be a space where people are considerate in natural language communication: + +There are terms in computing that were probably considered benign when +introduced but are uncomfortable to some. The project aims to de-emphasize +such terms in favor of alternatives that are at least as expressive - +but often manage to be even more descriptive. + +## Political Correctness + +A common thread in discussions was that the project merely follows some +fad, or that this is a "political correctness" measure, designed to please +one particular "team". While the project doesn't exist in a vacuum and +so there are outside influences on project members, the proposal wasn't +made with the purpose of demonstrating allegiance to any given cause - +except one: + +There are people who feel uncomfortable with some terms being used, +_especially_ when that use takes them out of their grave context +(e.g. slave when discussing slavery) and applies them to a rather benign +topic (e.g. coordination of multiple technical systems), taking away +the gravity of the term. + +That gets especially jarring when people aren't exposed to such terms +in abstract sociological discussions but when they stand for real issues +they encountered. + +When having to choose between using a well-established term that +affects people negatively who could otherwise contribute more happily +and undisturbed or an alternative just-as-good term that doesn't, the +decision should be simple. + +## Token gesture + +The other major point of contention is that such decisions are a token +gesture that doesn't change anything. It's true: No slave is freed +because coreboot rejects the use of the word. + +coreboot is ambitious enough as-is, in that the project offers +an alternative approach to firmware, sometimes against the vested +interests (and deep pockets) of the leaders of a multi-billion dollar +industry. Changing the preferred vocabulary isn't another attempt at +changing the world, it's one thing we do to try to make coreboot (and +coreboot only) a comfortable environment for everybody. + +## For everybody + +For everybody, but with a qualifier: We have certain community etiquette, +and we define some behavior we don't accept in our community, both +detailed in the Code of Conduct. + +Other than that, we're trying to accommodate people: The CoC lays out +that language should be interpreted as friendly by default, and to be +graceful in light of accidents. This also applies to the use of terms +that the project tries to avoid: The consequence of the use of such +terms (unless obviously employed to provoke a reaction - in that case, +please contact the arbitration team as outlined in the Code of Conduct) +should be a friendly reminder. The project is slow to sanction and that +won't change just because the wrong kind of words is used. + +## Interfacing with the world + +The project doesn't exist in a vacuum, and that also applies to the choice +of words made by other initiatives in low-level technology. When JEDEC +calls the participants of a SPI transaction "master" and "slave", there's +little we can do about that. We _could_ decide to use different terms, +but that wouldn't make things easier but harder, because such a deliberate +departure means that the original terms (and their original use) gain +lots of visibility every time (so there's no practical advantage) while +adding confusion, and therefore even more attention, to that situation. + +Sometimes there are abbreviations that can be used as substitutes, +and in that case the recommendation is to do that. + +As terms that we found to be best avoided are replaced in such +initiatives, we can follow up. Members of the community with leverage +in such organizations are encouraged to raise the concern there. + +## Dealing with uses + +There are existing uses in our documentation and code. When we decide to +retire a term that doesn't mean that everybody is supposed to stop doing +whatever they're doing and spend their time on purging terms. Instead, +ongoing development should look for alternatives (and so this could come +up in review). + +People can go through existing code and docs and sort out older instances, +and while that's encouraged it's no "stop the world" event. Changes +in flight in review may still be merged with such terms intact, but if +there's more work required for other reasons, we'd encourage moving away +from such terms. + +This document has a section on retired terms, presenting the rationale +as well as alternative terms that could be used instead. The main goal is +to be expressive: There's no point in just picking any alternative term, +choose something that explains the purpose well. + +As mentioned, missteps will happen. Point them out, but assume no ill +intent for as long as you can manage. + +## Discussing words to remove from active use + +There ought to be some process when terminology is brought up as a +negative to avoid. Do not to tell people that "they're feeling wrong" +when they have a negative reaction to certain terms, but also try to +avoid being offended for the sake of others. + +When bringing up a term, on the project's mailing list or, if you don't +feel safe doing that, by contacting the arbitration team, explain what's +wrong with the term and offer alternatives for uses within coreboot. + +With a term under discussion, see if there's particular value for us to +continue using the term (maybe in limited situations, like continuing +to use "slave" in SPI related code). + +Once the arbitration team considers the topic discussed completely and +found a consensus, it will present a decision in a leadership meeting. It +should explain why a term should or should not be used and in the latter +case offer alternatives. These decisions shall then be added to this +document. + +## Retired terminology + +### slave + +Replacing this term for something else had the highest approval rating +in early discussions, so it seems pretty universally considered a bad +choice and therefore should be avoided where possible. + +An exception is made where it's a term used in current standards and data +sheets: Trying to "hide" the term in such cases only puts a spotlight +on it every time code and data sheet are compared. + +Alternatives: subordinate, secondary, follower diff --git a/Documentation/conf.py b/Documentation/conf.py index f82fa0e182..3180fd9720 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -48,7 +48,7 @@ try: except ImportError: print("Error: Please install sphinxcontrib.ditaa for ASCII art conversion\n") else: - extensions += 'sphinxcontrib.ditaa' + extensions += ['sphinxcontrib.ditaa'] # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index e215c6ab11..40d747da9d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -4,6 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and they allow to easily reuse existing code accross platforms. +* [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) * [SoundWire](soundwire.md) +* [SMMSTOREv2](smmstorev2.md) +* [USB4 Retimer](retimer.md) diff --git a/Documentation/drivers/retimer.md b/Documentation/drivers/retimer.md new file mode 100644 index 0000000000..d83b50b26f --- /dev/null +++ b/Documentation/drivers/retimer.md @@ -0,0 +1,40 @@ +# USB4 Retimers + +# Introduction +As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in +newer revisions of the spec), it becomes more difficult to maintain signal +integrity for longer traces. Devices such as retimers and redrivers can be used +to help signals maintain their integrity over long distances. + +A redriver is a device that boosts the high-frequency content of a signal in +order to compensate for the attenuation typically caused by travelling through +various circuit components (PCB, connectors, CPU, etc.). Redrivers are not +protocol-aware, which makes them relatively simple. However, their effectiveness +is limited, and may not work at all in some scenarios. + +A retimer is a device that retransmits a fresh copy of the signal it receives, +by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since +this is a digital component, it may have firmware. + + +# Driver Usage + +Some operating systems may have the ability to update firmware on USB4 retimers, +and ultimately will need some way to power the device on and off so that its new +firmware can be loaded. This is achieved by providing a GPIO signal that can be +used for this purpose; its active state must be the one in which power is +applied to the retimer. This driver will generate the required ACPI AML code +which will toggle the GPIO in response to the kernel's request (through the +`_DSM` ACPI method). Simply put something like the following in your devicetree: + +``` +device pci 0.0 on + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A0)" + device generic 0 on end + end +end +``` + +replacing the GPIO with the appropriate pin and polarity. + diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md new file mode 100644 index 0000000000..cb79b8b6b8 --- /dev/null +++ b/Documentation/drivers/smmstorev2.md @@ -0,0 +1,221 @@ +# SMM based flash storage driver Version 2 + +This documents the API exposed by the x86 system management based +storage driver. + +## SMMSTOREv2 + +SMMSTOREv2 is a [SMM] mediated driver to read from, write to and erase +a predefined region in flash. It can be enabled by setting +`CONFIG_SMMSTORE=y` and `CONFIG_SMMSTORE_V2=y` in menuconfig. + +This can be used by the OS or the payload to implement persistent +storage to hold for instance configuration data, without needing to +implement a (platform specific) storage driver in the payload itself. + +### Storage size and alignment + +SMMSTORE version 2 requires a minimum alignment of 64 KiB, which should +be supported by all flash chips. Not having to perform read-modify-write +operations is desired, as it reduces complexity and potential for bugs. + +This can be used by a FTW (FaultTolerantWrite) implementation that uses +at least two regions in an A/B update scheme. The FTW implementation in +EDK2 uses three different regions in the store: + +- The variable store +- The FTW spare block +- The FTW working block + +All regions must be block-aligned, and the FTW spare size must be larger +than that of the variable store. FTW working block can be much smaller. +With 64 KiB as block size, the minimum size of the FTW-enabled store is: + +- The variable store: 1 block = 64 KiB +- The FTW spare block: 2 blocks = 2 * 64 KiB +- The FTW working block: 1 block = 64 KiB + +Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB. + +## API + +The API provides read and write access to an unformatted block storage. + +### Storage region + +By default SMMSTOREv2 will operate on a separate FMAP region called +`SMMSTORE`. The default generated FMAP will include such a region. On +systems with a locked FMAP, e.g. in an existing vboot setup with a +locked RO region, the option exists to add a cbfsfile called `smm_store` +in the `RW_LEGACY` (if CHROMEOS) or in the `COREBOOT` FMAP regions. It +is recommended for new builds using a handcrafted FMD that intend to +make use of SMMSTORE to include a sufficiently large `SMMSTORE` FMAP +region. It is mandatory to align the `SMMSTORE` region to 64KiB for +compatibility with the largest flash erase operation. + +When a default generated FMAP is used, the size of the FMAP region is +equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least 64 KiB. +To support a fault tolerant write mechanism, at least a multiple of +this size is recommended. + +### Communication buffer + +To prevent malicious ring0 code to access arbitrary memory locations, +SMMSTOREv2 uses a communication buffer in CBMEM/HOB for all transfers. +This buffer has to be at least 64 KiB in size and must be installed +before calling any of the SMMSTORE read or write operations. Usually, +coreboot will install this buffer to transfer data between ring0 and +the [SMM] handler. + +In order to get the communication buffer address, the payload or OS +has to read the coreboot table with tag `0x0039`, containing: + +```C +struct lb_smmstorev2 { + uint32_t tag; + uint32_t size; + uint32_t num_blocks; /* Number of writeable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in byte */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ +}; +``` + +The absence of this coreboot table entry indicates that there's no +SMMSTOREv2 support. + +### Blocks + +The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks +called *blocks*. Every block is at least the size of 64KiB to support +arbitrary NOR flash erase ops. A payload or OS must make no further +assumptions about the block or communication buffer size. + +### Generating the SMI + +SMMSTOREv2 is called via an SMI, which is generated via a write to the +IO port defined in the smi_cmd entry of the FADT ACPI table. `%al` +contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO +port. `%ah` contains the SMMSTOREv2 command. `%ebx` contains the +parameter buffer to the SMMSTOREv2 command. + +### Return values + +If a command succeeds, SMMSTOREv2 will return with +`SMMSTORE_RET_SUCCESS=0` in `%eax`. On failure SMMSTORE will return +`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands +`SMMSTORE_REG_UNSUPPORTED=2` is returned. + +**NOTE 1**: The caller **must** check the return value and should make +no assumption on the returned data if `%eax` does not contain +`SMMSTORE_RET_SUCCESS`. + +**NOTE 2**: If the SMI returns without changing `%ax`, it can be assumed +that the SMMSTOREv2 feature is not installed. + +### Calling arguments + +SMMSTOREv2 supports 3 subcommands that are passed via `%ah`, the +additional calling arguments are passed via `%ebx`. + +**NOTE**: The size of the struct entries are in the native word size of +smihandler. This means 32 bits in almost all cases. + +#### - SMMSTORE_CMD_INIT = 4 + +This installs the communication buffer to use and thus enables the +SMMSTORE handler. This command can only be executed once and is done +by the firmware. Calling this function at runtime has no effect. + +The additional parameter buffer `%ebx` contains a pointer to the +following struct: + +```C +struct smmstore_params_init { + uint32_t com_buffer; + uint32_t com_buffer_size; +} __packed; +``` + +INPUT: +- `com_buffer`: Physical address of the communication buffer (CBMEM) +- `com_buffer_size`: Size in bytes of the communication buffer + +#### - SMMSTORE_CMD_RAW_READ = 5 + +SMMSTOREv2 allows reading arbitrary data. It is up to the caller to +initialize the store with meaningful data before using it. + +The additional parameter buffer `%ebx` contains a pointer to the +following struct: + +```C +struct smmstore_params_raw_read { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; +``` + +INPUT: +- `bufsize`: Size of data to read within the communication buffer +- `bufoffset`: Offset within the communication buffer +- `block_id`: Block to read from + +#### - SMMSTORE_CMD_RAW_WRITE = 6 + +SMMSTOREv2 allows writing arbitrary data. It is up to the caller to +erase a block before writing it. + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_raw_write { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; +``` + +INPUT: +- `bufsize`: Size of data to write within the communication buffer +- `bufoffset`: Offset within the communication buffer +- `block_id`: Block to write to + +#### - SMMSTORE_CMD_RAW_CLEAR = 7 + +SMMSTOREv2 allows clearing blocks. A cleared block will read as `0xff`. +By providing multiple blocks the caller can implement a fault tolerant +write mechanism. It is up to the caller to clear blocks before writing +to them. + + +```C +struct smmstore_params_raw_clear { + uint32_t block_id; +} __packed; +``` + +INPUT: +- `block_id`: Block to erase + +#### Security + +Pointers provided by the payload or OS are checked to not overlap with +SMM. This protects the SMM handler from being compromised. + +As all information is exchanged using the communication buffer and +coreboot tables, there's no risk that a malicious application capable +of issuing SMIs could extract arbitrary data or modify the currently +running kernel. + +## External links + +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf) +Note that this differs significantly from coreboot's implementation. + +[SMM]: ../security/smm.md diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 59f675a2ff..4547f919ce 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -43,15 +43,42 @@ employer is aware and you are authorized to submit the code. For clarification, see the Developer's Certificate of Origin in the coreboot [Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). -* Let non-trivial patches sit in a review state for at least 24 hours -before submission. Remember that there are coreboot developers in timezones -all over the world, and everyone should have a chance to contribute. -Trivial patches would be things like whitespace changes or spelling fixes, -in general those that don’t impact the final binary output. The -24-hour period would start at submission, and would be restarted at any -update which significantly changes any part of the patch. Patches can be -'Fast-tracked' and submitted in under 24 hours with the agreement of at -least 3 +2 votes. +* In general, patches should remain open for review for at least 24 hours +since the last significant modification to the change. The purpose is to +let coreboot developers around the world have a chance to review. Complex +reworks, even if they don't change the purpose of the patch but the way +it's implemented, should restart the wait period. + +* A change can go in without the wait period if its purpose is to fix +a recently-introduced issue (build, boot or OS-level compatibility, not +necessarily identified by coreboot.org facilities). Its commit message +has to explain what change introduced the problem and the nature of +the problem so that the emergency need becomes apparent. The change +itself should be as limited in scope and impact as possible to make it +simple to assess the impact. Such a change can be merged early with 3 +Code-Review+2. For emergency fixes that affect a single project (SoC, +mainboard, ...) it's _strongly_ recommended to get a review by somebody +not involved with that project to ensure that the documentation of the +issue is clear enough. + +* Trivial changes that deal with minor issues like inconsistencies in +whitespace or spelling fixes that don't impact the final binary output +also don't need to wait. Such changes should point out in their commit +messages how the the author verified that the binary output is identical +(e.g. a TIMELESS build for a given configuration). When submitting +such changes early, the submitter must be different from the author +and must document the intent in the Gerrit discussion, e.g. "landed the +change early because it's trivial". Note that trivial fixes shouldn't +necessarily be expedited: Just like they're not critical enough for +things to go wrong because of them, they're not critical enough to +require quick handling. This exception merely serves to acknowledge that +a round-the-world review just isn't necessary for some types of changes. + +* As explained in our Code of Conduct, we try to assume the best of each +other in this community. It's okay to discuss mistakes (e.g. isolated +instances of non-trivial and non-critical changes submitted early) but +try to keep such inquiries blameless. If a change leads to problems with +our code, the focus should be on fixing the issue, not on assigning blame. * Do not +2 patches that you authored or own, even for something as trivial as whitespace fixes. When working on your own patches, it’s easy to diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 81a06eb410..13aeed5bd2 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -88,11 +88,6 @@ configurations together into a set of macros, e.g., ```C /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) - /* - * Set native function with RX Level/Edge configuration and disable - * input/output buffer if necessary - */ - #define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) /* General purpose output, with termination specified */ diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index ecdfe62d4a..037371bd34 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -52,7 +52,7 @@ command line. not have an answer yet, it stops and queries the user for the desired value. - olddefconfig - Generates a config, using the default value for any symbols not listed in the .config file. -- savedefconfig - Creates a ‘mini-config’ file, stripping out all of the symbols +- savedefconfig - Creates a ‘defconfig’ file, stripping out all of the symbols that were left as default values. This is very useful for debugging, and is how config files should be saved. - silentoldconfig - This evaluates the .config file the same way that the @@ -398,6 +398,8 @@ default <expr> \[if <expr>\] - If there is no 'default' entry for a symbol, it gets set to 'n', 0, 0x0, or “” depending on the type, however the 'bool' type is the only type that should be left without a default value. +- If possible, the declaration should happen before all default entries to make + it visible in Kconfig tools like menuconfig. -------------------------------------------------------------------------------- diff --git a/Documentation/index.md b/Documentation/index.md index a7c4869db2..fd1ecb1639 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -166,6 +166,7 @@ Contents: * [Project Ideas](contributing/project_ideas.md) * [Documentation Ideas](contributing/documentation_ideas.md) * [Code of Conduct](community/code_of_conduct.md) +* [Language style](community/language_style.md) * [Community forums](community/forums.md) * [Project services](community/services.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md index 63a56dcd7b..dcf1bb4e95 100644 --- a/Documentation/lib/fw_config.md +++ b/Documentation/lib/fw_config.md @@ -73,18 +73,18 @@ return true. ## Firmware Configuration Value -The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime +The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime but could also be defined at compile time if needed. There are two supported sources for providing this information to coreboot. ### CBFS -The value can be provided with a 32bit raw value in CBFS that is read by coreboot. The value +The value can be provided with a 64-bit raw value in CBFS that is read by coreboot. The value can be set at build time but also adjusted in an existing image with `cbfstool`. To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a -raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. +raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified file in CBFS use the value it contains when matching fields and options. @@ -291,8 +291,8 @@ field and option to check. struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; ``` diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index c6ccc7b868..ef5e892c36 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -5,6 +5,7 @@ ## Supported architectures +* aarch32 * aarch64 * riscv @@ -26,6 +27,13 @@ The section must be named in order to be found by the FIT parser: The FIT parser needs architecure support. +### aarch32 +The source code can be found in `src/arch/arm/fit_payload.c`. + +On aarch32 the kernel (a section named 'kernel') must be in **Image** +format and it needs a devicetree (a section named 'fdt') to boot. +The kernel will be placed close to "*DRAMSTART*". + ### aarch64 The source code can be found in `src/arch/arm64/fit_payload.c`. diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md new file mode 100644 index 0000000000..77615313e0 --- /dev/null +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -0,0 +1,170 @@ +# ASUS A88XM-E + +This page describes how to run coreboot on the [ASUS A88XM-E]. + +## Technology + +Both "Trinity" and "Richland" FM2 desktop processing units are working, +the CPU architecture in these CPUs/APUs are [Piledriver], +and their GPU is [TeraScale 3] (VLIW4-based). + +Kaveri is non-working at the moment (FM2+), +the CPU architecture in these CPUs/APUs are [Steamroller], +and their GPU is [Sea Islands] (GCN2-based). + +A10 Richland is recommended for the best performance and working IOMMU. + +```eval_rst ++------------------+--------------------------------------------------+ +| A88XM-E | | ++------------------+--------------------------------------------------+ +| DDR voltage IC | Nuvoton 3101S | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111G | ++------------------+--------------------------------------------------+ +| Northbridge | Integrated into CPU with IMC and GPU (APUs only) | ++------------------+--------------------------------------------------+ +| Southbridge | Bolton-D4 | ++------------------+--------------------------------------------------+ +| Sound IC | Realtek ALC887 | ++------------------+--------------------------------------------------+ +| Super I/O | ITE IT8603E | ++------------------+--------------------------------------------------+ +| VRM controller | DIGI VRM ASP1206 | ++------------------+--------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | [GD25Q64] | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | yes | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom], if the +AmdSpiRomProtect modules have been deleted in the factory image previously. + +### External flashing + +Using a PLCC Extractor or any other appropriate tool, carefully remove the +DIP-8 BIOS chip from its' socket while avoiding the bent pins, if possible. +To flash it, use a [flashrom]-supported USB CH341A programmer - preferably with a +green PCB - and double check that it's giving a 3.3V voltage on the socket pins. + +## Integrated graphics + +### Retrieve the VGA optionrom ("Retrieval via Linux kernel" method) + +Make sure a proprietary UEFI is flashed and boot Linux with iomem=relaxed flag. +Some Linux drivers (e.g. radeon for AMD) make option ROMs like the video blob +available to user space via sysfs. To use that to get the blob you need to +enable it first. To that end you need to determine the path within /sys +corresponding to your graphics chip. It looks like this: + + # /sys/devices/pci:/::./rom. + +You can get the respective information with lspci, for example: + + # lspci -tv + # -[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Family 16h Processor Root Complex + # +-01.0 Advanced Micro Devices, Inc. [AMD/ATI] Kabini [Radeon HD 8210] + # ... + +Here the the needed bits (for the ROM of the Kabini device) are: + + # PCI domain: (almost always) 0000 + # PCI bus: (also very commonly) 00 + # PCI slot: 01 (logical slot; different from any physical slots) + # PCI function: 0 (a PCI device might have multiple functions... shouldn't matter here) + +To enable reading of the ROM you need to write 1 to the respective file, e.g.: + + # echo 1 > /sys/devices/pci0000:00/0000:00:01.0/rom + +The same file should then contain the video blob and it should be possible to simply copy it, e.g.: + + # cp /sys/devices/pci0000:00/0000:00:01.0/rom vgabios.bin + +romheaders should print reasonable output for this file. + +This version is usable for all the GPUs. + 1002,9901 Trinity (Radeon HD 7660D) + 1002,9904 Trinity (Radeon HD 7560D) + 1002,990c Richland (Radeon HD 8670D) + 1002,990e Richland (Radeon HD 8570D) + 1002,9991 Trinity (Radeon HD 7540D) + 1002,9993 Trinity (Radeon HD 7480D) + 1002,9996 Richland (Radeon HD 8470D) + 1002,9998 Richland (Radeon HD 8370D) + 1002,999d Richland (Radeon HD 8550D) + 1002,130f Kaveri (Radeon R7) + +## Known issues + +- AHCI hot-plug +- S3 resume (sometimes) +- Windows 7 can't boot because of the incomplete ACPI implementation +- XHCI + +### XHCI ports can break after using any of the blobs, restarting the +board with factory image makes it work again as fallback. +Tested even with/without the Bolton and Hudson blobs. + +## Untested + +- audio over HDMI + +## TODOs + +- one ATOMBIOS module for all the integrated GPUs +- manage to work with Kaveri/Godavary (they are using a binaryPI) +- IRQ routing is done incorrect way - common problem of fam15h boards + +## Working + +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Gigabit Ethernet +- Hardware monitoring +- Integrated graphics +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard mouse (during payload, bootloader) +- SATA +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) +- IOMMU + +## Extra resources + +- [Board manual] + +[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/ +[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf +[flashrom]: https://flashrom.org/Flashrom +[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf +[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines +[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation +[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture) +[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md new file mode 100644 index 0000000000..326756199b --- /dev/null +++ b/Documentation/mainboard/clevo/n130wu/index.md @@ -0,0 +1,47 @@ +# Clevo N130WU + +## Hardware +### Technology +```eval_rst ++------------------+--------------------------------+ +| CPU | Intel i7-8550U | ++------------------+--------------------------------+ +| PCH | Intel Sunrise Point LP | ++------------------+--------------------------------+ +| EC / Super IO | ITE IT8587E | ++------------------+--------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------+ +``` + +### Flash chip +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Model | GD25Q64B | ++---------------------+-----------------+ +| Socketed flash | no | ++---------------------+-----------------+ +| Size | 8 MiB | ++---------------------+-----------------+ +| In circuit flashing | Yes | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Write protection | No | ++---------------------+-----------------+ +| Dual BIOS feature | No | ++---------------------+-----------------+ +| Internal flashing | Yes | ++---------------------+-----------------+ +``` + +## Board status +### Working +### Not Working +### Work in progress +### Untested + +## Also known as +* TUXEDO InfinityBook Pro 13 v3 diff --git a/Documentation/mainboard/emulation/qemu-i440fx.md b/Documentation/mainboard/emulation/qemu-i440fx.md new file mode 100644 index 0000000000..059ad123c5 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-i440fx.md @@ -0,0 +1,64 @@ +# qemu i440fx mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-i440fx mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot + +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M pc +``` + +### To run the experimental x86_64 version of coreboot +Running on qemu-system-x86_64 allows to run a 32 bit or 64 bit operating system, +as well as firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc -accel kvm -cpu host +``` diff --git a/Documentation/mainboard/emulation/qemu-q35.md b/Documentation/mainboard/emulation/qemu-q35.md new file mode 100644 index 0000000000..00163e89fc --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-q35.md @@ -0,0 +1,64 @@ +# qemu q35 mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-q35 mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M q35 +``` + +### To run the experimental x86_64 version of coreboot +Running on `qemu-system-x86_64` allows to run a 32 bit or 64 bit operating system +and firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 -accel kvm -cpu host +``` + diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index cdd32089e6..022a4e5ef1 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the Facebook Monolith. -Please note: the coreboot implementation for this boards is in its +Please note: the coreboot implementation for this board is in its Beta state and isn't fully tested yet. ## Required blobs @@ -104,7 +104,7 @@ solution. Wires need to be connected to be able to flash using an external progr - SMBus - Initialization with FSP - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) -- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) +- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629) - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7) - eMMC diff --git a/Documentation/mainboard/hp/2560p.md b/Documentation/mainboard/hp/2560p.md new file mode 100644 index 0000000000..0b51a89e38 --- /dev/null +++ b/Documentation/mainboard/hp/2560p.md @@ -0,0 +1,99 @@ +# HP EliteBook 2560p + +This page is about the notebook [HP EliteBook 2560p]. + +## Release status + +HP EliteBook 2560p was released in 2011 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: +1. EC firmware +2. Intel ME firmware + +EC firmware can be retrieved from the HP firmware update image, or the firmware +backup of the laptop. EC Firmware is part of the coreboot build process. +The guide on extracting EC firmware and using it to build coreboot is in +document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops). + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +## Programming + +The flash chip is located between the memory slots and the PCH, +covered by the base enclosure, which needs to be removed according to +the [Maintenance and Service Guide] to access the flash chip. An SPI +flash programmer using 3.3V voltage such as a ch341a programmer, and +an SOIC-8 clip can be used to read and flash the chip in-circuit. + +Pin 1 of the flash chip is at the side near the PCH. + +![Flash Chip in 2560p](2560p_flash.webp) + +For more details have a look at the general [flashing tutorial]. + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the back +bottom USB port. + +Schematic of this laptop can be found on [Lab One]. + +## Test status + +### Known issues + +- GRUB payload freezes if at_keyboard module is in the GRUB image + ([bug #141]) + +### Untested + +- Optical Drive +- VGA +- Fingerprint Reader +- Modem + +### Working + +- Integrated graphics init with libgfxinit +- SATA +- Audio: speaker and microphone +- Ethernet +- WLAN +- WWAN +- Bluetooth +- ExpressCard +- SD Card Reader +- SmartCard Reader +- eSATA +- USB +- DisplayPort +- Keyboard, touchpad and trackpoint +- EC ACPI support and thermal control +- Dock: all USB ports, DisplayPort, eSATA +- TPM +- Internal flashing when IFD is unlocked +- Using `me_cleaner` + + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Sandy/Ivy Bridge (FCPGA988) | ++------------------+--------------------------------------------------+ +| PCH | Intel Cougar Point QM67 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618 +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/ +[bug #141]: https://ticket.coreboot.org/issues/141 diff --git a/Documentation/mainboard/hp/2560p_flash.webp b/Documentation/mainboard/hp/2560p_flash.webp new file mode 100644 index 0000000000..8583fa0845 Binary files /dev/null and b/Documentation/mainboard/hp/2560p_flash.webp differ diff --git a/Documentation/mainboard/hp/folio_9480m.md b/Documentation/mainboard/hp/folio_9480m.md new file mode 100644 index 0000000000..20eed08a66 --- /dev/null +++ b/Documentation/mainboard/hp/folio_9480m.md @@ -0,0 +1,156 @@ +# HP EliteBook Folio 9480m + +This page is about the notebook [HP EliteBook Folio 9480m]. + +## Release status + +HP EliteBook Folio 9480m was released in 2014 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +![Two flash chips of HP EliteBook Folio 9480m](folio_9480m_flash.webp) + +HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + +To access the system flash, we need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 development board is tested to work. + +To access the private flash chip, we can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +Before flashing coreboot, we need to do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we'll not use or override + the protected bootblock and PEI region, as well as the EC firmware + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p --erase + +To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is: + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00ffffff bios + +The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the +BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data +region pd is the region protected by HP Sure Start): + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00bfffff bios + 00eb5000:00ffffff pd + +Write the above layout in a file, and use ifdtool to modify the IFD of a flash image. +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p --ifd -i bios -w build/coreboot.rom + +After coreboot is installed, the coreboot firmware can be updated with internal flashing: + + flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Known issues + +- GRUB payload freezes just like previous EliteBook laptops +- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system +- Sometimes all the USB devices can not be found in the OS after S3 resume + +### Untested + +- Fingerprint reader +- Smart Card reader + +### Working + +- i5-4310U CPU with 4G+4G memory +- SATA and M.2 SATA disk +- Ethernet +- WLAN +- WWAN +- SD card reader +- USB +- Keyboard and touchpad +- DisplayPort +- VGA +- Dock +- Audio output from speaker and headphone jack +- Webcam +- TPM +- EC ACPI +- S3 resume +- Arch Linux with Linux 5.8.9 +- Memory initialization with mrc.bin version 1.6.1 Build 2 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS, Tianocore +- EC firmware + - KBC Revision 92.15 from OEM firmware version 01.33 + - KBC Revision 92.17 from OEM firmware version 01.50 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926 +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980 +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/folio_9480m_flash.webp b/Documentation/mainboard/hp/folio_9480m_flash.webp new file mode 100644 index 0000000000..1abc306517 Binary files /dev/null and b/Documentation/mainboard/hp/folio_9480m_flash.webp differ diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md new file mode 100644 index 0000000000..a07d9d02c7 --- /dev/null +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -0,0 +1,60 @@ +# HP Sure Start + +According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset +and processor independent firmware intrusion detection and automatic repair system. +It is implemented in HP notebooks since 2013, and desktops since 2015. + +This document talks about some mechanism of HP Sure Start on some machines, and +the method to bypass it. + +## Laptops with SMSC MEC1322 embedded controller + +Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller. +The EC firmware implements HP Sure Start. + +A Haswell EliteBook has two flash chips. According to the strings in the EC firmware, +the 16MiB flash chip that stores the BIOS firmware is called the *system flash*, and +the 2MiB flash chip that stores part of the system flash content is called the +*private flash*. A Haswell ProBook 600 series laptop also uses MEC1322 and has similar +EC firmware, but the HP Sure Start functions are not enabled. + +The private flash is connected to the EC, and is not accessible by the OS. +It contains the following: + +- HP Sure Start policy header (starting with the string "POLI") +- A copy of the Intel Flash Descriptor +- A copy of the GbE firmware +- Machine Unique Data (MUD) +- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown +- A copy of the bootblock, UEFI PEI stage, and microcode + +If the IFD of the system flash does not match the hash in the private flash, for example, +modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD. + +If the content of the private flash is lost, the EC firmware will still copy the IFD, +bootblock and PEI to the private flash. However, the IFD is not protected after that. + +HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash. +EC firmware reads them from an absolute address of the system flash chip, which is +hardcoded in the EC firmware. It looks like this verification is done with a digital +signature. If the PEI volume is modified, EC firmware will recover it using the copy +in the private flash. If the private flash has no valid copies of the PEI volume, and +the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking. + +## Bypassing HP Sure Start + +First search the mainboard for the flash chips. If there are two flash chips, +the smaller one may be the private flash. + +For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down +the machine, then read the flash again. If the IFD is not modified, it is likely to +be recovered from the private flash. Find the private flash and erase it, then the IFD +can be modified. + +To bypass the bootblock and PEI verification, we can modify the IFD to make the +BIOS region not overlap with the protected region. Since the EC firmware is usually +located at the high address of the flash chip (and in the protected region), +we can leave it untouched, and do not need to extract the EC firmware to put it in +the coreboot image. + +[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3a7dd31742..b55876016a 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -16,6 +16,7 @@ This section contains documentation about coreboot on specific mainboards. ## ASUS +- [A88XM-E](asus/a88xm-e.md) - [F2A85-M](asus/f2a85-m.md) - [P5Q](asus/p5q.md) - [P8H61-M LX](asus/p8h61-m_lx.md) @@ -26,6 +27,10 @@ This section contains documentation about coreboot on specific mainboards. - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Clevo + +- [N130WU / N131WU](clevo/n130wu/index.md) + ## Dell - [OptiPlex 9010 SFF](dell/optiplex_9010.md) @@ -37,6 +42,8 @@ The boards in this section are not real mainboards, but emulators. - [Spike RISC-V emulator](emulation/spike-riscv.md) - [Qemu RISC-V emulator](emulation/qemu-riscv.md) - [Qemu AArch64 emulator](emulation/qemu-aarch64.md) +- [Qemu x86 Q35](emulation/qemu-q35.md) +- [Qemu x86 PC](emulation/qemu-i440fx.md) ## Facebook @@ -59,7 +66,10 @@ The boards in this section are not real mainboards, but emulators. ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [HP Sure Start](hp/hp_sure_start.md) +- [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) +- [EliteBook Folio 9480m](hp/folio_9480m.md) ## Intel @@ -67,6 +77,10 @@ The boards in this section are not real mainboards, but emulators. - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Kontron + +- [mAL-10](kontron/mal10.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) @@ -76,15 +90,15 @@ The boards in this section are not real mainboards, but emulators. - [X2xx common](lenovo/x2xx_series.md) - [vboot](lenovo/vboot.md) -### Arrandale series - -- [T410](lenovo/t410.md) - ### GM45 series - [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md) - [X301](lenovo/x301.md) +### Arrandale series + +- [T410](lenovo/t410.md) + ### Sandy Bridge series - [T420](lenovo/t420.md) @@ -115,6 +129,7 @@ The boards in this section are not real mainboards, but emulators. ## OCP +- [Delta Lake](ocp/deltalake.md) - [Tioga Pass](ocp/tiogapass.md) ## Open Cellular @@ -135,6 +150,10 @@ The boards in this section are not real mainboards, but emulators. - [Hermes](prodrive/hermes.md) +## Purism + +- [Librem Mini](purism/librem_mini.md) + ## Protectli - [FW2B / FW4B](protectli/fw2b_fw4b.md) @@ -158,6 +177,10 @@ The boards in this section are not real mainboards, but emulators. - [Lemur Pro](system76/lemp9.md) +## Texas Instruments + +- [Beaglebone Black](ti/beaglebone-black.md) + ## UP - [Squared](up/squared/index.md) diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md new file mode 100644 index 0000000000..b2eefc3df2 --- /dev/null +++ b/Documentation/mainboard/kontron/mal10.md @@ -0,0 +1,106 @@ +# Kontron mAL10 Computer-on-Modules platform + +The Kontron [mAL10] COMe is a credit card sized Computer-on-Modules +platform based on the Intel Atom E3900 Series, Pentium and Celeron +processors. + +## Technology + +```eval_rst ++------------------+----------------------------------+ +| COMe Type | mini pin-out type 10 | ++------------------+----------------------------------+ +| SoC | Intel Atom x5-E3940 (4 core) | ++------------------+----------------------------------+ +| GPU | Intel HD Graphics 500 | ++------------------+----------------------------------+ +| Coprocessor | Intel TXE 3.0 | ++------------------+----------------------------------+ +| RAM | 8GB DDR3L | ++------------------+----------------------------------+ +| eMMC Flash | 32GB eMMC pSLC | ++------------------+----------------------------------+ +| USB3 | x2 | ++------------------+----------------------------------+ +| USB2 | x6 | ++------------------+----------------------------------+ +| SATA | x2 | ++------------------+----------------------------------+ +| LAN | Intel I210IT, I211AT | ++------------------+----------------------------------+ +| Super IO/EC | Kontron CPLD/EC | ++------------------+----------------------------------+ +| HWM | NCT7802 | ++------------------+----------------------------------+ +``` + +## Building coreboot + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.kontron_mal10 +make +``` +## Payloads +- SeaBIOS +- Tianocore +- Linux as payload + +## Flashing coreboot + +The SPI flash can be accessed internally using [flashrom]. +The following command is used to flash BIOS region. + +```bash +$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all +``` + +## Hardware Monitor + +The Nuvoton [NCT7802Y] is a hardware monitoring IC, capable of monitor critical +system parameters including power supply voltages, fan speeds, and temperatures. +The remote inputs can be connected to CPU/GPU thermal diode or any thermal diode +sensors and thermistor. + +- 6 temperature sensors; +- 5 voltage sensors; +- 3 fan speed sensors; +- 4 sets of temperature setting points. + +PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU +temperature value is taken from a thermal resistor (NTC) that is placed very +close to the CPU. + +## Known issues + +- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 + Booting with the "CorebootPayload" [crashes]. +- Tianocore outputs video through an external GPU only. + +## Untested + +- IGD/LVDS +- SDIO + +## Tested and working + +- Kontron CPLD/EC (Serial ports, I2C port) +- NCT7802 [HWM](#Hardware Monitor) +- USB2/3 +- Gigabit Ethernet ports +- eMMC +- SATA +- PCIe ports +- IGD/DP + +## TODO +- Onboard audio (codec IDT 92HD73C1X5, currently disabled) +- S3 suspend/resume + +[mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf +[flashrom]: https://flashrom.org/Flashrom +[NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-server-series/nct7802y/?__locale=en +[crashes]: https://pastebin.com/cpCfrPCL diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e87969f9..b513c97e9b 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -9,6 +9,15 @@ the chip in your machine through flashrom: Note that this does not allow you to determine whether the chip is in a SOIC-8 or a SOIC-16 package. +## Installing with ME firmware + +To install coreboot and keep ME working, you don't need to do anything special +with the flash descriptor. Only flash the `bios` region externally and don't +touch any other regions: +```console +# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios +``` + ## Installing without ME firmware ```eval_rst @@ -89,7 +98,7 @@ $ make ``` If your flash is not 8 MB, you need to change values of `flcomp_density1` and -`flreg1_limit` in the ifd-x200.set file according to following table: +`flreg1_limit` in the `ifd-x200.set` file according to following table: ```eval_rst +-----------------+-------+-------+--------+ @@ -127,15 +136,6 @@ Chipset ---> Then build coreboot and flash whole `build/coreboot.rom` to the chip. -## Installing with ME firmware - -To install coreboot and keep ME working, you don't need to do anything special -with the flash descriptor. Just flash only `bios` externally and don't touch any -other regions: -```console -# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios -``` - ## Flash layout The flash layouts of the OEM firmware are as follows: diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index 08df76fdca..f364f07784 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -30,7 +30,6 @@ the laptop able to power on. ## Known Issues -- No audio output when using a headphone - Cannot get the mainboard serial number from the mainboard: the OEM UEFI firmware gets the serial number from an "emulated EEPROM" via I/O port 0x1630/0x1634, but it's still unknown how to make it work diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index c4c3284b8f..9ef2357c0f 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -1,29 +1,33 @@ # OCP Delta Lake This page describes coreboot support status for the [OCP] (Open Compute Project) -Delta Lake server platform. +Delta Lake server platform. This page is updated following each 4-weeks +build/test/release cycle. ## Introduction OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. -Delta Lake server is a single socket Cooper Lake Scalable Processor server. +Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server. Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled. -Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners -jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative solution. +The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative +solution. This development reached EVT exit equivalent status. ## Required blobs This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP - (Mass Production) of CooperLake Scalable Processor when the FSP is mature. -- Microcode: Not yet available to the public. -- ME binary: Not yet available to the public. + (Mass Production) of CPX-SP. +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. +- ME binary: Ignition binary will be made public some time after the MP + of CPX-SP. +- ACM binaries: only required for CBnT enablement. ## Payload - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. @@ -46,6 +50,16 @@ To power off/on the host: To connect to console through SOL (Serial Over Lan): sol-util slotx +## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. + ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs. @@ -55,58 +69,81 @@ as initramfs. - Type 2 -- Baseboard Information - Type 3 -- System Enclosure or Chassis - Type 4 -- Processor Information + - Type 7 -- Cache Information - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String - - Type 13 -- BIOS Language Information - Type 16 -- Physical Memory Array + - Type 17 -- Memory Device - Type 19 -- Memory Array Mapped Address + - Type 32 -- System Boot Information + - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information - Type 127 -- End-of-Table - - BMC integration: - BMC readiness check - IPMI commands - watchdog timer - POST complete pin acknowledgement + - Check BMC version: ipmidump -device - SEL record generation +- Converged Bootguard and TXT (CBnT) + - TPM + - Bootguard profile 0T + - TXT + - SRTM (verified through tboot) + - memory secret clearance upon ungraceful shutdown - Early serial output - port 80h direct to GPIO -- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT - Skipping memory training upon subsequent reboots by using MRC cache - BMC crash dump - Error injection through ITP +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - NIC card + - All 5 data drives +- Power button +- localboot +- netboot from IPv6 +- basic memory hardware error injection/detection (SMI handler not upstreamed) +- basic PCIe hardware error injection/detection (SMI handler not upstreamed) -## Firmware configurations -[ChromeOS VPD] is used to store most of the firmware configurations. -RO_VPD region holds default values, while RW_VPD region holds customized -values. +## Stress/performance tests passed +- OS warm reboot (1000 cycles) +- DC reboot (1000 cycles) +- AC reboot (1000 cycle) +- Mprime test (6 hours) +- StressAppTest (6 hours) +- Ptugen (6 hours) -VPD variables supported are: -- firmware_version: This variable holds overall firmware version. coreboot - uses that value to populate smbios type 1 version field. +## Performance tests on par with traditional firmware +- coremark +- SpecCPU +- Linkpack +- Iperf(IPv6) +- FIO + +## Other tests passed +- Power +- Thermal ## Known issues -- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not - support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. -- VT-d is not supported. An IPS ticket is filed with Intel. -- PCIe bifuration is not supported. An IPS ticket is filed with Intel. -- ME based power capping. This is a bug in ME. An IPS ticket is filed - with Intel. -- RO_VPD region as well as other RO regions are not write protected. -- HECI is not set up correctly, so BMC is not able to get PCH and DIMM - temperature sensor readings. +- MLC (Intel Memory Latency Check) and stream performance issue +- HECI access at OS run time: + - spsInfoLinux64 command fail to return ME version + - ptugen command fail to get memory power ## Feature gaps -- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers - at the moment. -- SMBIOS: - - Type 7 -- Cache Information - - Type 17 -- Memory Device - - Type 38 -- IPMI Device Information - - Type 41 -- Onboard Devices Extended Information -- ACPI: - - DMAR -- PFR/CBnT +- flashrom command not able to update ME region +- ACPI APEI tables +- PCIe hotplug, Virtual Pin Ports +- PCIe Live Error Recovery +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core ## Technology @@ -116,7 +153,7 @@ VPD variables supported are: +------------------------+---------------------------------------------+ | BMC | Aspeed AST 2500 | +------------------------+---------------------------------------------+ -| PCH | Intel Lewisburg C621 | +| PCH | Intel Lewisburg C620 Series | +------------------------+---------------------------------------------+ ``` diff --git a/Documentation/mainboard/purism/librem_mini.jpg b/Documentation/mainboard/purism/librem_mini.jpg new file mode 100644 index 0000000000..004235d013 Binary files /dev/null and b/Documentation/mainboard/purism/librem_mini.jpg differ diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md new file mode 100644 index 0000000000..f8ee00d6d5 --- /dev/null +++ b/Documentation/mainboard/purism/librem_mini.md @@ -0,0 +1,129 @@ +# Purism Librem Mini (v1, v2) + +This page describes how to run coreboot on the [Purism Librem Mini]. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-8565U/8665U (v1) | +| | Intel Core i7-10510U (v2) | ++------------------+--------------------------------------------------+ +| PCH | Whiskey Lake / Cannon Point LP (v1) | +| | Comet Lake LP Premium (Comet Lake-U) (v2) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8528E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine (CSME 12.x) (v1) | +| | Intel Management Engine (CSME 14.x) (v2) | ++------------------+--------------------------------------------------+ +``` + +![](librem_mini.jpg) +![](librem_mini_flash.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the FSP binary (done automatically +by the coreboot build system and included into the image; Coffee Lake for v1, +Comet Lake for v2) from the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by the build +system from the `3rdparty/intel-microcode` submodule. Official Purism release +images may include newer microcode, which is instead pulled from Purism's +[purism-blobs] repository. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using FSP/GOP display init). It can +be extracted via cbfstool from the existing board firmware or pulled from +the [purism-blobs] repository. + +## Intel Management Engine + +The Librem Mini uses version 12.x (v1) or 14.x (v2) of the Intel Management +Engine (ME) / Converged Security Engine (CSE). The ME/CSE is disabled using +the High Assurance Platform (HAP) bit, which puts the ME into a disabled state +after platform bring-up (BUP) and disables all PCI/HECI interfaces. +This can be verified via the coreboot cbmem utility: + + `sudo ./cbmem -1 | grep 'ME:'` + +provided coreboot has been modified to output the ME status even when +the PCI device is not visible/active (as it is in Purism's release builds). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.2 (v1.2-107-gb1f858f or later needed +for the Mini v2). Firmware an be easily flashed with internal programmer +(either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip, +and has a diode attached to the VCC line for in-system programming. +This chip is located on the bottom side of the board under the CPU heatsink, +in line with the front USB 2.0 ports. + +One has to remove all screws (in order): + + * 2 top cover screws + * 4 screws securing the mainboard to the chassis + * 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs) + +The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to +an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip. +Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV]. + +The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV), +but is not protected by a diode and therefore cannot be read/written to without +desoldering it from the mainboard. + +## Known issues + + * SeaBIOS can be finicky with detecting USB devices + * Mode switching with VGA option ROM display init can be slow and sometimes hangs + * Some SATA devices on the 2.5" interface can have issues operating at 6 Gbps, + despite the HSIO PHY settings being set optimally via experimentation. These devices + may show errors in dmesg and drop down to 3 Gbps, but should not fail to boot. + The same issue is present on the AMI vendor firmware. + +## Working + + * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init + (no libgfxinit support yet) + * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads + * Ethernet, m.2 2230 Wi-Fi + * System firmware updates via flashrom + * PCIe NVMe + * m.2 and SATA III + * Audio via front 3.5mm jack, HDMI, and DisplayPort + * SMBus (reading SPD from DIMMs) + * Initialization with FSP 2.0 (CFL for v1, CML for v2) + * S3 Suspend/Resume + * Booting PureOS 10.x, Debian 11.x, Qubes 4.1.0-alpha1, Linux Mint 20, Windows 10 2004 + +## Not working / untested + + * ITE IT8528E Super IO functions + + +[Purism Librem Mini]: https://puri.sm/products/librem-mini/ +[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs +[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/purism/librem_mini_flash.jpg b/Documentation/mainboard/purism/librem_mini_flash.jpg new file mode 100644 index 0000000000..d1c6071f25 Binary files /dev/null and b/Documentation/mainboard/purism/librem_mini_flash.jpg differ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 2cb945ae14..03bebad0ed 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -7,6 +7,7 @@ Controller etc. ## Supported boards - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) +- [X11SSH-F](x11ssh-f/x11ssh-f.md) - [X11SSM-F](x11ssm-f/x11ssm-f.md) ## Required proprietary blobs @@ -30,14 +31,12 @@ Look at the [flashing tutorial] and the board-specific section. These issues apply to all boards. Have a look at the board-specific issues, too. -- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726) - MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0]) ## ToDo - Fix issues above - Fix issues in board specific sections -- Fix TODOs mentioned in code - Add more boards! :-) ## Technology diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md new file mode 100644 index 0000000000..f009bbe2ae --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -0,0 +1,103 @@ +# Supermicro X11SSH-F + +This section details how to run coreboot on the [Supermicro X11SSH-F]. + +## Flashing coreboot + +The board can be flashed externally. [STM32-based programmers] worked. + +The flash IC "W25Q128.V" (detected by flashrom) can be found near PCH PCIe Slot 4. It is sometime +socketed, and covered by a sticker, hindering the observation of its precise model. + +It can be programmed in-system with a clip like pomona 5250. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## IGD + +If an IGD is integrated with CPU, it will be enabled on this board. Though there is no video output +for it (The onboard VGA port is connected to BMC), it is said to be capable of being used for compute +tasks, or for offloading graphics rendering via "muxless" [vga_witcheroo]. + +## Tested and working + +- SeaBIOS payload to boot Kali Linux live USB +- ECC ram (Linux' ie31200 driver works) +- Integrated graphics device available without output +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- S3 resume not working (vendor and coreboot) +- SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled) + +## ToDo + +- Fix known issues +- Testing other payloads + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 1x 3.0 x4 (in x8) | +| | 1x 3.0 x2 (in M.2 slot with key M) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port (connector may absent) | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSH-F] +- [Board manual] + +[Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[STM32-based programmers]: https://github.com/dword1511/stm32-vserprog +[vga_switcheroo]: https://01.org/linuxgraphics/gfx-docs/drm/gpu/vga-switcheroo.html diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md index 1caa34b3f7..1616676453 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -33,10 +33,6 @@ in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This See general issue section. -## ToDo - -- Fix TODOs mentioned in code - ## Technology ```eval_rst diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md index 5213bce6de..9f18b79cd8 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md @@ -4,11 +4,11 @@ This section details how to run coreboot on the [Supermicro X11SSM-F]. ## Flashing coreboot -The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. +The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this, +one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found +near PCH PCIe Slot 4. -The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards. - -For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip. +Flashing is also possible through the BMC web interface, when a valid license was entered. ## BMC (IPMI) @@ -16,6 +16,10 @@ This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC 32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a [MX25L25635F]. +## Disabling LAN firmware + +To disable the proprietary LAN firmware, the undocumented jumper J6 can be set to 2-3. + ## Tested and working - GRUB2 payload with Debian testing and kernel 5.2 @@ -32,14 +36,9 @@ This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC ## Known issues - See general issue section -- "only partially covers this bridge" info from Linux kernel (what does that mean?) - LNXTHERM missing - S3 resume not working -## ToDo - -- Fix TODOs mentioned in code - ## Technology ```eval_rst diff --git a/Documentation/mainboard/ti/beaglebone-black.md b/Documentation/mainboard/ti/beaglebone-black.md new file mode 100644 index 0000000000..db37e28099 --- /dev/null +++ b/Documentation/mainboard/ti/beaglebone-black.md @@ -0,0 +1,131 @@ +# Beaglebone Black +This page gives some details about the [BeagleBone Black] coreboot port and +describes how to build and run it. + +The port currently only supports booting coreboot from a micro SD card and has +some other limitations listed below. + +## Supported Boards +The Beaglebone port supports the following boards: + +- Beaglebone Black +- Beaglebone Black Wireless +- Beaglebone Pocket (untested, may need tweaking) +- Beaglebone Blue (untested, may need tweaking) +- Beaglebone Original (untested, may need tweaking) + +## Use Cases +This port was primarily developed as a learning exercise and there is +potentially little reason to use it compared to the defacto bootloader choice of +U-Boot. However, it does have some interesting practical use cases compared to +U-Boot: + +1. Choosing coreboot as a lightweight alternative to U-Boot. In this case, + coreboot is used to do the absolute minimum necessary to boot Linux, forgoing + some U-Boot features and functionality. Complex boot logic can then instead + be moved into Linux where it can be more flexibly and safely executed. This + is essentially the LinuxBoot philosophy. [U-Boot Falcon mode] has similar + goals to this as well. +2. Facilitating experimenting with coreboot on real hardware. The Beaglebone + Black is widely available at a low pricepoint (~$65) making it a great way to + experiment with coreboot on real ARMv7 hardware. It also works well as a + development platform as it has exposed pads for JTAG and, due to the way it + boots, is effectively impossible to brick. +3. The Beaglebone Black is often used as a external flasher and EHCI debug + gadget in the coreboot community, so many members have access to it and can + use it as a reference platform. + +## Quickstart +1. Run `make menuconfig` and select _TI_/_Beaglebone_ in the _Mainboard_ menu. +2. Add a payload as normal. +3. Run `make`. +4. Copy the resulting `build/MLO` file to the micro SD card at offset 128k - ie + `dd if=build/MLO of=/dev/sdcard seek=1 bs=128k`. + +**NOTE**: By default, the Beaglebone is configured to try to boot first from +eMMC before booting from SD card. To ensure that the Beaglebone boots from SD, +either erase the internal eMMC or hold the _S2_ button while powering on (note +that this has to be while powering on - ie when plugging in the USB or DC barrel +jack - the boot order doesn't change on reset) to prioritize SD in the boot +order. + +## Serial Console +By default, coreboot uses UART0 as the serial console. UART0 is available +through the J1 header on both the Beaglebone Black and Beaglebone Black +Wireless. The serial runs at 3.3V and 115200 8n1. + +The pin mapping is shown below for J1. + + ```eval_rst + +----------------------------+------------+ + | Pin number | Function | + +============================+============+ + | 1 (Closest to barrel jack) | GND | + +----------------------------+------------+ + | 4 | RX | + +----------------------------+------------+ + | 5 | TX | + +----------------------------+------------+ + ``` + +## Boot Process +The AM335x contains ROM code to allow booting in a number of different +configurations. More information about the boot ROM code can be found in the +AM335x technical reference manual (_SPRUH73Q_) in the _Initialization_ section. + +This coreboot port is currently configured to boot in "SD Raw Mode" where the +boot binary, with header ("Table of Contents" in TI's nomenclature), is placed +at the offset of 0x20000 (128KB) on the SD card. The boot ROM loads the coreboot +bootblock stage into SRAM and executes it. + +The bootblock and subsequent romstage and ramstage coreboot stages expect that +the coreboot image, containing the CBFS, is located at 0x20000 on the SD card. +All stages directly read from the SD card in order to load the next stage in +sequence. + +## Clock Initialization and PMIC +To simplify the port, the TPS65217C Power Management IC (PMIC) on the Beaglebone +Black is not configured by coreboot. By default, the PMIC reset values for +VDD_MPU (1.1V) and VDD_CORE (1.8V) are within the Operating Performance Point +(OPP) for the MPU PLL configuration set by the boot ROM of 500 MHz. + +When using Linux as a payload, the kernel will appropriately scale the core +voltages for the desired MPU clock frequency as defined in the device tree. + +One significant difference because of this to the U-Boot port is that the DCDC1 +rail that powers the DDR3 RAM will be 1.5V by default. The Micron DDR3 supports +both 1.35V and 1.5V and U-Boot makes use of this by setting it to 1.35V to +conserve power. Fortunately, Linux is again able to configure this rail but it +involves adding an entry to the device tree: + + &dcdc1_reg { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + +If this port was to be extended to work with boards or SoCs with different +requirements for the MPU clock frequency or different Operating Performance +Points, then the port may need to be extended to set the core voltages and MPU +PLL within coreboot, prior to loading a payload. Extending coreboot so that it +can configure the PMIC would also be necessary if there was a requirement for +coreboot to run at a different MPU frequency than the 500 MHz set by the boot +ROM. + +# Todo +- Allow coreboot to run from the Beaglebone Black's internal eMMC. This would + require updating the `mmc.c` driver to support running from both SD and eMMC. +- Support the boot ROMs *FAT mode* so that the coreboot binary can be placed on + a FAT partition. +- Increase the MMC read speed, it currently takes ~15s to read ~20MB which is a + bit slow. To do this, it should be possible to update the MMC driver to: + - Increase the supported blocksize (currently is always set to 1) + - Support 4-bit data width (currently only supports 1-bit data width) +- Convert the while loops in the MMC driver to timeout so that coreboot does not + hang on a bad SD card or when the SD card is removed during boot. + + +[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]: +https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon \ No newline at end of file diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index a80fd85804..d777f0e38b 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -75,7 +75,8 @@ be more frequent than was needed, so we scaled it back to twice a year. - [ ] Test the release from the actual release tarballs. - [ ] Push signed Tag to repo. - [ ] Announce that the release tag is done on IRC. -- [ ] Upload release files to web server +- [ ] Upload release files to web server. +- [ ] Also extract the release notes and place them on the web server. - [ ] Upload crossgcc sources to web server. - [ ] Update download page to point to files, push to repo. - [ ] Write and publish blog post with release notes. @@ -197,16 +198,16 @@ the coreboot server, and put them in the release directory at ```` People can now see the release tarballs on the website at -https://www.coreboot.org/releases/ + -The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at https://review.coreboot.org/cgit/homepage.git/tree/downloads.html +The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at -Here is an example commit to change it: https://review.coreboot.org/#/c/19515/ +Here is an example commit to change it: ## Upload crossgcc sources Sometimes the source files for older revisions of crossgcc disappear. To deal with that we maintain a mirror at -https://www.coreboot.org/releases/crossgcc-sources/ where we host the + where we host the sources used by the crossgcc scripts that are part of coreboot releases. Run @@ -220,7 +221,7 @@ sources. Download them yourself and copy them into the crossgcc-sources directory on the server. ## After the release is complete -Post the release notes on https://blogs.coreboot.org +Post the release notes on ## Making a branch At times we will need to create a branch, generally for patch fixes. diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 2910867f78..971d438ee0 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -1,18 +1,114 @@ -Upcoming release - coreboot 4.13 +coreboot 4.13 ================================ -The 4.13 release is planned for November 2020. +coreboot 4.13 was released on November 20th, 2020. -Update this document with changes that should be in the release notes. +Since 4.12 there were 4200 new commits by over 234 developers. +Of these, about 72 contributed to coreboot for the first time. -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +Thank you to all developers who again helped made coreboot better +than ever, and a big welcome to our new contributors! + +New mainboards +-------------- + +- Acer G43T-AM3 +- AMD Cereme +- Asus A88XM-E FM2+ +- Biostar TH61-ITX +- BostenTech GBYT4 +- Clevo L140CU/L141CU +- Dell OptiPlex 9010 +- Example Min86 (fake board) +- Google Ambassador +- Google Asurada +- Google Berknip +- Google Boldar +- Google Boten +- Google Burnet +- Google Cerise +- Google Coachz +- Google Dalboz +- Google Dauntless +- Google Delbin +- Google Dirinboz +- Google Dooly +- Google Drawcia +- Google Eldrid +- Google Elemi +- Google Esche +- Google Ezkinil +- Google Faffy +- Google Fennel +- Google Genesis +- Google Hayato +- Google Lantis +- Google Lindar +- Google Madoo +- Google Magolor +- Google Metaknight +- Google Morphius +- Google Noibat +- Google Pompom +- Google Shuboz +- Google Stern +- Google Terrador +- Google Todor +- Google Trembyle +- Google Vilboz +- Google Voema +- Google Volteer2 +- Google Voxel +- Google Willow +- Google Woomax +- Google Wyvern +- HP EliteBook 2560p +- HP EliteBook Folio 9480m +- HP ProBook 6360b +- Intel Alderlake-P RVP +- Kontron COMe-bSL6 +- Lenovo ThinkPad X230s +- Open Compute Project DeltaLake +- Prodrive Hermes +- Purism Librem Mini +- Purism Librem Mini v2 +- Siemens Chili +- Supermicro X11SSH-F +- System76 lemp9 + +Removed mainboards +------------------ + +- Google Cheza +- Google DragonEgg +- Google Ripto +- Google Sushi +- Open Compute Project SonoraPass Significant changes ------------------- +### Native refcode implementation for Bay Trail + +Bay Trail no longer needs a refcode binary to function properly. The refcode +was reimplemented as coreboot code, which should be functionally equivalent. +Thus, coreboot only needs to run the MRC.bin to successfully boot Bay Trail. + +### Unusual config files to build test more code + +There's some new highly-unusual config files, whose only purpose is to coerce +Jenkins into build-testing several disabled-by-default coreboot config options. +This prevents them from silently decaying over time because of build failures. + +### Initial support for Intel Trusted eXecution Technology + +coreboot now supports enabling Intel TXT. Though it's not feature-complete yet, +the code allows successfully launching tboot, a Measured Launch Environment. It +was tested on Haswell using an Asrock B85M Pro4 mainboard with TPM 2.0 on LPC. +Though support for other platforms is still not ready, it is being worked on. +The Haswell MRC.bin needs to be patched so as to enable DPR. Given that the MRC +binary cannot be redistributed, the best long-term solution is to replace it. + ### Hidden PCI devices This new functionality takes advantage of the existing 'hidden' keyword in the @@ -39,4 +135,126 @@ attributes as per their datasheet and convert those attributes into SPD files fo the platforms. More details about the tools are added in [README.md](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/spd_tools/intel/lp4x/README.md). -### Add significant changes here +### New version of SMM loader + +A new version of the SMM loader which accommodates platforms with over 32 +CPU threads. The existing version of SMM loader uses a 64K code/data +segment and only a limited number of CPU threads can fit into one segment +(because of save state, STM, other features, etc). This loader extends beyond +the 64K segment to accommodate additional CPUs and in theory allows as many +CPU threads as possible limited only by SMRAM space and not by 64K. By default +this loader version is disabled. Please see cpu/x86/Kconfig for more info. + +### Address Sanitizer + +coreboot now has an in-built Address Sanitizer, a runtime memory debugger +designed to find out-of-bounds access and use-after-scope bugs. It is made +available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo +Lake, and Haswell in romstage. Further, it can be enabled in romstage on other +x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for +more info. + +### Initial support for x86_64 + +The x86_64 code support has been revived and enabled for QEMU. While it started +as PoC and the only supported platform is an emulator, there's interest in +enabling additional platforms. It would allow to access more than 4GiB of memory +at runtime and possibly brings optimised code for faster execution times. +It still needs changes in assembly, fixed integer to pointer conversions in C, +wrappers for blobs, support for running Option ROMs, among other things. + +### Preparations to minimize enabling PCI bus mastering + +For security reasons, bus mastering should be enabled as late as possible. In +coreboot, it's usually not necessary and payloads should only enable it for +devices they use. Since not all payloads enable bus mastering properly yet, +some Kconfig options were added as an intermediate step to give some sort of +"backwards compatibility", which allow enabling or disabling bus mastering by +groups. + +Currently available groups are: + +* PCI bridges +* Any devices + +For now, "Any devices" is enabled by default to keep the traditional behaviour, +which also includes all other options. This is currently necessary, for instance, +for libpayload-based payloads as the drivers don't enable bus mastering for PCI +bridges. + +Exceptional cases, that may still need early bus master enabling in the future, +should get their own per-reason Kconfig option. Ideally before the next release. + +### Early runtime configurability of the console log level + +Traditionally, we didn't allow the log level of the `romstage` console +to be changed at runtime (e.g. via `get_option()`). It turned out that +the technical constraints for this (no global variables in `romstage`) +vanished long ago, though. The new behaviour is to query `get_option()` +now from the second stage that uses the console on. In other words, if +the `bootblock` already enables the console, the `romstage` log level +can be changed via `get_option()`. Keeping the log level of the first +console static ensures that we can see console output even if there's +a bug in the more involved code to query options. + +### Resource allocator v4 + +A new revision of resource allocator v4 is now added to coreboot that supports +mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does +not use the topmost available window for allocation. Instead, it uses the first +window within the address space that is available and satisfies the resource request. +This allows utilization of the entire available address space and also allows +allocation above the 4G boundary. The old resource allocator v3 is still retained for +some AMD platforms that do not conform to the requirements of the allocator. + +Deprecations +------------ + +### PCI bus master configuration options + +In order to minimize the usage of PCI bus mastering, the options we introduced in +this release will be dropped in a future release again. For more details, please +see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). + +### Resource allocator v3 + +Resource allocator v3 is retained in coreboot tree because the following platforms +do not conform to the requirements of the resource allocation i.e. not all the fixed +resources of the platform are provided during the `read_resources()` operation: + +* northbridge/amd/pi/00630F01 +* northbridge/amd/pi/00730F01 +* northbridge/amd/pi/00660F01 +* northbridge/amd/agesa/family14 +* northbridge/amd/agesa/family15tn +* northbridge/amd/agesa/family16kb + +In order to have a single unified allocator in coreboot, this notice is being added +to ensure that the platforms listed above are fixed before the next release. If there +is interest in maintaining support for these platforms beyond the next release, +please ensure that the platforms are fixed to conform to the expectations of resource +allocation. + +Notes +----- + +### Intel microcode updates + +Intel microcode updates tagged *microcode-20200616* are still included in our +builds. Note, [Intel released new microcode updates] +(https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) +tagged + +1. *microcode-20201110* +2. *microcode-20201112* +3. *microcode-20201118* + +with security updates for [INTEL-SA-00381] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00381.html) +and [INTEL-SA-00389] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00389.html). + +Due to too short time for rigorous testing and bad experience with botched +microcode updates in the past, these new updates are not included. Users wanting +to use those, can apply them in the operating system, or update the submodule +pointer themselves. diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md new file mode 100644 index 0000000000..43a8d0dc0b --- /dev/null +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -0,0 +1,16 @@ +Upcoming release - coreboot 4.14 +================================ + +The 4.14 release is planned for May 2021. + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 0575e93f3b..081d1fc89c 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -13,6 +13,7 @@ Release notes for previous releases * [4.10 - July 2019](coreboot-4.10-relnotes.md) * [4.11 - November 2019](coreboot-4.11-relnotes.md) * [4.12 - May 2020](coreboot-4.12-relnotes.md) +* [4.13 - November 2020](coreboot-4.13-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -24,4 +25,4 @@ Upcoming release ---------------- Please add to the release notes as changes are added: -* [4.13 - November 2020](coreboot-4.13-relnotes.md) +* [4.14 - May 2021](coreboot-4.14-relnotes.md) diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 845c0e7109..b94901b55c 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -8,6 +8,8 @@ - Facebook Monolith ## Google +- Asurada +- Hayato - Auron_Paine (Acer C740 Chromebook) - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531)) - Buddy (Acer Chromebase 24) @@ -20,7 +22,6 @@ - Tricky (Dell Chromebox 3010) - Zako (HP Chromebox G1) - Butterfly (HP Pavilion Chromebook 14) -- Cheza - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) @@ -35,7 +36,6 @@ - Daisy (Samsung Chromebook (2012)) - Deltan - Deltaur -- DragonEgg - Drallion - Eve (Google Pixelbook) - Fizz @@ -58,9 +58,12 @@ - Rainier - Akemi - Dratini +- Duffy Legacy (32MB) - Duffy +- Faffy - Hatch - Jinlon +- Kaisa Legacy (32MB) - Kaisa - Kohaku - Kindred @@ -68,10 +71,14 @@ - Mushu - Palkia - Nightfury +- Noibat - Puff - Helios_Diskswap - Stryke -- Sushi +- Wyvern +- Dooly +- Ambassador +- Genesis - Guado (ASUS Chromebox CN62) - Jecht - Rikku (Acer Chromebox CXI2) @@ -91,6 +98,12 @@ - Juniper - Kappa - Damu +- Cerise +- Stern +- Willow +- Esche +- Burnet +- Fennel - Link (Google Chromebook Pixel (2013)) - Mistral - Nyan @@ -101,13 +114,13 @@ - Hana (Lenovo N23 Yoga Chromebook) - Parrot (Acer C7/C710 Chromebook) - Peach Pit (Samsung Chromebook 2 11\") -- Atlas +- Atlas (Google Pixelbook Go) - Poppy - Nami -- Nautilus -- Nocturne -- Rammus -- Soraka +- Nautilus (Samsung Chromebook Plus (V2 / LTE)) +- Nocturne (Google Pixel Slate) +- Rammus (Asus Chromebook C425, Flip C433, Flip C434) +- Soraka (HP Chromebook x2) - Banjo (Acer Chromebook 15 (CB3-531)) - Candy (Dell Chromebook 11 3120) - Clapper (Lenovo N20 Chromebook) @@ -139,9 +152,11 @@ - Smaug (Google Pixel C) - Storm (OnHub Router TGR1900) - Stout (Lenovo Thinkpad X131e Chromebook) -- Trogdor -- Lazor - Bubs +- Coachz +- Lazor +- Pompom +- Trogdor - Veyron_Jaq (Haier Chromebook 11) - Veyron_Jerry (Hisense Chromebook 11) - Veyron_Mighty (Haier Chromebook 11(edu)) @@ -149,11 +164,22 @@ - Veyron_Speedy (ASUS C201 Chromebook) - Veyron_Mickey (Asus Chromebit CS10) - Veyron_Rialto +- Dalboz +- Vilboz +- Ezkinil +- Morphius +- Trembyle +- Berknip +- Woomax +- Dirinboz +- Shuboz ## HP - Z220 SFF Workstation ## Intel +- Alderlake-P RVP +- Alderlake-P RVP with Chrome EC - Basking Ridge CRB - Cannonlake U LPDDR4 RVP - Cannonlake Y LPDDR4 RVP @@ -206,6 +232,7 @@ - ThinkPad X1 - ThinkPad X230 - ThinkPad X230t +- ThinkPad X230s - ThinkPad X60 / X60s / X60t ## OpenCellular @@ -226,6 +253,7 @@ ## Supermicro - X11SSH-TF - X11SSM-F +- X11SSH-F ## UP - Squared diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index 23088cd12b..fffe25b023 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -240,47 +240,12 @@ in an Integration Guide. ## APCB setup APCBs are used to provide the PSP with SPD information and optionally a set of -GPIOs to use for selecting which SPD to load. - -### Prebuilt -The picasso `Makefile` expects APCBs to be located in -`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just -add the following to your mainboard's Makefile. - -``` -# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin -APCB_SOURCES = mandolin -``` +GPIOs to use for selecting which SPD to load. A list of APCB files should be +specified in `APCB_SOURCES`. ### Generating APCBs If you have a template APCB file, the `apcb_edit` tool can be used to inject the -SPD and GPIOs used to select the correct slot. Entries should match this -pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in -`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. -The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. -If a slot is empty, the special empty keyword can be used. This will generate -an APCB with an empty SPD. - -``` -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 -``` - -#### APCB Board ID GPIO configuration. -The GPIOs determine which memory SPD will be used during boot. -``` -# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL -# GPIO_NUMBER: FCH GPIO number -# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO -# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO - -APCB_BOARD_ID_GPIO0 = 121 1 0 -APCB_BOARD_ID_GPIO1 = 120 1 0 -APCB_BOARD_ID_GPIO2 = 131 3 0 -APCB_BOARD_ID_GPIO3 = 116 1 0 -``` +SPD and GPIOs used to select the correct slot. ## Footnotes diff --git a/Documentation/soc/intel/cse_fw_update/Layout_after.svg b/Documentation/soc/intel/cse_fw_update/Layout_after.svg new file mode 100644 index 0000000000..95720db6b5 --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/Layout_after.svg @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + Page-1 + + Rectangle.116 + DESC + + DESC + + Rectangle.117 + CSE - RO + + CSE - RO + + Rectangle.118 + + + + Rectangle.119 + COREBOOT_RO + + COREBOOT_RO + + Rectangle.120 + RW_MISC + + RW_MISC + + Rectangle.121 + FW_MAIN_B + + FW_MAIN_B + + Rectangle.122 + FW_MAIN_A + + FW_MAIN_A + + Sheet.123 + 0x1FFFFFF + + 0x1FFFFFF + + Sheet.124 + 0x0 + + 0x0 + + Rectangle.125 + RW_LEGACY + + RW_LEGACY + + Right Brace.126 + + + + Sheet.127 + HW WP + + HW WP + + Right Brace.128 + + + + Sheet.129 + SPI Controller WP via descriptor + + SPI Controller WP via descriptor + + Sheet.130 + + Rectangle.423 + CSE-RW + + CSE-RW + + + Sheet.132 + + Rectangle.423 + CSE-RW + + CSE-RW + + + Rectangle.134 + CSE-RW + + CSE-RW + + Universal connector.473 + + + + Universal connector.136 + + + + Sheet.138 + CSE RW copied during an update + + CSE RW copied during an update + + Right Brace.139 + + + + Sheet.140 + GRP0 Protected + + GRP0 Protected + + diff --git a/Documentation/soc/intel/cse_fw_update/Layout_before.svg b/Documentation/soc/intel/cse_fw_update/Layout_before.svg new file mode 100644 index 0000000000..d03754880e --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/Layout_before.svg @@ -0,0 +1,95 @@ + + + + + + + + Page-1 + + Rectangle.178 + DESC + + DESC + + Rectangle.179 + CSME/PMC + + CSME/PMC + + Rectangle.180 + + + + Rectangle.181 + COREBOOT_RO + + COREBOOT_RO + + Rectangle.182 + RW_MISC + + RW_MISC + + Rectangle.183 + FW_MAIN_B + + FW_MAIN_B + + Rectangle.184 + FW_MAIN_A + + FW_MAIN_A + + Sheet.94 + 0x1FFFFFF + + 0x1FFFFFF + + Sheet.95 + 0x0 + + 0x0 + + Rectangle.106 + RW_LEGACY + + RW_LEGACY + + Right Brace.398 + + + + Sheet.96 + HW WP + + HW WP + + Right Brace.115 + + + + Sheet.97 + SPI Controller WP via descriptor + + SPI Controller WP via descriptor + + diff --git a/Documentation/soc/intel/cse_fw_update/cse_fw_update.md b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md new file mode 100644 index 0000000000..98fe310113 --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md @@ -0,0 +1,127 @@ +CSE FW update mechanism for devices in field + +## Introduction + +CSE Firmware and PMC Firmware are critical components of Intel SoCs. +CSE and PMC cooperate by providing platform services during boot and other +power transition flows. + +## Problem Statement + +Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW +versions that are released by Intel to address important functional and security +bugs post-product launch will not be available to the end-user. Hence, the proposed +solution allows in-field CSE FW update to propagate those bug fixes +to end user platforms. + +## Design Proposal + +### CSE FW design Proposal: + +Key Elements: + +- CSE FW layout is composed of two bootable partitions (RO Recovery Partition + and RW Normal Partition). + +- Boot partition selection: An API-based mechanism is used to decide from which partition + CSE will boot. + +- The HECI APIs below will be supported in this CSE FW: + + - HMRFPO_ENABLE: This command requests the CSE enter a mode in which writes to + the CSE region from the CSE are disabled. It also grants temporary write access + to the RW partition from the host (RO is still protected by GPR0). + + - GET_PARTITION_INFO: The command retrieves information for each boot partition from CSE + like version, start/end offsets of a partition within CSE region, and boot + partition status. Also, it provides below information: + - The current boot partition which was used during this boot, + - The boot partition that will be used on the next CSE reset + - The number of boot partitions available in the CSE region + + - SET_BOOT_PARTITION_INFO: This command allows the firmware to request the + CSE to boot from either its RO or RW partition at its next reset. + + - DATA_CLEAR: This command requests the CSE to reset its data partition back + to manufacturing defaults + +FW Layout, RW/RO Partitions: + +The CSE RO partition is the first in the CSE boot order, hence it will be used +out of G3. RO partition contains minimum CSE code capable to boot platform and +execute FW update of RW partition. In addition to CSE code, the RO partition also +contains PMC FW patch and other CSE-loadable platform FW components. + +RW partition contains fully operational CSE FW, PMC FW, other CSE loadable +platform FW components. + +Boot partition selection: + +CSE FW shall support 2 APIs to get boot partition info, and set boot partition +info to notify CSE to select the partition on the next boot. + +### HOST FW Design proposal: + +Key Elements: + +- Build time artifacts: + + CSE RW Version update binary - The FW shall pack CSE RW update blob and + corresponding version binary which contains version of the CSE RW blob. + +- FW Update: + + coreboot will implement the logic to compare the CSE's FW version with CBFS + CSE RW binary's version in the firmware slot (FW_MAIN_A/FW_MAIN_B) and update + the CSE RW region if there is a version mismatch. If there is no version + mismatch, firmware skips CSE FW update. + +- Handling of CSE FW Downgrade: + + coreboot will send DATA_CLEAR HECI command when there is a CSE FW downgrade. + This must be done to avoid data mismatch due to CSE FW downgrade. Further, + CSE will restore the data back to manufacturing defaults after data reset. + + +## Implementation Details + + +To enable CSE FW update flow the following changes are required in coreboot: + +* Descriptor change may be required to accommodate CSE binary. The CSE binary is tied with +a platform. So CSE size may vary from one platform to another. +* FMAP changes may be required to accommodate CSE binary and CSE RW blob in the RW CBFS region. +Please check platform specific CSE kit for CSE binary information. +* CSE Lite SKU binary and CSE RW blob +* Makefile change to pack CSE RW binaries in the CBFS +* Implementation of update flow: + - Get CSE boot partition info using GET_BOOT_PARTITION_INFO HECI command. + - Get the cbfs_me_rw.version from the currently selected RW slot. + - If the version from the above 2 locations don't match, then start CSE FW update. + - If CSE is not booting from RO, then + - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION_INFO + HECI command. + - Send GLOBAL_RESET HECI command to reset the system. + - If RW update is a CSE FW downgrade, then coreboot has to send + DATA_CLEAR command to clear run time data of CSE. + - Enable HMRFPO Mode (Host ME Region Flash Protection Override) by + sending HMRFPO_ENABLE HECI command to CSE. + - Erase and Copy the CBFS CSE RW to CSE RW partition + - Set CSE's next boot partition to RW. + - Trigger Global Reset which resets both CSE and Host. + Then system should boot with the updated CSE. + +* The resulting flash layout is shown below: + +![Flash Layout](./Layout_before.svg) ![FlashLayout](./Layout_after.svg) + + + - Typical boot flow + + - Vboot selects the RW FW (FW_MAIN_A or FW_MAIN_B) to boot. + - coreboot skips CSE FW update flow if boot mode is recovery. + - If CSE RW blob is not locatable in the CBFS, then RW Firmware skips update flow + and sends SET_BOOT_PARTITION_INFO command to switch CSE to boot from RW + and issues Global Reset if CSE is already not booting from RW partition. + - The RW firmware will compare the CSE RW version with CSE RW blob in the slot. + - If there is a mismatch, then firmware will carry out update flow as explained before. diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 5f8e279841..214733140b 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -20,11 +20,6 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel :doc:`../../../mainboard/intel/icelake_rvp` ``` -3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google - ```eval_rst - :doc:`../../../mainboard/google/dragonegg` - ``` - ### Summary: * SoC is Ice Lake. * Reference platform is icelake_rvp. diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a1d6..71e427ebef 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -8,5 +8,7 @@ This section contains documentation about coreboot on specific Intel SOCs. - [FSP](fsp/index.md) - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) +- [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) +- [CSE FW Update](cse_fw_update/cse_fw_update.md) diff --git a/Documentation/soc/intel/microcode.md b/Documentation/soc/intel/microcode.md new file mode 100644 index 0000000000..0d65b74b11 --- /dev/null +++ b/Documentation/soc/intel/microcode.md @@ -0,0 +1,136 @@ +# Microcode updates + +When booting a modern x86 platform, one task of the firmware is to update +[microcode] to correct hardware bugs and mitigate security issues found +after silicon has been shipped. The [Pentium FDIV bug] could have been +fixed with a microcode update, had the Pentium used updateable microcode. +Starting with the Pentium Pro, CPU microcode can be updated by software. + +As per BIOS Writer's Guides, Intel defines a processor as the silicon and +the accompanying microcode update, and considers any processor that does +not have its microcode updated to be running out of specification. This +suggests that microcode is a crucial ingredient for correct operation. + +On multi-processor or Hyper-Threading-enabled systems, each thread has +its own microcode. Therefore, microcode must be updated on every thread. + +## When to update microcode + +When a CPU core comes out of reset, it uses microcode from an internal +ROM. This “default” microcode often contains bugs, so it needs to be +updated as soon as possible. For example, Core 2 CPUs can boot without +microcode updates, but have stability problems. On newer platforms, +it is nearly impossible to boot without having updated the microcode. +On some platforms, an updated microcode is required in order to enable +Cache-As-RAM or to be able to successfully initialize the DRAM. + +Plus, microcode needs to be loaded multiple times. Intel Document 504790 +explains that this is because of so-called *enhanced microcode updates*, +which are large updates with errata workarounds for both core and uncore. +In order to correctly apply enhanced microcode updates, the [MP-Init] +algorithm must be decomposed into multiple initialization phases. + +### Firmware Interface Table + +Beginning with 4th generation Intel Core processors, it is possible for +microcode to be updated before the CPU is taken out of reset. This is +accomplished by means of [FIT], a data structure which contains pointers +to various firmware ingredients in the BIOS flash. + +In rare cases, FIT microcode updates may not be successful. Therefore, +it is important to check that the microcode is up-to-date and, if not, +update it. This needs to be done as early as possible, like on older +processor generations without FIT support. + +Whether all threads on a processor get their microcode updated through +FIT is not clear. According to Intel Documents 493770 and 535094, FIT +microcode updates are applied to all cores within the package. However, +Intel Document 550049 states that FIT microcode updates are applied to +all threads within the package. + +## SMM bring-up + +Prior to SMM relocation, microcode must have been updated at least once. + +## Multi-Processor bring-up + +The BWG briefly describes microcode updates as part of the *MP-Init*. + +### MP-Init + +As part of the [MP-Init] sequence, two microcode updates are required. + +* The first update must happen as soon as one AP comes out of reset. +* The second update must happen after the MP-Init sequence has written MTRRs, + PRMRR, DCU mode and prefetcher configuration, SMM has been relocated, but + before clearing the MCE banks. + +## Recommendations + +The Linux kernel developer's recommendations are: +* Serialize microcode updates if possible. +* Idle as many APs as possible while updating. +* Idle the sibling thread on a Hyper-Threading enabled CPU while updating. + +## Platform BWGs + +The requirements specified in BWGs differ between platforms: + +### Sandy Bridge + +* Before setting up Cache-As-RAM, load microcode update into the SBSP. +* Losing (non-SBSP) NBSPs must load their microcode update before being placed + back in the wait-for-SIPI state. +* Sibling threads on HT must use a semaphore. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and PRMRRs. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and PRMRRs. + +Refer to Intel Document 504790 for details. + +### Haswell/Broadwell Client + +* A microcode update must exist in FIT. +* During the race to the BSP semaphore, each NBSP must load its microcode update. +* All HT enabled threads can load microcode in parallel. However, the + IA32_BIOS_UPDT_TRIG MSR is core-scoped, just like on other platforms. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and EMRR. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and EMRR and after SMM initialization. + +Refer to Intel Document 493770 and 535094 for details. + +### Broadwell Server + +* A microcode update must exist in FIT. +* Before setting up Cache-As-RAM, load microcode update into each BSP. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and EMRR. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and EMRR and after SMM initialization. + +Refer to Intel Document 546625 for details. + +### Skylake/Kaby Lake/Coffee Lake/Whiskey Lake/Comet Lake + +* A microcode update must exist in FIT. +* Before setting up Cache-As-RAM, load microcode update into the BSP. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the first update must happen as soon as one AP comes out of reset. +* In MP-Init the second update must happen after the MP-Init sequence has + written MTRRs, PRMRR, DCU mode and prefetcher configuration, but before + clearing the MCE banks. +* Microcode updates must happen on all threads. +* Sibling threads on HT should use a semaphore. + +Refer to Intel Document 550049 for details. + +[microcode]: https://en.wikipedia.org/wiki/Microcode +[Pentium FDIV bug]: https://en.wikipedia.org/wiki/Pentium_FDIV_bug +[FIT]: fit.md +[SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf +[MP-Init]: mp_init/mp_init.md diff --git a/Documentation/technotes/asan.md b/Documentation/technotes/asan.md new file mode 100644 index 0000000000..e0d503a2a2 --- /dev/null +++ b/Documentation/technotes/asan.md @@ -0,0 +1,302 @@ +# Address Sanitizer + +Memory safety is hard to achieve. We, as humans, are bound to make mistakes in +our code. While it may be straightforward to detect memory corruption bugs in +few lines of code, it becomes quite challenging to find those bugs in a massive +code. In such cases, 'Address Sanitizer' may prove to be useful and could help +save time. + +[Address Sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) +, also known as ASan, is a runtime memory debugger designed to find +out-of-bounds accesses and use-after-scope bugs. coreboot has an in-built +Address Sanitizer. Therefore, it is advised to take advantage of this debugging +tool while working on large patches. This would further help to ensure code +quality and make runtime code more robust. + +## Types of errors detected +ASan in coreboot catches the following types of memory bugs: + +### Stack buffer overflow +Example stack-out-of-bounds: +```c +void foo() +{ + int stack_array[5] = {0}; + int i, out; + for (i = 0; i < 10; i++) + out = stack_array[i]; +} +``` +In this example, the array is of length 5 but it is being read even beyond the +index 4. + +### Global buffer overflow +Example global-out-of-bounds: +```c +char a[] = "I use coreboot"; + +void foo() +{ + char b[] = "proprietary BIOS"; + strcpy(a + 6, b); +} +``` +In this example, +> well, you are replacing coreboot with proprietary BIOS. In any case, that's +an "error". + +Let's come to the memory bug. The string 'a' is of length 14 but it is being +written to even beyond that. + +### Use after scope +Example use-after-scope: +```c +volatile int *p = 0; + +void foo() { + { + int x = 0; + p = &x; + } + *p = 5; +} +``` +In this example, the value 5 is written to an undefined address instead of the +variable 'x'. This happens because 'x' can't be accessed outside its scope. + +## Using ASan + +In order to enable ASan on a supported platform, +select `Address sanitizer support` from `General setup` menu while configuring +coreboot. + +Then build coreboot and run the image as usual. If your code contains any of the +above-mentioned memory bugs, ASan will report them in the console log as shown +below: +```text +ASan: in + of bytes at addr +``` +where, + +`bug type` is either `stack-out-of-bounds`, `global-out-of-bounds` or +`use-after-scope`, + +`ip` is the address of the last good instruction before the bad access, + +`access type` is either `Read` or `Write`, + +`access size` is the number of bytes read or written, and + +`access address` is the memory location which is accessed while the error +occurs. + +Next, you have to use `ip` to retrieve the instruction which causes the error. +Since stages in coreboot are relocated, you need to normalize `ip`. For this, +first subtract the start address of the stage from `ip`. Then, read the section +headers from `.debug` file to determine the offset of the text segment. +Add this offset to the difference you calculated earlier. Let's call the +resultant address `ip'`. + +Next, read the contents of the symbol table and search for a function having +an address closest to `ip'`. This is the function in which our memory bug is +present. Let's denote the address of this function by `ip''`. + +Finally, read the assembly contents of the object file where this function is +present. Look for the affected function. Here, the instruction which exists at +the offset `ip' - ip''` corresponds to the address `ip`. Therefore, the very +next instruction is the one which causes the error. + +To see ASan in action, let's take an example. Suppose, there is a +stack-out-of-bounds error in cbfs.c that we aren’t aware of and we want ASan +to help us detect it. +```c +int cbfs_boot_region_device(struct region_device *rdev) +{ + int array[5], i; + boot_device_init(); + + for (i = 10; i > 0; i--) + array[i] = i; + + return vboot_locate_cbfs(rdev) && + fmap_locate_area_as_rdev("COREBOOT", rdev); +} +``` +First, we enable ASan from the configuration menu as shown above. Then, we +build coreboot and run the image. + +ASan reports the following error in the console log: +```text +ASan: stack-out-of-bounds in 0x7f7432fd +Write of 4 bytes at addr 0x7f7c2ac8 +``` +Here 0x7f7432fd is `ip` i.e. the address of the last good instruction before +the bad access. First we have to normalize this address as stated above. +As per the console log, this error happened in ramstage and the stage starts +from 0x7f72c000. So, let’s look at the sections headers of ramstage from +`ramstage.debug`. +```text +$ objdump -h build/cbfs/fallback/ramstage.debug + +build/cbfs/fallback/ramstage.debug: file format elf32-i386 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00070b20 00e00000 00e00000 00001000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .ctors 0000036c 00e70b20 00e70b20 00071b20 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 .data 0001c8f4 00e70e8c 00e70e8c 00071e8c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 3 .bss 00012940 00e8d780 00e8d780 0008e780 2**7 + ALLOC + 4 .heap 00004000 00ea00c0 00ea00c0 0008e780 2**0 + ALLOC +``` +As you can see, the offset of the text segment is 0x00e00000. Let's subtract the +start address of the stage from `ip` and add this offset to the difference. The +resultant address i.e. `ip'` is 0x00e172fd. + +Next, we read the contents of the symbol table and search for a function having +an address closest to 0x00e172fd. +```text +$ nm -n build/cbfs/fallback/ramstage.debug +........ +........ +00e17116 t _GLOBAL__sub_I_65535_1_gfx_get_init_done +00e17129 t tohex16 +00e171db T cbfs_load_and_decompress +00e1729b T cbfs_boot_region_device +00e17387 T cbfs_boot_locate +00e1740d T cbfs_boot_map_with_leak +00e174ef T cbfs_boot_map_optionrom +........ +........ +``` +The symbol having an address closest to 0x00e172fd is `cbfs_boot_region_device` and +its address i.e. `ip''` is 0x00e1729b. + +Now, as we know the affected function, let's read the assembly contents of +`cbfs_boot_region_device()` which is present in `cbfs.o` to find the faulty +instruction. +```text +$ objdump -d build/ramstage/lib/cbfs.o +........ +........ + 51: e8 fc ff ff ff call 52 + 56: 83 ec 0c sub $0xc,%esp + 59: 57 push %edi + 5a: 83 ef 04 sub $0x4,%edi + 5d: e8 fc ff ff ff call 5e + 62: 83 c4 10 add $0x10,%esp + 65: 89 5f 04 mov %ebx,0x4(%edi) + 68: 4b dec %ebx + 69: 75 eb jne 56 +........ +........ +``` +Here, we look for the instruction present at the offset 62 i.e. `ip' - ip''`. +The instruction is `add $0x10,%esp` and it corresponds to +`for (i = 10; i > 0; i--)` in our code. It means the very next instruction +i.e. `mov %ebx,0x4(%edi)` is the one that causes the error. Now, as we look at +C code of `cbfs_boot_region_device()` again, we find that this instruction +corresponds to `array[i] = i`. + +Voilà! We just caught the memory bug using ASan. + +## Supported platforms +Presently, the following architectures support ASan in ramstage: +```eval_rst ++------------------+--------------------------------+ +| Architecture | Notes | ++==================+================================+ +| x86 | Support for all x86 platforms | ++------------------+--------------------------------+ +``` + +And in romstage ASan is available on the following platforms: +```eval_rst ++---------------------+-----------------------------+ +| Platform | Notes | ++=====================+=============================+ +| QEMU i440-fx | | ++---------------------+-----------------------------+ +| Intel Apollo Lake | | ++---------------------+-----------------------------+ +| Intel Haswell | | ++---------------------+-----------------------------+ +``` +Alternatively, you can use `grep` to view the list of platforms that support +ASan in romstage: + + $ git grep "select HAVE_ASAN_IN_ROMSTAGE" + +If the x86 platform you are using is not listed here, there is +still a chance that it supports ASan in romstage. + +To test it, select `HAVE_ASAN_IN_ROMSTAGE` from the Kconfig file in the +platform's dedicated directory. Then, enable ASan from the config menu as +indicated in the previous section. + +If you are able to build coreboot without any errors and boot cleanly, that +means the platform supports ASan in romstage. In that case, please upload a +patch on Gerrit selecting this config option using 'ASan' topic. Also, update +the platform name in the table. + +However, if you end up in compilation errors or the linker error saying that +the cache got full, additional steps need to be taken to enable ASan in +romstage on the platform. While compile errors could be resolved easily and +therefore ASan in romstage has a good chance to be supported, a full cache is +an indication that it is way more work or even likely impossible to enable +ASan in romstage. + +## Future work +### Heap buffer overflow +Presently, ASan doesn't detect out-of-bounds accesses for the objects defined +in heap. + +To add support for these type of memory bugs, you have to make sure that +whenever some block of memory is allocated in the heap, the surrounding areas +(redzones) are poisoned. Correspondingly, these redzones should be unpoisoned +when the memory block is de-allocated. + +### ASan on other architectures +The following points should help when adding support for ASan to other +architectures like ARM or RISC-V: + +* Enabling ASan in ramstage on other architectures should be easy. You just +have to make sure the shadow memory is initialized as early as possible when +ramstage is loaded. This can be done by making a function call to `asan_init()` +at the appropriate place. + +* For romstage, you have to find out if there is enough room in the cache to fit +the shadow memory region. For this, find the boundary linker symbols for the +region you'd want to run ASan on, excluding the hardware mapped addresses. +Then define a new linker section named `asan_shadow` of size +`(_end - _start) >> 3`, where `_start` and `_end` are the linker symbols you +found earlier. This section should be appended to the region already occupied +by the coreboot program. Now build coreboot. If you don't see any errors while +building with the current translation function, ASan can be enabled on that +platform. + +* The shadow region we currently use consumes memory equal to 1/8th of the +program memory. So, if you end up in a linker error saying that the memory got +full, you'll have to use a more compact shadow region. In that case, the +translation function could be something like +`shadow = (mem >> 7) | shadow_offset`. Since the stack buffers are protected by +the compiler, you'll also have to create a GCC patch forcing it to use the new +translation function for this particular architecture. + +* Once you are sure that the architecture supports ASan in ramstage, select +`HAVE_ASAN_IN_RAMSTAGE` from the Kconfig file of that architecture. Similarly, +if the platform supports ASan in romstage, select `HAVE_ASAN_IN_ROMSTAGE` from +the platform's dedicated Kconfig file. + +### Post-processing script +Unlike Linux, coreboot doesn't have `%pS` printk format to dereference pointer +to its symbolic name. Therefore, we normalise the pointer address manually to +determine the name of the affected function and further use it to find the +instruction which causes the error. + +A custom script can be written to automate this process. diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index 5367e69aa2..a9320fb782 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,3 +3,4 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Address Sanitizer](asan.md) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 7e3da01572..e02812b68f 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -19,9 +19,21 @@ Download, configure, and build coreboot $ cd coreboot ### Step 3 - Build the coreboot toolchain -Please note that this can take a significant amount of time. +Please note that this can take a significant amount of time. Use `CPUS=` to +specify number of `make` jobs to run in parallel. - $ make crossgcc-i386 CPUS=$(nproc) +This will list toolchain options and supported architectures: + + $ make help_toolchain + +Here are some examples: + + $ make crossgcc-i386 CPUS=$(nproc) # build i386 toolchain + $ make crossgcc-aarch64 CPUS=$(nproc) # build Aarch64 toolchain + $ make crossgcc-riscv CPUS=$(nproc) # build RISC-V toolchain + +Note that the i386 toolchain is currently used for all x86 platforms, including +x86_64. Also note that you can possibly use your system toolchain, but the results are not reproducible, and may have issues, so this is not recommended. See step 5 diff --git a/Documentation/util.md b/Documentation/util.md index 27a7c9cab9..8e03333194 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -20,7 +20,7 @@ status repository `Bash` `Go` * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C file `Python` * __cbfstool__ - * _cbfstool_ - For manipulating CBFS file `C` + * [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file `C` * _fmaptool_ - Converts plaintext fmd files into fmap blobs `C` * _rmodtool_ - Creates rmodules `C` * _ifwitool_ - For manipulating IFWI `C` diff --git a/MAINTAINERS b/MAINTAINERS index 924247edaf..7a82159919 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -137,6 +137,14 @@ Maintainers List (try to look for most precise areas first) # Mainboards ################################################################################ +AMD family 17h and 19h reference boards +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +S: Maintained +F: src/mainboard/amd/majolica/ +F: src/mainboard/amd/mandolin/ + APPLE MAINBOARDS M: Evgeny Zinoviev S: Maintained @@ -208,6 +216,14 @@ F: src/mainboard/asus/p8z77-v_lx2/ +CLEVO MAINBOARDS +M: Felix Singer +M: Michael Niewöhner +S: Supported +F: src/mainboard/clevo/ + + + FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks M: Wim Vervoorn @@ -225,19 +241,19 @@ F: src/mainboard/facebook/monolith/ GETAC P470 MAINBOARD M: Patrick Georgi S: Maintained -F: src/mainboard/getac/p470 +F: src/mainboard/getac/p470/ GIGABYTE GA-G41M-ES2L MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/gigabyte/ga-g41m-es2l +F: src/mainboard/gigabyte/ga-g41m-es2l/ GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons S: Maintained -F: src/mainboard/gigabyte/ga-h61m-series +F: src/mainboard/gigabyte/ga-h61m-series/ @@ -265,7 +281,7 @@ F: src/mainboard/google/stout/ INTEL D510MO MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/intel/d510mo +F: src/mainboard/intel/d510mo/ INTEL STRAGO MAINBOARD M: Hannah Williams @@ -274,6 +290,21 @@ F: /src/mainboard/intel/strago/ +KONTRON BSL6 MAINBOARD +M: Felix Singer +M: Nico Huber +S: Supported +F: src/mainboard/kontron/bsl6/ + +KONTRON MAL10 MAINBOARD +M: Maxim Polyakov +M: Nico Huber +M: Felix Singer +S: Supported +F: src/mainboard/kontron/mal10/ + + + LENOVO MAINBOARDS M: Alexander Couzens M: Patrick Rudolph @@ -291,7 +322,7 @@ LIBRETREND LT1000 MAINBOARD M: Piotr Król M: Michał Żygowski S: Maintained -F: src/mainboard/libretrend/lt1000 +F: src/mainboard/libretrend/lt1000/ OCP DELTALAKE MAINBOARD @@ -302,7 +333,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Supported -F: src/mainboard/ocp/deltalake +F: src/mainboard/ocp/deltalake/ OCP TIOGAPASS MAINBOARD M: Jonathan Zhang @@ -312,7 +343,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Maintained -F: src/mainboard/ocp/tiogapass +F: src/mainboard/ocp/tiogapass/ @@ -352,14 +383,14 @@ PRODRIVE HERMES MAINBOARD M: Christian Walter M: Patrick Rudolph S: Maintained -F: src/mainboard/prodrive/hermes +F: src/mainboard/prodrive/hermes/ PURISM MAINBOARDS M: Matt DeVillier S: Supported -F: src/mainboard/purism +F: src/mainboard/purism/ @@ -371,6 +402,12 @@ F: src/mainboard/samsung/stumpy/ +SIEMENS CHILI MAINBAORD +M: Felix Singer +M: Nico Huber +S: Supported +F: src/mainboard/siemens/chili/ + SIEMENS MC_xxxx MAINBOARDS M: Werner Zeh S: Maintained @@ -393,7 +430,7 @@ F: src/mainboard/supermicro/x10slm-f/ SUPERMICRO X11-LGA1151-SERIES M: Michael Niewöhner S: Maintained -F: src/mainboard/supermicro/x11-lga1151-series +F: src/mainboard/supermicro/x11-lga1151-series/ ################################################################################ # Architectures @@ -404,7 +441,6 @@ M: Julius Werner S: Supported F: src/arch/arm/ F: src/arch/arm64/ -F: src/soc/mediatek/ F: src/soc/nvidia/ F: src/soc/rockchip/ F: util/nvidia/ @@ -499,12 +535,13 @@ F: src/drivers/intel/ F: src/include/cpu/intel/ INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB +M: Suresh Bellampalli M: Vanessa Eusebio -M: David Guckian -S: Odd Fixes +M: Michal Motyl +M: Mariusz Szafranski +S: Maintained F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ -F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/ INTEL FSP 1.1 M: Lee Leahy @@ -522,6 +559,28 @@ F: src/drivers/intel/fsp2_0/ # Systems on a Chip ################################################################################ +AMD Cezanne +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +S: Maintained +F: src/soc/amd/cezanne/ + +AMD common SoC code +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +S: Maintained +F: src/soc/amd/common/ + +AMD Picasso +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +S: Maintained +F: src/soc/amd/picasso/ +F: src/vendorcode/amd/fsp/picasso/ + INTEL APOLLOLAKE_SOC M: Andrey Petrov S: Maintained @@ -532,8 +591,8 @@ M: Piotr Król M: Michał Żygowski M: Frans Hendriks S: Maintained -F: /src/soc/intel/braswell -F: /src/vendorcode/intel/fsp/fsp1_1/braswell +F: /src/soc/intel/braswell/ +F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang @@ -544,13 +603,18 @@ M: Ryback Hung < M: Bryant Ou S: Supported F: src/soc/intel/xeon_sp -F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp -F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ + +MEDIATEK SOCS +M: Hung-Te Lin +S: Supported +F: src/soc/mediatek/ ORPHANED ARM SOCS S: Orphaned F: src/cpu/armltd/ -F: src/cpu/ti/ +F: src/soc/ti/ F: src/soc/qualcomm/ F: src/soc/samsung/ F: util/exynos/ @@ -573,13 +637,13 @@ F: payloads/coreinfo/ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer M: Martin Roth -F: payloads/external +F: payloads/external/ LINUXBOOT PAYLOAD INTEGRATION M: Christian Walter M: Marcello Sylvester Bauer S: Supported -F: payloads/external/LinuxBoot +F: payloads/external/LinuxBoot/ ################################################################################ # Utilities @@ -653,6 +717,8 @@ F: src/drivers/aspeed/common/ F: src/drivers/aspeed/ast2050/ ACPI +M: Lance Zhao +S: Supported F: src/acpi/ F: src/arch/x86/acpi/ F: util/acpi/ @@ -682,8 +748,13 @@ OPTION ROM EXECUTION & X86EMU F: src/device/oprom/ CBFS -F: src/include/cbfs.h -F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +M: Julius Werner +F: src/include/cbfs* +F: src/commonlib/bsd/include/commonlib/bsd/cbfs* +F: src/commonlib/bsd/cbfs* +F: src/lib/cbfs.c + +CBFSTOOL F: util/cbfstool/ CBMEM @@ -704,7 +775,7 @@ TPM SUPPORT M: Christian Walter S: Supported F: src/drivers/*/tpm/ -F: src/security/tpm +F: src/security/tpm/ SUPERIOS & SUPERIOTOOL M: Felix Held @@ -722,7 +793,7 @@ ELTAN VENDORCODE M: Frans Hendriks M: Wim Vervoorn S: Maintained -F: src/vendorcode/eltan +F: src/vendorcode/eltan/ MISSING: TIMERS / DELAYS diff --git a/Makefile b/Makefile index 2705c66b51..ec0f95b595 100644 --- a/Makefile +++ b/Makefile @@ -8,6 +8,7 @@ src := src srck := $(top)/util/kconfig obj ?= build override obj := $(subst $(top)/,,$(abspath $(obj))) +xcompile ?= $(obj)/xcompile objutil ?= $(obj)/util objk := $(objutil)/kconfig absobj := $(abspath $(obj)) @@ -119,7 +120,7 @@ UNIT_TEST:=1 NOCOMPILE:= endif -.xcompile: util/xcompile/xcompile +$(xcompile): util/xcompile/xcompile rm -f $@ $< $(XGCCPATH) > $@.tmp \mv -f $@.tmp $@ 2> /dev/null @@ -146,15 +147,17 @@ ifneq ($(UNIT_TEST),1) include $(DOTCONFIG) endif -# in addition to the dependency below, create the file if it doesn't exist -# to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +# The toolchain requires xcompile to determine the ARCH_SUPPORTED, so we can't +# wait for make to generate the file. +$(if $(wildcard $(xcompile)),, $(shell \ + mkdir -p $(dir $(xcompile)) && \ + util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile))) --include .xcompile +include $(xcompile) ifneq ($(XCOMPILE_COMPLETE),1) -$(shell rm -f .xcompile) -$(error .xcompile deleted because it's invalid. \ +$(shell rm -f $(xcompile)) +$(error $(xcompile) deleted because it's invalid. \ Restarting the build should fix that, or explain the problem) endif @@ -440,10 +443,10 @@ doxygen_simple: doxyplatform doxygen_platform: $(obj)/project_filelist.txt echo echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)" - export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_VENDOR)/$(CONFIG_MAINBOARD_PART_NUMBER)"; \ + export DOXYGEN_OUTPUT_DIR="$$( echo $(DOXYGEN_OUTPUT_DIR)/$(call strip_quotes, $(CONFIG_MAINBOARD_VENDOR))_$(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER)) | sed 's|[^A-Za-z0-9/]|_|g' )"; \ mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \ export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \ - export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) ($(CONFIG_MAINBOARD_PART_NUMBER)) version $(KERNELVERSION)"; \ + export DOXYGEN_PLATFORM="$(call strip_quotes, $(CONFIG_MAINBOARD_DIR)) \($(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER))\) version $(KERNELVERSION)"; \ $(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform doxyclean: doxygen-clean diff --git a/Makefile.inc b/Makefile.inc index 89bb3e4239..a67b22c84d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -13,6 +13,7 @@ CONFIG_CBFS_PREFIX:=$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE)) CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE)) CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) +CONFIG_CHIPSET_DEVICETREE:=$(call strip_quotes, $(CONFIG_CHIPSET_DEVICETREE)) CONFIG_MEMLAYOUT_LD_FILE:=$(call strip_quotes, $(CONFIG_MEMLAYOUT_LD_FILE)) ####################################################################### @@ -34,7 +35,8 @@ COREBOOT_EXPORTS += KERNELVERSION # Basic component discovery MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) -COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR +CARRIER_DIR:=$(call strip_quotes,$(CONFIG_CARRIER_DIR)) +COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR CARRIER_DIR ## Final build results, which CBFSTOOL uses to create the final ## rom image file, are placed under $(objcbfs). @@ -75,14 +77,15 @@ PHONY+= clean-abuild coreboot check-style build-dirs build_complete ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi +subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) -subdirs-y += src/superio -subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) +subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*) +subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen -subdirs-y += util/futility util/marvell util/bincfg util/supermicro +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool +subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu +subdirs-y += util/ifdtool subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security @@ -181,9 +184,6 @@ decompressor-generic-ccopts += -D__DECOMPRESSOR__ bootblock-generic-ccopts += -D__BOOTBLOCK__ romstage-generic-ccopts += -D__ROMSTAGE__ ramstage-generic-ccopts += -D__RAMSTAGE__ -ifeq ($(CONFIG_TRACE),y) -ramstage-c-ccopts += -finstrument-functions -endif ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif @@ -264,12 +264,14 @@ REDUNDANT_OFFSET_REMARK = 2158 # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 +IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK) + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) -else -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) +IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING) endif +IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST)) + define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw @@ -280,6 +282,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl + echo " IASL "$(IASL_WARNINGS_LIST)" warning types were ignored!" if ! $(IASL) -d $$@ 2>&1 | grep -Eq 'ACPI (Warning|Error)'; then \ echo " IASL $$@ disassembled correctly."; \ true; \ @@ -331,9 +334,9 @@ endef # arg2: binary file cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ - printf " CC+STRIP $(@)\n"; \ + printf " CC+STRIP $(1)\n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ - $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ + $(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \ rm -f $(2).tmp) \ $(eval DEPENDENCIES += $(2).d) @@ -411,6 +414,10 @@ CPPFLAGS_common += -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler. CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" +ifeq ($(BUILD_TIMELESS),1) +CPPFLAGS_common += -D__TIMELESS__ +endif + ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL)$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y) CPPFLAGS_ramstage += -Isrc/device/oprom/include endif @@ -418,10 +425,10 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) @@ -514,7 +521,8 @@ build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ - util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \ + util/genbuild_h/genbuild_h.sh $(xcompile) \ + >$(build_h)t 2>/dev/null; \ cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t $(build_h): $$(shell $$(build_h_check)) @@ -524,6 +532,12 @@ $(build_h): $$(shell $$(build_h_check)) build-dirs $(objcbfs) $(objgenerated): mkdir -p $(objcbfs) $(objgenerated) +$(obj)/build_info: + @echo 'COREBOOT_VERSION: $(call strip_quotes,$(KERNELVERSION))' > $@.tmp + @echo 'MAINBOARD_VENDOR: $(call strip_quotes,$(CONFIG_MAINBOARD_VENDOR))' >> $@.tmp + @echo 'MAINBOARD_PART_NUMBER: $(call strip_quotes,$(CONFIG_MAINBOARD_PART_NUMBER))' >> $@.tmp + mv $@.tmp $@ + ####################################################################### # Build the tools CBFSTOOL:=$(objutil)/cbfstool/cbfstool @@ -563,15 +577,8 @@ endif BINCFG:=$(objutil)/bincfg/bincfg IFDTOOL:=$(objutil)/ifdtool/ifdtool -$(IFDTOOL): - @printf " Compile IFDTOOL\n" - +$(MAKE) -C $(top)/util/ifdtool - cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool -$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -588,19 +595,34 @@ $(obj)/config.h: $(objutil)/kconfig/conf # Creation of these is architecture and mainboard independent DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_DEVICETREE) +SCONFIG_OPTIONS := --mainboard_devtree=$(DEVICETREE_FILE) + ifneq ($(CONFIG_OVERRIDE_DEVICETREE),) - OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_DEVICETREE) +SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE_FILE) +endif +ifneq ($(CONFIG_CHIPSET_DEVICETREE),) +CHIPSET_DEVICETREE_FILE := $(src)/$(CONFIG_CHIPSET_DEVICETREE) +SCONFIG_OPTIONS += --chipset_devtree=$(CHIPSET_DEVICETREE_FILE) endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c -DEVICETREE_STATIC_H := $(obj)/static.h +SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) -$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig +DEVICETREE_STATIC_H := $(obj)/static.h +SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) + +DEVICETREE_DEVICENAMES_H := $(obj)/static_devices.h +SCONFIG_OPTIONS += --output_d=$(DEVICETREE_DEVICENAMES_H) + +DEVICETREE_FWCONFIG_H := $(obj)/static_fw_config.h +SCONFIG_OPTIONS += --output_f=$(DEVICETREE_FWCONFIG_H) + +$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) @@ -805,6 +827,10 @@ endif # cbfs-add-cmd-for-region # $(call cbfs-add-cmd-for-region,file in extract_nth format,region name) +# +# CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply +# add commands with any additional arguments for cbfstool. +# Example: --ext-win-base --ext-win-size define cbfs-add-cmd-for-region $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \ @@ -819,8 +845,8 @@ define cbfs-add-cmd-for-region -r $(2) \ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ - $(call extract_nth,7,$(1)) - + $(call extract_nth,7,$(1)) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) endef # Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a @@ -944,6 +970,25 @@ else FMAP_SMMSTORE_ENTRY := endif +ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y) +FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) +FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE)) +FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000) +FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)) +else +FMAP_SPD_CACHE_ENTRY := +endif + +ifeq ($(CONFIG_VPD),y) +FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) +FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE) +FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(FMAP_VPD_BASE) $(FMAP_VPD_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)) +else +FMAP_VPD_ENTRY := +endif + # # X86 FMAP region # @@ -1020,6 +1065,8 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ + -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ + -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp @@ -1043,6 +1090,7 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) @@ -1053,7 +1101,8 @@ ifeq ($(CONFIG_ARCH_X86),y) -t bootblock \ $(TXTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ - $(TS_OPTIONS) + $(TS_OPTIONS) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -1065,10 +1114,11 @@ else # ifeq ($(CONFIG_ARCH_X86),y) -f $@.tmp.2 \ -n "header pointer" \ -t "cbfs header" \ - -b -4 + -b -4 \ + $(CBFSTOOL_ADD_CMD_OPTIONS) rm -f $@.tmp.2 endif # ifeq ($(CONFIG_ARCH_X86),y) - $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) + $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) $(prebuild-files) true mv $@.tmp $@ else # ifneq ($(CONFIG_UPDATE_IMAGE),y) @@ -1088,74 +1138,30 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif -FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG)) - ifeq ($(CONFIG_HAVE_RAMSTAGE),y) RAMSTAGE=$(objcbfs)/ramstage.elf else RAMSTAGE= endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) +add_intermediate = \ + $(1): $(2) | $(INTERMEDIATE) \ + $(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif -ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - @printf " SeaBIOS Thread optionroms\n" - $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif +# Print final FIT table $(IFITTOOL) -f $@.tmp -D -r COREBOOT - -# Second FIT in TOP_SWAP bootblock +# Print final TS BOOTBLOCK FIT table ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) -# INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG adds a region as first ucode into the seconds bootblock -ifneq ($(FIT_ENTRY),) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif + @printf " TOP SWAP FIT table\n" $(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT - -endif - -endif # !CONFIG_UPDATE_IMAGE +endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" @@ -1220,6 +1226,10 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision revision-file := $(obj)/build.h revision-type := raw +cbfs-files-y += build_info +build_info-file := $(obj)/build_info +build_info-type := raw + BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))) cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX) bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) @@ -1241,7 +1251,7 @@ cbfs-get-segments-cmd = $(CBFSTOOL) $(obj)/coreboot.pre print -v | sed -n \ ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \ sed -n '/ $(1)$$/s/^\([0-9a-fA-F]*\) .*/0x\1/p' -check-ramstage-overlaps: $(obj)/coreboot.pre +$(call add_intermediate, check-ramstage-overlaps, $(obj)/coreboot.pre) programs=$$($(foreach file,$(check-ramstage-overlap-files), \ $(call cbfs-get-segments-cmd,$(file)) ; )) ; \ regions=$$($(foreach region,$(check-ramstage-overlap-regions), \ @@ -1267,6 +1277,4 @@ check-ramstage-overlaps: $(obj)/coreboot.pre pstart= ; pend= ; \ done -INTERMEDIATE+=check-ramstage-overlaps -PHONY+=check-ramstage-overlaps endif diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 new file mode 100644 index 0000000000..563f83ac5e --- /dev/null +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -0,0 +1,49 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + Code coverage +# + UBSAN +# + Debug options +# + SMMSTORE +# + Silicon Image SIL3114 driver +# + Genesys Logic GL9763E driver +# + EM100 support +# + SMM module loader V2 +CONFIG_COVERAGE=y +CONFIG_UBSAN=y +CONFIG_VENDOR_ASROCK=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_CONSOLE_POST=y +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_FINALIZE_USB_ROUTE_XHCI is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_SIZE=0x30000 +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_USBDEBUG=y +CONFIG_USBDEBUG_DONGLE_FTDI_FT232H=y +CONFIG_DRIVERS_SIL_3114=y +CONFIG_DRIVERS_GENESYSLOGIC_GL9763E=y +# CONFIG_SQUELCH_EARLY_SMP is not set +CONFIG_CONSOLE_SPI_FLASH=y +CONFIG_POST_DEVICE_PCI_PCIE=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_COVERAGE=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y +CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_X86_SMM_LOADER_VERSION2=y +CONFIG_EM100=y diff --git a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms new file mode 100644 index 0000000000..856701fee8 --- /dev/null +++ b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms @@ -0,0 +1,10 @@ +# Known-working configuration to boot with TXT enabled. Since BIOS +# and SINIT ACM blobs are missing, use something else as placeholder. +# Used ACMs were extracted from a Supermicro X10SLH firmware update. +CONFIG_VENDOR_ASROCK=y +CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_USER_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_LOGGING=y diff --git a/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 new file mode 100644 index 0000000000..167909da0d --- /dev/null +++ b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 @@ -0,0 +1,38 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + PCIe hotplug +# + Fatal assertions +# + Debug options +# + SMMSTORE +# + YABEL +# + VESA framebuffer +# + EM100 support +CONFIG_VENDOR_ASUS=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_ASUS_P8Z77_V_LX2=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y +CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF=y +CONFIG_VGA_ROM_RUN=y +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_SMMSTORE=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_RAM_SETUP=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y +CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_EM100=y diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index 011f16356c..e39ff590fd 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -4,6 +4,5 @@ CONFIG_FATAL_ASSERTS=y CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_PIRQ=y CONFIG_DEBUG_MALLOC=y -CONFIG_TRACE=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 new file mode 100644 index 0000000000..0ddb3f1339 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -0,0 +1 @@ +CONFIG_CPU_QEMU_X86_64=y diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi new file mode 100644 index 0000000000..09dfbe35cf --- /dev/null +++ b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi @@ -0,0 +1,41 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + SMMSTORE +# + OXPCIE support +# + FSP MP init +# + EM100Pro SPI console +# + Debug options +CONFIG_VENDOR_PORTWELL=y +CONFIG_CONSOLE_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_ENABLE_BUILTIN_COM1=y +CONFIG_ONBOARD_MEM_KINGSTON=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y +CONFIG_SOC_INTEL_DEBUG_CONSENT=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_SOFTWARE_I2C=y +CONFIG_SMMSTORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_UART_OXPCIE=y +CONFIG_DRIVERS_GENESYSLOGIC_GL9755=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DISPLAY_VBT=y +CONFIG_DISPLAY_FSP_ENTRY_POINTS=y +CONFIG_DISPLAY_UPD_DATA=y +CONFIG_EM100PRO_SPI_CONSOLE=y +CONFIG_DISPLAY_MTRRS=y +CONFIG_GDB_STUB=y +CONFIG_GDB_WAIT=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_REALMODE_DEBUG=y +CONFIG_DEBUG_BOOT_STATE=y diff --git a/configs/config.purism_librem15_v4.txt_build_test b/configs/config.purism_librem15_v4.txt_build_test new file mode 100644 index 0000000000..f2de8bc59f --- /dev/null +++ b/configs/config.purism_librem15_v4.txt_build_test @@ -0,0 +1,8 @@ +# Not meant for actual use. Exercises Intel TXT code. Since BIOS +# and SINIT ACM blobs are missing, use something else as placeholder. +CONFIG_VENDOR_PURISM=y +CONFIG_BOARD_PURISM_LIBREM15_V4=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_LOGGING=y diff --git a/configs/config.stm b/configs/config.purism_librem15_v4_stm similarity index 100% rename from configs/config.stm rename to configs/config.purism_librem15_v4_stm diff --git a/configs/config.scaleway_tagada b/configs/config.scaleway_tagada new file mode 100644 index 0000000000..eaa428831b --- /dev/null +++ b/configs/config.scaleway_tagada @@ -0,0 +1,15 @@ +CONFIG_VENDOR_SCALEWAY=y +CONFIG_BOARD_SCALEWAY_TAGADA=y +CONFIG_CBFS_SIZE=0x400000 +CONFIG_CONSOLE_POST=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_IQAT_ENABLE is not set +CONFIG_LEGACY_UART_MODE=y +CONFIG_USE_DENVERTON_NS_FSP_CAR=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd" +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_BOOT_STATE=y diff --git a/payloads/Kconfig b/payloads/Kconfig index cfb28d6e81..627bb95c9c 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_ELF config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -97,7 +97,7 @@ config PAYLOAD_FIT_SUPPORT bool "FIT support" default n default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. diff --git a/payloads/coreinfo/.gitignore b/payloads/coreinfo/.gitignore new file mode 100644 index 0000000000..101045e012 --- /dev/null +++ b/payloads/coreinfo/.gitignore @@ -0,0 +1,2 @@ +lpbuild/ +lp.config* diff --git a/payloads/coreinfo/AUTHORS b/payloads/coreinfo/AUTHORS new file mode 100644 index 0000000000..772018081d --- /dev/null +++ b/payloads/coreinfo/AUTHORS @@ -0,0 +1,14 @@ +# This is the list of coreinfo authors for copyright purposes. +# +# This does not necessarily list everyone who has contributed code, since in +# some cases, their employer may be the copyright holder. To see the full list +# of contributors, and their email addresses, see the revision history in source +# control. +# Run the below commands in the coreinfo repo for additional information. +# To see a list of contributors: git log --pretty=format:%an | sort | uniq +# For patches adding or removing a name: git log -i -S "NAME" --source --all + +Advanced Micro Devices, Inc. +Dave Jones +Jordan Crouse +Uwe Hermann diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index 3b69c0c559..2c1f91c874 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2008 Uwe Hermann -## ## SPDX-License-Identifier: GPL-2.0-only # For a description of the syntax of this configuration file, @@ -46,6 +42,15 @@ config PAYLOAD_INFO_VERSION help The version number of this payload. +config LTO + bool "Use link time optimization (LTO)" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. This option + is most effective when LTO is also enabled in libpayload, which + is done separately. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 4171796350..cd58f392dd 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -1,8 +1,3 @@ -## -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2008 Uwe Hermann -## ## SPDX-License-Identifier: GPL-2.0-only src := $(CURDIR) @@ -81,9 +76,13 @@ ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ @@ -128,10 +127,9 @@ include $(srck)/Makefile else clean: - rm -rf build/*.elf build/*.o .xcompile + rm -rf build lpbuild .xcompile distclean: clean - rm -rf build lpbuild rm -f .config* lp.config* .PHONY: clean distclean diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index 1502a559dd..5a87f28340 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" @@ -19,14 +7,12 @@ #define LINES_SHOWN 19 #define TAB_WIDTH 2 - /* Globals that are used for tracking screen state */ static char *g_buf = NULL; static s32 g_line = 0; static s32 g_lines_count = 0; static s32 g_max_cursor_line = 0; - /* Copied from libpayload/drivers/cbmem_console.c */ struct cbmem_console { u32 size; @@ -37,7 +23,6 @@ struct cbmem_console { #define CURSOR_MASK ((1 << 28) - 1) #define OVERFLOW (1 << 31) - static u32 char_width(char c, u32 cursor, u32 screen_width) { if (c == '\n') { @@ -110,7 +95,7 @@ static int bootlog_module_init(void) return -1; } - struct cbmem_console *console = lib_sysinfo.cbmem_cons; + struct cbmem_console *console = phys_to_virt(lib_sysinfo.cbmem_cons); if (console == NULL) { return -1; } diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index f22453e4e8..adbe2778aa 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include "endian.h" diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 074d73a475..87032d5990 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 35e5016ae6..b357f97988 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/coreinfo.h b/payloads/coreinfo/coreinfo.h index 004a5e9663..b96af89efd 100644 --- a/payloads/coreinfo/coreinfo.h +++ b/payloads/coreinfo/coreinfo.h @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef COREINFO_H_ #define COREINFO_H_ diff --git a/payloads/coreinfo/cpuid.S b/payloads/coreinfo/cpuid.S index b004052080..84cdc77874 100644 --- a/payloads/coreinfo/cpuid.S +++ b/payloads/coreinfo/cpuid.S @@ -1,18 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ /* calling syntax: docpuid(idx,eax,ebx,ecx,edx) */ diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 96c495a170..b937e4c1d4 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -1,19 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ #include "coreinfo.h" diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index dd5ce366fb..2ec9929b60 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Jordan Crouse - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include "coreinfo.h" diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c index 9ac734a76c..99c6e9b69f 100644 --- a/payloads/coreinfo/nvram_module.c +++ b/payloads/coreinfo/nvram_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 019f8d05a4..ff01770868 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include @@ -163,7 +151,7 @@ static int pci_module_redraw(WINDOW *win) return 0; } -static void pci_scan_bus(int bus) +static void ci_pci_scan_bus(int bus) { int slot, func; unsigned int val; @@ -208,7 +196,7 @@ static void pci_scan_bus(int bus) busses = pci_read_config32(dev, REG_PRIMARY_BUS); - pci_scan_bus((busses >> 8) & 0xff); + ci_pci_scan_bus((busses >> 8) & 0xff); } } @@ -252,7 +240,7 @@ static int pci_module_handle(int key) static int pci_module_init(void) { - pci_scan_bus(0); + ci_pci_scan_bus(0); return 0; } diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index abb8472ff5..762707f5e5 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index 32f1866693..3a24930748 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include @@ -147,7 +137,7 @@ static int timestamps_module_init(void) if (ret) return -1; - struct timestamp_table *timestamps = lib_sysinfo.tstamp_table; + struct timestamp_table *timestamps = phys_to_virt(lib_sysinfo.tstamp_table); if (timestamps == NULL) return -1; diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore new file mode 100644 index 0000000000..ebca42908b --- /dev/null +++ b/payloads/external/.gitignore @@ -0,0 +1,10 @@ +depthcharge/depthcharge/ +FILO/filo/ +GRUB2/grub2/ +LinuxBoot/linuxboot/ +SeaBIOS/seabios/ +tianocore/tianocore/ +tint/tint/ +U-Boot/u-boot/ +Memtest86Plus/memtest86plus/ +iPXE/ipxe/ diff --git a/payloads/external/BOOTBOOT/Kconfig b/payloads/external/BOOTBOOT/Kconfig new file mode 100644 index 0000000000..c9d7133b71 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig @@ -0,0 +1,6 @@ +if PAYLOAD_BOOTBOOT + +config PAYLOAD_FILE + default "payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf" + +endif diff --git a/payloads/external/BOOTBOOT/Kconfig.name b/payloads/external/BOOTBOOT/Kconfig.name new file mode 100644 index 0000000000..082a9b1ec2 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_BOOTBOOT + bool "BOOTBOOT" + depends on ARCH_X86 || ARCH_ARM64 + help + Select this option if you want to build a coreboot image + with a BOOTBOOT Protocol payload. + + See https://gitlab.com/bztsrc/bootboot for more information. diff --git a/payloads/external/BOOTBOOT/Makefile b/payloads/external/BOOTBOOT/Makefile new file mode 100644 index 0000000000..2460c183bb --- /dev/null +++ b/payloads/external/BOOTBOOT/Makefile @@ -0,0 +1,44 @@ +project_git_repo=https://gitlab.com/bztsrc/bootboot.git +project_dir=bootboot +ifeq ($(CONFIG_COREBOOT_BUILD),) +include ../../../.config +endif +ifeq ($(CONFIG_ARCH_ARM64),y) +loader_dir=$(project_dir)/aarch64-cb +else +loader_dir=$(project_dir)/x86_64-cb +endif + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: bootboot + +checkout: + echo " GIT BOOTBOOT $(loader_dir)" + test -L $(project_dir) || test -d $(project_dir) || \ + git clone $(project_git_repo) $(project_dir) + +bootboot: libpayload + echo " MAKE $(loader_dir)" + $(MAKE) -C $(loader_dir) LIBCONFIG_PATH=../../../libpayload + +libpayload: checkout + cp $(loader_dir)/lib.config ../../libpayload/.config + cd ../../libpayload && $(MAKE) oldconfig && \ + $(MAKE) && $(MAKE) DESTDIR=../external/BOOTBOOT/$(loader_dir) install + +clean: + test -d $(loader_dir) && $(MAKE) -C $(loader_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: checkout bootboot libpayload clean distclean print-repo-info diff --git a/payloads/external/FILO/Kconfig b/payloads/external/FILO/Kconfig index 94d5e18df0..1cf171d2cf 100644 --- a/payloads/external/FILO/Kconfig +++ b/payloads/external/FILO/Kconfig @@ -5,9 +5,9 @@ choice default FILO_STABLE config FILO_STABLE - bool "0.6.0" + bool "tested" help - Stable FILO version + Tested FILO version config FILO_MASTER bool "HEAD" diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index a89ea2af59..6175cfe62c 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -1,6 +1,6 @@ TAG-$(CONFIG_FILO_MASTER)=origin/master NAME-$(CONFIG_FILO_MASTER)=MASTER -TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad +TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412 NAME-$(CONFIG_FILO_STABLE)=STABLE project_git_repo=https://review.coreboot.org/filo.git diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 591d649d8f..c2689e1871 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only if PAYLOAD_LINUXBOOT @@ -135,7 +131,6 @@ config LINUXBOOT_KERNEL_UIMAGE endchoice - config LINUXBOOT_DTB_FILE string "Compiled devicetree file" depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index 013873269f..4d3decd923 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -1,6 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only config PAYLOAD_LINUXBOOT diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 45b1764932..c91b1d43da 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=linuxboot diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 5dec401e1a..990672936d 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only SHELL := /bin/bash diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 07c453d65b..0cf91fec5b 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=$(shell pwd)/linuxboot diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ef0990c9b7..9c1a569c09 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -1,10 +1,3 @@ -################################################################################ -## -## -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # set up payload config and version files for later inclusion @@ -106,6 +99,29 @@ bootorder-file := $(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)) bootorder-type := raw endif +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(call add_intermediate, seabios_ps2_timeout, $(obj)/coreboot.pre $(CBFSTOOL)) + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/ps2-keyboard-spinup 2>/dev/null) + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup +endif +endif + +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(call add_intermediate, seabios_sercon, $(obj)/coreboot.pre $(CBFSTOOL)) + @printf " SeaBIOS Add sercon-port file\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/sercon-port 2>/dev/null) + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port +endif + +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +$(call add_intermediate, seabios_thread_optionroms, $(obj)/coreboot.pre $(CBFSTOOL)) + @printf " SeaBIOS Thread optionroms\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/threads 2>/dev/null) + $(CBFSTOOL) $< add-int -i 2 -n etc/threads +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) @@ -132,6 +148,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ + CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ @@ -303,3 +320,8 @@ payloads/external/Yabits/uefi/build/uefi.elf yabits: CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ MFLAGS= MAKEFLAGS= + +# BOOTBOOT + +payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf: + $(MAKE) -C payloads/external/BOOTBOOT all diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 5aec5c8156..3853cb9586 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_MEMTEST_MASTER)=origin/master diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 21e47206f4..9aea2d012b 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.13.0" + bool "1.14.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index cd646d9d73..cdcd426770 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069 +TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 6d186ad1c9..38dfe99a0e 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2015 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019-4 tag diff --git a/payloads/external/Yabits/Makefile b/payloads/external/Yabits/Makefile index 74f00efa65..adac77e810 100644 --- a/payloads/external/Yabits/Makefile +++ b/payloads/external/Yabits/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_YABITS_MASTER)=origin/master diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 0b81d183e9..6c8049a3d7 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config PXE diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 2a9e8c9b64..3e12f611a1 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019.3 - Last commit of March 2019 diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 7d5f038ebd..87b6e15582 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -100,4 +100,12 @@ config TIANOCORE_BOOTSPLASH_FILE If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. +config TIANOCORE_BOOT_TIMEOUT + int + default 2 + help + The length of time in seconds for which the boot splash/menu prompt will be displayed. + For boards with an internal display, the default value of 2s is generally sufficient. + For boards without an internal display, a value of 5s is generally sufficient. + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 9945411880..198c17f6fe 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2017 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # force the shell to bash - the edksetup.sh script doesn't work with dash @@ -41,12 +37,16 @@ ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) TIMER=-DUSE_HPET_TIMER endif +TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) + ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) - BUILD_STR=-q -a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) +ARCH=-a IA32 -p $(bootloader)/$(bootloader)Ia32.dsc else - BUILD_STR=-q -a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) +ARCH=-a IA32 -a X64 -p $(bootloader)/$(bootloader)Ia32X64.dsc endif +BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor) + all: clean build $(project_dir): diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 253bfea9dd..9473c02c57 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -18,9 +18,9 @@ patch: download cd tint; \ if [ -e debian ]; then \ rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi + touch Makefile; \ + patch -l -p1 < ../libpayload_tint.patch; \ + fi download: test -d tint || { wget $(project_url); \ diff --git a/payloads/libpayload/.gitignore b/payloads/libpayload/.gitignore new file mode 100644 index 0000000000..c7b20fc357 --- /dev/null +++ b/payloads/libpayload/.gitignore @@ -0,0 +1 @@ +install/ diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index b5dc9a3c8b..7a502b5853 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -79,6 +79,14 @@ config COMPILER_LLVM_CLANG endchoice +config LTO + bool "Use link time optimization (LTO)" + default n + depends on COMPILER_GCC + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n @@ -367,10 +375,6 @@ config PC_KEYBOARD default y if ARCH_X86 # uses IO default n -config PC_KEYBOARD_AT_TRANSLATED - bool "AT Translation keyboard device" - default n - config PC_KEYBOARD_LAYOUT_US bool "English (US) keyboard layout" depends on PC_KEYBOARD diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index b5687c3859..0b08c70af7 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -118,6 +118,11 @@ NOCOMPILE:=1 endif endif +xcompile ?= $(obj)/xcompile +$(xcompile): $(top)/../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc real-all: config @@ -126,13 +131,17 @@ else # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell $(top)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +$(if $(wildcard $(xcompile)),,$(shell \ + mkdir -p $(dir $(xcompile)) && \ + $(top)/../../util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile))) -.xcompile: $(top)/../../util/xcompile/xcompile - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null +include $(xcompile) --include .xcompile +ifneq ($(XCOMPILE_COMPLETE),1) +$(shell rm -f $(xcompile)) +$(error $(xcompile) deleted because it's invalid. \ + Restarting the build should fix that, or explain the problem) +endif CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) @@ -294,7 +303,7 @@ doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) clean-for-update: doxygen-clean clean-for-update-target - rm -f $(allobjs) .xcompile + rm -f $(allobjs) $(xcompile) rm -f $(DEPENDENCIES) rmdir -p $(alldirs) 2>/dev/null >/dev/null || true diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 2acf2266da..fc679dd27e 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -55,7 +55,8 @@ subdirs-$(CONFIG_LP_CBFS) += libcbfs subdirs-$(CONFIG_LP_LZMA) += liblzma subdirs-$(CONFIG_LP_LZ4) += liblz4 -INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h +INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) +INCLUDES += -include include/kconfig.h -include include/compiler.h CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer @@ -64,7 +65,14 @@ CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror -$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto +endif + +$(obj)/libpayload.config: $(DOTCONFIG) + cp $< $@ + +$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config cmp $@ $< 2>/dev/null || cp $< $@ library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a @@ -116,7 +124,7 @@ install: real-target install -m 755 bin/lpas $(DESTDIR)/libpayload/bin install -m 644 bin/lp.functions $(DESTDIR)/libpayload/bin install -m 644 $(DOTCONFIG) $(DESTDIR)/libpayload/libpayload.config - install -m 755 .xcompile $(DESTDIR)/libpayload/libpayload.xcompile + install -m 755 $(xcompile) $(DESTDIR)/libpayload/libpayload.xcompile clean-for-update-target: rm -f $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a diff --git a/payloads/libpayload/arch/arm/cpu.S b/payloads/libpayload/arch/arm/cpu.S index 4a1d41dc4d..a5ff12dc3d 100644 --- a/payloads/libpayload/arch/arm/cpu.S +++ b/payloads/libpayload/arch/arm/cpu.S @@ -81,7 +81,7 @@ lsl ip, ip, r2 @ shift by that into way position mov r0, #1 lsl r2, r0, r2 @ r2 now contains the way decr - mov r0, r3 @ get sets/level (no way yet) + mov r0, r3 @ get sets/level (no way yet) orr r3, r3, ip @ merge way into way/set/level bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1 sub r2, r2, r0 @ subtract from way decr diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 1fa9ced1be..bc4c233479 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -625,14 +625,10 @@ static void mmu_extract_ranges(struct memrange *cb_ranges, static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) { struct mmu_memrange *fb_range; - static struct cb_framebuffer modified_fb; - struct cb_framebuffer *framebuffer = lib_sysinfo.framebuffer; + struct cb_framebuffer *framebuffer = &lib_sysinfo.framebuffer; uint32_t fb_size; /* Check whether framebuffer is needed */ - if (framebuffer == NULL) - return; - fb_size = framebuffer->bytes_per_line * framebuffer->y_resolution; if (!fb_size) return; @@ -652,16 +648,7 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) if (fb_range == NULL) mmu_error(); - /* - * Set framebuffer address. However, one needs to use a freshly - * allocated framebuffer structure because the one in the coreboot - * table is part of a checksum calculation. Therefore, one cannot - * modify a field without recomputing the necessary checksum - * calcuation. - */ - modified_fb = *framebuffer; - modified_fb.physical_address = fb_range->base; - lib_sysinfo.framebuffer = &modified_fb; + framebuffer->physical_address = fb_range->base; } /* @@ -718,3 +705,8 @@ void mmu_presysinfo_enable(void) mmu_init(&usedmem_ranges); mmu_enable(); } + +const struct mmu_ranges *mmu_get_used_ranges(void) +{ + return &usedmem_ranges; +} diff --git a/payloads/libpayload/arch/arm64/virtual.c b/payloads/libpayload/arch/arm64/virtual.c index 2d336e301e..9450ac0d86 100644 --- a/payloads/libpayload/arch/arm64/virtual.c +++ b/payloads/libpayload/arch/arm64/virtual.c @@ -30,7 +30,6 @@ unsigned long virtual_offset = 0; - int getpagesize(void) { return 4096; diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index 2be47bc0ce..05cf58b446 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -52,5 +52,4 @@ config DIE_ON_UNKNOWN_INTERRUPT endchoice - endif diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 62011612a5..e0671064c8 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -127,7 +127,6 @@ void apic_start_delay(unsigned int usec) enable_interrupts(); } - void apic_wait_delay(void) { /* Loop in case another interrupt has fired and resumed execution. */ diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index bf16b71f97..38ede875c7 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -49,7 +49,7 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) { - info->mrc_cache = get_cbmem_ptr(ptr); + info->mrc_cache = get_cbmem_addr(ptr); } int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c index df2c0ac9ba..373c8417b3 100644 --- a/payloads/libpayload/arch/x86/delay.c +++ b/payloads/libpayload/arch/x86/delay.c @@ -38,7 +38,6 @@ /* Let's assume APIC interrupts take at least 100us */ #define APIC_INTERRUPT_LATENCY_NS (100 * NSECS_PER_USEC) - void arch_ndelay(uint64_t ns) { uint64_t delta = ns * timer_hz() / NSECS_PER_SEC; diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c index ffa57bb08f..5dd606746f 100644 --- a/payloads/libpayload/arch/x86/sysinfo.c +++ b/payloads/libpayload/arch/x86/sysinfo.c @@ -78,5 +78,10 @@ int lib_get_sysinfo(void) lib_sysinfo.memrange[1].type = CB_MEM_RAM; } +#if CONFIG(LP_PCI) + pci_init(&lib_sysinfo.pacc); + pci_scan_bus(&lib_sysinfo.pacc); +#endif + return ret; } diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index 1ff2cd6d55..6dcfd5b27f 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,6 +33,10 @@ #include #include +#include +#include + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -41,11 +45,11 @@ uint32_t cpu_khz; /** - * Calculate the speed of the processor for use in delays. + * @brief Measure the speed of the processor for use in delays * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -71,7 +75,116 @@ unsigned int get_cpu_speed(void) * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Calculates the core clock frequency via CPUID 0x15 + * + * Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models + * supporting this leaf didn't provide the nominal crystal frequency in ecx, + * hence we use hard coded values for them. + */ +static int get_cpu_khz_xtal(void) +{ + uint32_t ecx, edx, num, denom; + uint64_t nominal; + + if (cpuid_max() < 0x15) + return -1; + cpuid(0x15, denom, num, ecx, edx); + + if (denom == 0 || num == 0) + return -1; + + if (ecx != 0) { + nominal = ecx; + } else { + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case SKYLAKE_U_Y: + case SKYLAKE_S_H: + case KABYLAKE_U_Y: + case KABYLAKE_S_H: + nominal = 24000000; + break; + case APOLLOLAKE: + nominal = 19200000; + break; + default: + return -1; + } + } + + return nominal * num / denom / 1000; +} + +/** + * @brief Returns three times the bus clock in kHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case NEHALEM: + return 400 * 1000; /* 133 MHz */ + case SANDYBRIDGE: + case IVYBRIDGE: + case HASWELL: + case HASWELL_U: + case HASWELL_GT3E: + case BROADWELL: + case BROADWELL_U: + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/** + * @brief Returns the calculated CPU frequency + * + * Over the years, multiple ways to discover the CPU frequency have been + * exposed through CPUID and MSRs. Try the most recent and accurate first + * (crystal information in CPUID leaf 0x15) and then fall back to older + * methods. + * + * This should cover all Intel Core i processors at least. For older + * processors we fall back to the PIT calibration. + */ +static int get_cpu_khz_fast(void) +{ + /* Try core crystal clock frequency first (supposed to be more accurate). */ + const int cpu_khz_xtal = get_cpu_khz_xtal(); + if (cpu_khz_xtal > 0) + return cpu_khz_xtal; + + /* Try `bus clock * speedstep multiplier`. */ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + /* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return bus_x3 * mult / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } diff --git a/payloads/libpayload/arch/x86/virtual.c b/payloads/libpayload/arch/x86/virtual.c index 2d336e301e..9450ac0d86 100644 --- a/payloads/libpayload/arch/x86/virtual.c +++ b/payloads/libpayload/arch/x86/virtual.c @@ -30,7 +30,6 @@ unsigned long virtual_offset = 0; - int getpagesize(void) { return 4096; diff --git a/payloads/libpayload/bin/lp.functions b/payloads/libpayload/bin/lp.functions index 3911c42a5b..fd26956243 100644 --- a/payloads/libpayload/bin/lp.functions +++ b/payloads/libpayload/bin/lp.functions @@ -35,6 +35,10 @@ warn() { echo "Warning: $1" } +# For in-tree builds, allow to override the libpayload build dir. + +_OBJ=${_OBJ:-$BASE/../build} + # If the user didn't specify LIBPAYLOAD_PREFIX, then preload it # with the default prefix value @@ -48,8 +52,8 @@ fi if [ -f $BASE/../lib/libpayload.a ]; then _LIBDIR=$BASE/../lib -elif [ -f $BASE/../build/libpayload.a ]; then - _LIBDIR=$BASE/../build +elif [ -f $_OBJ/libpayload.config ]; then + _LIBDIR=$_OBJ else _LIBDIR=$LIBPAYLOAD_PREFIX/lib fi diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 2657a1a1b1..c0fe56adf5 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -57,11 +57,17 @@ BASE=`dirname $0` # This will set the _LIBDIR and _INCDIR variables used below . $BASE/lp.functions +if [ $_LIBDIR != $_OBJ ]; then + _DOTCONFIG=$BASE/../libpayload.config + _XCOMPILE=$BASE/../libpayload.xcompile +else + _DOTCONFIG=$_OBJ/libpayload.config + _XCOMPILE=$_OBJ/xcompile +fi + # include libpayload config -if [ -f $BASE/../libpayload.config ]; then - . $BASE/../libpayload.config -elif [ -f $BASE/../.config ]; then - . $BASE/../.config +if [ -f $_DOTCONFIG ]; then + . $_DOTCONFIG else echo "Can't find config" exit 1 @@ -137,14 +143,19 @@ while [ $# -gt 0 ]; do shift done -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" -if [ "$CONFIG_LP_PDCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses" -fi +if [ $_LIBDIR = $_OBJ ]; then + _CFLAGS="$_CFLAGS -I$_OBJ" -if [ "$CONFIG_LP_TINYCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses" + if [ "$CONFIG_LP_PDCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses -I$BASE/../curses/pdcurses-backend" + _CFLAGS="$_CFLAGS -I$BASE/../curses/form -I$BASE/../curses/menu" + fi + + if [ "$CONFIG_LP_TINYCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses" + fi fi # Check for the -fno-stack-protector silliness @@ -152,9 +163,10 @@ fi trygccoption -fno-stack-protector [ $? -eq 0 ] && _CFLAGS="$_CFLAGS -fno-stack-protector" -_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" +_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" +_CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" +_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then @@ -166,15 +178,15 @@ else _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` if [ -f $_ARCHLIBDIR/head.o ]; then HEAD_O=$_ARCHLIBDIR/head.o - elif [ -f $BASE/../build/head.o ]; then - HEAD_O=$BASE/../build/head.o + elif [ -f $_OBJ/head.o ]; then + HEAD_O=$_OBJ/head.o else echo "Could not find head.o" exit 1 fi - if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && - grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] && + grep -q fix-cortex-a53-843419 $_XCOMPILE; then _LDFLAGS="$_LDFLAGS -Wl,--fix-cortex-a53-843419" fi diff --git a/payloads/libpayload/configs/config.cheza b/payloads/libpayload/configs/config.cheza deleted file mode 100644 index 5f60392fdb..0000000000 --- a/payloads/libpayload/configs/config.cheza +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_LP_CHROMEOS=y -CONFIG_LP_ARCH_ARM64=y -CONFIG_LP_TIMER_ARM64_ARCH=y diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 896039ea0b..4ef1ed15b7 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -5,4 +5,4 @@ CONFIG_LP_USB_UHCI=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -CONFIG_LP_HEAP_SIZE=262144 +CONFIG_LP_HEAP_SIZE=1048576 diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c index fce96a3463..5f54431a82 100644 --- a/payloads/libpayload/crypto/sha1.c +++ b/payloads/libpayload/crypto/sha1.c @@ -115,7 +115,6 @@ SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH]) a = b = c = d = e = 0; } - /* * SHA1Init - Initialize new context */ @@ -132,7 +131,6 @@ SHA1Init(SHA1_CTX *context) context->state[4] = 0xC3D2E1F0; } - /* * Run your data through this. */ @@ -155,7 +153,6 @@ SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len) (void)memcpy(&context->buffer[j], &data[i], len - i); } - /* * Add padding and return the message digest. */ diff --git a/payloads/libpayload/curses/PDCurses/curses.h b/payloads/libpayload/curses/PDCurses/curses.h index 5f651fef44..45245ae0b1 100644 --- a/payloads/libpayload/curses/PDCurses/curses.h +++ b/payloads/libpayload/curses/PDCurses/curses.h @@ -41,6 +41,7 @@ PDCurses portable platform definitions list: /*----------------------------------------------------------------------*/ #include +#include #include #include /* Required by X/Open usage below */ @@ -48,12 +49,6 @@ PDCurses portable platform definitions list: # include #endif -#if defined(__cplusplus) || defined(__cplusplus__) || defined(__CPLUSPLUS) -extern "C" -{ -# define bool _bool -#endif - /*---------------------------------------------------------------------- * * PDCurses Manifest Constants @@ -82,8 +77,6 @@ extern "C" * */ -typedef unsigned char bool; /* PDCurses Boolean type */ - #ifdef CHTYPE_LONG # if _LP64 typedef unsigned int chtype; diff --git a/payloads/libpayload/curses/PDCurses/demos/tui.c b/payloads/libpayload/curses/PDCurses/demos/tui.c index 62e0d53767..41f34ba410 100644 --- a/payloads/libpayload/curses/PDCurses/demos/tui.c +++ b/payloads/libpayload/curses/PDCurses/demos/tui.c @@ -46,14 +46,12 @@ void rmerror(void); # define EDITBOXCOLOR (A_BOLD | A_REVERSE) #endif - #define th 1 /* title window height */ #define mh 1 /* main menu height */ #define sh 2 /* status window height */ #define bh (LINES - th - mh - sh) /* body window height */ #define bw COLS /* body window width */ - /******************************* STATIC ************************************/ static WINDOW *wtitl, *wmain, *wbody, *wstat; /* title, menu, body, status win*/ @@ -360,7 +358,6 @@ static void cleanup(void) /* cleanup curses settings */ } } - /******************************* EXTERNAL **********************************/ void clsbody(void) diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c index e77d2c78ce..b96a027282 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c @@ -116,7 +116,6 @@ ScrollBoxClassRec scrollBoxClassRec = { WidgetClass scrollBoxWidgetClass = (WidgetClass)&scrollBoxClassRec; - /************************************************************************ * * * Private Routines * diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h index 5825862744..9ba7d67331 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h @@ -42,7 +42,6 @@ */ - /* Class record constants */ extern WidgetClass scrollBoxWidgetClass; diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h b/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h index 44551386bc..902edeebb7 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h @@ -56,7 +56,6 @@ typedef struct { XtGeometryMask last_query_mode; } ScrollBoxPart; - /************************************************************************ * * * Full instance record declaration * diff --git a/payloads/libpayload/curses/PDCurses/x11/x11.c b/payloads/libpayload/curses/PDCurses/x11/x11.c index 69c3199b54..46444d4471 100644 --- a/payloads/libpayload/curses/PDCurses/x11/x11.c +++ b/payloads/libpayload/curses/PDCurses/x11/x11.c @@ -276,7 +276,6 @@ static char *program_name; #define RCOLOR(name, value) RPIXEL(color##name, Color##name, value) - #define RSTRINGP(name1, name2, param) { \ #name1, #name2, XtRString, \ MAX_PATH, APPDATAOFF(name1), XtRString, (XtPointer)param \ diff --git a/payloads/libpayload/curses/curses.h b/payloads/libpayload/curses/curses.h index 1699250de6..b802adb3f4 100644 --- a/payloads/libpayload/curses/curses.h +++ b/payloads/libpayload/curses/curses.h @@ -87,7 +87,7 @@ * User-definable tweak to disable the include of . */ #ifndef NCURSES_ENABLE_STDBOOL_H -#define NCURSES_ENABLE_STDBOOL_H 0 //// XXX +#define NCURSES_ENABLE_STDBOOL_H 1 #endif /* diff --git a/payloads/libpayload/curses/curses.priv.h b/payloads/libpayload/curses/curses.priv.h index 78b7ff3cc9..31ec80f1bb 100644 --- a/payloads/libpayload/curses/curses.priv.h +++ b/payloads/libpayload/curses/curses.priv.h @@ -32,7 +32,6 @@ * and: Thomas E. Dickey 1996-on * ****************************************************************************/ - /* * $Id: curses.priv.h,v 1.314 2006/12/10 00:55:14 tom Exp $ * @@ -497,7 +496,6 @@ struct screen { chtype * _acs_map; /* the real alternate-charset map */ bool * _screen_acs_map; - /* used in lib_vidattr.c */ bool _use_rmso; /* true if we may use 'rmso' */ bool _use_rmul; /* true if we may use 'rmul' */ @@ -980,7 +978,6 @@ extern NCURSES_EXPORT(void) name (void); \ }\ TR(TRACE_ATTRS, ("new attribute is %s", _traceattr((S))));} - #define toggle_attr_off(S,at) {\ if (PAIR_NUMBER(at) > 0) {\ (S) &= ~(at|A_COLOR);\ diff --git a/payloads/libpayload/curses/form/form.h b/payloads/libpayload/curses/form/form.h index d7bb85adf4..2f55e42591 100644 --- a/payloads/libpayload/curses/form/form.h +++ b/payloads/libpayload/curses/form/form.h @@ -106,7 +106,6 @@ typedef struct fieldnode { NCURSES_FIELD_INTERNALS } FIELD; - /********* * FORM * *********/ @@ -138,7 +137,6 @@ typedef struct formnode { } FORM; - /************** * FIELDTYPE * **************/ diff --git a/payloads/libpayload/curses/menu/eti.h b/payloads/libpayload/curses/menu/eti.h index baa6190d8f..152ada76ce 100644 --- a/payloads/libpayload/curses/menu/eti.h +++ b/payloads/libpayload/curses/menu/eti.h @@ -36,19 +36,19 @@ #define NCURSES_ETI_H_incl 1 #define E_OK (0) -#define E_SYSTEM_ERROR (-1) -#define E_BAD_ARGUMENT (-2) -#define E_POSTED (-3) -#define E_CONNECTED (-4) -#define E_BAD_STATE (-5) -#define E_NO_ROOM (-6) +#define E_SYSTEM_ERROR (-1) +#define E_BAD_ARGUMENT (-2) +#define E_POSTED (-3) +#define E_CONNECTED (-4) +#define E_BAD_STATE (-5) +#define E_NO_ROOM (-6) #define E_NOT_POSTED (-7) #define E_UNKNOWN_COMMAND (-8) #define E_NO_MATCH (-9) #define E_NOT_SELECTABLE (-10) -#define E_NOT_CONNECTED (-11) +#define E_NOT_CONNECTED (-11) #define E_REQUEST_DENIED (-12) -#define E_INVALID_FIELD (-13) +#define E_INVALID_FIELD (-13) #define E_CURRENT (-14) #endif diff --git a/payloads/libpayload/curses/menu/menu.h b/payloads/libpayload/curses/menu/menu.h index 1fdd9e795d..1df980c551 100644 --- a/payloads/libpayload/curses/menu/menu.h +++ b/payloads/libpayload/curses/menu/menu.h @@ -132,7 +132,6 @@ typedef struct tagMENU } MENU; - /* Define keys */ #define REQ_LEFT_ITEM (KEY_MAX + 1) @@ -170,7 +169,6 @@ typedef struct tagMENU # define MAX_COMMAND (KEY_MAX + 128) #endif - /* --------- prototypes for libmenu functions ----------------------------- */ extern NCURSES_EXPORT(ITEM **) menu_items (const MENU *); @@ -244,7 +242,6 @@ extern NCURSES_EXPORT(int) menu_request_by_name (const char *); extern NCURSES_EXPORT(int) set_menu_spacing (MENU *,int,int,int); extern NCURSES_EXPORT(int) menu_spacing (const MENU *,int *,int *,int *); - extern NCURSES_EXPORT(bool) item_value (const ITEM *); extern NCURSES_EXPORT(bool) item_visible (const ITEM *); diff --git a/payloads/libpayload/curses/menu/mf_common.h b/payloads/libpayload/curses/menu/mf_common.h index 681672dc34..d40c7b9806 100644 --- a/payloads/libpayload/curses/menu/mf_common.h +++ b/payloads/libpayload/curses/menu/mf_common.h @@ -66,7 +66,6 @@ extern int errno; #define MODULE_ID(id) /*nothing*/ #endif - /* Maximum regular 8-bit character code */ #define MAX_REGULAR_CHARACTER (0xff) diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index ffd9bd4769..d3bf84efab 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -163,7 +163,6 @@ chtype console_acs_map[128] = // FIXME: Ugly (and insecure!) hack! char sprintf_tmp[1024]; - int curses_flags = (F_ENABLE_CONSOLE | F_ENABLE_SERIAL); /* Return bit mask for clearing color pair number if given ch has color */ diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c index 053802cbd9..22d5312c3a 100644 --- a/payloads/libpayload/drivers/cbmem_console.c +++ b/payloads/libpayload/drivers/cbmem_console.c @@ -38,7 +38,7 @@ struct cbmem_console { #define CURSOR_MASK ((1 << 28) - 1) #define OVERFLOW (1 << 31) -static struct cbmem_console *cbmem_console_p; +static uintptr_t cbmem_console_p; static struct console_output_driver cbmem_console_driver = { @@ -47,27 +47,32 @@ static struct console_output_driver cbmem_console_driver = static void do_write(const void *buffer, size_t count) { - memcpy(cbmem_console_p->body + (cbmem_console_p->cursor & CURSOR_MASK), - buffer, count); - cbmem_console_p->cursor += count; + struct cbmem_console *const cbmem_cons = phys_to_virt(cbmem_console_p); + + memcpy(cbmem_cons->body + (cbmem_cons->cursor & CURSOR_MASK), buffer, count); + cbmem_cons->cursor += count; } void cbmem_console_init(void) { + const struct cbmem_console *const cbmem_cons = phys_to_virt(lib_sysinfo.cbmem_cons); + cbmem_console_p = lib_sysinfo.cbmem_cons; - if (cbmem_console_p && cbmem_console_p->size) + + if (cbmem_console_p && cbmem_cons->size) console_add_output_driver(&cbmem_console_driver); } void cbmem_console_write(const void *buffer, size_t count) { - while ((cbmem_console_p->cursor & CURSOR_MASK) + count >= - cbmem_console_p->size) { - size_t still_fits = cbmem_console_p->size - - (cbmem_console_p->cursor & CURSOR_MASK); + struct cbmem_console *const cbmem_cons = phys_to_virt(cbmem_console_p); + + while ((cbmem_cons->cursor & CURSOR_MASK) + count >= + cbmem_cons->size) { + size_t still_fits = cbmem_cons->size - (cbmem_cons->cursor & CURSOR_MASK); do_write(buffer, still_fits); - cbmem_console_p->cursor &= ~CURSOR_MASK; - cbmem_console_p->cursor |= OVERFLOW; + cbmem_cons->cursor &= ~CURSOR_MASK; + cbmem_cons->cursor |= OVERFLOW; buffer += still_fits; count -= still_fits; } @@ -77,7 +82,7 @@ void cbmem_console_write(const void *buffer, size_t count) char *cbmem_console_snapshot(void) { - const struct cbmem_console *console_p = cbmem_console_p; + const struct cbmem_console *const console_p = phys_to_virt(cbmem_console_p); char *console_c; uint32_t size, cursor, overflow; diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 50d013dbaf..a89b9d9717 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -28,6 +28,7 @@ #include #include +#include #include #include "i8042.h" @@ -111,6 +112,19 @@ static u8 fifo_pop(struct fifo *fifo) return ret; } +/** Peek on the head of fifo queue. + * Returns the oldest object on the queue if any. + * In case the queue is empty 0 is returned. + * @fifo: Fifo to use + */ +static u8 fifo_peek(struct fifo *fifo) +{ + if (fifo_is_empty(fifo)) + return 0; + + return fifo->buf[fifo->rx]; +} + /** Destroys a fifo queue. * @fifo: Fifo to use */ @@ -159,7 +173,7 @@ static u8 i8042_wait_cmd_rdy(void) */ static u8 i8042_wait_data_rdy(void) { - int retries = 10000; + int retries = 30000; while (retries-- && !(read_status() & OBF)) udelay(50); @@ -318,6 +332,24 @@ void i8042_write_data(u8 data) return; } +/** + * Send command & data to keyboard controller. + * + * @param cmd: The command to be sent. + * @param data: The data to be sent. + * Returns 0 on success, -1 on failure. + */ +static int i8042_cmd_with_data(const u8 cmd, const u8 data) +{ + const int ret = i8042_cmd(cmd); + if (ret != 0) + return ret; + + i8042_write_data(data); + + return ret; +} + /** * Probe for keyboard controller data and queue it. */ @@ -371,6 +403,14 @@ u8 i8042_read_data_ps2(void) return fifo_pop(ps2_fifo); } +/** + * Returns available keyboard data without advancing the queue. + */ +u8 i8042_peek_data_ps2(void) +{ + return fifo_peek(ps2_fifo); +} + /** * Returns available mouse data, if any. */ @@ -408,3 +448,36 @@ int i8042_wait_read_aux(void) return (retries <= 0) ? -1 : i8042_read_data_aux(); } + +/** + * Get the keyboard scancode translation state. + * + * Returns: -1 on timeout, 1 if the controller translates + * scancode set #2 to #1, and 0 if not. + */ +int i8042_get_kbd_translation(void) +{ + const int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (cfg < 0) + return cfg; + + return !!(cfg & I8042_CMD_BYTE_XLATE); +} + +/** + * Sets the keyboard scancode translation state. + * + * Returns: -1 on timeout, 0 otherwise. + */ +int i8042_set_kbd_translation(const bool xlate) +{ + int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (cfg < 0) + return cfg; + + if (xlate) + cfg |= I8042_CMD_BYTE_XLATE; + else + cfg &= ~I8042_CMD_BYTE_XLATE; + return i8042_cmd_with_data(I8042_CMD_WR_CMD_BYTE, cfg); +} diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 6d15d1e0c5..bcb42fd13d 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -56,9 +56,6 @@ #define I8042_MODE_SCROLL_LOCK_ON (1 << 0) #define I8042_MODE_SCROLL_LOCK_OFF (0 << 0) #define I8042_KBCMD_SET_SCANCODE 0xf0 -#define I8042_SCANCODE_SET_1 (1) -#define I8042_SCANCODE_SET_2 (2) -#define I8042_SCANCODE_SET_3 (3) #define I8042_KBCMD_SET_TYPEMATIC 0xf3 #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index eb94199ec0..91a51bb0ee 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -27,12 +27,21 @@ * SUCH DAMAGE. */ +#include +#include + #include #include #include #include "i8042.h" +#ifdef DEBUG +#define debug(x...) printf(x) +#else +#define debug(x...) do {} while (0) +#endif + #define POWER_BUTTON 0x90 #define MEDIA_KEY_PREFIX 0xE0 @@ -169,16 +178,253 @@ static struct layout_maps keyboard_layouts[] = { #endif }; -static unsigned char keyboard_cmd(unsigned char cmd) +static void keyboard_drain_input(void) { - i8042_write_data(cmd); - - return i8042_wait_read_ps2() == 0xfa; + while (i8042_data_ready_ps2()) + (void)i8042_read_data_ps2(); } -int keyboard_havechar(void) +static bool keyboard_cmd(unsigned char cmd) { - return i8042_data_ready_ps2(); + const uint64_t timeout_us = cmd == I8042_KBCMD_RESET ? 1*1000*1000 : 200*1000; + const uint64_t start_time = timer_us(0); + + i8042_write_data(cmd); + + do { + if (!i8042_data_ready_ps2()) { + udelay(50); + continue; + } + + const uint8_t data = i8042_read_data_ps2(); + switch (data) { + case 0xfa: + return true; + case 0xfe: + return false; + default: + /* Warn only if we already disabled keyboard input. */ + if (cmd != I8042_KBCMD_DEFAULT_DIS) + debug("WARNING: Keyboard sent spurious 0x%02x.\n", data); + break; + } + } while (timer_us(start_time) < timeout_us); + + debug("ERROR: Keyboard command timed out.\n"); + return false; +} + +static bool set_scancode_set(const unsigned char set) +{ + bool ret; + + if (set < 1 || set > 3) + return false; + + ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); + if (!ret) { + debug("ERROR: Keyboard set scancode failed!\n"); + return ret; + } + + ret = keyboard_cmd(set); + if (!ret) { + debug("ERROR: Keyboard scancode set#%u failed!\n", set); + return ret; + } + + return ret; +} + +static enum keyboard_state { + STATE_INIT = 0, + STATE_SIMPLIFIED_INIT, + STATE_DISABLE_SCAN, + STATE_DRAIN_INPUT, + STATE_DISABLE_TRANSLATION, + STATE_START_SELF_TEST, + STATE_SELF_TEST, + STATE_CONFIGURE, + STATE_CONFIGURE_SET1, + STATE_ENABLE_TRANSLATION, + STATE_ENABLE_SCAN, + STATE_RUNNING, + STATE_IGNORE, +} keyboard_state; + +#define STATE_NAMES_ENTRY(name) [STATE_##name] = #name +static const char *const state_names[] = { + STATE_NAMES_ENTRY(INIT), + STATE_NAMES_ENTRY(SIMPLIFIED_INIT), + STATE_NAMES_ENTRY(DISABLE_SCAN), + STATE_NAMES_ENTRY(DRAIN_INPUT), + STATE_NAMES_ENTRY(DISABLE_TRANSLATION), + STATE_NAMES_ENTRY(START_SELF_TEST), + STATE_NAMES_ENTRY(SELF_TEST), + STATE_NAMES_ENTRY(CONFIGURE), + STATE_NAMES_ENTRY(CONFIGURE_SET1), + STATE_NAMES_ENTRY(ENABLE_TRANSLATION), + STATE_NAMES_ENTRY(ENABLE_SCAN), + STATE_NAMES_ENTRY(RUNNING), + STATE_NAMES_ENTRY(IGNORE), +}; + +__attribute__((unused)) +static const char *state_name(enum keyboard_state state) +{ + if (state >= ARRAY_SIZE(state_names) || !state_names[state]) + return ""; + return state_names[state]; +} + +static uint64_t keyboard_time; +static uint64_t state_time; + +static void keyboard_poll(void) +{ + enum keyboard_state next_state = keyboard_state; + unsigned int i; + + switch (keyboard_state) { + + case STATE_INIT: + /* Wait until keyboard_init() has been called. */ + break; + + case STATE_SIMPLIFIED_INIT: + /* On the first try, start opportunistically, do + the first steps at once and skip the self-test. */ + (void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + keyboard_drain_input(); + (void)i8042_set_kbd_translation(false); + next_state = STATE_CONFIGURE; + break; + + case STATE_DISABLE_SCAN: + (void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + next_state = STATE_DRAIN_INPUT; + break; + + case STATE_DRAIN_INPUT: + /* Limit number of bytes drained per poll. */ + for (i = 0; i < 50 && i8042_data_ready_ps2(); ++i) + (void)i8042_read_data_ps2(); + if (i == 0) + next_state = STATE_DISABLE_TRANSLATION; + break; + + case STATE_DISABLE_TRANSLATION: + /* Be opportunistic and assume it's disabled on failure. */ + (void)i8042_set_kbd_translation(false); + next_state = STATE_START_SELF_TEST; + break; + + case STATE_START_SELF_TEST: + if (!keyboard_cmd(I8042_KBCMD_RESET)) + debug("ERROR: Keyboard self-test couldn't be started.\n"); + /* We ignore errors and always move to the self-test state + which will simply try again if necessary. */ + next_state = STATE_SELF_TEST; + break; + + case STATE_SELF_TEST: + if (!i8042_data_ready_ps2()) { + if (timer_us(state_time) > 5*1000*1000) { + debug("WARNING: Keyboard self-test timed out.\n"); + next_state = STATE_DISABLE_SCAN; + } + break; + } + + const uint8_t self_test_result = i8042_read_data_ps2(); + switch (self_test_result) { + case 0xaa: + debug("INFO: Keyboard self-test succeeded.\n"); + next_state = STATE_CONFIGURE; + break; + case 0xfc: + case 0xfd: + /* Failure. Try again. */ + debug("WARNING: Keyboard self-test failed.\n"); + next_state = STATE_START_SELF_TEST; + break; + default: + debug("WARNING: Keyboard self-test received spurious 0x%02x\n", + self_test_result); + break; + } + break; + + case STATE_CONFIGURE: + if (set_scancode_set(2)) + next_state = STATE_ENABLE_TRANSLATION; + else + next_state = STATE_CONFIGURE_SET1; + break; + + case STATE_CONFIGURE_SET1: + if (!set_scancode_set(1)) { + debug("ERROR: Keyboard failed to set any scancode set.\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_ENABLE_SCAN; + break; + + case STATE_ENABLE_TRANSLATION: + if (i8042_set_kbd_translation(true) != 0) { + debug("ERROR: Keyboard controller set translation failed!\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_ENABLE_SCAN; + break; + + case STATE_ENABLE_SCAN: + if (!keyboard_cmd(I8042_KBCMD_EN)) { + debug("ERROR: Keyboard enable scanning failed!\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_RUNNING; + break; + + case STATE_RUNNING: + /* TODO: Use echo command to detect detach. */ + break; + + case STATE_IGNORE: + /* TODO: Try again after timeout if it ever seems useful. */ + break; + + } + + switch (next_state) { + case STATE_INIT: + case STATE_RUNNING: + case STATE_IGNORE: + break; + default: + if (timer_us(keyboard_time) > 30*1000*1000) + next_state = STATE_IGNORE; + break; + } + + if (keyboard_state != next_state) { + debug("INFO: Keyboard advancing state to '%s'.\n", state_name(next_state)); + keyboard_state = next_state; + state_time = timer_us(0); + } +} + +bool keyboard_havechar(void) +{ + keyboard_poll(); + return keyboard_state == STATE_RUNNING && i8042_data_ready_ps2(); } unsigned char keyboard_get_scancode(void) @@ -306,88 +552,27 @@ int keyboard_set_layout(char *country) } static struct console_input_driver cons = { - .havekey = keyboard_havechar, + .havekey = (int (*)(void))keyboard_havechar, .getchar = keyboard_getchar, .input_type = CONSOLE_INPUT_TYPE_EC, }; -/* Enable keyboard translated */ -static int enable_translated(void) -{ - if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { - int cmd = i8042_read_data_ps2(); - cmd |= I8042_CMD_BYTE_XLATE; - if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) { - i8042_write_data(cmd); - } else { - printf("ERROR: i8042_cmd WR_CMD failed!\n"); - return 0; - } - } else { - printf("ERROR: i8042_cmd RD_CMD failed!\n"); - return 0; - } - return 1; -} - -/* Set scancode set 1 */ -static int set_scancode_set(void) -{ - unsigned int ret; - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret) { - printf("ERROR: Keyboard set scancode failed!\n"); - return ret; - } - - ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); - return ret; - } - - /* - * Set default parameters. - * Fix for broken QEMU PS/2 make scancodes. - */ - ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); - return ret; - } - - /* Enable scanning */ - ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret) { - printf("ERROR: Keyboard enable scanning failed!\n"); - return ret; - } - - return ret; -} - void keyboard_init(void) { + if (keyboard_state != STATE_INIT) + return; + map = &keyboard_layouts[0]; /* Initialized keyboard controller. */ if (!i8042_probe() || !i8042_has_ps2()) return; - /* Empty keyboard buffer */ - while (keyboard_havechar()) - keyboard_getchar(); - /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) { - if (!enable_translated()) - return; - } else { - if (!set_scancode_set()) - return; - } + keyboard_state = STATE_SIMPLIFIED_INIT; + keyboard_time = state_time = timer_us(0); console_add_input_driver(&cons); } @@ -402,20 +587,18 @@ void keyboard_disconnect(void) if (!i8042_has_ps2()) return; - /* Empty keyboard buffer */ - while (keyboard_havechar()) - keyboard_getchar(); - /* Disable scanning */ keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + keyboard_drain_input(); /* Send keyboard disconnect command */ i8042_cmd(I8042_CMD_DIS_KB); /* Hand off with empty buffer */ - while (keyboard_havechar()) - keyboard_getchar(); + keyboard_drain_input(); /* Release keyboard controller driver */ i8042_close(); + + keyboard_state = STATE_INIT; } diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index 40bd2fc882..4794e9b249 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -42,7 +42,6 @@ #include #include - /** * PCs can have either 64 (very old ones), 128, or 256 bytes of CMOS RAM. * diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 3a14d77df9..b6d234222d 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -26,8 +26,11 @@ * SUCH DAMAGE. */ +#define __STDC_FORMAT_MACROS + #include #include +#include u8 *mem_accessor_base; @@ -53,7 +56,7 @@ struct nvram_accessor *use_mem = &(struct nvram_accessor) { struct cb_cmos_option_table *get_system_option_table(void) { - return lib_sysinfo.option_table; + return phys_to_virt(lib_sysinfo.cmos_option_table); } int options_checksum_valid(const struct nvram_accessor *nvram) @@ -325,7 +328,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti /* only works on little endian. 26 bytes is enough for a 64bit value in decimal */ *dest = malloc(26); - sprintf(*dest, "%llu", *(u64*)raw); + sprintf(*dest, "%" PRIu64, *(u64 *)raw); break; case 's': *dest = strdup(raw); diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index b0e9d03c20..1df34c41ea 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -132,9 +132,9 @@ void serial_init(void) void serial_console_init(void) { - if (!lib_sysinfo.serial) + if (!lib_sysinfo.cb_serial) return; - cb_serial = *lib_sysinfo.serial; + cb_serial = *(struct cb_serial *)phys_to_virt(lib_sysinfo.cb_serial); serial_init(); diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 5a9079b46b..bc5ebbbc1b 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -553,9 +553,7 @@ static struct console_output_driver consout = {}; /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; - - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; consin.havekey = serial_havechar; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index ef4ce80849..93e2129185 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -343,9 +343,9 @@ int serial_getchar(void) /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; + struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial); - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; base_uart_addr = (void *) sc_ptr->baseaddr; diff --git a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c index 3d0e6de335..77def46831 100644 --- a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c +++ b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /* For simplicity sake let's rely on coreboot initializing the UART. */ #include #include @@ -275,7 +274,8 @@ static struct console_output_driver consout = { static struct qup_regs *uart_base_address(void) { - return (void *)(uintptr_t)lib_sysinfo.serial->baseaddr; + const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial); + return phys_to_virt(serial->baseaddr); } static void uart_qupv3_tx_flush(void) @@ -332,7 +332,7 @@ int serial_getchar(void) void serial_console_init(void) { - if (!lib_sysinfo.serial) + if (!lib_sysinfo.cb_serial) return; console_add_output_driver(&consout); diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 1a7b9e901b..2ed6af1749 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -541,9 +541,9 @@ int serial_getchar(void) /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; + struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial); - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr; diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c index 6ca5dc4717..7a6f0e1c39 100644 --- a/payloads/libpayload/drivers/serial/s5p.c +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -90,10 +90,12 @@ static struct console_input_driver s5p_serial_input = void serial_init(void) { - if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial); + + if (!lib_sysinfo.cb_serial || !serial->baseaddr) return; - uart_regs = (struct s5p_uart *)lib_sysinfo.serial->baseaddr; + uart_regs = (struct s5p_uart *)serial->baseaddr; } void serial_console_init(void) diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index fea52c8903..0c2cc8a665 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -12,7 +12,7 @@ config STORAGE config STORAGE_64BIT_LBA bool "Use 64-bit integers to address sectors" depends on STORAGE - default n + default y help If this is selected, sectors will be addressed by an 64-bit integer. Select this to support LBA-48 for ATA drives. @@ -45,7 +45,7 @@ config STORAGE_AHCI config STORAGE_AHCI_ONLY_TESTED bool "Only enable tested controllers" depends on STORAGE_AHCI - default y + default n help - If this option is selected only AHCI controllers which are known + If this option is selected, only AHCI controllers which are known to work will be used. diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 9f9b9b589a..6a6fbfd418 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -39,7 +39,6 @@ #include "ahci_private.h" - #ifdef DEBUG_STATUS static inline u32 _ahci_clear_status(volatile u32 *const reg, const char *const r, @@ -64,7 +63,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg) #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r) #endif - static inline int ahci_port_is_active(const hba_port_t *const port) { return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK)) @@ -229,34 +227,28 @@ static u32 working_controllers[] = { 0x8086 | 0x5ae3 << 16, /* Apollo Lake */ }; #endif -static void ahci_init_pci(pcidev_t dev) + +void ahci_initialize(struct pci_dev *dev) { int i; - const u16 class = pci_read_config16(dev, 0xa); - if (class != 0x0106) - return; - const u16 vendor = pci_read_config16(dev, 0x00); - const u16 device = pci_read_config16(dev, 0x02); - #if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) - const u32 vendor_device = pci_read_config32(dev, 0x0); + const u32 vendor_device = dev->vendor_id | dev->device_id << 16; for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) break; if (i == ARRAY_SIZE(working_controllers)) { printf("ahci: Not using untested SATA controller " - "%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev), - PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + "%02x:%02x.%02x (%04x:%04x).\n", dev->bus, + dev->dev, dev->func, dev->vendor_id, dev->device_id); return; } #endif printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n", - PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id); - hba_ctrl_t *const ctrl = phys_to_virt( - pci_read_config32(dev, 0x24) & ~0x3ff); + hba_ctrl_t *const ctrl = phys_to_virt(pci_read_long(dev, 0x24) & ~0x3ff); hba_port_t *const ports = ctrl->ports; /* Reset host controller. */ @@ -275,8 +267,8 @@ static void ahci_init_pci(pcidev_t dev) ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; /* Enable bus mastering. */ - const u16 command = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + const u16 command = pci_read_word(dev, PCI_COMMAND); + pci_write_word(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); /* Probe for devices. */ for (i = 0; i < 32; ++i) { @@ -284,19 +276,3 @@ static void ahci_init_pci(pcidev_t dev) ahci_port_probe(ctrl, &ports[i], i + 1); } } - -void ahci_initialize(void) -{ - int bus, dev, func; - - for (bus = 0; bus < 256; ++bus) { - for (dev = 0; dev < 32; ++dev) { - const u16 class = - pci_read_config16(PCI_DEV(bus, dev, 0), 0xa); - if (class != 0xffff) { - for (func = 0; func < 8; ++func) - ahci_init_pci(PCI_DEV(bus, dev, func)); - } - } - } -} diff --git a/payloads/libpayload/drivers/storage/ahci_ata.c b/payloads/libpayload/drivers/storage/ahci_ata.c index 514692e39f..062b7ac71b 100644 --- a/payloads/libpayload/drivers/storage/ahci_ata.c +++ b/payloads/libpayload/drivers/storage/ahci_ata.c @@ -37,7 +37,6 @@ #include "ahci_private.h" - ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev, const lba_t start, size_t count, u8 *const buf) diff --git a/payloads/libpayload/drivers/storage/ahci_atapi.c b/payloads/libpayload/drivers/storage/ahci_atapi.c index 9984b4b78d..1a757d7e9b 100644 --- a/payloads/libpayload/drivers/storage/ahci_atapi.c +++ b/payloads/libpayload/drivers/storage/ahci_atapi.c @@ -35,10 +35,8 @@ #include #include - #include "ahci_private.h" - ssize_t ahci_packet_read_cmd(atapi_dev_t *const _dev, const u8 *const cmd, const size_t cmdlen, u8 *const buf, const size_t buflen) diff --git a/payloads/libpayload/drivers/storage/ahci_common.c b/payloads/libpayload/drivers/storage/ahci_common.c index b8fdad202c..f3abc5f7fb 100644 --- a/payloads/libpayload/drivers/storage/ahci_common.c +++ b/payloads/libpayload/drivers/storage/ahci_common.c @@ -37,7 +37,6 @@ #include "ahci_private.h" - #ifdef DEBUG_STATUS static inline u32 _ahci_clear_status(volatile u32 *const reg, const char *const r, @@ -62,7 +61,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg) #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r) #endif - /** Give a buffer with even address. */ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev, u8 *const user_buf, const size_t len, diff --git a/payloads/libpayload/drivers/storage/ahci_private.h b/payloads/libpayload/drivers/storage/ahci_private.h index 7f7c592048..1e8c85f199 100644 --- a/payloads/libpayload/drivers/storage/ahci_private.h +++ b/payloads/libpayload/drivers/storage/ahci_private.h @@ -120,7 +120,6 @@ typedef volatile struct { #define HBA_CTRL_INTR_EN (1 << 1) #define HBA_CTRL_RESET (1 << 0) - typedef volatile struct { u8 dma_setup_fis[28]; u8 _reserved0[4]; @@ -229,5 +228,4 @@ ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev, const lba_t start, size_t count, u8 *const buf); - #endif /* _AHCI_PRIVATE_H */ diff --git a/payloads/libpayload/drivers/storage/ata.c b/payloads/libpayload/drivers/storage/ata.c index 68f88f6eb7..00f1d88854 100644 --- a/payloads/libpayload/drivers/storage/ata.c +++ b/payloads/libpayload/drivers/storage/ata.c @@ -33,7 +33,6 @@ #include - /** Reads non-sector-aligned blocks of 512 bytes. */ static ssize_t ata_read_unaligned(ata_dev_t *const dev, const lba_t blk_start, size_t blk_count, diff --git a/payloads/libpayload/drivers/storage/atapi.c b/payloads/libpayload/drivers/storage/atapi.c index f42c1f4b80..7f46e9cc3e 100644 --- a/payloads/libpayload/drivers/storage/atapi.c +++ b/payloads/libpayload/drivers/storage/atapi.c @@ -33,7 +33,6 @@ #include #include - static int atapi_request_sense(atapi_dev_t *const dev) { u8 cdb[12] = { 0, }; diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index 3ddafdce07..4b585bae3a 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -27,12 +27,10 @@ */ #include -#if CONFIG(LP_STORAGE_AHCI) -# include -#endif +#include +#include #include - static storage_dev_t **devices = NULL; static size_t devices_length = 0; static size_t dev_count = 0; @@ -109,7 +107,18 @@ ssize_t storage_read_blocks512(const size_t dev_num, */ void storage_initialize(void) { +#if CONFIG(LP_PCI) + struct pci_dev *dev; + for (dev = lib_sysinfo.pacc.devices; dev; dev = dev->next) { + switch (dev->device_class) { #if CONFIG(LP_STORAGE_AHCI) - ahci_initialize(); + case PCI_CLASS_STORAGE_AHCI: + ahci_initialize(dev); + break; +#endif + default: + break; + } + } #endif } diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index dd1601367b..3df7d2409c 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -300,7 +300,6 @@ static void start_setup(struct usbdev_ctrl *this, int ep) udc_handle_setup(this, ep, &dr); } - static void chipidea_enqueue_packet(struct usbdev_ctrl *this, int endpoint, int in_dir, void *data, int len, int zlp, int autofree) { diff --git a/payloads/libpayload/drivers/usb/dwc2_rh.c b/payloads/libpayload/drivers/usb/dwc2_rh.c index ff15e9902d..c0f25f907a 100644 --- a/payloads/libpayload/drivers/usb/dwc2_rh.c +++ b/payloads/libpayload/drivers/usb/dwc2_rh.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ - #include #include "generic_hub.h" #include "dwc2_private.h" diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index cb3c1c543e..58fc64eead 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -28,6 +28,7 @@ //#define USB_DEBUG +#include #include #include #include @@ -46,15 +47,15 @@ static void dump_td(u32 addr) usb_debug("|..[OUT]............................................|\n"); else usb_debug("|..[]...............................................|\n"); - usb_debug("|:|============ EHCI TD at [0x%08lx] ==========|:|\n", addr); - usb_debug("|:| ERRORS = [%ld] | TOKEN = [0x%08lx] | |:|\n", + usb_debug("|:|============ EHCI TD at [0x%08"PRIx32"] ==========|:|\n", addr); + usb_debug("|:| ERRORS = [%"PRId32"] | TOKEN = [0x%08"PRIx32"] | |:|\n", 3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Next qTD [0x%08lx] |:|\n", td->next_qtd); + usb_debug("|:| Next qTD [0x%08"PRIx32"] |:|\n", td->next_qtd); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Alt. Next qTD [0x%08lx] |:|\n", td->alt_next_qtd); + usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| | Bytes to Transfer |[%05ld] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); + usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8); usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15); usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7); @@ -277,9 +278,11 @@ static int wait_for_tds(qtd_t *head) if (cur->next_qtd & 1) { break; } - if (0) dump_td(virt_to_phys(cur)); + if (0) + dump_td(virt_to_phys(cur)); /* helps debugging the TD chain */ - if (0) usb_debug("\nmoving from %x to %x\n", cur, phys_to_virt(cur->next_qtd)); + if (0) + usb_debug("\nmoving from %p to %p\n", cur, phys_to_virt(cur->next_qtd)); cur = phys_to_virt(cur->next_qtd); } return result; @@ -426,7 +429,6 @@ oom: return -1; } - /* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, u8 *src) @@ -544,7 +546,6 @@ oom: return -1; } - typedef struct _intr_qtd_t intr_qtd_t; struct _intr_qtd_t { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index e51f332822..edb1b4ad4d 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -171,7 +171,6 @@ ehci_rh_poll (usbdev_t *dev) ehci_rh_scanport (dev, port); } - void ehci_rh_init (usbdev_t *dev) { diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 87674eec6b..f35d1ff0e8 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -29,6 +29,7 @@ //#define USB_DEBUG #include +#include #include #include "ohci_private.h" #include "ohci.h" @@ -59,7 +60,7 @@ dump_td (td_t *cur) else usb_debug("|..[]...............................................|\n"); usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur)); - usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08lx] | |:|\n", + usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08"PRIx32"] | |:|\n", 3 - ((cur->config & (3UL << 26)) >> 26), cur->config); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28); @@ -69,11 +70,11 @@ dump_td (td_t *cur) usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24); usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Current Buffer Pointer [0x%08lx] |:|\n", cur->current_buffer_pointer); + usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Next TD [0x%08lx] |:|\n", cur->next_td); + usb_debug("|:| Next TD [0x%08"PRIx32"] |:|\n", cur->next_td); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Current Buffer End [0x%08lx] |:|\n", cur->buffer_end); + usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end); usb_debug("|:|-----------------------------------------------|:|\n"); usb_debug("|...................................................|\n"); usb_debug("+---------------------------------------------------+\n"); @@ -88,9 +89,9 @@ dump_ed (ed_t *cur) usb_debug("+---------------------------------------------------+\n"); usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", cur->next_ed & ~0xFUL); usb_debug("+---------------------------------------------------+\n"); - usb_debug("| | @ 0x%08lx : |\n", cur->config); + usb_debug("| | @ 0x%08"PRIx32" : |\n", cur->config); usb_debug("| C | Maximum Packet Length | [%04ld] |\n", ((cur->config & (0x3fffUL << 16)) >> 16)); - usb_debug("| O | Function Address | [%04ld] |\n", cur->config & 0x7F); + usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F); usb_debug("| N | Endpoint Number | [%02ld] |\n", (cur->config & (0xFUL << 7)) >> 7); usb_debug("| F | Endpoint Direction | [%ld] |\n", ((cur->config & (3UL << 11)) >> 11)); usb_debug("| I | Endpoint Speed | [%ld] |\n", ((cur->config & (1UL << 13)) >> 13)); @@ -468,7 +469,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, head->tail_pointer = virt_to_phys(final_td); head->head_pointer = virt_to_phys(first_td); - usb_debug("ohci_control(): doing transfer with %x. first_td at %x\n", + usb_debug("%s(): doing transfer with %x. first_td at %"PRIxPTR"\n", __func__, head->config & ED_FUNC_MASK, virt_to_phys(first_td)); #ifdef USB_DEBUG dump_ed(head); @@ -506,7 +507,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) td_t *cur, *next; int remaining = dalen; u8 *data = src; - usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); + usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); if (!dma_coherent(src)) { data = OHCI_INST(ep->dev->controller)->dma_buffer; @@ -596,7 +597,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) head->tail_pointer = virt_to_phys(cur); head->head_pointer = virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0); - usb_debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n", + usb_debug("doing bulk transfer with %x(%x). first_td at %"PRIxPTR", last %"PRIxPTR"\n", head->config & ED_FUNC_MASK, (head->config & ED_EP_MASK) >> ED_EP_SHIFT, virt_to_phys(first_td), virt_to_phys(cur)); @@ -627,7 +628,6 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) return result; } - struct _intr_queue; struct _intrq_td { diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index 796be29a01..e29e5901bf 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -36,7 +36,7 @@ // FIXME: fake typedef enum { CMD} reg; - enum { + enum HcRhDescriptorAReg { NumberDownstreamPorts = 1 << 0, PowerSwitchingMode = 1 << 8, NoPowerSwitching = 1 << 9, @@ -44,19 +44,19 @@ OverCurrentProtectionMode = 1 << 11, NoOverCurrentProtection = 1 << 12, PowerOnToPowerGoodTime = 1 << 24 - } HcRhDescriptorAReg; + }; - enum { + enum HcRhDescriptorAMask { NumberDownstreamPortsMask = MASK(0, 8), PowerOnToPowerGoodTimeMask = MASK(24, 8) - } HcRhDescriptorAMask; + }; - enum { + enum HcRhDescriptorBReg { DeviceRemovable = 1 << 0, PortPowerControlMask = 1 << 16 - } HcRhDescriptorBReg; + }; - enum { + enum HcRhPortStatusRead { CurrentConnectStatus = 1 << 0, PortEnableStatus = 1 << 1, PortSuspendStatus = 1 << 2, @@ -69,8 +69,9 @@ PortSuspendStatusChange = 1 << 18, PortOverCurrentIndicatorChange = 1 << 19, PortResetStatusChange = 1 << 20 - } HcRhPortStatusRead; - enum { + }; + + enum HcRhPortStatusSet { ClearPortEnable = 1 << 0, SetPortEnable = 1 << 1, SetPortSuspend = 1 << 2, @@ -78,29 +79,30 @@ SetPortReset = 1 << 4, SetPortPower = 1 << 8, ClearPortPower = 1 << 9, - } HcRhPortStatusSet; + }; - enum { + enum HcRhStatusReg { LocalPowerStatus = 1 << 0, OverCurrentIndicator = 1 << 1, DeviceRemoteWakeupEnable = 1 << 15, LocalPowerStatusChange = 1 << 16, OverCurrentIndicatorChange = 1 << 17, ClearRemoteWakeupEnable = 1 << 31 - } HcRhStatusReg; + }; - enum { + enum HcFmIntervalOffset { FrameInterval = 1 << 0, FSLargestDataPacket = 1 << 16, FrameIntervalToggle = 1 << 31 - } HcFmIntervalOffset; - enum { + }; + + enum HcFmIntervalMask { FrameIntervalMask = MASK(0, 14), FSLargestDataPacketMask = MASK(16, 15), FrameIntervalToggleMask = MASK(31, 1) - } HcFmIntervalMask; + }; - enum { + enum HcControlReg { ControlBulkServiceRatio = 1 << 0, PeriodicListEnable = 1 << 2, IsochronousEnable = 1 << 3, @@ -110,12 +112,12 @@ InterruptRouting = 1 << 8, RemoteWakeupConnected = 1 << 9, RemoteWakeupEnable = 1 << 10 - } HcControlReg; + }; - enum { + enum HcControlMask { ControlBulkServiceRatioMask = MASK(0, 2), HostControllerFunctionalStateMask = MASK(6, 2) - } HcControlMask; + }; enum { USBReset = 0*HostControllerFunctionalState, @@ -124,24 +126,24 @@ USBSuspend = 3*HostControllerFunctionalState }; - enum { + enum HcCommandStatusReg { HostControllerReset = 1 << 0, ControlListFilled = 1 << 1, BulkListFilled = 1 << 2, OwnershipChangeRequest = 1 << 3, SchedulingOverrunCount = 1 << 16 - } HcCommandStatusReg; + }; - enum { + enum HcCommandStatusMask { SchedulingOverrunCountMask = MASK(16, 2) - } HcCommandStatusMask; + }; - enum { + enum HcFmRemainingReg { FrameRemaining = 1 << 0, FrameRemainingToggle = 1 << 31 - } HcFmRemainingReg; + }; - enum { + enum HcInterruptStatusReg { SchedulingOverrung = 1 << 0, WritebackDoneHead = 1 << 1, StartofFrame = 1 << 2, @@ -150,7 +152,7 @@ FrameNumberOverflow = 1 << 5, RootHubStatusChange = 1 << 6, OwnershipChange = 1 << 30 - } HcInterruptStatusReg; + }; typedef struct { // Control and Status Partition diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index c6a178703c..b87ec26965 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -29,6 +29,7 @@ //#define USB_DEBUG #include +#include #include #include "uhci.h" #include "uhci_private.h" @@ -79,14 +80,14 @@ static void td_dump(td_t *td) (td->ptr & (1UL << 2)) >> 2, (td->ptr & (1UL << 1)) >> 1, td->ptr & 1UL); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| T | Maximum Length | [%04lx] |:|\n", (td->token & (0x7FFUL << 21)) >> 21); - usb_debug("|:| O | PID CODE | [%04lx] |:|\n", td->token & 0xFF); - usb_debug("|:| K | Endpoint | [%04lx] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); + usb_debug("|:| O | PID CODE | [%04"PRIx32"] |:|\n", td->token & 0xFF); + usb_debug("|:| K | Endpoint | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); usb_debug("|:| E | Device Address | [%04lx] |:|\n", (td->token & (0x7FUL << 8)) >> 8); usb_debug("|:| N | Data Toggle | [%lx] |:|\n", (td->token & (1UL << 19)) >> 19); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| C | Short Packet Detector | [%lx] |:|\n", (td->ctrlsts & (1UL << 29)) >> 29); usb_debug("|:| O | Error Counter | [%lx] |:|\n", - (td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT); + (td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT); usb_debug("|:| N | Low Speed Device | [%lx] |:|\n", (td->ctrlsts & (1UL << 26)) >> 26); usb_debug("|:| T | Isochronous Select | [%lx] |:|\n", (td->ctrlsts & (1UL << 25)) >> 25); usb_debug("|:| R | Interrupt on Complete (IOC) | [%lx] |:|\n", (td->ctrlsts & (1UL << 24)) >> 24); @@ -101,7 +102,7 @@ static void td_dump(td_t *td) usb_debug("|:| S ----------------------------------------|:|\n"); usb_debug("|:| | Actual Length | [%04lx] |:|\n", td->ctrlsts & 0x7FFUL); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Buffer pointer [0x%08lx] |:|\n", td->bufptr); + usb_debug("|:| Buffer pointer [0x%08"PRIx32"] |:|\n", td->bufptr); usb_debug("|:|-----------------------------------------------|:|\n"); usb_debug("|...................................................|\n"); usb_debug("+---------------------------------------------------+\n"); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index b14abb4b35..ed33147c51 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -28,6 +28,7 @@ //#define USB_DEBUG +#include #include #include @@ -229,7 +230,7 @@ get_free_address (hci_t *controller) int i = controller->latest_address + 1; for (; i != controller->latest_address; i++) { if (i >= ARRAY_SIZE(controller->devices) || i < 1) { - usb_debug("WARNING: Device addresses for controller %#x" + usb_debug("WARNING: Device addresses for controller %#" PRIxPTR " wrapped around!\n", controller->reg_base); i = 0; continue; @@ -275,7 +276,7 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0) bMaxPacketSize0 = 9; } return 1 << bMaxPacketSize0; - default: /* GCC is stupid and cannot deal with enums correctly */ + default: /* GCC is stupid and cannot deal with enums correctly */ return 8; } } diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 921e17608e..87e87411fe 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -131,8 +131,6 @@ const char *countries[36][2] = { /* 36 - 255: Reserved */ }; - - struct layout_maps { const char *country; const short map[4][0x80]; @@ -247,7 +245,6 @@ static const struct layout_maps keyboard_layouts[] = { //#endif }; - static void usb_hid_keyboard_queue(int ch) { /* ignore key presses if buffer full */ if (keycount < KEYBOARD_BUFFER_SIZE) @@ -316,7 +313,6 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst, if (skip) continue; - /* Mask off KB_MOD_CTRL */ keypress = map->map[modifiers & 0x03][current->keys[i]]; @@ -397,7 +393,6 @@ static struct console_input_driver cons = { .input_type = CONSOLE_INPUT_TYPE_USB, }; - static int usb_hid_set_layout (const char *country) { /* FIXME should be per keyboard */ diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c old mode 100755 new mode 100644 index ed91c9938b..96c4946b76 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -613,7 +613,6 @@ usb_msc_init (usbdev_t *dev) usb_debug (" it uses %s protocol\n", msc_protocol_strings[interface->bInterfaceProtocol]); - if (interface->bInterfaceProtocol != 0x50) { usb_debug (" Protocol not supported.\n"); usb_detach_device (dev->controller, dev->address); diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 749ff0a066..c40e641c4c 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -194,7 +194,7 @@ xhci_init (unsigned long physical_bar) xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff; xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff; - xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); + xhci_debug("regbase: 0x%"PRIxPTR"\n", physical_bar); xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg)); xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff); @@ -208,8 +208,8 @@ xhci_init (unsigned long physical_bar) } xhci_debug("context size: %dB\n", CTXSIZE(xhci)); - xhci_debug("maxslots: 0x%02lx\n", CAP_GET(MAXSLOTS, xhci->capreg)); - xhci_debug("maxports: 0x%02lx\n", CAP_GET(MAXPORTS, xhci->capreg)); + xhci_debug("maxslots: 0x%02"PRIx32"\n", CAP_GET(MAXSLOTS, xhci->capreg)); + xhci_debug("maxports: 0x%02"PRIx32"\n", CAP_GET(MAXPORTS, xhci->capreg)); const unsigned pagesize = xhci->opreg->pagesize << 12; xhci_debug("pagesize: 0x%04x\n", pagesize); @@ -374,7 +374,7 @@ xhci_reinit (hci_t *controller) /* Initialize command ring */ xhci_init_cycle_ring(&xhci->cr, COMMAND_RING_SIZE); - xhci_debug("command ring @%p (0x%08x)\n", + xhci_debug("command ring @%p (0x%08"PRIxPTR")\n", xhci->cr.ring, virt_to_phys(xhci->cr.ring)); xhci->opreg->crcr_lo = virt_to_phys(xhci->cr.ring) | CRCR_RCS; xhci->opreg->crcr_hi = 0; @@ -384,9 +384,9 @@ xhci_reinit (hci_t *controller) /* Initialize event ring */ xhci_reset_event_ring(&xhci->er); - xhci_debug("event ring @%p (0x%08x)\n", + xhci_debug("event ring @%p (0x%08"PRIxPTR")\n", xhci->er.ring, virt_to_phys(xhci->er.ring)); - xhci_debug("ERST Max: 0x%lx -> 0x%lx entries\n", + xhci_debug("ERST Max: 0x%"PRIx32" -> 0x%x entries\n", CAP_GET(ERST_MAX, xhci->capreg), 1 << CAP_GET(ERST_MAX, xhci->capreg)); memset((void*)xhci->ev_ring_table, 0x00, sizeof(erst_entry_t)); diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c index d633cc5762..a4078030c6 100644 --- a/payloads/libpayload/drivers/usb/xhci_commands.c +++ b/payloads/libpayload/drivers/usb/xhci_commands.c @@ -75,7 +75,13 @@ xhci_wait_for_command(xhci_t *const xhci, /* Abort command on timeout */ xhci_debug("Aborting command (@%p), CRCR: 0x%"PRIx32"\n", cmd_trb, xhci->opreg->crcr_lo); - xhci->opreg->crcr_lo |= CRCR_CS | CRCR_CA; + /* + * Ref. xHCI Specification Revision 1.2, May 2019. + * Section 5.4.5, Table 5-24. + * + * Abort the command and stop the ring. + */ + xhci->opreg->crcr_lo |= CRCR_CA; xhci->opreg->crcr_hi = 0; cc = xhci_wait_for_command_aborted(xhci, cmd_trb); diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c index 32a43fcfeb..139ea59619 100644 --- a/payloads/libpayload/drivers/usb/xhci_events.c +++ b/payloads/libpayload/drivers/usb/xhci_events.c @@ -226,7 +226,15 @@ xhci_wait_for_event_type(xhci_t *const xhci, return *timeout_us; } -/* returns cc of command in question (pointed to by `address`) */ +/* + * Ref. xHCI Specification Revision 1.2, May 2019. + * Section 4.6.1.2. + * + * Process events from xHCI Abort command. + * + * Returns CC_COMMAND_RING_STOPPED on success and TIMEOUT on failure. + */ + int xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) { @@ -239,12 +247,13 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) int cc = TIMEOUT; /* * Expects two command completion events: - * The first with CC == COMMAND_ABORTED should point to address, + * The first with CC == COMMAND_ABORTED should point to address + * (not present if command was not running), * the second with CC == COMMAND_RING_STOPPED should point to new dq. */ while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if ((xhci->er.cur->ptr_low == virt_to_phys(address)) && - (xhci->er.cur->ptr_high == 0)) { + (xhci->er.cur->ptr_high == 0)) { cc = TRB_GET(CC, xhci->er.cur); xhci_advance_event_ring(xhci); break; @@ -252,20 +261,31 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) xhci_handle_command_completion_event(xhci); } - if (!timeout_us) - xhci_debug("Warning: Timed out waiting for COMMAND_ABORTED.\n"); + if (timeout_us == 0) { + xhci_debug("Warning: Timed out waiting for " + "COMMAND_ABORTED or COMMAND_RING_STOPPED.\n"); + goto update_and_return; + } + if (cc == CC_COMMAND_RING_STOPPED) { + /* There may not have been a command to abort. */ + goto update_and_return; + } + + timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */ while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if (TRB_GET(CC, xhci->er.cur) == CC_COMMAND_RING_STOPPED) { - xhci->cr.cur = phys_to_virt(xhci->er.cur->ptr_low); + cc = CC_COMMAND_RING_STOPPED; xhci_advance_event_ring(xhci); break; } xhci_handle_command_completion_event(xhci); } - if (!timeout_us) + if (timeout_us == 0) xhci_debug("Warning: Timed out " "waiting for COMMAND_RING_STOPPED.\n"); + +update_and_return: xhci_update_event_dq(xhci); return cc; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 8e11937ac5..34d3651daf 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -204,7 +204,7 @@ typedef transfer_ring_t command_ring_t; #define SC_UADDR_LEN 8 #define SC_STATE_FIELD f4 /* STATE - Slot State */ #define SC_STATE_START 27 -#define SC_STATE_LEN 8 +#define SC_STATE_LEN 5 #define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN) #define SC_GET(tok, sc) (((sc)->SC_##tok##_FIELD & SC_MASK(tok)) \ >> SC_##tok##_START) @@ -363,7 +363,7 @@ typedef struct erst_entry { #define CAP_CSZ_LEN 1 #define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN) -#define CAP_GET(tok, cap) (((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \ +#define CAP_GET(tok, cap) ((read32(&(cap)->CAP_##tok##_FIELD) & CAP_MASK(tok)) \ >> CAP_##tok##_START) #define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32) @@ -515,7 +515,6 @@ static inline int xhci_ep_id(const endpoint_t *const ep) { return ((ep->endpoint & 0x7f) * 2) + (ep->direction != OUT); } - #ifdef XHCI_DUMPS void xhci_dump_slotctx(const slotctx_t *); void xhci_dump_epctx(const epctx_t *); diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 9b711c8586..bf4c2bc5c1 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -135,7 +135,6 @@ xhci_rh_enable_port(usbdev_t *const dev, int port) return 0; } - static const generic_hub_ops_t xhci_rh_ops = { .hub_status_changed = xhci_rh_hub_status_changed, .port_status_changed = xhci_rh_port_status_changed, diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index c21665d0c0..51922d9b06 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -60,7 +60,7 @@ static const u32 vga_colors[] = { (0xFF << 16) | (0xFF << 8) | 0xFF, }; -struct cb_framebuffer fbinfo; +static struct cb_framebuffer fbinfo; static unsigned short *chars; /* Shorthand for up-to-date virtual framebuffer address */ @@ -138,7 +138,6 @@ static void corebootfb_putchar(u8 row, u8 col, unsigned int ch) ((((vga_colors[fg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos); } - dst = FB + ((row * font_height) * fbinfo.bytes_per_line); dst += (col * font_width * (fbinfo.bits_per_pixel >> 3)); @@ -223,13 +222,10 @@ static void corebootfb_set_cursor(unsigned int x, unsigned int y) static int corebootfb_init(void) { - if (lib_sysinfo.framebuffer == NULL) + if (!lib_sysinfo.framebuffer.physical_address) return -1; - fbinfo = *lib_sysinfo.framebuffer; - - if (fbinfo.physical_address == 0) - return -1; + fbinfo = lib_sysinfo.framebuffer; font_init(fbinfo.x_resolution); diff --git a/payloads/libpayload/drivers/video/geodelx.c b/payloads/libpayload/drivers/video/geodelx.c index 7c51fc21e6..8799bca669 100644 --- a/payloads/libpayload/drivers/video/geodelx.c +++ b/payloads/libpayload/drivers/video/geodelx.c @@ -176,7 +176,6 @@ static void init_video_mode(void) writel(((vga_mode.hactive - 1) << 16) | (vga_mode.vactive - 1), DC + 0x5C); - /* Write the VG configuration */ writel(0x290000F | vga_mode.synccfg, VG + 0x08); diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 54d3dfa2b2..563f2961c7 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -41,12 +41,17 @@ static struct rect canvas; static struct rect screen; +static uint8_t *gfx_buffer; + /* * Framebuffer is assumed to assign a higher coordinate (larger x, y) to * a higher address */ -static struct cb_framebuffer *fbinfo; -static uint8_t *fbaddr; +static const struct cb_framebuffer *fbinfo; + +/* Shorthand for up-to-date virtual framebuffer address */ +#define REAL_FB ((unsigned char *)phys_to_virt(fbinfo->physical_address)) +#define FB (gfx_buffer ? gfx_buffer : REAL_FB) #define LOG(x...) printf("CBGFX: " x) #define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT) @@ -61,17 +66,53 @@ static const struct vector vzero = { .y = 0, }; +struct color_transformation { + uint8_t base; + int16_t scale; +}; + +struct color_mapping { + struct color_transformation red; + struct color_transformation green; + struct color_transformation blue; + int enabled; +}; + +static struct color_mapping color_map; + +static inline void set_color_trans(struct color_transformation *trans, + uint8_t bg_color, uint8_t fg_color) +{ + trans->base = bg_color; + trans->scale = fg_color - bg_color; +} + +int set_color_map(const struct rgb_color *background, + const struct rgb_color *foreground) +{ + if (background == NULL || foreground == NULL) + return CBGFX_ERROR_INVALID_PARAMETER; + + set_color_trans(&color_map.red, background->red, foreground->red); + set_color_trans(&color_map.green, background->green, + foreground->green); + set_color_trans(&color_map.blue, background->blue, foreground->blue); + color_map.enabled = 1; + + return CBGFX_SUCCESS; +} + +void clear_color_map(void) +{ + color_map.enabled = 0; +} + struct blend_value { uint8_t alpha; struct rgb_color rgb; }; -static struct blend_value blend = { - .alpha = 0, - .rgb.red = 0, - .rgb.green = 0, - .rgb.blue = 0, -}; +static struct blend_value blend; int set_blend(const struct rgb_color *rgb, uint8_t alpha) { @@ -99,6 +140,11 @@ static void add_vectors(struct vector *out, out->y = v1->y + v2->y; } +static int fraction_equal(const struct fraction *f1, const struct fraction *f2) +{ + return (int64_t)f1->n * f2->d == (int64_t)f2->n * f1->d; +} + static int is_valid_fraction(const struct fraction *f) { return f->d != 0; @@ -109,17 +155,31 @@ static int is_valid_scale(const struct scale *s) return is_valid_fraction(&s->x) && is_valid_fraction(&s->y); } +static void reduce_fraction(struct fraction *out, int64_t n, int64_t d) +{ + /* Simplest way to reduce the fraction until fitting in int32_t */ + int shift = log2(MAX(ABS(n), ABS(d)) >> 31) + 1; + out->n = n >> shift; + out->d = d >> shift; +} + +/* out = f1 + f2 */ static void add_fractions(struct fraction *out, const struct fraction *f1, const struct fraction *f2) { - int64_t n, d; - int shift; - n = (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d; - d = (int64_t)f1->d * f2->d; - /* Simplest way to reduce the fraction until fitting in int32_t */ - shift = log2(MAX(ABS(n), ABS(d)) >> 31) + 1; - out->n = n >> shift; - out->d = d >> shift; + reduce_fraction(out, + (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d, + (int64_t)f1->d * f2->d); +} + +/* out = f1 - f2 */ +static void subtract_fractions(struct fraction *out, + const struct fraction *f1, + const struct fraction *f2) +{ + reduce_fraction(out, + (int64_t)f1->n * f2->d - (int64_t)f2->n * f1->d, + (int64_t)f1->d * f2->d); } static void add_scales(struct scale *out, @@ -166,6 +226,15 @@ static int within_box(const struct vector *v, const struct rect *bound) return -1; } +/* Helper function that applies color_map to the color. */ +static inline uint8_t apply_map(uint8_t color, + const struct color_transformation *trans) +{ + if (!color_map.enabled) + return color; + return trans->base + trans->scale * color / UINT8_MAX; +} + /* * Helper function that applies color and opacity from blend struct * into the color. @@ -184,13 +253,16 @@ static inline uint32_t calculate_color(const struct rgb_color *rgb, { uint32_t color = 0; - color |= (apply_blend(rgb->red, blend.rgb.red) + color |= (apply_blend(apply_map(rgb->red, &color_map.red), + blend.rgb.red) >> (8 - fbinfo->red_mask_size)) << fbinfo->red_mask_pos; - color |= (apply_blend(rgb->green, blend.rgb.green) + color |= (apply_blend(apply_map(rgb->green, &color_map.green), + blend.rgb.green) >> (8 - fbinfo->green_mask_size)) << fbinfo->green_mask_pos; - color |= (apply_blend(rgb->blue, blend.rgb.blue) + color |= (apply_blend(apply_map(rgb->blue, &color_map.blue), + blend.rgb.blue) >> (8 - fbinfo->blue_mask_size)) << fbinfo->blue_mask_pos; if (invert) @@ -229,7 +301,7 @@ static inline void set_pixel(struct vector *coord, uint32_t color) break; } - uint8_t * const pixel = fbaddr + rcoord.y * bpl + rcoord.x * bpp / 8; + uint8_t * const pixel = FB + rcoord.y * bpl + rcoord.x * bpp / 8; for (i = 0; i < bpp / 8; i++) pixel[i] = (color >> (i * 8)); } @@ -243,12 +315,9 @@ static int cbgfx_init(void) if (initialized) return 0; - fbinfo = lib_sysinfo.framebuffer; - if (!fbinfo) - return CBGFX_ERROR_FRAMEBUFFER_INFO; + fbinfo = &lib_sysinfo.framebuffer; - fbaddr = phys_to_virt((uint8_t *)(uintptr_t)(fbinfo->physical_address)); - if (!fbaddr) + if (!fbinfo->physical_address) return CBGFX_ERROR_FRAMEBUFFER_ADDR; switch (fbinfo->orientation) { @@ -477,6 +546,59 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, return CBGFX_SUCCESS; } +int draw_line(const struct scale *pos1, const struct scale *pos2, + const struct fraction *thickness, const struct rgb_color *rgb) +{ + struct fraction len; + struct vector top_left; + struct vector size; + struct vector p, t; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + const uint32_t color = calculate_color(rgb, 0); + + if (!is_valid_fraction(thickness)) + return CBGFX_ERROR_INVALID_PARAMETER; + + transform_vector(&top_left, &canvas.size, pos1, &canvas.offset); + if (fraction_equal(&pos1->y, &pos2->y)) { + /* Horizontal line */ + subtract_fractions(&len, &pos2->x, &pos1->x); + struct scale dim = { + .x = { .n = len.n, .d = len.d }, + .y = { .n = thickness->n, .d = thickness->d }, + }; + transform_vector(&size, &canvas.size, &dim, &vzero); + size.y = MAX(size.y, 1); + } else if (fraction_equal(&pos1->x, &pos2->x)) { + /* Vertical line */ + subtract_fractions(&len, &pos2->y, &pos1->y); + struct scale dim = { + .x = { .n = thickness->n, .d = thickness->d }, + .y = { .n = len.n, .d = len.d }, + }; + transform_vector(&size, &canvas.size, &dim, &vzero); + size.x = MAX(size.x, 1); + } else { + LOG("Only support horizontal and vertical lines\n"); + return CBGFX_ERROR_INVALID_PARAMETER; + } + + add_vectors(&t, &top_left, &size); + if (within_box(&t, &canvas) < 0) { + LOG("Line exceeds canvas boundary\n"); + return CBGFX_ERROR_BOUNDARY; + } + + for (p.y = top_left.y; p.y < t.y; p.y++) + for (p.x = top_left.x; p.x < t.x; p.x++) + set_pixel(&p, color); + + return CBGFX_SUCCESS; +} + int clear_canvas(const struct rgb_color *rgb) { const struct rect box = { @@ -507,7 +629,7 @@ int clear_screen(const struct rgb_color *rgb) * We assume that for 32bpp the high byte gets ignored anyway. */ if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || (((color >> 16) & 0xff) == (color & 0xff)))) { - memset(fbaddr, color & 0xff, fbinfo->y_resolution * bpl); + memset(FB, color & 0xff, fbinfo->y_resolution * bpl); } else { for (p.y = 0; p.y < screen.size.height; p.y++) for (p.x = 0; p.x < screen.size.width; p.x++) @@ -736,24 +858,25 @@ static int draw_bitmap_v3(const struct vector *top_left, } /* - * Initialize the sample array for this line. For pixels to the - * left of S0 there are no corresponding input pixels so just - * copy the S0 values over. - * - * Also initialize the equals counter, which counts how many of - * the latest pixels were exactly equal. We know the columns - * left of S0 must be equal to S0, so start with that number. + * Initialize the sample array for this line, and also + * the equals counter, which counts how many of the latest + * pixels were exactly equal. */ - int equals = S0 * SSZ; + int equals = 0; uint8_t last_equal = ypix[0][0]; - for (sy = 0; sy < SSZ; sy++) { - for (sx = S0; sx < SSZ; sx++) { - if (sx >= dim_org->width) { + for (sx = 0; sx < SSZ; sx++) { + for (sy = 0; sy < SSZ; sy++) { + if (sx - S0 >= dim_org->width) { sample[sx][sy] = sample[sx - 1][sy]; equals++; continue; } - uint8_t i = ypix[sy][sx - S0]; + /* + * For pixels to the left of S0 there are no + * corresponding input pixels so just use + * ypix[sy][0]. + */ + uint8_t i = ypix[sy][MAX(0, sx - S0)]; if (pal_to_rgb(i, pal, header->colors_used, &sample[sx][sy])) goto bitmap_error; @@ -764,8 +887,6 @@ static int draw_bitmap_v3(const struct vector *top_left, equals = 1; } } - for (sx = S0 - 1; sx >= 0; sx--) - sample[sx][sy] = sample[S0][sy]; } ix = 0; @@ -1138,3 +1259,37 @@ int get_bitmap_dimension(const void *bitmap, size_t sz, struct scale *dim_rel) return CBGFX_SUCCESS; } + +int enable_graphics_buffer(void) +{ + if (gfx_buffer) + return CBGFX_SUCCESS; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + size_t buffer_size = fbinfo->y_resolution * fbinfo->bytes_per_line; + gfx_buffer = malloc(buffer_size); + if (!gfx_buffer) { + LOG("%s: Failed to create graphics buffer (%zu bytes).\n", + __func__, buffer_size); + return CBGFX_ERROR_GRAPHICS_BUFFER; + } + + return CBGFX_SUCCESS; +} + +int flush_graphics_buffer(void) +{ + if (!gfx_buffer) + return CBGFX_ERROR_GRAPHICS_BUFFER; + + memcpy(REAL_FB, gfx_buffer, fbinfo->y_resolution * fbinfo->bytes_per_line); + return CBGFX_SUCCESS; +} + +void disable_graphics_buffer(void) +{ + free(gfx_buffer); + gfx_buffer = NULL; +} diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index 5a1dd98a59..2b1e9e120c 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -194,4 +194,12 @@ struct mmu_memrange* mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges, */ void mmu_presysinfo_memory_used(uint64_t base, uint64_t size); void mmu_presysinfo_enable(void); + +/* + * Functions for exposing the used memory ranges to payloads. The ranges contain + * all used memory ranges that are actually used by payload. i.e. _start -> _end + * in linker script, the coreboot tables and framebuffer/DMA allocated in MMU + * initialization. + */ +const struct mmu_ranges *mmu_get_used_ranges(void); #endif // __ARCH_ARM64_MMU_H__ diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 397e08b301..fc4caa4417 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -49,7 +49,6 @@ #include #include #include -#include /** These are standard values for the known compression alogrithms that coreboot knows about for stages and diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h index 84e76f26d1..72e512267a 100644 --- a/payloads/libpayload/include/cbgfx.h +++ b/payloads/libpayload/include/cbgfx.h @@ -56,6 +56,8 @@ #define CBGFX_ERROR_FRAMEBUFFER_ADDR 0x15 /* portrait screen not supported */ #define CBGFX_ERROR_PORTRAIT_SCREEN 0x16 +/* cannot use buffered I/O */ +#define CBGFX_ERROR_GRAPHICS_BUFFER 0x17 struct fraction { int32_t n; @@ -132,6 +134,22 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, const struct fraction *thickness, const struct fraction *radius); +/** + * Draw a horizontal or vertical line segment on screen. If horizontal, pos1 + * must be the left endpoint. If vertical, pos1 must be the top endpoint. When + * the specified thickness is zero (or truncated to zero), a line with 1-pixel + * width will be drawn. + * + * @param[in] pos1 Start position of the line relative to the canvas. + * @param[in] pos2 End position of the line relative to the canvas. + * @param[in] thickness Thickness of the line relative to the canvas. + * @param[in] rgb Color of the line. + * + * @return CBGFX_* error codes + */ +int draw_line(const struct scale *pos1, const struct scale *pos2, + const struct fraction *thickness, const struct rgb_color *rgb); + /** * Clear the canvas */ @@ -211,6 +229,24 @@ int draw_bitmap_direct(const void *bitmap, size_t size, */ int get_bitmap_dimension(const void *bitmap, size_t sz, struct scale *dim_rel); +/** + * Setup color mappings of background and foreground colors. Black and white + * pixels will be mapped to the background and foreground colors, respectively. + * Call clear_color_map() to disabled color mapping. + * + * @param[in] background Background color. + * @param[in] foreground Foreground color. + * + * @return CBGFX_* error codes + */ +int set_color_map(const struct rgb_color *background, + const struct rgb_color *foreground); + +/** + * Clear color mappings. + */ +void clear_color_map(void); + /** * Setup alpha and rgb values for alpha blending. When alpha is != 0, * this enables a translucent layer of color (defined by rgb) to be @@ -228,8 +264,6 @@ int set_blend(const struct rgb_color *rgb, uint8_t alpha); /** * Clear alpha and rgb values, thus disabling any alpha blending. - * - * @return CBGFX_* error codes */ void clear_blend(void); @@ -240,3 +274,24 @@ void clear_blend(void); * 0 = min alpha argument, 0% opacity */ #define ALPHA(percentage) MIN(255, (256 * percentage / 100)) + +/** + * Enable buffered I/O. All CBGFX operations will be redirected to a working + * buffer, and only updated (redrawn) when flush_graphics_buffer() is called. + * + * @return CBGFX_* error codes + */ +int enable_graphics_buffer(void); + +/** + * Redraw buffered graphics data to real screen if graphics buffer is already + * enabled. + * + * @return CBGFX_* error codes + */ +int flush_graphics_buffer(void); + +/** + * Stop using buffered I/O and release allocated memory. + */ +void disable_graphics_buffer(void); diff --git a/payloads/libpayload/include/compiler.h b/payloads/libpayload/include/compiler.h index 0d56cbea4b..ee2ff88d10 100644 --- a/payloads/libpayload/include/compiler.h +++ b/payloads/libpayload/include/compiler.h @@ -1,29 +1,39 @@ -/* - * - * Copyright 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ -#ifndef __COMPILER_H__ -#define __COMPILER_H__ +#ifndef _COMMONLIB_BSD_COMPILER_H_ +#define _COMMONLIB_BSD_COMPILER_H_ +#ifndef __packed #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) #else #define __packed __attribute__((packed)) #endif +#endif +#ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) +#endif + +#ifndef __always_unused #define __always_unused __attribute__((unused)) +#endif + +#ifndef __must_check #define __must_check __attribute__((warn_unused_result)) +#endif + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif + +#ifndef __noreturn +#define __noreturn __attribute__((noreturn)) +#endif + +#ifndef __always_inline +#define __always_inline inline __attribute__((always_inline)) +#endif /* This evaluates to the type of the first expression, unless that is constant in which case it evalutates to the type of the second. This is useful when @@ -32,7 +42,7 @@ literals. By using this macro, the promotion can happen at the time the literal is assigned to the temporary variable. If the literal doesn't fit in the chosen type, -Werror=overflow will catch it, so this should be safe. */ -#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) typeof( \ +#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) __typeof__( \ __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) /* This creates a unique local variable name for use in macros. */ diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 91d3520ad5..e042a900b9 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -31,6 +31,7 @@ #include #include +#include enum { CB_TAG_UNUSED = 0x0000, @@ -78,6 +79,8 @@ enum { CB_TAG_MMC_INFO = 0x0035, CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, + CB_TAG_SMMSTOREV2 = 0x0039, + CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -258,10 +261,11 @@ struct cb_x86_rom_mtrr { uint32_t index; }; -struct cb_strapping_id { - uint32_t tag; +/* Memory map windows to translate addresses between SPI flash space and host address space. */ +struct flash_mmap_window { + uint32_t flash_base; + uint32_t host_base; uint32_t size; - uint32_t id_code; }; struct cb_spi_flash { @@ -270,6 +274,12 @@ struct cb_spi_flash { uint32_t flash_size; uint32_t sector_size; uint32_t erase_cmd; + /* + * Number of mmap windows used by the platform to decode addresses between SPI flash + * space and host address space. This determines the number of entries in mmap_table. + */ + uint32_t mmap_count; + struct flash_mmap_window mmap_table[0]; }; struct cb_boot_media_params { @@ -315,6 +325,16 @@ struct cb_mmc_info { int32_t early_cmd1_status; }; +struct cb_board_config { + uint32_t tag; + uint32_t size; + + struct cbuint64 fw_config; + uint32_t board_id; + uint32_t ram_code; + uint32_t sku_id; +}; + #define CB_MAX_SERIALNO_LENGTH 32 struct cb_cmos_option_table { @@ -395,5 +415,5 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) + (sizeof((_rec)->map[0]) * (_idx))) /* Helper functions */ -void *get_cbmem_ptr(unsigned char *ptr); +uintptr_t get_cbmem_addr(const void *cbmem_tab_entry); #endif diff --git a/payloads/libpayload/include/ctype.h b/payloads/libpayload/include/ctype.h index c1ca698e1c..98cb306180 100644 --- a/payloads/libpayload/include/ctype.h +++ b/payloads/libpayload/include/ctype.h @@ -50,5 +50,4 @@ int tolower(int c); int toupper(int c); /** @} */ - #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 25080d85ed..a33d8bb382 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -42,8 +42,8 @@ #ifndef _LIBPAYLOAD_H #define _LIBPAYLOAD_H +#include #include -#include #include #include #include @@ -186,7 +186,7 @@ int add_reset_handler(void (*new_handler)(void)); */ void keyboard_init(void); void keyboard_disconnect(void); -int keyboard_havechar(void); +bool keyboard_havechar(void); unsigned char keyboard_get_scancode(void); int keyboard_getchar(void); int keyboard_set_layout(char *country); @@ -233,11 +233,15 @@ u8 i8042_data_ready_ps2(void); u8 i8042_data_ready_aux(void); u8 i8042_read_data_ps2(void); +u8 i8042_peek_data_ps2(void); u8 i8042_read_data_aux(void); int i8042_wait_read_ps2(void); int i8042_wait_read_aux(void); +int i8042_get_kbd_translation(void); +int i8042_set_kbd_translation(bool xlate); + /** @} */ /** @@ -445,6 +449,8 @@ u8 hex2bin(u8 h); void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__((noreturn)); +/* Population Count: number of bits that are one */ +static inline int popcnt(u32 x) { return __builtin_popcount(x); } /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { @@ -454,8 +460,16 @@ static inline int clz(u32 x) static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -/** @} */ +static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } +static inline int clz64(u64 x) +{ + return x ? __builtin_clzll(x) : sizeof(x) * 8; +} + +static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } +static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } +/** @} */ /** * @defgroup mmio MMIO helper functions @@ -475,7 +489,6 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, #endif /** @} */ - /** * @defgroup hash Hashing functions * @{ diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 8c11d6b33f..5e21060130 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -66,6 +66,7 @@ #define PCI_ROM_ADDRESS1 0x38 // on bridges #define PCI_ROM_ADDRESS_MASK ~0x7ff +#define PCI_CLASS_STORAGE_AHCI 0x0106 #define PCI_CLASS_MEMORY_OTHER 0x0580 #define PCI_VENDOR_ID_INTEL 0x8086 @@ -74,6 +75,7 @@ struct pci_dev { u16 domain; u8 bus, dev, func; u16 vendor_id, device_id; + u16 device_class; struct pci_dev *next; }; diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index 7d579a7bc4..c9ac701987 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -344,7 +344,6 @@ struct { \ #define XSIMPLEQ_EMPTY(head) (XSIMPLEQ_FIRST(head) == XSIMPLEQ_END(head)) #define XSIMPLEQ_NEXT(head, elm, field) XSIMPLEQ_XOR(head, ((elm)->field.sqx_next)) - #define XSIMPLEQ_FOREACH(var, head, field) \ for ((var) = XSIMPLEQ_FIRST(head); \ (var) != XSIMPLEQ_END(head); \ @@ -398,7 +397,6 @@ struct { \ XSIMPLEQ_XOR(head, &(elm)->field.sqx_next); \ } while (0) - /* * Tail queue definitions. */ @@ -442,7 +440,6 @@ struct { \ ((tvar) = TAILQ_NEXT(var, field), 1); \ (var) = (tvar)) - #define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ for((var) = TAILQ_LAST(head, headname); \ (var) != TAILQ_END(head); \ diff --git a/payloads/libpayload/include/stdbool.h b/payloads/libpayload/include/stdbool.h new file mode 100644 index 0000000000..33858d51f2 --- /dev/null +++ b/payloads/libpayload/include/stdbool.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __STDBOOL_H +#define __STDBOOL_H + +#define bool _Bool +#define false 0 +#define true (!false) + +#endif diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 0aa032297a..18a0920a61 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -26,9 +26,11 @@ * SUCH DAMAGE. */ +#include + #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(void); +void ahci_initialize(struct pci_dev *dev); #endif diff --git a/payloads/libpayload/include/storage/ata.h b/payloads/libpayload/include/storage/ata.h index 39937dbe34..43249e7513 100644 --- a/payloads/libpayload/include/storage/ata.h +++ b/payloads/libpayload/include/storage/ata.h @@ -33,7 +33,6 @@ #include "storage.h" - /* ATA commands */ enum { ATA_READ_DMA = 0xc8, diff --git a/payloads/libpayload/include/storage/atapi.h b/payloads/libpayload/include/storage/atapi.h index eea5c332f8..5a6e244032 100644 --- a/payloads/libpayload/include/storage/atapi.h +++ b/payloads/libpayload/include/storage/atapi.h @@ -34,7 +34,6 @@ #include "storage.h" #include "ata.h" - /* ATAPI commands */ enum { ATAPI_TEST_UNIT_READY = 0x00, diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h index 7a2a84bef7..32933fd97c 100644 --- a/payloads/libpayload/include/storage/storage.h +++ b/payloads/libpayload/include/storage/storage.h @@ -32,14 +32,12 @@ #include #include - #if !CONFIG(LP_STORAGE_64BIT_LBA) typedef u32 lba_t; #else typedef u64 lba_t; #endif - typedef enum { PORT_TYPE_IDE = (1 << 0), PORT_TYPE_SATA = (1 << 1), @@ -54,7 +52,6 @@ typedef enum { POLL_MEDIUM_PRESENT = 1, } storage_poll_t; - struct storage_dev; typedef struct storage_dev { @@ -70,7 +67,6 @@ typedef struct storage_dev { int storage_device_count(void); int storage_attach_device(storage_dev_t *dev); - storage_poll_t storage_probe(size_t dev_num); ssize_t storage_read_blocks512(size_t dev_num, lba_t start, size_t count, unsigned char *buf); diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index ca263e4410..393881d9cc 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -83,5 +83,4 @@ size_t strlcpy(char *d, const char *s, size_t n); size_t strlcat(char *d, const char *s, size_t n); /** @} */ - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 6e83f684df..5a24e1405f 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -29,6 +29,9 @@ #ifndef _SYSINFO_H #define _SYSINFO_H +#include +#include + /* Maximum number of memory range definitions. */ #define SYSINFO_MAX_MEM_RANGES 32 /* Allow a maximum of 8 GPIOs */ @@ -37,19 +40,21 @@ /* Up to 10 MAC addresses */ #define SYSINFO_MAX_MACS 10 +/* Maximum of 2 MMAP windows for decoding SPI flash. */ +#define SYSINFO_MAX_MMAP_WINDOWS 2 + #include -struct cb_serial; - /* - * All pointers in here shall be virtual. + * This is a collection of information and pointers gathered + * mostly from the coreboot table. * - * If a relocation happens after the last call to lib_get_sysinfo(), - * it is up to the user to call lib_get_sysinfo() again. + * We do not store virtual pointers in here to avoid problems + * with self-relocating payloads. */ struct sysinfo_t { unsigned int cpu_khz; - struct cb_serial *serial; + uintptr_t cb_serial; unsigned short ser_ioport; unsigned long ser_base; // for mmapped serial @@ -61,62 +66,71 @@ struct sysinfo_t { unsigned int type; } memrange[SYSINFO_MAX_MEM_RANGES]; - struct cb_cmos_option_table *option_table; + uintptr_t cmos_option_table; u32 cmos_range_start; u32 cmos_range_end; u32 cmos_checksum_location; u32 vbnv_start; u32 vbnv_size; - char *version; - char *extra_version; - char *build; - char *compile_time; - char *compile_by; - char *compile_host; - char *compile_domain; - char *compiler; - char *linker; - char *assembler; + uintptr_t version; + uintptr_t extra_version; + uintptr_t build; + uintptr_t compile_time; + uintptr_t compile_by; + uintptr_t compile_host; + uintptr_t compile_domain; + uintptr_t compiler; + uintptr_t linker; + uintptr_t assembler; - char *cb_version; + uintptr_t cb_version; - struct cb_framebuffer *framebuffer; + struct cb_framebuffer framebuffer; int num_gpios; struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; int num_macs; struct mac_address macs[SYSINFO_MAX_MACS]; - char *serialno; + uintptr_t serialno; unsigned long *mbtable; /** Pointer to the multiboot table */ - struct cb_header *header; - struct cb_mainboard *mainboard; + uintptr_t cb_header; + uintptr_t cb_mainboard; - void *vboot_workbuf; + uintptr_t vboot_workbuf; #if CONFIG(LP_ARCH_X86) int x86_rom_var_mtrr_index; #endif - void *tstamp_table; - void *cbmem_cons; - void *mrc_cache; - void *acpi_gnvs; + uintptr_t tstamp_table; + uintptr_t cbmem_cons; + uintptr_t mrc_cache; + uintptr_t acpi_gnvs; -#define UNDEFINED_STRAPPING_ID (~0) +#define UNDEFINED_STRAPPING_ID (~0) +#define UNDEFINED_FW_CONFIG ~((uint64_t)0) u32 board_id; u32 ram_code; u32 sku_id; - void *wifi_calibration; + /* + * A payload using this field is responsible for ensuring it checks its + * value against UNDEFINED_FW_CONFIG before using it. + */ + u64 fw_config; + + uintptr_t wifi_calibration; uint64_t ramoops_buffer; uint32_t ramoops_buffer_size; struct { uint32_t size; uint32_t sector_size; uint32_t erase_cmd; + uint32_t mmap_window_count; + struct flash_mmap_window mmap_table[SYSINFO_MAX_MMAP_WINDOWS]; } spi_flash; uint64_t fmap_offset; uint64_t cbfs_offset; @@ -124,11 +138,15 @@ struct sysinfo_t { uint64_t boot_media_size; uint64_t mtc_start; uint32_t mtc_size; - void *chromeos_vpd; - int mmc_early_wake_status; + uintptr_t chromeos_vpd; + int mmc_early_wake_status; /* Pointer to FMAP cache in CBMEM */ - void *fmap_cache; + uintptr_t fmap_cache; + +#if CONFIG(LP_PCI) + struct pci_access pacc; +#endif }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index f79fc27711..43c7b4279d 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -334,7 +334,7 @@ int usb_interface_check(u16 vendor, u16 device); #define USB_QUIRK_TEST (1 << 31) #define USB_QUIRK_NONE 0 -static inline void usb_debug(const char *fmt, ...) +static inline void __attribute__((format(printf, 1, 2))) usb_debug(const char *fmt, ...) { #ifdef USB_DEBUG va_list ap; diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index 83733016fe..ddd606a072 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -32,4 +32,52 @@ #define cpuid(fn, eax, ebx, ecx, edx) \ asm("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "0"(fn)) +#define _declare_cpuid(reg) \ + static inline unsigned int cpuid_##reg(unsigned int fn) \ + { \ + unsigned int eax, ebx, ecx, edx; \ + cpuid(fn, eax, ebx, ecx, edx); \ + return reg; \ + } + +_declare_cpuid(eax) +_declare_cpuid(ebx) +_declare_cpuid(ecx) +_declare_cpuid(edx) + +#undef _declare_cpuid + +static inline unsigned int cpuid_max(void) +{ + return cpuid_eax(0); +} + +static inline unsigned int cpuid_family(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xff00000) >> (20 - 4) | (eax & 0xf00) >> 8; +} + +static inline unsigned int cpuid_model(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; +} + +enum intel_fam6_model { + NEHALEM = 0x25, + SANDYBRIDGE = 0x2a, + IVYBRIDGE = 0x3a, + HASWELL = 0x3c, + BROADWELL_U = 0x3d, + HASWELL_U = 0x45, + HASWELL_GT3E = 0x46, + BROADWELL = 0x47, + SKYLAKE_U_Y = 0x4e, + APOLLOLAKE = 0x5c, + SKYLAKE_S_H = 0x5e, + KABYLAKE_U_Y = 0x8e, + KABYLAKE_S_H = 0x9e, +}; + #endif diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index c6fb57fde9..7e23afe2e5 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -41,10 +41,10 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -void *get_cbmem_ptr(unsigned char *ptr) +uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - return phys_to_virt(cbmem->cbmem_tab); + const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry; + return cbmem->cbmem_tab; } static void cb_parse_memory(void *ptr, struct sysinfo_t *info) @@ -80,12 +80,12 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info) static void cb_parse_serial(void *ptr, struct sysinfo_t *info) { - info->serial = ((struct cb_serial *)ptr); + info->cb_serial = virt_to_phys(ptr); } static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) { - info->vboot_workbuf = get_cbmem_ptr(ptr); + info->vboot_workbuf = get_cbmem_addr(ptr); } static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) @@ -130,42 +130,33 @@ static void cb_parse_mac_addresses(unsigned char *ptr, static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { - info->tstamp_table = get_cbmem_ptr(ptr); + info->tstamp_table = get_cbmem_addr(ptr); } static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) { - info->cbmem_cons = get_cbmem_ptr(ptr); + info->cbmem_cons = get_cbmem_addr(ptr); } static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { - info->acpi_gnvs = get_cbmem_ptr(ptr); + info->acpi_gnvs = get_cbmem_addr(ptr); } -static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_strapping_id *const cbbid = (struct cb_strapping_id *)ptr; - info->board_id = cbbid->id_code; -} - -static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_strapping_id *const ram_code = (struct cb_strapping_id *)ptr; - info->ram_code = ram_code->id_code; -} - -static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_strapping_id *const sku_id = (struct cb_strapping_id *)ptr; - info->sku_id = sku_id->id_code; + struct cb_board_config *const config = (struct cb_board_config *)ptr; + info->fw_config = cb_unpack64(config->fw_config); + info->board_id = config->board_id; + info->ram_code = config->ram_code; + info->sku_id = config->sku_id; } #if CONFIG(LP_NVRAM) static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { - /* ptr points to a coreboot table entry and is already virtual */ - info->option_table = ptr; + /* ptr is already virtual, but we want to keep physical addresses */ + info->cmos_option_table = virt_to_phys(ptr); } static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) @@ -180,19 +171,21 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) #if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { - /* ptr points to a coreboot table entry and is already virtual */ - info->framebuffer = ptr; + info->framebuffer = *(struct cb_framebuffer *)ptr; } #endif -static void cb_parse_string(unsigned char *ptr, char **info) +static void cb_parse_string(const void *const ptr, uintptr_t *const info) { - *info = (char *)((struct cb_string *)ptr)->string; + /* ptr is already virtual (str->string just an offset to that), + but we want to keep physical addresses */ + const struct cb_string *const str = ptr; + *info = virt_to_phys(str->string); } static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) { - info->wifi_calibration = get_cbmem_ptr(ptr); + info->wifi_calibration = get_cbmem_addr(ptr); } static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) @@ -218,6 +211,13 @@ static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info) info->spi_flash.size = flash->flash_size; info->spi_flash.sector_size = flash->sector_size; info->spi_flash.erase_cmd = flash->erase_cmd; + + if (flash->mmap_count == 0) + return; + + info->spi_flash.mmap_window_count = MIN(flash->mmap_count, SYSINFO_MAX_MMAP_WINDOWS); + memcpy(info->spi_flash.mmap_table, flash->mmap_table, + info->spi_flash.mmap_window_count * sizeof(struct flash_mmap_window)); } static void cb_parse_boot_media_params(unsigned char *ptr, @@ -233,12 +233,12 @@ static void cb_parse_boot_media_params(unsigned char *ptr, static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) { - info->chromeos_vpd = get_cbmem_ptr(ptr); + info->chromeos_vpd = get_cbmem_addr(ptr); } static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) { - info->fmap_cache = get_cbmem_ptr(ptr); + info->fmap_cache = get_cbmem_addr(ptr); } #if CONFIG(LP_TIMER_RDTSC) @@ -282,12 +282,13 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; - info->header = header; + info->cb_header = virt_to_phys(header); /* Initialize IDs as undefined in case they don't show up in table. */ info->board_id = UNDEFINED_STRAPPING_ID; info->ram_code = UNDEFINED_STRAPPING_ID; info->sku_id = UNDEFINED_STRAPPING_ID; + info->fw_config = UNDEFINED_FW_CONFIG; /* Now, walk the tables. */ ptr += header->header_bytes; @@ -353,7 +354,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) break; #endif case CB_TAG_MAINBOARD: - info->mainboard = (struct cb_mainboard *)ptr; + info->cb_mainboard = virt_to_phys(ptr); break; case CB_TAG_GPIO: cb_parse_gpios(ptr, info); @@ -379,14 +380,8 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_ACPI_GNVS: cb_parse_acpi_gnvs(ptr, info); break; - case CB_TAG_BOARD_ID: - cb_parse_board_id(ptr, info); - break; - case CB_TAG_RAM_CODE: - cb_parse_ram_code(ptr, info); - break; - case CB_TAG_SKU_ID: - cb_parse_sku_id(ptr, info); + case CB_TAG_BOARD_CONFIG: + cb_parse_board_config(ptr, info); break; case CB_TAG_WIFI_CALIBRATION: cb_parse_wifi_calibration(ptr, info); diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 8b22daa9cc..20f9ef38e1 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -123,7 +123,8 @@ int dma_coherent(void *ptr) return !dma_initialized() || (dma->start <= ptr && dma->end > ptr); } -static void *alloc(int len, struct memory_type *type) +/* Find free block of size >= len */ +static hdrtype_t volatile *find_free_block(int len, struct memory_type *type) { hdrtype_t header; hdrtype_t volatile *ptr = (hdrtype_t volatile *)type->start; @@ -156,37 +157,53 @@ static void *alloc(int len, struct memory_type *type) halt(); } - if (header & FLAG_FREE) { - if (len <= size) { - hdrtype_t volatile *nptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + len); - int nsize = size - (HDRSIZE + len); - - /* If there is still room in this block, - * then mark it as such otherwise account - * the whole space for that block. - */ - - if (nsize > 0) { - /* Mark the block as used. */ - *ptr = USED_BLOCK(len); - - /* Create a new free block. */ - *nptr = FREE_BLOCK(nsize); - } else { - /* Mark the block as used. */ - *ptr = USED_BLOCK(size); - } - - return (void *)((uintptr_t)ptr + HDRSIZE); - } - } + if ((header & FLAG_FREE) && len <= size) + return ptr; ptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + size); } while (ptr < (hdrtype_t *) type->end); /* Nothing available. */ - return (void *)NULL; + return NULL; +} + +/* Mark the block with length 'len' as used */ +static void use_block(hdrtype_t volatile *ptr, int len) +{ + /* Align the size. */ + len = ALIGN_UP(len, HDRSIZE); + + hdrtype_t volatile *nptr = (hdrtype_t volatile *) + ((uintptr_t)ptr + HDRSIZE + len); + int size = SIZE(*ptr); + int nsize = size - (HDRSIZE + len); + + /* + * If there is still room in this block, then mark it as such otherwise + * account the whole space for that block. + */ + if (nsize > 0) { + /* Mark the block as used. */ + *ptr = USED_BLOCK(len); + + /* Create a new free block. */ + *nptr = FREE_BLOCK(nsize); + } else { + /* Mark the block as used. */ + *ptr = USED_BLOCK(size); + } +} + +static void *alloc(int len, struct memory_type *type) +{ + hdrtype_t volatile *ptr = find_free_block(len, type); + + if (ptr == NULL) + return NULL; + + use_block(ptr, len); + return (void *)((uintptr_t)ptr + HDRSIZE); } static void _consolidate(struct memory_type *type) @@ -229,6 +246,10 @@ void free(void *ptr) hdrtype_t hdr; struct memory_type *type = heap; + /* No action occurs on NULL. */ + if (ptr == NULL) + return; + /* Sanity check. */ if (ptr < type->start || ptr >= type->end) { type = dma; @@ -277,6 +298,7 @@ void *calloc(size_t nmemb, size_t size) void *realloc(void *ptr, size_t size) { void *ret, *pptr; + hdrtype_t volatile *block; unsigned int osize; struct memory_type *type = heap; @@ -300,18 +322,23 @@ void *realloc(void *ptr, size_t size) * reallocated the new space. */ free(ptr); - ret = alloc(size, type); + + block = find_free_block(size, type); + if (block == NULL) + return NULL; + + ret = (void *)((uintptr_t)block + HDRSIZE); /* - * if ret == NULL, then doh - failure. - * if ret == ptr then woo-hoo! no copy needed. + * If ret == ptr, then no copy is needed. Otherwise, move the memory to + * the new location, which might be before the old one and overlap since + * the free() above includes a _consolidate(). */ - if (ret == NULL || ret == ptr) - return ret; + if (ret != ptr) + memmove(ret, ptr, osize > size ? size : osize); - /* Move the memory to the new location. Might be before the old location - and overlap since the free() above includes a _consolidate(). */ - memmove(ret, ptr, osize > size ? size : osize); + /* Mark the block as used. */ + use_block(block, size); return ret; } diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index daa53f1bcb..fff295e54c 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -90,7 +90,7 @@ static void *default_memmove(void *dst, const void *src, size_t n) ssize_t i; if (src > dst) - return memcpy(dst, src, n); + return default_memcpy(dst, src, n); if (!IS_ALIGNED((uintptr_t)dst, sizeof(unsigned long)) || !IS_ALIGNED((uintptr_t)src, sizeof(unsigned long))) { @@ -145,7 +145,6 @@ static int default_memcmp(const void *s1, const void *s2, size_t n) int memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("default_memcmp"))); - void *memchr(const void *s, int c, size_t n) { unsigned char *p = (unsigned char *)s; diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index a481fef7eb..46c3c019bd 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -521,7 +521,6 @@ unsigned long int strtoul(const char *ptr, char **endptr, int base) return val; } - /** * Determine the number of leading characters in s that match characters in a * @param s A pointer to the string to analyse diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index c0a3313e86..6780008d4c 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -31,11 +31,14 @@ * General time functions */ +#define __STDC_FORMAT_MACROS + #include #include #if CONFIG(LP_ARCH_X86) && CONFIG(LP_NVRAM) #include #endif +#include extern u32 cpu_khz; @@ -173,7 +176,7 @@ u64 timer_us(u64 base) if (hz == 0) { hz = timer_hz(); if (hz < 1000000) { - printf("Timer frequency %lld is too low, " + printf("Timer frequency %" PRIu64 " is too low, " "must be at least 1MHz.\n", hz); halt(); } diff --git a/payloads/libpayload/liblzma/lzmadecode.c b/payloads/libpayload/liblzma/lzmadecode.c index 1cf647d27b..c8115d308a 100644 --- a/payloads/libpayload/liblzma/lzmadecode.c +++ b/payloads/libpayload/liblzma/lzmadecode.c @@ -33,12 +33,10 @@ #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } #define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) @@ -56,7 +54,6 @@ do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \ res -= (1 << numLevels); } - #define kNumPosBitsMax 4 #define kNumPosStatesMax (1 << kNumPosBitsMax) @@ -74,7 +71,6 @@ #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) #define kNumLenProbs (LenHigh + kLenNumHighSymbols) - #define kNumStates 12 #define kNumLitStates 7 @@ -143,7 +139,6 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; int lc = vs->Properties.lc; - int state = 0; UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; int len = 0; @@ -164,7 +159,6 @@ int LzmaDecode(CLzmaDecoderState *vs, RC_INIT(inStream, inSize); - while(nowPos < outSize) { CProb *prob; @@ -379,7 +373,6 @@ int LzmaDecode(CLzmaDecoderState *vs, if (rep0 > nowPos) return LZMA_RESULT_DATA_ERROR; - do { previousByte = outStream[nowPos - rep0]; @@ -391,7 +384,6 @@ int LzmaDecode(CLzmaDecoderState *vs, } RC_NORMALIZE; - *inSizeProcessed = (SizeT)(Buffer - inStream); *outSizeProcessed = nowPos; return LZMA_RESULT_OK; diff --git a/payloads/libpayload/liblzma/lzmadecode.h b/payloads/libpayload/liblzma/lzmadecode.h index 34c9f14c33..05ff0a3397 100644 --- a/payloads/libpayload/liblzma/lzmadecode.h +++ b/payloads/libpayload/liblzma/lzmadecode.h @@ -32,7 +32,6 @@ typedef UInt32 SizeT; #define LZMA_RESULT_OK 0 #define LZMA_RESULT_DATA_ERROR 1 - #define LZMA_BASE_SIZE 1846 #define LZMA_LIT_SIZE 768 @@ -56,10 +55,8 @@ typedef struct _CLzmaDecoderState CLzmaProperties Properties; CProb *Probs; - } CLzmaDecoderState; - int LzmaDecode(CLzmaDecoderState *vs, const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 27347e3bf8..200ae18435 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -72,8 +72,7 @@ int pci_write_long(struct pci_dev *dev, int pos, u32 data) struct pci_access *pci_alloc(void) { - struct pci_access *pacc = malloc(sizeof(*pacc)); - return pacc; + return malloc(sizeof(struct pci_access)); } void pci_init(struct pci_access *pacc) @@ -179,6 +178,7 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, uint8_t bus) dev->func = func; dev->vendor_id = val & 0xffff; dev->device_id = (uint16_t)(val >> 16); + dev->device_class = pci_read_config16(PCI_DEV(bus, slot, func), PCI_CLASS_DEVICE); dev->next = 0; hdr = pci_read_config8(PCI_DEV(bus, slot, func), diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index eb70af90b7..637e45dee1 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -28,7 +28,7 @@ # Sample libpayload Makefile. include ../.config -include ../.xcompile +include ../build/xcompile ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 diff --git a/payloads/nvramcui/.gitignore b/payloads/nvramcui/.gitignore new file mode 100644 index 0000000000..4885853d42 --- /dev/null +++ b/payloads/nvramcui/.gitignore @@ -0,0 +1,2 @@ +build +libpayload diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index bf7053b9a6..269d558d19 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -26,9 +26,9 @@ else endif clean: - rm -f nvramcui.elf + rm -rf build libpayload nvramcui.elf distclean: clean - rm -rf build libpayload .config .config.old + rm -rf .config .config.old .PHONY: all clean distclean diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index ee3de1cde0..db3e522d60 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -37,7 +37,7 @@ static int max(int x, int y) return y; } -void render_form(FORM *form) +static void render_form(FORM *form) { int y, x, line; WINDOW *w = form_win(form); diff --git a/src/Kconfig b/src/Kconfig index a4c2fa6010..33065cbddb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -270,6 +270,45 @@ config UBSAN say N because it adds a small performance penalty and may abort on code that happens to work in spite of the UB. +config HAVE_ASAN_IN_ROMSTAGE + bool + default n + +config ASAN_IN_ROMSTAGE + bool + default n + help + Enable address sanitizer in romstage for platform. + +config HAVE_ASAN_IN_RAMSTAGE + bool + default n + +config ASAN_IN_RAMSTAGE + bool + default n + help + Enable address sanitizer in ramstage for platform. + +config ASAN + bool "Address sanitizer support" + default n + select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE + select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE + help + Enable address sanitizer - runtime memory debugger, + designed to find out-of-bounds accesses and use-after-scope bugs. + + This feature consumes up to 1/8 of available memory and brings about + ~1.5x performance slowdown. + + If unsure, say N. + +if ASAN + comment "Before using this feature, make sure that " + comment "asan_shadow_offset_callback patch is applied to GCC." +endif + choice prompt "Stage Cache for ACPI S3 resume" default NO_STAGE_CACHE if !HAVE_ACPI_RESUME @@ -497,6 +536,17 @@ source "src/vendorcode/*/Kconfig" source "src/arch/*/Kconfig" +config CHIPSET_DEVICETREE + string + default "" + help + This symbol allows a chipset to provide a set of default settings in + a devicetree which are common to all mainboards. This may include + devices (including alias names), chip drivers, register settings, + and others. This path is relative to the src/ directory. + + Example: "chipset.cb" + endmenu source "src/device/Kconfig" @@ -504,6 +554,7 @@ source "src/device/Kconfig" menu "Generic Drivers" source "src/drivers/*/Kconfig" source "src/drivers/*/*/Kconfig" +source "src/drivers/*/*/*/Kconfig" source "src/commonlib/storage/Kconfig" endmenu @@ -839,7 +890,7 @@ config DEBUG_SMI bool "Output verbose SMI debug messages" default n depends on HAVE_SMI_HANDLER - select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH + select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH help This option enables additional SMI related debug messages. @@ -854,7 +905,7 @@ config DEBUG_PERIODIC_SMI # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config DEBUG_MALLOC - prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 + prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL bool default n help @@ -864,6 +915,15 @@ config DEBUG_MALLOC If unsure, say N. +# Only visible if DEBUG_SPEW (8) is set. +config DEBUG_RESOURCES + bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL + default n + help + This option enables additional PCI memory and IO debug messages. + Note: This option will increase the size of the coreboot image. + If unsure, say N. + config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n @@ -879,7 +939,7 @@ config DEBUG_CONSOLE_INIT # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config REALMODE_DEBUG - prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 + prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL bool default n depends on PCI_OPTION_ROM_RUN_REALMODE @@ -1053,15 +1113,14 @@ config DEBUG_INTEL_ME is present on Intel 6-series chipsets. endif -config TRACE - bool "Trace function calls" +config DEBUG_FUNC + bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 default n help - If enabled, every function will print information to console once - the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) - the 0xaaaabbbb is the actual function and 0xccccdddd is EIP - of calling function. Please note some printk related functions - are omitted from trace to have good looking console dumps. + This option enables additional function entry and exit debug messages + for select functions. + Note: This option will increase the size of the coreboot image. + If unsure, say N. config DEBUG_COVERAGE bool "Debug code coverage" @@ -1105,7 +1164,6 @@ config EM100 endmenu - ############################################################################### # Set variables with no prompt - these can be set anywhere, and putting at # the end of this file gives the most flexibility. diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 07008db7a9..2727889f9e 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,8 +24,11 @@ config ACPI_INTEL_HARDWARE_SLEEP_VALUES Provide common definitions for Intel hardware PM1_CNT register sleep values. -config ACPI_NO_SMI_GNVS +config ACPI_SOC_NVS bool + help + Set to indicate exists for the platform with a definition + for global_nvs. config ACPI_NO_PCAT_8259 bool @@ -37,3 +40,9 @@ config HAVE_ACPI_TABLES help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. + +config ACPI_LPIT + bool + depends on HAVE_ACPI_TABLES + help + Selected by platforms that support and fill Intel Low Power Idle Table. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index f70b23ff5b..1cd837dd88 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dptf.c ramstage-y += acpigen_dsm.c @@ -11,10 +12,13 @@ ramstage-y += acpigen_usb.c ramstage-y += device.c ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c ramstage-y += gnvs.c +ramstage-$(CONFIG_ACPI_SOC_NVS) += nvs.c ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c +postcar-y += acpi_pm.c + ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c endif diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index ccd8d2526d..6f64d108f9 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -468,7 +468,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { struct device *dev; for (dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_fill_ssdt) + if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt) dev->ops->acpi_fill_ssdt(dev); current = (unsigned long) acpigen_get_current(); } @@ -752,7 +752,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->revision = get_acpi_table_revision(HPET); /* Fill out HPET address. */ - addr->space_id = 0; /* Memory */ + addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; addr->bit_width = 64; addr->bit_offset = 0; addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; @@ -878,6 +878,35 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, header->checksum = acpi_checksum((void *)ivrs, header->length); } +void acpi_create_crat(struct acpi_crat_header *crat, + unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, + unsigned long current)) +{ + acpi_header_t *header = &(crat->header); + unsigned long current = (unsigned long)crat + sizeof(struct acpi_crat_header); + + memset((void *)crat, 0, sizeof(struct acpi_crat_header)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "CRAT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(struct acpi_crat_header); + header->revision = get_acpi_table_revision(CRAT); + + current = acpi_fill_crat(crat, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)crat; + header->checksum = acpi_checksum((void *)crat, header->length); +} + unsigned long acpi_write_hpet(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -1251,14 +1280,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) /* should be 0 ACPI 3.0 */ fadt->reserved = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) - fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) - fadt->preferred_pm_profile = PM_TABLET; - else - fadt->preferred_pm_profile = PM_DESKTOP; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); arch_fill_fadt(fadt); @@ -1271,6 +1293,44 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) acpi_checksum((void *) fadt, header->length); } +void acpi_create_lpit(acpi_lpit_t *lpit) +{ + acpi_header_t *header = &(lpit->header); + unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); + + memset((void *)lpit, 0, sizeof(acpi_lpit_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "LPIT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->revision = get_acpi_table_revision(LPIT); + header->oem_revision = 42; + header->length = sizeof(acpi_lpit_t); + + current = acpi_fill_lpit(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)lpit; + header->checksum = acpi_checksum((void *)lpit, header->length); +} + +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid) +{ + memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t)); + lpi_desc->header.length = sizeof(acpi_lpi_desc_ncst_t); + lpi_desc->header.type = ACPI_LPI_DESC_TYPE_NATIVE_CSTATE; + lpi_desc->header.uid = uid; + + return lpi_desc->header.length; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -1291,6 +1351,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_tcpa_t *tcpa; acpi_tpm2_t *tpm2; acpi_madt_t *madt; + acpi_lpit_t *lpit; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -1347,9 +1408,7 @@ unsigned long write_acpi_tables(unsigned long start) return fw; } - dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; @@ -1362,12 +1421,12 @@ unsigned long write_acpi_tables(unsigned long start) return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); + slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size); if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) - || memcmp(slic_file->signature, "SLIC", 4) != 0)) { + || (memcmp(slic_file->signature, "SLIC", 4) != 0 + && memcmp(slic_file->signature, "MSDM", 4) != 0))) { slic_file = 0; } @@ -1413,6 +1472,9 @@ unsigned long write_acpi_tables(unsigned long start) current += sizeof(acpi_header_t); acpigen_set_current((char *) current); + + acpi_fill_gnvs(); + for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_inject_dsdt) dev->ops->acpi_inject_dsdt(dev); @@ -1487,6 +1549,18 @@ unsigned long write_acpi_tables(unsigned long start) } } + if (CONFIG(ACPI_LPIT)) { + printk(BIOS_DEBUG, "ACPI: * LPIT\n"); + + lpit = (acpi_lpit_t *)current; + acpi_create_lpit(lpit); + if (lpit->header.length >= sizeof(acpi_lpit_t)) { + current += lpit->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, lpit); + } + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; @@ -1495,6 +1569,7 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); } + current = acpi_align_current(current); printk(BIOS_DEBUG, "current = %lx\n", current); @@ -1540,7 +1615,7 @@ void *acpi_find_wakeup_vector(void) void *wake_vec; int i; - if (!acpi_is_wakeup()) + if (!acpi_is_wakeup_s3()) return NULL; printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); @@ -1626,7 +1701,7 @@ int get_acpi_table_revision(enum acpi_tables table) case VFCT: /* ACPI 2.0/3.0/4.0: 1 */ return 1; case IVRS: - return IVRS_FORMAT_FIXED; + return IVRS_FORMAT_MIXED; case DBG2: return 0; case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ @@ -1643,6 +1718,10 @@ int get_acpi_table_revision(enum acpi_tables table) return 5; case BERT: return 1; + case CRAT: + return 1; + case LPIT: /* ACPI 5.1 up to 6.3: 0 */ + return 0; default: return -1; } diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c new file mode 100644 index 0000000000..540b6d2bee --- /dev/null +++ b/src/acpi/acpi_pm.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* This is filled with acpi_handoff_wakeup_s3() call early in ramstage. */ +static int acpi_slp_type = -1; + +static void acpi_handoff_wakeup(void) +{ + if (acpi_slp_type < 0) { + if (romstage_handoff_is_resume()) { + printk(BIOS_DEBUG, "S3 Resume\n"); + acpi_slp_type = ACPI_S3; + } else { + printk(BIOS_DEBUG, "Normal boot\n"); + acpi_slp_type = ACPI_S0; + } + } +} + +int acpi_handoff_wakeup_s3(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S3); +} + +void __weak mainboard_suspend_resume(void) +{ +} + +/* Default mapping to ACPI FADT preferred_pm_profile field. */ +uint8_t acpi_get_preferred_pm_profile(void) +{ + switch (smbios_mainboard_enclosure_type()) { + case SMBIOS_ENCLOSURE_LAPTOP: + case SMBIOS_ENCLOSURE_CONVERTIBLE: + return PM_MOBILE; + case SMBIOS_ENCLOSURE_DETACHABLE: + case SMBIOS_ENCLOSURE_TABLET: + return PM_TABLET; + case SMBIOS_ENCLOSURE_DESKTOP: + return PM_DESKTOP; + case SMBIOS_ENCLOSURE_UNKNOWN: + default: + return PM_UNSPECIFIED; + } +} diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index a4a74f65d7..9a5543d5a4 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -10,6 +10,8 @@ #define ACPIGEN_MAXLEN 0xfffff +#define CPPC_PACKAGE_NAME "GCPC" + #include #include #include @@ -284,12 +286,15 @@ static void acpigen_emit_multi_namestring(const char *name) pathlen[0] = count; } - void acpigen_emit_namestring(const char *namepath) { int dotcount = 0, i; int dotpos = 0; + /* Check for NULL pointer */ + if (!namepath) + return; + /* We can start with a '\'. */ if (namepath[0] == '\\') { acpigen_emit_byte('\\'); @@ -341,7 +346,7 @@ void acpigen_write_scope(const char *name) void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op) { - /* = DeRefOf ([ = DeRefOf ([]) */ acpigen_write_store(); acpigen_emit_byte(DEREF_OP); acpigen_emit_byte(INDEX_OP); @@ -351,6 +356,52 @@ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, ui acpigen_emit_byte(dest_op); } +void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src) +{ + /* DeRefOf ([]) = */ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_byte(package_op); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op) +{ + /* = [] */ + acpigen_write_store(); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ + acpigen_emit_byte(dest_op); +} + +void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src) +{ + /* [] = */ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +void acpigen_set_package_element_namestr(const char *package, unsigned int element, + const char *src) +{ + /* [] = */ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* @@ -409,7 +460,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores) * len is region length. * OperationRegion(regionname, regionspace, regionoffset, regionlength) */ -void acpigen_write_opregion(struct opregion *opreg) +void acpigen_write_opregion(const struct opregion *opreg) { /* OpregionOp */ acpigen_emit_ext_op(OPREGION_OP); @@ -506,6 +557,12 @@ static void acpigen_write_field_name(const char *name, uint32_t size) acpigen_write_field_length(size); } +static void acpigen_write_field_reserved(uint32_t size) +{ + acpigen_emit_byte(0); + acpigen_write_field_length(size); +} + /* * Generate ACPI AML code for Field * Arg0: region name @@ -516,6 +573,7 @@ static void acpigen_write_field_name(const char *name, uint32_t size) * struct fieldlist l[] = { * FIELDLIST_OFFSET(0x84), * FIELDLIST_NAMESTR("PMCS", 2), + * FIELDLIST_RESERVED(6), * }; * acpigen_write_field("UART", l, ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK | * FIELD_PRESERVE); @@ -523,7 +581,8 @@ static void acpigen_write_field_name(const char *name, uint32_t size) * Field (UART, AnyAcc, NoLock, Preserve) * { * Offset (0x84), - * PMCS, 2 + * PMCS, 2, + * , 6, * } */ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, @@ -547,6 +606,10 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou acpigen_write_field_name(l[i].name, l[i].bits); current_bit_pos += l[i].bits; break; + case RESERVED: + acpigen_write_field_reserved(l[i].bits); + current_bit_pos += l[i].bits; + break; case OFFSET: acpigen_write_field_offset(l[i].bits, current_bit_pos); current_bit_pos = l[i].bits; @@ -687,7 +750,7 @@ void acpigen_write_empty_PTC(void) .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 0, .bit_offset = 0, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0, .addrh = 0, }; @@ -833,6 +896,23 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, coreFreq, power, control, status); } +void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries) +{ + size_t pstate; + + acpigen_write_name("_PSS"); + acpigen_write_package(nentries); + for (pstate = 0; pstate < nentries; pstate++) { + acpigen_write_PSS_package( + pstate_values->core_freq, pstate_values->power, + pstate_values->transition_latency, pstate_values->bus_master_latency, + pstate_values->control_value, pstate_values->status_value); + pstate_values++; + } + + acpigen_pop_len(); +} + void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { acpigen_write_name("_PSD"); @@ -851,8 +931,8 @@ void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { acpigen_write_package(4); acpigen_write_register_resource(&cstate->resource); - acpigen_write_dword(cstate->ctype); - acpigen_write_dword(cstate->latency); + acpigen_write_byte(cstate->ctype); + acpigen_write_word(cstate->latency); acpigen_write_dword(cstate->power); acpigen_pop_len(); } @@ -862,7 +942,7 @@ void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) int i; acpigen_write_name("_CST"); acpigen_write_package(nentries+1); - acpigen_write_dword(nentries); + acpigen_write_integer(nentries); for (i = 0; i < nentries; i++) acpigen_write_CST_package_entry(cstate + i); @@ -876,7 +956,7 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, acpigen_write_name("_CSD"); acpigen_write_package(1); acpigen_write_package(6); - acpigen_write_byte(6); // 6 values + acpigen_write_integer(6); // 6 values acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); @@ -930,8 +1010,6 @@ void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) acpigen_pop_len(); } - - void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* @@ -1217,6 +1295,22 @@ void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst) acpigen_emit_namestring(dst); } +/* Store (src, "namestr") */ +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_namestring(dst); +} + +/* Store (src, dst) */ +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(dst); +} + /* Or (arg1, arg2, res) */ void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) { @@ -1276,6 +1370,14 @@ void acpigen_write_debug_op(uint8_t op) acpigen_emit_ext_op(DEBUG_OP); } +/* Store (str, DEBUG) */ +void acpigen_write_debug_namestr(const char *str) +{ + acpigen_write_store(); + acpigen_emit_namestring(str); + acpigen_emit_ext_op(DEBUG_OP); +} + void acpigen_write_if(void) { acpigen_emit_byte(IF_OP); @@ -1339,6 +1441,14 @@ void acpigen_write_else(void) acpigen_write_len_f(); } +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count) +{ + acpigen_emit_byte(SHIFT_LEFT_OP); + acpigen_emit_byte(src_result); + acpigen_write_integer(count); + acpigen_emit_byte(ZERO_OP); +} + void acpigen_write_to_buffer(uint8_t src, uint8_t dst) { acpigen_emit_byte(TO_BUFFER_OP); @@ -1353,6 +1463,13 @@ void acpigen_write_to_integer(uint8_t src, uint8_t dst) acpigen_emit_byte(dst); } +void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op) +{ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_namestring(source); + acpigen_emit_byte(dst_op); +} + void acpigen_write_byte_buffer(uint8_t *arr, size_t size) { size_t i; @@ -1396,6 +1513,12 @@ void acpigen_write_return_integer(uint64_t arg) acpigen_write_integer(arg); } +void acpigen_write_return_namestr(const char *arg) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(arg); +} + void acpigen_write_return_string(const char *arg) { acpigen_emit_byte(RETURN_OP); @@ -1521,8 +1644,6 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count) acpigen_pop_len(); /* Method _DSM */ } -#define CPPC_PACKAGE_NAME "\\GCPC" - void acpigen_write_CPPC_package(const struct cppc_config *config) { u32 i; @@ -1553,7 +1674,7 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) for (i = 0; i < max; ++i) { const acpi_addr_t *reg = &(config->regs[i]); if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY && - reg->bit_width == 32 && reg->access_size == 0) { + reg->bit_width == 32 && reg->access_size == ACPI_ACCESS_SIZE_UNDEFINED) { acpigen_write_dword(reg->addrl); } else { acpigen_write_register_resource(reg); @@ -1564,9 +1685,12 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) void acpigen_write_CPPC_method(void) { + char pscope[16]; + snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + acpigen_write_method("_CPC", 0); acpigen_emit_byte(RETURN_OP); - acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_emit_namestring(pscope); acpigen_pop_len(); } @@ -1772,7 +1896,6 @@ void acpigen_write_rom(void *bios, const size_t length) acpigen_pop_len(); } - /* Soc-implemented functions -- weak definitions. */ int __weak acpigen_soc_read_rx_gpio(unsigned int gpio_num) { @@ -1809,7 +1932,7 @@ int __weak acpigen_soc_clear_tx_gpio(unsigned int gpio_num) * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); @@ -1817,7 +1940,7 @@ int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) return acpigen_soc_set_tx_gpio(gpio->pins[0]); } -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_set_tx_gpio(gpio->pins[0]); @@ -1825,7 +1948,7 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } -void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_read_rx_gpio(gpio->pins[0]); @@ -1833,7 +1956,7 @@ void acpigen_get_rx_gpio(struct acpi_gpio *gpio) acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } -void acpigen_get_tx_gpio(struct acpi_gpio *gpio) +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_get_tx_gpio(gpio->pins[0]); @@ -1971,3 +2094,103 @@ void acpigen_notify(const char *namestr, int value) acpigen_emit_namestring(namestr); acpigen_write_integer(value); } + +static void _create_field(uint8_t aml_op, uint8_t srcop, size_t byte_offset, const char *name) +{ + acpigen_emit_byte(aml_op); + acpigen_emit_byte(srcop); + acpigen_write_integer(byte_offset); + acpigen_emit_namestring(name); +} + +void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_BYTE_OP, op, byte_offset, name); +} + +void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_WORD_OP, op, byte_offset, name); +} + +void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_DWORD_OP, op, byte_offset, name); +} + +void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_QWORD_OP, op, byte_offset, name); +} + +void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts) +{ + acpigen_write_name("_PCT"); + acpigen_write_package(0x02); + acpigen_write_register_resource(perf_ctrl); + acpigen_write_register_resource(perf_sts); + + acpigen_pop_len(); +} + +void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value) +{ + acpigen_write_package(0x08); + acpigen_write_dword(pstate_value->core_freq); + acpigen_write_dword(pstate_value->power); + acpigen_write_dword(pstate_value->transition_latency); + acpigen_write_dword(pstate_value->bus_master_latency); + + acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_value, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_value, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_mask, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_mask, sizeof(uint64_t)); + + acpigen_pop_len(); +} + +void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, size_t nentries) +{ + size_t pstate; + + acpigen_write_name("XPSS"); + acpigen_write_package(nentries); + for (pstate = 0; pstate < nentries; pstate++) { + acpigen_write_xpss_package(pstate_values); + pstate_values++; + } + + acpigen_pop_len(); +} + +/* Delay up to wait_ms until provided namestr matches expected value. */ +void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value) +{ + uint32_t wait_ms_segment = 1; + uint32_t segments = wait_ms; + + /* Sleep in 16ms segments if delay is more than 32ms. */ + if (wait_ms > 32) { + wait_ms_segment = 16; + segments = wait_ms / 16; + } + + acpigen_write_store_int_to_op(segments, LOCAL7_OP); + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_emit_byte(ZERO_OP); + + /* If name is not provided then just delay in a loop. */ + if (name) { + acpigen_write_if_lequal_namestr_int(name, value); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } + + acpigen_write_sleep(wait_ms_segment); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_pop_len(); /* While */ +} diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 0c44b8f8ba..3877daa88b 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -2,6 +2,8 @@ #include #include +#include +#include /* Defaults */ #define DEFAULT_RAW_UNIT "ma" @@ -17,6 +19,7 @@ enum { DEFAULT_TRIP_POINT = 0xFFFFFFFFull, DEFAULT_WEIGHT = 100, DPTF_MAX_ART_THRESHOLDS = 10, + FPS_REVISION = 0, PPCC_REVISION = 2, RAPL_PL1_INDEX = 0, RAPL_PL2_INDEX = 1, @@ -353,7 +356,8 @@ void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count) /* _FPS - Fan Performance States */ acpigen_write_name("_FPS"); - pkg_count = acpigen_write_package(0); + pkg_count = acpigen_write_package(1); /* 1 for Revision */ + acpigen_write_integer(FPS_REVISION); /* revision */ for (i = 0; i < max_count; ++i) { /* diff --git a/src/acpi/acpigen_dsm.c b/src/acpi/acpigen_dsm.c index 2336537d0b..fc53ddff4d 100644 --- a/src/acpi/acpigen_dsm.c +++ b/src/acpi/acpigen_dsm.c @@ -7,28 +7,27 @@ #define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" +/* I2C HID currently supports revision 1 only, for which, only 1 additional + * function is supported. Thus, the query function should return 0x3: + * bit 0 = additional function supported + * bit 1 = function with index 1 supported + * All other revisions do not support additional functions and hence return 0 +*/ + static void i2c_hid_func0_cb(void *arg) { /* ToInteger (Arg1, Local2) */ acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); - /* If (LEqual (Local2, 0x0)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x0); - /* Return (Buffer (One) { 0x1f }) */ - acpigen_write_return_singleton_buffer(0x1f); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3 }) */ + acpigen_write_return_singleton_buffer(0x3); acpigen_pop_len(); /* Pop : If */ /* Else */ acpigen_write_else(); - /* If (LEqual (Local2, 0x1)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); - /* Return (Buffer (One) { 0x3f }) */ - acpigen_write_return_singleton_buffer(0x3f); - acpigen_pop_len(); /* Pop : If */ - /* Else */ - acpigen_write_else(); /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); /* Pop : Else */ - acpigen_pop_len(); /* Pop : Else */ } static void i2c_hid_func1_cb(void *arg) diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 1379a89c18..be20220e31 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -1,13 +1,12 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include #include +#include +#include #define KEYMAP(scancode, keycode) (((uint32_t)(scancode) << 16) | (keycode & 0xFFFF)) #define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF) diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 90a9b77c60..7448b3b569 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -71,7 +71,7 @@ static void add_device_ref(struct acpi_dp *dsd, const char *path; char *fresh; - if (!dev) + if (!dev || !dev->enabled) return; /* diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c index 4bcf892745..8d96769160 100644 --- a/src/acpi/chromeos-gnvs.c +++ b/src/acpi/chromeos-gnvs.c @@ -6,7 +6,10 @@ void gnvs_assign_chromeos(void) { - chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(); + chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs()); + if (!gnvs_chromeos) + return; + chromeos_init_chromeos_acpi(gnvs_chromeos); /* EC can override to ECFW_RW. */ @@ -15,3 +18,12 @@ void gnvs_assign_chromeos(void) if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; } + +void gnvs_set_ecfw_rw(void) +{ + chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs()); + if (!gnvs_chromeos) + return; + + gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; +} diff --git a/src/acpi/device.c b/src/acpi/device.c index b119abd61f..5de31b7776 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #if CONFIG(GENERIC_GPIO_LIB) @@ -197,7 +198,6 @@ int acpi_device_status(const struct device *dev) return ACPI_STATUS_DEVICE_ALL_ON; } - /* Write the unique _UID based on ACPI device path. */ void acpi_device_write_uid(const struct device *dev) { @@ -1019,33 +1019,72 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, return dp_array; } +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const struct acpi_gpio_res_params *params, + size_t param_count) +{ + struct acpi_dp *gpio; + uint32_t i; + + if (!dp || !param_count) + return NULL; + + gpio = acpi_dp_new_table(name); + if (!gpio) + return NULL; + + /* + * Generate ACPI identifiers as follows: + * Package () { + * name, // e.g. cs-gpios + * Package() { + * ref, index, pin, active_low, // GPIO-0 (params[0]) + * ref, index, pin, active_low, // GPIO-1 (params[1]) + * ... + * } + * } + */ + for (i = 0; i < param_count; i++, params++) { + /* + * If refs is NULL, leave a hole in the gpio array. This can be used in + * conditions where some controllers use both GPIOs and native signals. + */ + if (!params->ref) { + acpi_dp_add_integer(gpio, NULL, 0); + continue; + } + + /* The device that has _CRS containing GpioIO()/GpioInt() */ + acpi_dp_add_reference(gpio, NULL, params->ref); + + /* Index of the GPIO resource in _CRS starting from zero */ + acpi_dp_add_integer(gpio, NULL, params->index); + + /* Pin in the GPIO resource, typically zero */ + acpi_dp_add_integer(gpio, NULL, params->pin); + + /* Set if pin is active low */ + acpi_dp_add_integer(gpio, NULL, params->active_low); + } + acpi_dp_add_array(dp, gpio); + + return gpio; + +} + + struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low) { - if (!dp) - return NULL; + struct acpi_gpio_res_params param = { + .ref = ref, + .index = index, + .pin = pin, + .active_low = active_low, + }; - struct acpi_dp *gpio = acpi_dp_new_table(name); - - if (!gpio) - return NULL; - - /* The device that has _CRS containing GpioIO()/GpioInt() */ - acpi_dp_add_reference(gpio, NULL, ref); - - /* Index of the GPIO resource in _CRS starting from zero */ - acpi_dp_add_integer(gpio, NULL, index); - - /* Pin in the GPIO resource, typically zero */ - acpi_dp_add_integer(gpio, NULL, pin); - - /* Set if pin is active low */ - acpi_dp_add_integer(gpio, NULL, active_low); - - acpi_dp_add_array(dp, gpio); - - return gpio; + return acpi_dp_add_gpio_array(dp, name, ¶m, 1); } /* diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index fbc84b36fd..10a77d39de 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -24,11 +24,20 @@ void *acpi_get_gnvs(void) static void gnvs_assign_cbmc(void) { - uint32_t *gnvs_cbmc = gnvs_cbmc_ptr(); + uint32_t *gnvs_cbmc = gnvs_cbmc_ptr(gnvs); if (gnvs_cbmc) *gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); } +/* Needs implementation in platform code. */ +__weak uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs_) +{ + return NULL; +} + +__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { } +__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { } + void *gnvs_get_or_create(void) { size_t gnvs_size; @@ -41,10 +50,12 @@ void *gnvs_get_or_create(void) return gnvs; gnvs_size = gnvs_size_of_array(); + if (!gnvs_size) + return NULL; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size); if (!gnvs) - return gnvs; + return NULL; memset(gnvs, 0, gnvs_size); @@ -57,13 +68,15 @@ void *gnvs_get_or_create(void) return gnvs; } -void acpi_inject_nvsa(void) +void acpi_fill_gnvs(void) { - uintptr_t gnvs_address = (uintptr_t)acpi_get_gnvs(); - if (!gnvs_address) + if (!gnvs) return; + soc_fill_gnvs(gnvs); + mainboard_fill_gnvs(gnvs); + acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", gnvs_address); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); acpigen_pop_len(); } diff --git a/src/acpi/nvs.c b/src/acpi/nvs.c new file mode 100644 index 0000000000..063819158c --- /dev/null +++ b/src/acpi/nvs.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +size_t gnvs_size_of_array(void) +{ + return sizeof(struct global_nvs); +} + +uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs) +{ + return &gnvs->cbmc; +} + +/* Some have no chromeos entry. */ +#if CONFIG(MAINBOARD_HAS_CHROMEOS) +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} +#endif diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index eef2650685..63367bb2c0 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -27,11 +27,6 @@ endif # CONFIG_ARCH_ARM ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h - decompressor-y += boot.c bootblock-y += boot.c decompressor-y += div0.c @@ -119,6 +114,8 @@ ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += clock.c +ramstage-y += boot_linux.S +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c rmodules_arm-y += memset.S rmodules_arm-y += memcpy.S diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 5f34c6049b..0ed11ac8d1 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -5,7 +5,6 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ - #include void tlb_invalidate_all(void) diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index e1879c0b30..47813a78f8 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -62,14 +62,43 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop + /* Set stackpointer in internal RAM */ + ldr sp, =_estack + + /* + * For platforms where the flash is memory mapped (qemu), check if the + * bootblock needs to relocate itself. + */ +check_position: + adr r0, check_position + ldr r1, =check_position + + cmp r0, r1 + beq call_bootblock + + /* Calculate source */ + ldr r2, =_program + sub r1, r1, r2 + sub r1, r0, r1 + /* Get destination */ + ldr r0, =_program + /* Get size */ + ldr r2, =_eprogram + sub r2, r2, r0 + + bl memcpy + + /* Get absolute address */ + ldr lr, =call_bootblock + /* Directly modify pc as branch instruction changes the state */ + mov pc, lr + call_bootblock: /* Restore parameter passed in by maskrom/vendor firmware. */ ldr r0, =maskrom_param str r10, [r0] - /* Set stackpointer in internal RAM to call bootblock main() */ - ldr sp, =_estack ldr r0,=0x00000000 /* * The current design of cpu_info places the struct at the top of the diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c index 7267e83948..06ed599c44 100644 --- a/src/arch/arm/armv7/cache_m.c +++ b/src/arch/arm/armv7/cache_m.c @@ -3,7 +3,6 @@ * cache.c: Cache maintenance routines for ARMv7-M */ - #include void tlb_invalidate_all(void) diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 610659243d..c53119c8d1 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -23,6 +23,19 @@ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 */ +#if ENV_USER_SPACE +/* + * Empty macro for code running in userspace. Trying to manipulate the + * cache from userspace hangs the system. To run code at a privileged level, + * the userspace code needs to execute an API call to the privileged mode + * code. + */ +.macro dcache_apply_all crm + bx lr +.endm + +#else + .macro dcache_apply_all crm dsb mov r3, #-2 @ initialize level so that we start at 0 @@ -82,6 +95,8 @@ bx lr .endm +#endif /* ENV_USER_SPACE */ + /* * Bring an ARM processor we just gained control of (e.g. from IROM) into a * known state regarding caches/SCTLR. Completely cleans and invalidates diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 51b4860768..66ce53392d 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -87,9 +87,6 @@ typedef uint32_t pte_t; static pte_t *const ttb_buff = (void *)_ttb; -/* Not all boards want to use subtables and declare them in memlayout.ld. */ -DECLARE_OPTIONAL_REGION(ttb_subtables); - static struct { pte_t value; const char *name; diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 8c876de0b0..b18473b924 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -1,14 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +void boot_linux(void *kernel_ptr, void *fdt_ptr); + void arch_prog_run(struct prog *prog) { void (*doit)(void *); cache_sync_instructions(); - doit = prog_entry(prog); - doit(prog_entry_arg(prog)); + switch (prog_cbfs_type(prog)) { + case CBFS_TYPE_FIT: + /* + * We only load Linux payloads from the ramstage, so provide a hint to + * the linker that the below functions do not need to be included in + * earlier stages. + */ + if (!ENV_RAMSTAGE) + break; + + dcache_mmu_disable(); + boot_linux(prog_entry(prog), prog_entry_arg(prog)); + break; + default: + doit = prog_entry(prog); + doit(prog_entry_arg(prog)); + } } diff --git a/src/arch/arm/boot_linux.S b/src/arch/arm/boot_linux.S new file mode 100644 index 0000000000..e3985eae56 --- /dev/null +++ b/src/arch/arm/boot_linux.S @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Required to jump to kernel in ARM state */ +.arm +/* void boot_linux(void *kernel_ptr, void *fdt_ptr); */ +ENTRY(boot_linux) + /* Save kernel ptr */ + mov r3, r0 + /* Set R2 = fdt */ + mov r2, r1 + /* Set R0 = 0x00000000 as expected by Linux ABI */ + mov r0, #0 + /* Set R1 = 0xffffffff as expected by Linux ABI */ + mov r1, #-1 + /* Linux ABI expects SVC mode (0x13) with IRQ(7) and FIQ(6) disabled. */ + msr cpsr_cxf, #0xd3 + /* Jump to kernel */ + mov pc, r3 +ENDPROC(boot_linux) diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c new file mode 100644 index 0000000000..9777e3c1e5 --- /dev/null +++ b/src/arch/arm/fit_payload.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/** + * Place the region in free memory range. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + void *arg = NULL; + + /** + * The kernel ARM documentation recommends loading the kernel above 32MiB + * in order to avoid the need to need to relocate prior to decompression. + */ + kernel->offset = (uintptr_t)_dram + 32 * MiB; + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + if (!bootmem_walk(fit_place_mem, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * To ensure the fdt is not overwritten by the kernel decompressor, place + * the fdt above the 128 MB from the start of RAM, as recommended by the + * kernel documentation. + */ + fdt->offset = (uintptr_t)_dram + 128 * MiB; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = fdt->offset + fdt->size; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/arch/arm/id.S b/src/arch/arm/id.S deleted file mode 100644 index 3d3df9643a..0000000000 --- a/src/arch/arm/id.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h index 5245bd1a02..0a3a4d4676 100644 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ b/src/arch/arm/include/armv4/arch/smp/spinlock.h @@ -4,12 +4,10 @@ #define _ARCH_SMP_SPINLOCK_H #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #include #define boot_cpu() 1 diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 3b47a5bf0c..0c68fc7c51 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -11,8 +11,6 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { - DECLARE_OPTIONAL_REGION(ttb_subtables); - bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE); bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables), BM_MEM_RAMSTAGE); diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 920ff5db51..6b49743633 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -26,11 +26,8 @@ decompressor-y += div0.c bootblock-y += div0.c decompressor-y += eabi_compat.c bootblock-y += eabi_compat.c -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h +decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 88e68e759e..f3a075522e 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -63,10 +63,8 @@ static void print_regs(struct exc_state *exc_state) regs->x[30], regs->sp); } - static struct exception_handler *handlers[NUM_EXC_VIDS]; - int exception_handler_register(uint64_t vid, struct exception_handler *h) { if (vid >= NUM_EXC_VIDS) @@ -122,7 +120,6 @@ static void print_exception_and_die(struct exc_state *state, uint64_t idx) die("exception death"); } - static int handle_exception(struct exc_state *state, uint64_t idx) { int ret = EXC_RET_ABORT; diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S deleted file mode 100644 index 3d3df9643a..0000000000 --- a/src/arch/arm64/id.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index 58bedda9c5..72ed772500 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -27,7 +27,6 @@ struct exception_handler { struct exception_handler *next; }; - /* * Register a handler provided with the associated vector id. Returns 0 on * success, < 0 on error. Note that registration is not thread/interrupt safe. diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 321d348602..b97297c1b9 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -5,8 +5,6 @@ #include #include -DECLARE_OPTIONAL_REGION(bl31); - void arch_write_tables(uintptr_t coreboot_table) { } diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 106c61ad95..b443f056d1 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -8,27 +8,3 @@ .org 0x100, 0xff _start: b _start - .section ".id", "a", %progbits - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz "4" //COREBOOT_VERSION -vendor: - .asciz "qemu" //CONFIG_MAINBOARD_VENDOR -part: - .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor - /* Reverse offset to the part number */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part - /* of this romimage */ -.long CONFIG_ROM_SIZE - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/ppc64/id.ld b/src/arch/ppc64/id.ld deleted file mode 100644 index 74497408b2..0000000000 --- a/src/arch/ppc64/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - *(.id) - } -} diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index d3d15ff055..f8c1121f1a 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -17,13 +17,11 @@ static inline void outl(uint32_t value, uint16_t port) { } - static inline uint8_t inb(uint16_t port) { return 0; } - static inline uint16_t inw(uint16_t port) { return 0; diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc deleted file mode 100644 index 21f7d49ac3..0000000000 --- a/src/arch/ppc64/prologue.inc +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 7e9072b6cd..ad678b7fe5 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 5501a0c710..c1894c70ca 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -12,7 +12,6 @@ void mstatus_init(void); // need to setup mstatus so we know we have virtual memory - #define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \ static inline type name(type *p); \ static inline type name(type *p) \ diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index eff51fc96e..a17b7dd454 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -132,7 +131,6 @@ static struct memory_instruction_info *match_instruction(uintptr_t insn) return NULL; } - static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) { uint16_t ins = mprv_read_mxr_u16((uint16_t *)vaddr); @@ -158,7 +156,6 @@ static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) return -1; } - void handle_misaligned(trapframe *tf) { uintptr_t insn = 0; diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 38fc05e210..654bef03d6 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -49,7 +49,6 @@ static uintptr_t sbi_clear_ipi(void) return 0; } - /* * sbi is triggered by the s-mode ecall * parameter : register a0 a1 a2 diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index b3e13ff9fb..1d58602627 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 4935ef5ece..9fc75f455c 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -5,8 +5,6 @@ #include #include -DECLARE_OPTIONAL_REGION(opensbi); - void arch_write_tables(uintptr_t coreboot_table) { } diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 660ff2d4d2..4de8c96f1c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -4,6 +4,7 @@ config ARCH_X86 bool select PCI select RELOCATABLE_MODULES + select HAVE_ASAN_IN_RAMSTAGE # stage selectors for x86 @@ -27,6 +28,13 @@ config ARCH_RAMSTAGE_X86_32 bool select ARCH_X86 +config ARCH_ALL_STAGES_X86_32 + bool + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + # stage selectors for x64 config ARCH_BOOTBLOCK_X86_64 @@ -49,12 +57,19 @@ config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 +config ARCH_ALL_STAGES_X86_64 + bool + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 + if ARCH_X86 config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 - default 0xfffea000 + default 0xfffe9000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. @@ -73,16 +88,6 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 && SMP -config X86_RESET_VECTOR - hex - depends on ARCH_X86 - default 0xfffffff0 - help - Specify the location of the x86 reset vector. In traditional devices - this must match the architectural reset vector to produce a bootable - image. Nontraditional designs may use this to position the reset - vector into its desired location. - config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 @@ -139,6 +144,13 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated +config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings. + config PC80_SYSTEM bool default y if ARCH_X86 @@ -174,10 +186,6 @@ config HPET_ADDRESS hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE -config ID_SECTION_OFFSET - hex - default 0x80 - # 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00690ba02e..2d3cda7e78 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -45,25 +45,6 @@ pci$(stripped_vgabios_dgpu_id).rom-type := optionrom # common support for early assembly includes ############################################################################### -# Chipset specific assembly stubs in the romstage program flow. Certain -# boards have more than one assembly stub so collect those and put them -# into a single generated file. -crt0s = $(cpu_incs-y) - -$(objgenerated)/assembly.inc: build-dirs $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ - - -define early_x86_assembly_entry_rule -# $1 stage name -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated assembly.inc is a proper -# dependency. -$(1)-y += assembly_entry.S -$(call src-to-obj,$(1),$(dir)/assembly_entry.S): $(objgenerated)/assembly.inc -endef - define early_x86_stage # $1 stage name # $2 oformat @@ -98,6 +79,7 @@ bootblock-y += memmove.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += gdt_init.S bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c @@ -121,6 +103,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += assembly_entry.S verstage-y += boot.c verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S @@ -142,8 +125,6 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c verstage-libs ?= -$(eval $(call early_x86_assembly_entry_rule,verstage)) - ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y) $(eval $(call early_x86_stage,verstage,elf32-i386)) else @@ -158,11 +139,9 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +romstage-y += assembly_entry.S romstage-y += boot.c romstage-y += post.c -# gdt_init.S is included by entry32.inc when romstage is the first C -# environment. romstage-y += gdt_init.S romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c @@ -178,8 +157,6 @@ romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= -$(eval $(call early_x86_assembly_entry_rule,romstage)) - ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call early_x86_stage,romstage,elf32-i386)) else @@ -195,10 +172,13 @@ endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 # postcar ############################################################################### +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) $(eval $(call create_class_compiler,postcar,x86_32)) +else +$(eval $(call create_class_compiler,postcar,x86_64)) +endif postcar-generic-ccopts += -D__POSTCAR__ -postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += post.c postcar-y += gdt_init.S @@ -241,6 +221,7 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += post.c ramstage-y += c_start.S +ramstage-y += c_exit.S ramstage-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c @@ -255,6 +236,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios_defaults.c ramstage-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 4872c07228..ec1fafcd3c 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -5,48 +5,8 @@ #include #include #include -#include #include #include -#include - -#if ENV_RAMSTAGE || ENV_POSTCAR - -/* This is filled with acpi_is_wakeup() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_is_wakeup(void) -{ - acpi_handoff_wakeup(); - /* Both resume from S2 and resume from S3 restart at CPU reset */ - return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); -} - -int acpi_is_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - -int acpi_is_wakeup_s4(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S4); -} -#endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 @@ -55,12 +15,10 @@ asmlinkage void (*acpi_do_wakeup)(uintptr_t vector) = (void *)WAKEUP_BASE; extern unsigned char __wakeup; extern unsigned int __wakeup_size; -static void acpi_jump_to_wakeup(void *vector) +void __noreturn acpi_resume(void *wake_vec) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); - return; - } + /* Call mainboard resume handler first, if defined. */ + mainboard_suspend_resume(); /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); @@ -69,21 +27,8 @@ static void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector); -} - -void __weak mainboard_suspend_resume(void) -{ -} - -void acpi_resume(void *wake_vec) -{ - /* Restore GNVS pointer in SMM if found. */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Call mainboard resume handler first, if defined. */ - mainboard_suspend_resume(); - post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); + acpi_do_wakeup((uintptr_t)wake_vec); + + die("Failed the jump to wakeup vector\n"); } diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index fb48469c55..31670c29b6 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -15,12 +15,22 @@ #define _STACK_TOP _ecar_stack #endif +#ifdef __x86_64__ +.code64 +#else +.code32 +#endif + .section ".text._start", "ax", @progbits .global _start _start: /* Migrate GDT to this text segment */ +#ifdef __x86_64__ + call gdt_init64 +#else call gdt_init +#endif /* reset stack pointer to CAR/EARLYRAM stack */ mov $_STACK_TOP, %esp @@ -49,6 +59,10 @@ debug_spinloop: #if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif + +#if CONFIG(ASAN_IN_ROMSTAGE) + call asan_init +#endif call car_stage_entry /* Expect to never return. */ diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index db9d69e74d..777a0b7d90 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) { @@ -19,6 +21,13 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) void arch_prog_run(struct prog *prog) { +#if ENV_RAMSTAGE && defined(__x86_64__) + const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); + const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); + + /* On x86 coreboot payloads expect to be called in protected mode */ + protected_mode_jump(entry, arg); +#else #ifdef __x86_64__ void (*doit)(void *arg); #else @@ -27,4 +36,5 @@ void arch_prog_run(struct prog *prog) #endif doit = prog_entry(prog); doit(prog_entry_arg(prog)); +#endif } diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld new file mode 100644 index 0000000000..479259fcbe --- /dev/null +++ b/src/arch/x86/bootblock.ld @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +gdtptr_offset = gdtptr & 0xffff; +nullidt_offset = nullidt & 0xffff; + +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +#if CONFIG(SIPI_VECTOR_IN_ROM) +_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); +ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +#endif + +SECTIONS { + /* Trigger an error if I have an unusable start address */ + _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + + . = _ID_SECTION; + .id (.): { + KEEP(*(.id)); + } + + /* Flashrom and FILO have two alternatives for the location of .id section. */ + _ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR; + _ID_SECTION = _ID_SECTION_END - SIZEOF(.id); + + . = _FIT_POINTER; + .fit_pointer (.): { + KEEP(*(.fit_pointer)); + } + _FIT_POINTER = SIZEOF(.fit_pointer) ? 0xffffffc0 : _X86_RESET_VECTOR; + + . = 0xfffffff0; + _X86_RESET_VECTOR = .; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413e70..387920e38a 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@ #include -.section .text +.section .init._start, "ax", @progbits /* * Include the old code for reset vector and protected mode entry. That code has @@ -20,12 +20,6 @@ #include #include - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 3fbdbec2cd..e2dfcf4610 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -18,7 +18,7 @@ int legacy_romstage_selector(struct prog *romstage) const char *boot_candidate; size_t stages_len; - boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len); + boot_candidate = cbfs_map("coreboot-stages", &stages_len); if (!boot_candidate) boot_candidate = default_filenames; diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S new file mode 100644 index 0000000000..e5b9bf8d74 --- /dev/null +++ b/src/arch/x86/c_exit.S @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + + +#ifdef __x86_64__ + + /* + * Functions to handle mode switches from long mode to protected + * mode. + */ +.text +.code64 + .section ".text.protected_mode_jump", "ax", @progbits + .globl protected_mode_jump +protected_mode_jump: + + push %rbp + mov %rsp, %rbp + + /* Arguments to stack */ + push %rdi + push %rsi + + #include + + movl -8(%ebp), %eax /* Function to call */ + movl -16(%ebp), %ebx /* Argument 0 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + subl $12, %esp + pushl %ebx /* Argument 0 */ + + jmp *%eax +#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 4e2ae08a47..8bebf87435 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -91,6 +91,10 @@ _start: andl $0xFFFFFFF0, %esp +#if CONFIG(ASAN_IN_RAMSTAGE) + call asan_init +#endif + #if CONFIG(GDB_WAIT) call gdb_hw_init call gdb_stub_breakpoint @@ -138,10 +142,10 @@ gdtaddr: /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot - * which is defined in entry32.inc + * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple - * gdt from ROM (that in entry32.inc) which only contains those + * gdt from ROM (that in gdt_init.S) which only contains those * entries we need for protected mode. * * When we're executing code from RAM, we want to do more complex @@ -231,10 +235,4 @@ setCodeSelectorLongJump: # restore rsp, it might not have been 16-byte aligned on entry mov %rdx, %rsp ret - - .previous -.code64 -#else - .previous -.code32 #endif diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 17b774845b..9f8c2ad045 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -11,18 +11,17 @@ /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; + . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ -#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 12K) #endif - /* Vboot measured boot TCPA log measurements. - * Needs to be transferred until CBMEM is available - */ #if CONFIG(TPM_MEASURED_BOOT) + /* Vboot measured boot TCPA log measurements. + * Needs to be transferred until CBMEM is available */ TPM_TCPA_LOG(., 2K) #endif /* Stack for CAR stages. Since it persists across all stages that @@ -33,8 +32,8 @@ _ecar_stack = .; /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that - * multiple stages (romstage and verstage) have a consistent - * link address of these shared objects. */ + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG(PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); @@ -49,14 +48,17 @@ TIMESTAMP(., 0x200) +#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + . += 80; + _ecar_ehci_dbg_info = .; /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -72,8 +74,12 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; - _car_unallocated_start = .; +#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) + _shadow_size = (_ebss - _car_region_start) >> 3; + REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) +#endif + _car_unallocated_start = .; _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } . = _car_region_end; @@ -106,7 +112,7 @@ _rom_mtrr_base = _rom_mtrr_mask; . = 0xffffff00; .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); @@ -114,3 +120,7 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE) +_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); +_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); +#endif diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 939a862e3c..d054cfe72c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -287,7 +287,6 @@ void cpu_initialize(unsigned int index) printk(BIOS_DEBUG, "Using generic CPU ops (good)\n"); } - /* Initialize the CPU */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 958ebfc41c..f10c7bf8ba 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -180,8 +180,6 @@ static uint32_t gdb_stub_registers[NUM_REGS]; #define GDB_EXC_SOFTWARE 149 /* Software generated exception */ #define GDB_EXC_BREAKPOINT 150 /* Breakpoint */ - - static unsigned char exception_to_signal[] = { [0] = GDB_SIGFPE, /* divide by zero */ [1] = GDB_SIGTRAP, /* debug exception */ @@ -222,7 +220,6 @@ static const char hexchars[] = "0123456789abcdef"; static char in_buffer[BUFMAX]; static char out_buffer[BUFMAX]; - static inline void stub_putc(int ch) { gdb_tx_byte(ch); @@ -283,7 +280,6 @@ static void copy_to_hex(char *buf, void *addr, unsigned long count) *buf = 0; } - /* convert the hex array pointed to by buf into binary to be placed in mem */ /* return a pointer to the character AFTER the last byte written */ static void copy_from_hex(void *addr, char *buf, unsigned long count) @@ -298,7 +294,6 @@ static void copy_from_hex(void *addr, char *buf, unsigned long count) } } - /* scan for the sequence $# */ static int get_packet(char *buffer) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a921ee5d7d..fae7899e17 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -2,6 +2,7 @@ #include #include +#include .section ".module_parameters", "aw", @progbits /* stack_top indicates the stack to pull MTRR information from. */ @@ -10,6 +11,30 @@ post_car_stack_top: .long 0 .long 0 +#if defined(__x86_64__) +.code64 +.macro pop_eax_edx + pop %rax + mov %rax, %rdx + shr $32, %rdx +.endm +.macro pop_ebx_esi + pop %rbx + mov %rbx, %rsi + shr $32, %rsi +.endm +#else +.code32 +.macro pop_eax_edx + pop %eax + pop %edx +.endm +.macro pop_ebx_esi + pop %ebx + pop %esi +.endm +#endif + .text .global _start _start: @@ -17,7 +42,11 @@ _start: is expected to be implemented in assembly. */ /* Migrate GDT to this text segment */ +#if defined(__x86_64__) + call gdt_init64 +#else call gdt_init +#endif #ifdef __x86_64__ mov %rdi, _cbmem_top_ptr @@ -26,15 +55,27 @@ _start: movl 4(%esp), %eax movl %eax, _cbmem_top_ptr #endif + /* Make sure _cbmem_top_ptr hits dram before invd */ + movl $1, %eax + cpuid + btl $CPUID_FEATURE_CLFLUSH_BIT, %edx + jnc skip_clflush + clflush _cbmem_top_ptr +skip_clflush: /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car /* Enable caching if not already enabled. */ +#ifdef __x86_64__ + mov %cr0, %rax + and $(~(CR0_CD | CR0_NW)), %eax + mov %rax, %cr0 +#else mov %cr0, %eax and $(~(CR0_CD | CR0_NW)), %eax mov %eax, %cr0 - +#endif /* Ensure cache is clean. */ invd @@ -61,8 +102,13 @@ _start: /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp +#if defined(__x86_64__) + mov %rbp, %rdi +#else sub $12, %esp push %ebp +#endif + call soc_set_mtrrs /* Ignore fixing up %esp since we're setting it a new value. */ @@ -73,7 +119,7 @@ _start: call soc_enable_mtrrs #else /* CONFIG_SOC_SETS_MSRS */ /* Clear variable MTRRs. */ - pop %ebx /* Number to clear */ + pop_ebx_esi /* ebx: Number to clear, esi: Number to set */ test %ebx, %ebx jz 2f xor %eax, %eax @@ -89,23 +135,20 @@ _start: 2: /* Set Variable MTRRs based on stack contents. */ - pop %ebx /* Number to set. */ - test %ebx, %ebx + test %esi, %esi jz 2f mov $(MTRR_PHYS_BASE(0)), %ecx 1: /* Write MTRR base. */ - pop %eax - pop %edx + pop_eax_edx wrmsr inc %ecx /* Write MTRR mask. */ - pop %eax - pop %edx + pop_eax_edx wrmsr inc %ecx - dec %ebx + dec %esi jnz 1b 2: diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index d90aba64d3..f33a1517d8 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .code32 -.section ".text._gdt_", "ax", @progbits + +.section .init, "ax", @progbits + +.section .init._gdt_, "ax", @progbits .globl gdt_init gdt_init: @@ -15,6 +18,35 @@ gdtptr: .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ +#ifdef __x86_64__ +.code64 +.section .init._gdt64_, "ax", @progbits + .globl gdt_init64 +gdt_init64: + /* Workaround a bug in the assembler. + * The following code doesn't work: + * lgdt gdtptr64 + * + * The assembler tries to save memory by using 32bit displacement addressing mode. + * Displacements are using signed integers. + * This is fine in protected mode, as the negative address points to the correct + * address > 2GiB, but in long mode this doesn't work at all. + * Tests showed that QEMU can gracefully handle it, but real CPUs can't. + * + * Use the movabs pseudo instruction to force using a 64bit absolute address. + */ + movabs $gdtptr64, %rax + lgdt (%rax) + ret + +.previous + .align 4 +.globl gdtptr64 +gdtptr64: + .word gdt_end - gdt -1 /* compute the table limit */ + .quad gdt /* we know the offset */ +#endif + .align 4 gdt: /* selgdt 0, unused */ diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 798b25d1f1..574a7dcb91 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -2,27 +2,23 @@ #include - .section ".id", "a", @progbits +.section ".id", "a", @progbits - .globl __id_start -__id_start: ver: .asciz COREBOOT_VERSION vendor: .asciz CONFIG_MAINBOARD_VENDOR part: .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the - *vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the - * vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the - * part number - */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end -__id_end: -.previous +#if ENV_X86_64 +.long 0xffffffff - ver + 1 /* Reverse offset to the version */ +.long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */ +.long 0xffffffff - part + 1 /* Reverse offset to the part number */ +#else +.long - ver /* Reverse offset to the version */ +.long - vendor /* Reverse offset to the vendor id */ +.long - part /* Reverse offset to the part number */ +#endif + +.long CONFIG_ROM_SIZE /* Size of this romimage */ diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index ea8d7e9dbd..0000000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index c6a2f30408..060e1a43f2 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -82,7 +82,6 @@ static inline acpi_hest_generic_data_v300_t *acpi_hest_generic_data3( /* Find the address of a Generic Data structure's CPER error record section */ #define section_of_acpientry(A, B) ((typeof(A))((u8 *)(B) + sizeof(*(B)))) - /* Add a context to an existing IA32/X64-type error entry */ cper_ia32x64_context_t *new_cper_ia32x64_ctx( acpi_generic_error_status_t *status, diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h index c73591579a..1ef927e0fb 100644 --- a/src/arch/x86/include/arch/boot/boot.h +++ b/src/arch/x86/include/arch/boot/boot.h @@ -7,4 +7,15 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_386 +#include +/* + * Jump to function in protected mode. + * @arg func_ptr Function to jump to in protected mode + * @arg Argument to pass to called function + * + * @noreturn + */ +void protected_mode_jump(uint32_t func_ptr, + uint32_t argument); + #endif /* ASM_I386_BOOT_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 82f470ec2d..b622465a25 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -269,6 +269,12 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) } +/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ +static __always_inline void cpu_relax(void) +{ + __asm__ __volatile__("rep;nop" : : : "memory"); +} + #define asmlinkage __attribute__((regparm(0))) /* diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d01d5f6511..00fb277ec0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -73,7 +73,6 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) ); } - static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 7626206e12..4037e48a7f 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -67,6 +67,4 @@ static __always_inline void atomic_dec(atomic_t *v) : "m" (v->counter)); } - - #endif /* ARCH_SMP_ATOMIC_H */ diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index d6378731ed..25c23e68f5 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -23,7 +23,6 @@ */ #define MAX_APICS 16 - #define SMP_FLOATING_TABLE_LEN sizeof(struct intel_mp_floating) struct intel_mp_floating { @@ -130,7 +129,6 @@ enum mp_irq_source_types { #define MP_IRQ_TRIGGER_LEVEL 0xc #define MP_IRQ_TRIGGER_MASK 0xc - struct mpc_config_lintsrc { u8 mpc_type; u8 mpc_irqtype; diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 41189933d9..799ac2c8b8 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -29,6 +29,7 @@ typedef struct { #define barrier() __asm__ __volatile__("" : : : "memory") #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) #define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) +#undef barrier #define spin_lock_string \ "\n1:\t" \ @@ -62,21 +63,13 @@ static __always_inline void spin_unlock(spinlock_t *lock) : "=m" (lock->lock) : : "memory"); } -/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ -static __always_inline void cpu_relax(void) -{ - __asm__ __volatile__("rep;nop" : : : "memory"); -} - #else #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #endif diff --git a/src/arch/x86/include/mode_switch.h b/src/arch/x86/include/mode_switch.h new file mode 100644 index 0000000000..0c46da5c62 --- /dev/null +++ b/src/arch/x86/include/mode_switch.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#if ENV_X86_64 +int protected_mode_call_narg(uint32_t arg_count, + uint32_t func_ptr, + uint32_t opt_arg1, + uint32_t opt_arg2); + +/* + * Drops into protected mode and calls the function, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * + * The called function doesn't have arguments and returns an int. + */ +static inline int protected_mode_call(void *func) +{ + return protected_mode_call_narg(0, (uintptr_t)func, 0, 0); +} + +/* + * Drops into protected mode and calls the function, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * Only the lower 32bits of the argument are passed to the called function. + * + * The called function have one argument and returns an int. + */ +static inline int protected_mode_call_1arg(void *func, uint32_t arg1) +{ + return protected_mode_call_narg(1, (uintptr_t)func, arg1, 0); +} + +/* + * Drops into protected mode and calls the function, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * Only the lower 32bits of the argument are passed to the called function. + * + * The called function has two arguments and returns an int. + */ +static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) +{ + return protected_mode_call_narg(2, (uintptr_t)func, arg1, arg2); +} +#else +static inline int protected_mode_call(void *func) +{ + int (*doit)(void) = func; + + return doit(); +} + +static inline int protected_mode_call_1arg(void *func, uint32_t arg1) +{ + int (*doit)(uint32_t arg1) = func; + + return doit(arg1); +} + +static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) +{ + int (*doit)(uint32_t arg1, uint32_t arg2) = func; + + return doit(arg1, arg2); +} +#endif diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 2f23219de5..1cfdf89175 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include void *memcpy(void *dest, const void *src, size_t n) { unsigned long d0, d1, d2; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)src, n, false, _RET_IP_); + check_memory_region((unsigned long)dest, n, true, _RET_IP_); +#endif + asm volatile( #ifdef __x86_64__ "rep ; movsd\n\t" diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 3659cc9f96..52694fa360 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,7 +28,7 @@ SECTIONS #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, + BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" @@ -39,11 +39,5 @@ SECTIONS } #if ENV_BOOTBLOCK -/* Bootblock specific scripts which provide more SECTION directives. */ -#include -#include -#include -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include -#endif +#include #endif /* ENV_BOOTBLOCK */ diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index cdd1e8dc70..3ec50b26ae 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -4,12 +4,20 @@ */ #include +#include +#include void *memmove(void *dest, const void *src, size_t n) { int d0, d1, d2, d3, d4, d5; char *ret = dest; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)src, n, false, _RET_IP_); + check_memory_region((unsigned long)dest, n, true, _RET_IP_); +#endif + __asm__ __volatile__( /* Handle more 16bytes in loop */ "cmp $0x10, %0\n\t" diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 17963426c0..fc09a9bd52 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -4,6 +4,8 @@ #include #include +#include +#include typedef uint32_t op_t; @@ -12,6 +14,11 @@ void *memset(void *dstpp, int c, size_t len) int d0; unsigned long int dstp = (unsigned long int) dstpp; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)dstpp, len, true, _RET_IP_); +#endif + /* This explicit register allocation improves code very much indeed. */ register op_t x asm("ax"); diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 66ba0e145b..f0ccc86fbe 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -2,6 +2,7 @@ #include #include +#include /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) @@ -13,3 +14,12 @@ const struct region_device *boot_device_ro(void) { return &boot_dev.rdev; } + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + table->flash_base = 0; + table->host_base = (uint32_t)(uintptr_t)rom_base; + table->size = CONFIG_ROM_SIZE; + + return 1; +} diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 18a36cd3d1..362650dea9 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -28,7 +28,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr); - sum = rt->checksum - sum; if (sum != rt->checksum) { @@ -106,8 +105,6 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) /* If it's not yet routed, use it */ if (!already_routed) break; - /* But if it was already routed, try the next one */ - continue; } /* Now we got our IRQ */ return irq; diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 3c5799bca8..aaf989da19 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -73,7 +73,6 @@ static u8 smbios_get_device_type_from_dev(struct device *dev) } } - int smbios_add_string(u8 *start, const char *str) { int i = 1; @@ -158,86 +157,53 @@ static int smbios_processor_name(u8 *start) return smbios_add_string(start, str); } -/* this function will fill the corresponding manufacturer */ -void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, - struct smbios_type17 *t) +static const char *get_dimm_manufacturer_name(const uint16_t mod_id) { switch (mod_id) { case 0x9b85: - t->manufacturer = smbios_add_string(t->eos, - "Crucial"); - break; + return "Crucial"; case 0x4304: - t->manufacturer = smbios_add_string(t->eos, - "Ramaxel"); - break; + return "Ramaxel"; case 0x4f01: - t->manufacturer = smbios_add_string(t->eos, - "Transcend"); - break; + return "Transcend"; case 0x9801: - t->manufacturer = smbios_add_string(t->eos, - "Kingston"); - break; + return "Kingston"; case 0x987f: - t->manufacturer = smbios_add_string(t->eos, - "Hynix"); - break; + return "Hynix"; case 0x9e02: - t->manufacturer = smbios_add_string(t->eos, - "Corsair"); - break; + return "Corsair"; case 0xb004: - t->manufacturer = smbios_add_string(t->eos, - "OCZ"); - break; + return "OCZ"; case 0xad80: - t->manufacturer = smbios_add_string(t->eos, - "Hynix/Hyundai"); - break; + return "Hynix/Hyundai"; case 0x3486: - t->manufacturer = smbios_add_string(t->eos, - "Super Talent"); - break; + return "Super Talent"; case 0xcd04: - t->manufacturer = smbios_add_string(t->eos, - "GSkill"); - break; + return "GSkill"; case 0xce80: - t->manufacturer = smbios_add_string(t->eos, - "Samsung"); - break; + return "Samsung"; case 0xfe02: - t->manufacturer = smbios_add_string(t->eos, - "Elpida"); - break; + return "Elpida"; case 0x2c80: - t->manufacturer = smbios_add_string(t->eos, - "Micron"); - break; - default: { - char string_buffer[256]; - - snprintf(string_buffer, sizeof(string_buffer), - "Unknown (%x)", mod_id); - t->manufacturer = smbios_add_string(t->eos, - string_buffer); - break; - } + return "Micron"; + default: + return NULL; } } -/* this function will fill the corresponding locator */ -void __weak smbios_fill_dimm_locator(const struct dimm_info *dimm, - struct smbios_type17 *t) + +/* this function will fill the corresponding manufacturer */ +void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t) { - char locator[40]; + const char *const manufacturer = get_dimm_manufacturer_name(mod_id); - snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", - dimm->channel_num, dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); + if (manufacturer) { + t->manufacturer = smbios_add_string(t->eos, manufacturer); + } else { + char string_buffer[256]; - snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); - t->bank_locator = smbios_add_string(t->eos, locator); + snprintf(string_buffer, sizeof(string_buffer), "Unknown (%x)", mod_id); + t->manufacturer = smbios_add_string(t->eos, string_buffer); + } } static void trim_trailing_whitespace(char *buffer, size_t buffer_size) @@ -256,8 +222,7 @@ static void trim_trailing_whitespace(char *buffer, size_t buffer_size) } /** This function will fill the corresponding part number */ -static void smbios_fill_dimm_part_number(const char *part_number, - struct smbios_type17 *t) +static void smbios_fill_dimm_part_number(const char *part_number, struct smbios_type17 *t) { int invalid; size_t i, len; @@ -303,21 +268,27 @@ static void smbios_fill_dimm_serial_number(const struct dimm_info *dimm, char serial[9]; snprintf(serial, sizeof(serial), "%02hhx%02hhx%02hhx%02hhx", - dimm->serial[0], dimm->serial[1], dimm->serial[2], - dimm->serial[3]); + dimm->serial[0], dimm->serial[1], dimm->serial[2], dimm->serial[3]); t->serial_number = smbios_add_string(t->eos, serial); } static int create_smbios_type17_for_dimm(struct dimm_info *dimm, - unsigned long *current, int *handle) + unsigned long *current, int *handle, + int type16_handle) { struct smbios_type17 *t = (struct smbios_type17 *)*current; memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; - t->clock_speed = dimm->ddr_frequency; - t->speed = dimm->ddr_frequency; + if (dimm->configured_speed_mts != 0) + t->clock_speed = dimm->configured_speed_mts; + else + t->clock_speed = dimm->ddr_frequency; + if (dimm->max_speed_mts != 0) + t->speed = dimm->max_speed_mts; + else + t->speed = dimm->ddr_frequency; t->type = SMBIOS_MEMORY_DEVICE; if (dimm->dimm_size < 0x7fff) { t->size = dimm->dimm_size; @@ -360,11 +331,13 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, t->maximum_voltage = dimm->vdd_voltage; /* Synchronous = 1 */ - t->type_detail = 0x0080; + t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; /* no handle for error information */ t->memory_error_information_handle = 0xFFFE; t->attributes = dimm->rank_per_dimm; t->handle = *handle; + t->phys_memory_array_handle = type16_handle; + *handle += 1; t->length = sizeof(struct smbios_type17) - 2; return t->length + smbios_string_table_len(t->eos); @@ -425,11 +398,6 @@ static const char *get_bios_version(void) return coreboot_version; } -const char *__weak smbios_mainboard_bios_version(void) -{ - return NULL; -} - static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -446,7 +414,7 @@ static int smbios_write_type0(unsigned long *current, int handle) #if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES) u32 version_offset = (u32)smbios_string_table_len(t->eos); /* SMBIOS offsets start at 1 rather than 0 */ - chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); + chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1); #endif t->bios_version = smbios_add_string(t->eos, get_bios_version()); uint32_t rom_size = CONFIG_ROM_SIZE; @@ -454,8 +422,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_rom_size = (rom_size / 65535) - 1; if (CONFIG_ROM_SIZE >= 1 * GiB) { - t->extended_bios_rom_size = - DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14); + t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14); } else { t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); } @@ -463,6 +430,8 @@ static int smbios_write_type0(unsigned long *current, int handle) t->system_bios_major_release = coreboot_major_revision; t->system_bios_minor_release = coreboot_minor_revision; + smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release); + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | BIOS_CHARACTERISTICS_SELECTABLE_BOOT | @@ -480,121 +449,6 @@ static int smbios_write_type0(unsigned long *current, int handle) return len; } -const char *__weak smbios_mainboard_serial_number(void) -{ - return CONFIG_MAINBOARD_SERIAL_NUMBER; -} - -const char *__weak smbios_mainboard_version(void) -{ - return CONFIG_MAINBOARD_VERSION; -} - -const char *__weak smbios_mainboard_manufacturer(void) -{ - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; -} - -const char *__weak smbios_mainboard_product_name(void) -{ - return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; -} - -const char *__weak smbios_mainboard_asset_tag(void) -{ - return ""; -} - -u8 __weak smbios_mainboard_feature_flags(void) -{ - return 0; -} - -const char *__weak smbios_mainboard_location_in_chassis(void) -{ - return ""; -} - -smbios_board_type __weak smbios_mainboard_board_type(void) -{ - return SMBIOS_BOARD_TYPE_UNKNOWN; -} - -/* - * System Enclosure or Chassis Types as defined in SMBIOS specification. - * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, - * convertible, or tablet enclosure will be used if the appropriate - * system type is selected. - */ -smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) -{ - if (CONFIG(SYSTEM_TYPE_LAPTOP)) - return SMBIOS_ENCLOSURE_LAPTOP; - else if (CONFIG(SYSTEM_TYPE_TABLET)) - return SMBIOS_ENCLOSURE_TABLET; - else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) - return SMBIOS_ENCLOSURE_CONVERTIBLE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) - return SMBIOS_ENCLOSURE_DETACHABLE; - else - return SMBIOS_ENCLOSURE_DESKTOP; -} - -const char *__weak smbios_system_serial_number(void) -{ - return smbios_mainboard_serial_number(); -} - -const char *__weak smbios_system_version(void) -{ - return smbios_mainboard_version(); -} - -const char *__weak smbios_system_manufacturer(void) -{ - return smbios_mainboard_manufacturer(); -} - -const char *__weak smbios_system_product_name(void) -{ - return smbios_mainboard_product_name(); -} - -void __weak smbios_system_set_uuid(u8 *uuid) -{ - /* leave all zero */ -} - -unsigned int __weak smbios_cpu_get_max_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -unsigned int __weak smbios_cpu_get_current_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -const char *__weak smbios_system_sku(void) -{ - return ""; -} - -const char * __weak smbios_chassis_version(void) -{ - return ""; -} - -const char * __weak smbios_chassis_serial_number(void) -{ - return ""; -} - -const char * __weak smbios_processor_serial_number(void) -{ - return ""; -} - static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) @@ -603,10 +457,84 @@ static int get_socket_type(void) return 0x13; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) return 0x15; + if (CONFIG(XEON_SP_COMMON_BASE)) + return 0x36; return 0x02; /* Unknown */ } +unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + return meminfo->ecc_capable ? + MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; +} + +unsigned int __weak smbios_processor_external_clock(void) +{ + return 0; /* Unknown */ +} + +unsigned int __weak smbios_processor_characteristics(void) +{ + return 0; +} + +unsigned int __weak smbios_processor_family(struct cpuid_result res) +{ + return (res.eax > 0) ? 0x0c : 0x6; +} + +unsigned int __weak smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; +} + +unsigned int __weak smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_UNKNOWN; +} + +unsigned int __weak smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */ +} + +/* Returns the processor voltage in 100mV units */ +unsigned int __weak smbios_cpu_get_voltage(void) +{ + return 0; /* Unknown */ +} + +static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache) +{ + size_t max_logical_cpus_sharing_cache = 0; + size_t number_of_cpus_per_package = 0; + size_t max_logical_cpus_per_package = 0; + struct cpuid_result res; + + if (!cpu_have_cpuid()) + return 1; + + res = cpuid(1); + + max_logical_cpus_per_package = (res.ebx >> 16) & 0xff; + + max_logical_cpus_sharing_cache = ((res_deterministic_cache.eax >> 14) & 0xfff) + 1; + + /* Check if it's last level cache */ + if (max_logical_cpus_sharing_cache == max_logical_cpus_per_package) + return 1; + + if (cpuid_get_max_func() >= 0xb) { + res = cpuid_ext(0xb, 1); + number_of_cpus_per_package = res.ebx & 0xff; + } else { + number_of_cpus_per_package = max_logical_cpus_per_package; + } + + return number_of_cpus_per_package / max_logical_cpus_sharing_cache; +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -616,12 +544,9 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_system_manufacturer()); - t->product_name = smbios_add_string(t->eos, - smbios_system_product_name()); - t->serial_number = smbios_add_string(t->eos, - smbios_system_serial_number()); + t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer()); + t->product_name = smbios_add_string(t->eos, smbios_system_product_name()); + t->serial_number = smbios_add_string(t->eos, smbios_system_serial_number()); t->sku = smbios_add_string(t->eos, smbios_system_sku()); t->version = smbios_add_string(t->eos, smbios_system_version()); #ifdef CONFIG_MAINBOARD_FAMILY @@ -633,8 +558,7 @@ static int smbios_write_type1(unsigned long *current, int handle) return len; } -static int smbios_write_type2(unsigned long *current, int handle, - const int chassis_handle) +static int smbios_write_type2(unsigned long *current, int handle, const int chassis_handle) { struct smbios_type2 *t = (struct smbios_type2 *)*current; int len = sizeof(struct smbios_type2); @@ -643,12 +567,9 @@ static int smbios_write_type2(unsigned long *current, int handle, t->type = SMBIOS_BOARD_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_mainboard_manufacturer()); - t->product_name = smbios_add_string(t->eos, - smbios_mainboard_product_name()); - t->serial_number = smbios_add_string(t->eos, - smbios_mainboard_serial_number()); + t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer()); + t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); + t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); t->asset_tag = smbios_add_string(t->eos, smbios_mainboard_asset_tag()); t->feature_flags = smbios_mainboard_feature_flags(); @@ -670,8 +591,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_system_manufacturer()); + t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer()); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; @@ -687,9 +607,13 @@ static int smbios_write_type3(unsigned long *current, int handle) static int smbios_write_type4(unsigned long *current, int handle) { + unsigned int cpu_voltage; struct cpuid_result res; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); + uint16_t characteristics = 0; + static unsigned int cnt = 0; + char buf[8]; /* Provide sane defaults even for CPU without CPUID */ res.eax = res.edx = 0; @@ -702,11 +626,15 @@ static int smbios_write_type4(unsigned long *current, int handle) t->type = SMBIOS_PROCESSOR_INFORMATION; t->handle = handle; t->length = len - 2; + + snprintf(buf, sizeof(buf), "CPU%d", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + t->processor_id[0] = res.eax; t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = (res.eax > 0) ? 0x0c : 0x6; + t->processor_family = smbios_processor_family(res); t->processor_type = 3; /* System Processor */ /* * If CPUID leaf 11 is available, calculate "core count" by dividing @@ -724,25 +652,57 @@ static int smbios_write_type4(unsigned long *current, int handle) if (leaf_b_threads == 0) { leaf_b_threads = 1; } - t->core_count = leaf_b_cores / leaf_b_threads; + t->core_count2 = leaf_b_cores / leaf_b_threads; + t->core_count = t->core_count2 > 0xff ? 0xff : t->core_count2; + t->thread_count2 = leaf_b_cores; + t->thread_count = t->thread_count2 > 0xff ? 0xff : t->thread_count2; } else { t->core_count = (res.ebx >> 16) & 0xff; + t->core_count2 = t->core_count; + t->thread_count2 = t->core_count2; + t->thread_count = t->thread_count2; } /* Assume we enable all the cores always, capped only by MAX_CPUS */ t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); + t->core_enabled2 = MIN(t->core_count2, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); + t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED; t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { t->max_speed = cpuid_ebx(0x16); t->current_speed = cpuid_eax(0x16); /* base frequency */ + t->external_clock = cpuid_ecx(0x16); } else { t->max_speed = smbios_cpu_get_max_speed_mhz(); t->current_speed = smbios_cpu_get_current_speed_mhz(); + t->external_clock = smbios_processor_external_clock(); } + + if (cpu_have_cpuid()) { + res = cpuid(1); + + if ((res.ecx) & BIT(5)) + characteristics |= BIT(6); /* BIT6: Enhanced Virtualization */ + + if ((res.edx) & BIT(28)) + characteristics |= BIT(4); /* BIT4: Hardware Thread */ + + if (((cpuid_eax(0x80000000) - 0x80000000) + 1) > 2) { + res = cpuid(0x80000001); + + if ((res.edx) & BIT(20)) + characteristics |= BIT(5); /* BIT5: Execute Protection */ + } + } + t->processor_characteristics = characteristics | smbios_processor_characteristics(); + cpu_voltage = smbios_cpu_get_voltage(); + if (cpu_voltage > 0) + t->voltage = 0x80 | cpu_voltage; + *current += len; return len; } @@ -752,19 +712,17 @@ static int smbios_write_type4(unsigned long *current, int handle) * Fill in some fields with constant values, as gathering the information * from CPUID is impossible. */ -static int -smbios_write_type7(unsigned long *current, - const int handle, - const u8 level, - const u8 sram_type, - const enum smbios_cache_associativity associativity, - const enum smbios_cache_type type, - const size_t max_cache_size, - const size_t cache_size) +static int smbios_write_type7(unsigned long *current, + const int handle, + const u8 level, + const u8 sram_type, + const enum smbios_cache_associativity associativity, + const enum smbios_cache_type type, + const size_t max_cache_size, + const size_t cache_size) { struct smbios_type7 *t = (struct smbios_type7 *)*current; int len = sizeof(struct smbios_type7); - static unsigned int cnt = 0; char buf[8]; memset(t, 0, sizeof(struct smbios_type7)); @@ -772,13 +730,13 @@ smbios_write_type7(unsigned long *current, t->handle = handle; t->length = len - 2; - snprintf(buf, sizeof(buf), "CACHE%x", cnt++); + snprintf(buf, sizeof(buf), "CACHE%x", level); t->socket_designation = smbios_add_string(t->eos, buf); t->cache_configuration = SMBIOS_CACHE_CONF_LEVEL(level) | SMBIOS_CACHE_CONF_LOCATION(0) | /* Internal */ SMBIOS_CACHE_CONF_ENABLED(1) | /* Enabled */ - SMBIOS_CACHE_CONF_OPERATION_MODE(3); /* Unknown */ + SMBIOS_CACHE_CONF_OPERATION_MODE(smbios_cache_conf_operation_mode(level)); if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) { t->max_cache_size = max_cache_size / KiB; @@ -818,7 +776,7 @@ smbios_write_type7(unsigned long *current, t->supported_sram_type = sram_type; t->current_sram_type = sram_type; t->cache_speed = 0; /* Unknown */ - t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->error_correction_type = smbios_cache_error_correction_type(level); t->system_cache_type = type; len = t->length + smbios_string_table_len(t->eos); @@ -827,8 +785,7 @@ smbios_write_type7(unsigned long *current, } /* Convert the associativity as integer to the SMBIOS enum if available */ -static enum smbios_cache_associativity -smbios_cache_associativity(const u8 num) +static enum smbios_cache_associativity smbios_cache_associativity(const u8 num) { switch (num) { case 1: @@ -914,8 +871,8 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; - const size_t cache_size = assoc * partitions * cache_line_size * - number_of_sets; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets + * get_number_of_caches(res); if (!cache_type) /* No more caches in the system */ @@ -944,7 +901,7 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, const int h = (*handle)++; update_max(len, *max_struct_size, smbios_write_type7(current, h, - level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, + level, smbios_cache_sram_type(), associativity, type, cache_size, cache_size)); if (type4) { @@ -1006,10 +963,7 @@ int smbios_write_type9(unsigned long *current, int *handle, t->type = SMBIOS_SYSTEM_SLOTS; t->handle = *handle; t->length = len - 2; - if (name) - t->slot_designation = smbios_add_string(t->eos, name); - else - t->slot_designation = smbios_add_string(t->eos, "SLOT"); + t->slot_designation = smbios_add_string(t->eos, name ? name : "SLOT"); t->slot_type = type; /* TODO add slot_id supoort, will be "_SUN" for ACPI devices */ t->slot_data_bus_width = bandwidth; @@ -1056,7 +1010,52 @@ static int smbios_write_type11(unsigned long *current, int *handle) return len; } -static int smbios_write_type17(unsigned long *current, int *handle) +static int smbios_write_type16(unsigned long *current, int *handle) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + + int len; + int i; + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + printk(BIOS_INFO, "Create SMBIOS type 16\n"); + + if (meminfo->max_capacity_mib == 0 || meminfo->number_of_devices == 0) { + /* Fill in defaults if not provided */ + meminfo->number_of_devices = 0; + meminfo->max_capacity_mib = 0; + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { + meminfo->max_capacity_mib += meminfo->dimm[i].dimm_size; + meminfo->number_of_devices += !!meminfo->dimm[i].dimm_size; + } + } + + memset(t, 0, sizeof(*t)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len = sizeof(*t) - 2; + + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->memory_error_correction = smbios_memory_error_correction_type(meminfo); + + /* no error information handle available */ + t->memory_error_information_handle = 0xFFFE; + t->maximum_capacity = meminfo->max_capacity_mib * (MiB / KiB); + t->number_of_memory_devices = meminfo->number_of_devices; + + len += smbios_string_table_len(t->eos); + + *current += len; + (*handle)++; + return len; +} + +static int smbios_write_type17(unsigned long *current, int *handle, int type16) { int len = sizeof(struct smbios_type17); int totallen = 0; @@ -1068,17 +1067,73 @@ static int smbios_write_type17(unsigned long *current, int *handle) return 0; /* can't find mem info in cbmem */ printk(BIOS_INFO, "Create SMBIOS type 17\n"); - for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); - i++) { + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { struct dimm_info *dimm; dimm = &meminfo->dimm[i]; - len = create_smbios_type17_for_dimm(dimm, current, handle); + /* + * Windows 10 GetPhysicallyInstalledSystemMemory functions reads SMBIOS tables + * type 16 and type 17. The type 17 tables need to point to a type 16 table. + * Otherwise, the physical installed memory size is guessed from the system + * memory map, which results in a slightly smaller value than the actual size. + */ + len = create_smbios_type17_for_dimm(dimm, current, handle, type16); *current += len; totallen += len; } return totallen; } +static int smbios_write_type19(unsigned long *current, int *handle, int type16) +{ + struct smbios_type19 *t = (struct smbios_type19 *)*current; + int len = sizeof(struct smbios_type19); + int i; + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + memset(t, 0, sizeof(struct smbios_type19)); + + t->type = SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS; + t->length = len - 2; + t->handle = *handle; + t->memory_array_handle = type16; + + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { + if (meminfo->dimm[i].dimm_size > 0) { + t->extended_ending_address += meminfo->dimm[i].dimm_size; + t->partition_width++; + } + } + t->extended_ending_address *= MiB; + + /* Check if it fits into regular address */ + if (t->extended_ending_address >= KiB && + t->extended_ending_address < 0x40000000000ULL) { + /* + * FIXME: The starting address is SoC specific, but SMBIOS tables are only + * exported on x86 where it's always 0. + */ + + t->starting_address = 0; + t->ending_address = t->extended_ending_address / KiB - 1; + t->extended_starting_address = ~0; + t->extended_ending_address = ~0; + } else { + t->starting_address = ~0; + t->ending_address = ~0; + t->extended_starting_address = 0; + t->extended_ending_address--; + } + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + static int smbios_write_type32(unsigned long *current, int handle) { struct smbios_type32 *t = (struct smbios_type32 *)*current; @@ -1160,7 +1215,7 @@ static int smbios_write_type127(unsigned long *current, int handle) /* Generate Type41 entries from devicetree */ static int smbios_walk_device_tree_type41(struct device *dev, int *handle, - unsigned long *current) + unsigned long *current) { static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; @@ -1240,16 +1295,14 @@ static int smbios_walk_device_tree_type9(struct device *dev, int *handle, dev->path.pci.devfn); } -static int smbios_walk_device_tree(struct device *tree, int *handle, - unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { struct device *dev; int len = 0; for (dev = tree; dev; dev = dev->next) { if (dev->enabled && dev->ops && dev->ops->get_smbios_data) { - printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), - dev_name(dev)); + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } len += smbios_walk_device_tree_type9(dev, handle, current); @@ -1261,6 +1314,7 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; + struct smbios_entry30 *se3; unsigned long tables; int len = 0; int max_struct_size = 0; @@ -1273,43 +1327,44 @@ unsigned long smbios_write_tables(unsigned long current) current += sizeof(struct smbios_entry); current = ALIGN_UP(current, 16); + se3 = (struct smbios_entry30 *)current; + current += sizeof(struct smbios_entry30); + current = ALIGN_UP(current, 16); + tables = current; - update_max(len, max_struct_size, smbios_write_type0(¤t, - handle++)); - update_max(len, max_struct_size, smbios_write_type1(¤t, - handle++)); - update_max(len, max_struct_size, smbios_write_type2(¤t, - handle, handle + 1)); /* The chassis handle is the next one */ + update_max(len, max_struct_size, smbios_write_type0(¤t, handle++)); + update_max(len, max_struct_size, smbios_write_type1(¤t, handle++)); + + /* The chassis handle is the next one */ + update_max(len, max_struct_size, smbios_write_type2(¤t, handle, handle + 1)); handle++; - update_max(len, max_struct_size, smbios_write_type3(¤t, - handle++)); + update_max(len, max_struct_size, smbios_write_type3(¤t, handle++)); struct smbios_type4 *type4 = (struct smbios_type4 *)current; - update_max(len, max_struct_size, smbios_write_type4(¤t, - handle++)); - len += smbios_write_type7_cache_parameters(¤t, &handle, - &max_struct_size, type4); - update_max(len, max_struct_size, smbios_write_type11(¤t, - &handle)); + update_max(len, max_struct_size, smbios_write_type4(¤t, handle++)); + len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4); + update_max(len, max_struct_size, smbios_write_type11(¤t, &handle)); if (CONFIG(ELOG)) update_max(len, max_struct_size, - elog_smbios_write_type15(¤t,handle++)); - update_max(len, max_struct_size, smbios_write_type17(¤t, - &handle)); - update_max(len, max_struct_size, smbios_write_type32(¤t, - handle++)); + elog_smbios_write_type15(¤t, handle++)); + + const int type16 = handle; + update_max(len, max_struct_size, smbios_write_type16(¤t, &handle)); + update_max(len, max_struct_size, smbios_write_type17(¤t, &handle, type16)); + update_max(len, max_struct_size, smbios_write_type19(¤t, &handle, type16)); + update_max(len, max_struct_size, smbios_write_type32(¤t, handle++)); update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, - &handle, ¤t)); + &handle, ¤t)); - update_max(len, max_struct_size, smbios_write_type127(¤t, - handle++)); + update_max(len, max_struct_size, smbios_write_type127(¤t, handle++)); + /* Install SMBIOS 2.1 entry point */ memset(se, 0, sizeof(struct smbios_entry)); memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); - se->major_version = 2; - se->minor_version = 8; + se->major_version = 3; + se->minor_version = 0; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1318,8 +1373,20 @@ unsigned long smbios_write_tables(unsigned long current) se->struct_table_length = len; se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, - sizeof(struct smbios_entry) - - 0x10); + sizeof(struct smbios_entry) - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); + + /* Install SMBIOS 3.0 entry point */ + memset(se3, 0, sizeof(struct smbios_entry30)); + memcpy(se3->anchor, "_SM3_", 5); + se3->length = sizeof(struct smbios_entry30); + se3->major_version = 3; + se3->minor_version = 0; + + se3->struct_table_address = (u64)tables; + se3->struct_table_length = len; + + se3->checksum = smbios_checksum((u8 *)se3, sizeof(struct smbios_entry30)); + return current; } diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c new file mode 100644 index 0000000000..4d8883f3cd --- /dev/null +++ b/src/arch/x86/smbios_defaults.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* this function will fill the corresponding locator */ +__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char locator[40]; + + snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", + dimm->channel_num, dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); + t->bank_locator = smbios_add_string(t->eos, locator); +} + +__weak const char *smbios_mainboard_bios_version(void) +{ + return NULL; +} + +__weak const char *smbios_mainboard_serial_number(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} + +__weak const char *smbios_mainboard_version(void) +{ + return CONFIG_MAINBOARD_VERSION; +} + +__weak const char *smbios_mainboard_manufacturer(void) +{ + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; +} + +__weak const char *smbios_mainboard_product_name(void) +{ + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +__weak const char *smbios_mainboard_asset_tag(void) +{ + return ""; +} + +__weak u8 smbios_mainboard_feature_flags(void) +{ + return 0; +} + +__weak const char *smbios_mainboard_location_in_chassis(void) +{ + return ""; +} + +__weak smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_UNKNOWN; +} + +__weak void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + *ec_major_revision = 0x0; + *ec_minor_revision = 0x0; +} + +/* + * System Enclosure or Chassis Types as defined in SMBIOS specification. + * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, + * convertible, or tablet enclosure will be used if the appropriate + * system type is selected. + */ +__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (CONFIG(SYSTEM_TYPE_LAPTOP)) + return SMBIOS_ENCLOSURE_LAPTOP; + else if (CONFIG(SYSTEM_TYPE_TABLET)) + return SMBIOS_ENCLOSURE_TABLET; + else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) + return SMBIOS_ENCLOSURE_DETACHABLE; + else + return SMBIOS_ENCLOSURE_DESKTOP; +} + +__weak const char *smbios_system_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +__weak const char *smbios_system_version(void) +{ + return smbios_mainboard_version(); +} + +__weak const char *smbios_system_manufacturer(void) +{ + return smbios_mainboard_manufacturer(); +} + +__weak const char *smbios_system_product_name(void) +{ + return smbios_mainboard_product_name(); +} + +__weak void smbios_system_set_uuid(u8 *uuid) +{ + /* leave all zero */ +} + +__weak unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak const char *smbios_system_sku(void) +{ + return ""; +} + +__weak const char *smbios_chassis_version(void) +{ + return ""; +} + +__weak const char *smbios_chassis_serial_number(void) +{ + return ""; +} + +__weak const char *smbios_processor_serial_number(void) +{ + return ""; +} diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index 087c59b8e7..393bcf54ed 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -20,7 +20,8 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) -.section .text +.code32 +.section .init .global walkcbfs_asm /* diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9e65..1a38e4a89f 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,6 +30,20 @@ ramstage-y += cbfs.c smm-y += cbfs.c postcar-y += cbfs.c +bootblock-y += bsd/cbfs_private.c +verstage-y += bsd/cbfs_private.c +romstage-y += bsd/cbfs_private.c +postcar-y += bsd/cbfs_private.c +ramstage-y += bsd/cbfs_private.c +smm-y += bsd/cbfs_private.c + +bootblock-y += bsd/cbfs_mcache.c +verstage-y += bsd/cbfs_mcache.c +romstage-y += bsd/cbfs_mcache.c +postcar-y += bsd/cbfs_mcache.c +ramstage-y += bsd/cbfs_mcache.c +smm-y += bsd/cbfs_mcache.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c new file mode 100644 index 0000000000..0d5d8e0221 --- /dev/null +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include +#include + +/* + * A CBFS metadata cache is an in memory data structure storing CBFS file headers (= metadata). + * It is defined by its start pointer and size. It contains a sequence of variable-length + * union mcache_entry entries. There is no overall header structure for the cache. + * + * Each mcache_entry is the raw metadata for a CBFS file (including attributes) in the same form + * as stored on flash (i.e. values in big-endian), except that the CBFS magic signature in the + * first 8 bytes ('LARCHIVE') is overwritten with mcache-internal bookkeeping data. The first 4 + * bytes are a magic number (MCACHE_MAGIC_FILE) and the next 4 bytes are the absolute offset in + * bytes on the cbfs_dev_t that this metadata blob was found at. (Note that depending on the + * implementation of cbfs_dev_t, this offset may still be relative to the start of a subregion + * of the underlying storage device.) + * + * The length of an mcache_entry (i.e. length of the underlying metadata blob) is encoded in the + * metadata (entry->file.h.offset). The next mcache_entry begins at the next + * CBFS_MCACHE_ALIGNMENT boundary after that. The cache is terminated by a special 4-byte + * mcache_entry that consists only of a magic number (MCACHE_MAGIC_END or MCACHE_MAGIC_FULL). + */ + +#define MCACHE_MAGIC_FILE 0x454c4946 /* 'FILE' */ +#define MCACHE_MAGIC_FULL 0x4c4c5546 /* 'FULL' */ +#define MCACHE_MAGIC_END 0x444e4524 /* '$END' */ + +union mcache_entry { + union cbfs_mdata file; + struct { /* These fields exactly overlap file.h.magic */ + uint32_t magic; + uint32_t offset; + }; +}; + +struct cbfs_mcache_build_args { + void *mcache; + void *end; + int count; +}; + +static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata, + size_t already_read, void *arg) +{ + struct cbfs_mcache_build_args *args = arg; + union mcache_entry *entry = args->mcache; + const uint32_t data_offset = be32toh(mdata->h.offset); + + if (args->end - args->mcache < data_offset) + return CB_CBFS_CACHE_FULL; + + if (cbfs_copy_fill_metadata(args->mcache, mdata, already_read, dev, offset)) + return CB_CBFS_IO; + + entry->magic = MCACHE_MAGIC_FILE; + entry->offset = offset; + + args->mcache += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT); + args->count++; + + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size, + struct vb2_hash *metadata_hash) +{ + struct cbfs_mcache_build_args args = { + .mcache = mcache, + .end = mcache + ALIGN_DOWN(size, CBFS_MCACHE_ALIGNMENT) + - sizeof(uint32_t), /* leave space for terminating magic */ + .count = 0, + }; + + assert(size > sizeof(uint32_t) && IS_ALIGNED((uintptr_t)mcache, CBFS_MCACHE_ALIGNMENT)); + cb_err_t ret = cbfs_walk(dev, build_walker, &args, metadata_hash, 0); + union mcache_entry *entry = args.mcache; + if (ret == CB_CBFS_NOT_FOUND) { + ret = CB_SUCCESS; + entry->magic = MCACHE_MAGIC_END; + } else if (ret == CB_CBFS_CACHE_FULL) { + ERROR("mcache overflow, should increase CBFS_MCACHE size!\n"); + entry->magic = MCACHE_MAGIC_FULL; + } + + LOG("mcache @%p built for %d files, used %#zx of %#zx bytes\n", mcache, + args.count, args.mcache + sizeof(entry->magic) - mcache, size); + return ret; +} + +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out) +{ + const size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */ + const void *end = mcache + mcache_size; + const void *current = mcache; + + while (current + sizeof(uint32_t) <= end) { + const union mcache_entry *entry = current; + + if (entry->magic == MCACHE_MAGIC_END) + return CB_CBFS_NOT_FOUND; + if (entry->magic == MCACHE_MAGIC_FULL) + return CB_CBFS_CACHE_FULL; + + assert(entry->magic == MCACHE_MAGIC_FILE); + const uint32_t data_offset = be32toh(entry->file.h.offset); + const uint32_t data_length = be32toh(entry->file.h.len); + if (namesize <= data_offset - offsetof(union cbfs_mdata, h.filename) && + memcmp(name, entry->file.h.filename, namesize) == 0) { + LOG("Found '%s' @%#x size %#x in mcache @%p\n", + name, entry->offset, data_length, current); + *data_offset_out = entry->offset + data_offset; + memcpy(mdata_out, &entry->file, data_offset); + return CB_SUCCESS; + } + + current += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT); + } + + ERROR("CBFS mcache overflow!\n"); + return CB_ERR; +} + +size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size) +{ + const void *end = mcache + mcache_size; + const void *current = mcache; + + while (current + sizeof(uint32_t) < end) { + const union mcache_entry *entry = current; + + if (entry->magic == MCACHE_MAGIC_FULL || entry->magic == MCACHE_MAGIC_END) { + current += sizeof(entry->magic); + break; + } + + assert(entry->magic == MCACHE_MAGIC_FILE); + current += ALIGN_UP(be32toh(entry->file.h.offset), CBFS_MCACHE_ALIGNMENT); + } + + return current - mcache; +} diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c new file mode 100644 index 0000000000..527860db75 --- /dev/null +++ b/src/commonlib/bsd/cbfs_private.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include +#include + +static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer) +{ + const size_t devsize = cbfs_dev_size(dev); + DEBUG("Looking for next file @%#zx...\n", *offset); + *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT); + while (*offset + sizeof(*buffer) < devsize) { + if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer)) + return CB_CBFS_IO; + + if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0) + return CB_SUCCESS; + + *offset += CBFS_ALIGNMENT; + } + + DEBUG("End of CBFS reached\n"); + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags) +{ + const bool do_hash = CBFS_ENABLE_HASHING && metadata_hash; + struct vb2_digest_context dc; + vb2_error_t vbrv; + + assert(CBFS_ENABLE_HASHING || (!metadata_hash && !(flags & CBFS_WALK_WRITEBACK_HASH))); + if (do_hash && (vbrv = vb2_digest_init(&dc, metadata_hash->algo))) { + ERROR("Metadata hash digest (%d) init error: %#x\n", metadata_hash->algo, vbrv); + return CB_ERR_ARG; + } + + size_t offset = 0; + cb_err_t ret_header; + cb_err_t ret_walker = CB_CBFS_NOT_FOUND; + union cbfs_mdata mdata; + while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) { + const uint32_t attr_offset = be32toh(mdata.h.attributes_offset); + const uint32_t data_offset = be32toh(mdata.h.offset); + const uint32_t data_length = be32toh(mdata.h.len); + const uint32_t type = be32toh(mdata.h.type); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_NULL); + + DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", + offset, type, attr_offset, data_offset, data_length); + if (data_offset > sizeof(mdata)) { + ERROR("File metadata @%#zx too large\n", offset); + goto next_file; + } + + if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY)) + goto next_file; + + /* When hashing we need to read everything. Otherwise skip the attributes. + attr_offset may be 0, which means there are no attributes. */ + ssize_t todo; + if (do_hash || attr_offset == 0) + todo = data_offset - sizeof(mdata.h); + else + todo = attr_offset - sizeof(mdata.h); + if (todo <= 0 || data_offset < attr_offset) { + ERROR("Corrupt file header @%#zx\n", offset); + goto next_file; + } + + /* Read the rest of the metadata (filename, and possibly attributes). */ + assert(todo > 0 && todo <= sizeof(mdata) - sizeof(mdata.h)); + if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h), + offset + sizeof(mdata.h), todo) != todo) + return CB_CBFS_IO; + DEBUG("File name: '%s'\n", mdata.h.filename); + + if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset)) + return CB_ERR; + + if (walker && ret_walker == CB_CBFS_NOT_FOUND) + ret_walker = walker(dev, offset, &mdata, sizeof(mdata.h) + todo, arg); + + /* Return IO errors immediately. For others, finish the hash first if needed. */ + if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash)) + return ret_walker; + +next_file: + offset += data_offset + data_length; + } + + if (ret_header != CB_CBFS_NOT_FOUND) + return ret_header; + + if (do_hash) { + uint8_t real_hash[VB2_MAX_DIGEST_SIZE]; + size_t hash_size = vb2_digest_size(metadata_hash->algo); + if (vb2_digest_finalize(&dc, real_hash, hash_size)) + return CB_ERR; + if (flags & CBFS_WALK_WRITEBACK_HASH) + memcpy(metadata_hash->raw, real_hash, hash_size); + else if (memcmp(metadata_hash->raw, real_hash, hash_size) != 0) + return CB_CBFS_HASH_MISMATCH; + } + + return ret_walker; +} + +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset) +{ + /* First, copy the stuff that cbfs_walk() already read for us. */ + memcpy(dst, src, already_read); + + /* Then read in whatever metadata may be left (will only happen in non-hashing case). */ + const size_t todo = be32toh(src->h.offset) - already_read; + assert(todo <= sizeof(*dst) - already_read); + if (todo && cbfs_dev_read(dev, dst->raw + already_read, offset + already_read, + todo) != todo) + return CB_CBFS_IO; + return CB_SUCCESS; +} + +struct cbfs_lookup_args { + union cbfs_mdata *mdata_out; + const char *name; + size_t namesize; + size_t *data_offset_out; +}; + +static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata, + size_t already_read, void *arg) +{ + struct cbfs_lookup_args *args = arg; + /* Check if the name we're looking for could fit, then we can safely memcmp() it. */ + if (args->namesize > already_read - offsetof(union cbfs_mdata, h.filename) || + memcmp(args->name, mdata->h.filename, args->namesize) != 0) + return CB_CBFS_NOT_FOUND; + + LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); + if (cbfs_copy_fill_metadata(args->mdata_out, mdata, already_read, dev, offset)) + return CB_CBFS_IO; + + *args->data_offset_out = offset + be32toh(mdata->h.offset); + return CB_SUCCESS; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash) +{ + struct cbfs_lookup_args args = { + .mdata_out = mdata_out, + .name = name, + .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */ + .data_offset_out = data_offset_out, + }; + return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0); +} + +const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset + sizeof(struct cbfs_file_attribute) <= end) { + const struct cbfs_file_attribute *attr = (const void *)mdata->raw + offset; + const uint32_t tag = be32toh(attr->tag); + const uint32_t len = be32toh(attr->len); + + if (offset + len > end) { + ERROR("Attribute %s[%u] overflows end of metadata\n", + mdata->h.filename, tag); + return NULL; + } + if (tag == attr_tag) { + if (size_check && len != size_check) { + ERROR("Attribute %s[%u] size mismatch: %u != %zu\n", + mdata->h.filename, tag, len, size_check); + return NULL; + } + return attr; + } + offset += len; + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab419a7709..b61b956524 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -34,6 +34,12 @@ enum cb_err { CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave device response, try again? */ CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ + + /* CBFS errors */ + CB_CBFS_IO = -400, /**< Underlying I/O error */ + CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ + CB_CBFS_HASH_MISMATCH = -402, /**< Master hash validation failed */ + CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h new file mode 100644 index 0000000000..9fe740c917 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_ +#define _COMMONLIB_BSD_CBFS_PRIVATE_H_ + + +#include +#include +#include +#include +#include +#include + +/* + * This header implements low-level CBFS access APIs that can be shared across different + * host applications (e.g. coreboot, libpayload, cbfstool). For verification purposes it + * implements the metadata hashing part but not the file hashing part, so the host application + * will need to verify file hashes itself after loading each file. Host applications that use + * verification should implement wrapper APIs that combine the lookup, loading and hashing steps + * into a single, safe function call and outside of the code implementing those APIs should not + * be accessing the low-level APIs in this file directly (e.g. coreboot SoC/driver code should + * never directly #include this file, and always use the higher level APIs in src/lib/cbfs.c). + * + * needs to be provided by the host application using this CBFS library. It must + * define the following type, macros and functions: + * + * cbfs_dev_t An opaque type representing a CBFS storage backend. + * CBFS_ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise. (Only for + * metadata hashing. Host application needs to check file hashes itself.) + * ERROR(...) printf-style macro to print errors. + * LOG(...) printf-style macro to print normal-operation log messages. + * DEBUG(...) printf-style macro to print detailed debug output. + * + * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size); + * Read |size| bytes starting at |offset| from |dev| into |buffer|. + * Returns amount of bytes read on success and < 0 on error. + * This function *MUST* sanity-check offset/size on its own. + * + * size_t cbfs_dev_size(cbfs_dev_t dev); + * Return the total size in bytes of the CBFS storage (actual CBFS area). + */ +#include + +/* + * Helper structure to allocate space for a blob of metadata on the stack. + * NOTE: The fields in any union cbfs_mdata or any of its substructures from cbfs_serialized.h + * should always remain in the same byte order as they are stored on flash (= big endian). To + * avoid byte-order confusion, fields should always and only be converted to host byte order at + * exactly the time they are read from one of these structures into their own separate variable. + */ +union cbfs_mdata { + struct cbfs_file h; + uint8_t raw[CBFS_METADATA_MAX_SIZE]; +}; + +/* Flags that modify behavior of cbfs_walk(). */ +enum cbfs_walk_flags { + /* Write the calculated hash back out to |metadata_hash->hash| rather than comparing it. + |metadata_hash->algo| must still have been initialized by the caller. */ + CBFS_WALK_WRITEBACK_HASH = (1 << 0), + /* Call |walker| for empty file entries (i.e. entries with one of the CBFS_TYPE_DELETED + types that mark free space in the CBFS). Otherwise, those entries will be skipped. + Either way, these entries are never included in the metadata_hash calculation. */ + CBFS_WALK_INCLUDE_EMPTY = (1 << 1), +}; + +/* + * Traverse a CBFS and call a |walker| callback function for every file. Can additionally + * calculate a hash over the metadata of all files in the CBFS. If |metadata_hash| is NULL, + * hashing is disabled. If |walker| is NULL, will just traverse and hash the CBFS without + * invoking any callbacks (and always return CB_CBFS_NOT_FOUND unless there was another error). + * + * |arg| and |dev| will be passed through to |walker| unmodified. |offset| is the absolute + * offset in |dev| at which the current file metadata starts. |mdata| is a temporary buffer + * (only valid for the duration of this call to |walker|) containing already read metadata from + * the current file, up to |already_read| bytes. This will always at least contain the header + * fields and filename, but may contain more (i.e. attributes), depending on whether hashing is + * enabled. |walker| should call into cbfs_copy_fill_medadata() to copy the metadata of a file + * to a persistent buffer and automatically load remaining metadata from |dev| as needed based + * on the value of |already_read|. + * + * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further + * files. Any other return code will be used as the final return code for cbfs_walk(). It will + * return immediately unless it needs to calculate a hash in which case it will still traverse + * the remaining CBFS (but not call |walker| anymore). + * + * Returns, from highest to lowest priority: + * CB_CBFS_IO - There was an IO error with the CBFS device (always considered fatal) + * CB_CBFS_HASH_MISMATCH - |metadata_hash| was provided and did not match the CBFS + * CB_SUCCESS/ - First non-CB_CBFS_NOT_FOUND code returned by walker() + * CB_CBFS_NOT_FOUND - walker() returned CB_CBFS_NOT_FOUND for every file in the CBFS + */ +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags); + +/* + * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata + * of a file into a permanent buffer. Will copy the |already_read| metadata from |src| into + * |dst| and load remaining metadata from |dev| as required. + */ +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset); + +/* Find a file named |name| in the CBFS on |dev|. Copy its metadata (including attributes) + * into |mdata_out| and pass out the offset to the file data on the CBFS device. + * Verify the metadata with |metadata_hash| if provided. */ +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash); + +/* Both base address and size of CBFS mcaches must be aligned to this value! */ +#define CBFS_MCACHE_ALIGNMENT sizeof(uint32_t) /* Largest data type used in CBFS */ + +/* Build an in-memory CBFS metadata cache out of the CBFS on |dev| into a |mcache_size| bytes + * memory area at |mcache|. Also verify |metadata_hash| unless it is NULL. If this returns + * CB_CBFS_CACHE_FULL, the mcache is still valid and can be used, but lookups may return + * CB_CBFS_CACHE_FULL for files that didn't fit to indicate that the caller needs to fall back + * to cbfs_lookup(). */ +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size, + struct vb2_hash *metadata_hash); + +/* + * Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|. + * Pass out offset to the file data (on the original CBFS device used for cbfs_mcache_build()). + */ +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out); + +/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ +size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); + +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). + If |size| is not 0, will check that it matches the length of the attribute (if found)... + else caller is responsible for checking the |len| field to avoid reading out-of-bounds. */ +const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check); + +#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index af4baf512b..ac4b38f7a2 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -4,46 +4,42 @@ #define _CBFS_SERIALIZED_H_ #include +#include -/** These are standard values for the known compression - algorithms that coreboot knows about for stages and - payloads. Of course, other CBFS users can use whatever - values they want, as long as they understand them. */ +enum cbfs_compression { + CBFS_COMPRESS_NONE = 0, + CBFS_COMPRESS_LZMA = 1, + CBFS_COMPRESS_LZ4 = 2, +}; -#define CBFS_COMPRESS_NONE 0 -#define CBFS_COMPRESS_LZMA 1 -#define CBFS_COMPRESS_LZ4 2 +enum cbfs_type { + CBFS_TYPE_DELETED = 0x00000000, + CBFS_TYPE_NULL = 0xffffffff, + CBFS_TYPE_BOOTBLOCK = 0x01, + CBFS_TYPE_CBFSHEADER = 0x02, + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_SELF = 0x20, + CBFS_TYPE_FIT = 0x21, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_TYPE_FSP = 0x60, + CBFS_TYPE_MRC = 0x61, + CBFS_TYPE_MMA = 0x62, + CBFS_TYPE_EFI = 0x63, + CBFS_TYPE_STRUCT = 0x70, + CBFS_TYPE_CMOS_DEFAULT = 0xaa, + CBFS_TYPE_SPD = 0xab, + CBFS_TYPE_MRC_CACHE = 0xac, + CBFS_TYPE_CMOS_LAYOUT = 0x01aa, +}; -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_TYPE_DELETED 0x00000000 -#define CBFS_TYPE_DELETED2 0xffffffff -#define CBFS_TYPE_BOOTBLOCK 0x01 -#define CBFS_TYPE_STAGE 0x10 -#define CBFS_TYPE_SELF 0x20 -#define CBFS_TYPE_FIT 0x21 -#define CBFS_TYPE_OPTIONROM 0x30 -#define CBFS_TYPE_BOOTSPLASH 0x40 -#define CBFS_TYPE_RAW 0x50 -#define CBFS_TYPE_VSA 0x51 -#define CBFS_TYPE_MBI 0x52 -#define CBFS_TYPE_MICROCODE 0x53 -#define CBFS_TYPE_FSP 0x60 -#define CBFS_TYPE_MRC 0x61 -#define CBFS_TYPE_MMA 0x62 -#define CBFS_TYPE_EFI 0x63 -#define CBFS_TYPE_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_TYPE_SPD 0xab -#define CBFS_TYPE_MRC_CACHE 0xac -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -#define CBFS_HEADER_MAGIC 0x4F524243 -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 +#define CBFS_HEADER_MAGIC 0x4F524243 /* BE: 'ORBC' */ +#define CBFS_HEADER_VERSION1 0x31313131 /* BE: '1111' */ +#define CBFS_HEADER_VERSION2 0x31313132 /* BE: '1112' */ #define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 /* this is the master cbfs header - it must be located somewhere available @@ -67,9 +63,15 @@ struct cbfs_header { /* "Unknown" refers to CBFS headers version 1, * before the architecture was defined (i.e., x86 only). */ -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 +enum cbfs_architecture { + CBFS_ARCHITECTURE_UNKNOWN = 0xFFFFFFFF, + CBFS_ARCHITECTURE_X86 = 0x00000001, + CBFS_ARCHITECTURE_ARM = 0x00000010, + CBFS_ARCHITECTURE_AARCH64 = 0x0000aa64, + CBFS_ARCHITECTURE_MIPS = 0x00000100, /* deprecated */ + CBFS_ARCHITECTURE_RISCV = 0xc001d0de, + CBFS_ARCHITECTURE_PPC64 = 0x407570ff, +}; /** This is a component header - every entry in the CBFS will have this header. @@ -87,6 +89,7 @@ struct cbfs_header { */ #define CBFS_FILE_MAGIC "LARCHIVE" +#define CBFS_METADATA_MAX_SIZE 256 struct cbfs_file { char magic[8]; @@ -94,8 +97,13 @@ struct cbfs_file { uint32_t type; uint32_t attributes_offset; uint32_t offset; + char filename[0]; } __packed; +#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406 +_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); +#endif + /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their specific fields. */ @@ -108,13 +116,16 @@ struct cbfs_file_attribute { /* Depending on how the header was initialized, it may be backed with 0x00 or * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ -#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ +enum cbfs_file_attr_tag { + CBFS_FILE_ATTR_TAG_UNUSED = 0, + CBFS_FILE_ATTR_TAG_UNUSED2 = 0xffffffff, + CBFS_FILE_ATTR_TAG_COMPRESSION = 0x42435a4c, /* BE: 'BCZL' */ + CBFS_FILE_ATTR_TAG_HASH = 0x68736148, /* BE: 'hsaH' */ + CBFS_FILE_ATTR_TAG_POSITION = 0x42435350, /* BE: 'BCSP' */ + CBFS_FILE_ATTR_TAG_ALIGNMENT = 0x42434c41, /* BE: 'BCLA' */ + CBFS_FILE_ATTR_TAG_IBB = 0x32494242, /* BE: '2IBB' */ + CBFS_FILE_ATTR_TAG_PADDING = 0x47444150, /* BE: 'GNDP' */ +}; struct cbfs_file_attr_compression { uint32_t tag; @@ -124,12 +135,11 @@ struct cbfs_file_attr_compression { uint32_t decompressed_size; } __packed; +/* Actual size in CBFS may be larger/smaller than struct size! */ struct cbfs_file_attr_hash { uint32_t tag; uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; + struct vb2_hash hash; } __packed; struct cbfs_file_attr_position { @@ -144,7 +154,6 @@ struct cbfs_file_attr_align { uint32_t alignment; } __packed; - /*** Component sub-headers ***/ /* Following are component sub-headers for the "standard" @@ -177,11 +186,13 @@ struct cbfs_payload { struct cbfs_payload_segment segments; }; -#define PAYLOAD_SEGMENT_CODE 0x434F4445 -#define PAYLOAD_SEGMENT_DATA 0x44415441 -#define PAYLOAD_SEGMENT_BSS 0x42535320 -#define PAYLOAD_SEGMENT_PARAMS 0x50415241 -#define PAYLOAD_SEGMENT_ENTRY 0x454E5452 +enum cbfs_payload_segment_type { + PAYLOAD_SEGMENT_CODE = 0x434F4445, /* BE: 'CODE' */ + PAYLOAD_SEGMENT_DATA = 0x44415441, /* BE: 'DATA' */ + PAYLOAD_SEGMENT_BSS = 0x42535320, /* BE: 'BSS ' */ + PAYLOAD_SEGMENT_PARAMS = 0x50415241, /* BE: 'PARA' */ + PAYLOAD_SEGMENT_ENTRY = 0x454E5452, /* BE: 'ENTR' */ +}; struct cbfs_optionrom { uint32_t compression; diff --git a/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h new file mode 100644 index 0000000000..d5e54b508e --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ + +#ifndef _COMMONLIB_BSD_METADATA_HASH_H_ +#define _COMMONLIB_BSD_METADATA_HASH_H_ + +#include +#include + +/* This structure is embedded somewhere in the (uncompressed) bootblock. */ +struct metadata_hash_anchor { + uint8_t magic[8]; + struct vb2_hash cbfs_hash; + /* NOTE: This is just reserving space. sizeof(struct vb2_hash) may change between + configurations/versions and cannot be relied upon, so the FMAP hash must be placed + right after the actual data for the particular CBFS hash algorithm used ends. */ + uint8_t reserved_space_for_fmap_hash[VB2_MAX_DIGEST_SIZE]; +} __packed; + +/* Always use this function to figure out the actual location of the FMAP hash. It always uses + the same algorithm as the CBFS hash. */ +static inline uint8_t *metadata_hash_anchor_fmap_hash(struct metadata_hash_anchor *anchor) +{ + return anchor->cbfs_hash.raw + vb2_digest_size(anchor->cbfs_hash.algo); +} + +/* + * Do not use this constant anywhere else in coreboot code to ensure the bit pattern really only + * appears once in the CBFS image. The only coreboot file allowed to use this is + * src/lib/metadata_anchor.c to define the actual anchor data structure. It is defined here so + * that it can be shared with cbfstool (which may use it freely). + */ +#define DO_NOT_USE_METADATA_HASH_ANCHOR_MAGIC_DO_NOT_USE "\xadMdtHsh\x15" + +#endif /* _COMMONLIB_BSD_MASTER_HASH_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h new file mode 100644 index 0000000000..3a87cda1c4 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ +#if defined(__FreeBSD__) +#include +#else +#include +#endif diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 3822e8c60f..73185a5051 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 115f99a68e..f256938d5f 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -7,21 +7,6 @@ #include #include -#if !defined(LOG) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#endif -#if defined(CONFIG) - -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - -#elif !defined(DEBUG) -#define DEBUG(x...) -#endif - static size_t cbfs_next_offset(const struct region_device *cbfs, const struct cbfsf *f) { @@ -350,7 +335,7 @@ int cbfs_vb2_hash_contents(const struct region_device *cbfs, if (cbfsf_file_type(fh, &ftype)) return VB2_ERROR_UNKNOWN; - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2) + if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) continue; rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 90aa0b2571..6565c1dcd3 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -3,7 +3,7 @@ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ -#include +#include #include #include @@ -11,6 +11,7 @@ struct cbfsf { struct region_device metadata; struct region_device data; + union cbfs_mdata mdata; }; /* Locate file by name and optional type. Returns 0 on success else < 0 on diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a06bc..f58d7b11c2 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -25,6 +25,7 @@ #define CBMEM_ID_IGD_OPREGION 0x4f444749 #define CBMEM_ID_IMD_ROOT 0xff4017ff #define CBMEM_ID_IMD_SMALL 0x53a11439 +#define CBMEM_ID_MDATA_HASH 0x6873484D #define CBMEM_ID_MEMINFO 0x494D454D #define CBMEM_ID_MMA_DATA 0x4D4D4144 #define CBMEM_ID_MMC_STATUS 0x4d4d4353 @@ -55,6 +56,7 @@ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 +#define CBMEM_ID_TPM_PPI 0x54505049 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 @@ -67,7 +69,10 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_CBFS_RO_MCACHE 0x524d5346 +#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f +#define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -128,5 +133,7 @@ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ - { CBMEM_ID_FMAP, "FMAP "}, + { CBMEM_ID_FMAP, "FMAP "}, \ + { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index b7e59ad35b..be40c3818f 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -62,15 +62,15 @@ enum { LB_TAG_DMA = 0x0022, LB_TAG_RAM_OOPS = 0x0023, LB_TAG_ACPI_GNVS = 0x0024, - LB_TAG_BOARD_ID = 0x0025, + LB_TAG_BOARD_ID = 0x0025, /* deprecated */ LB_TAG_VERSION_TIMESTAMP = 0x0026, LB_TAG_WIFI_CALIBRATION = 0x0027, - LB_TAG_RAM_CODE = 0x0028, + LB_TAG_RAM_CODE = 0x0028, /* deprecated */ LB_TAG_SPI_FLASH = 0x0029, LB_TAG_SERIALNO = 0x002a, LB_TAG_MTC = 0x002b, LB_TAG_VPD = 0x002c, - LB_TAG_SKU_ID = 0x002d, + LB_TAG_SKU_ID = 0x002d, /* deprecated */ LB_TAG_BOOT_MEDIA_PARAMS = 0x0030, LB_TAG_CBMEM_ENTRY = 0x0031, LB_TAG_TSC_INFO = 0x0032, @@ -80,6 +80,10 @@ enum { LB_TAG_TCPA_LOG = 0x0036, LB_TAG_FMAP = 0x0037, LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, + LB_TAG_SMMSTOREV2 = 0x0039, + LB_TAG_TPM_PPI_HANDOFF = 0x003a, + LB_TAG_BOARD_CONFIG = 0x0040, + /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -140,7 +144,6 @@ struct lb_record { uint32_t size; /* size of record (in bytes) */ }; - struct lb_memory_range { struct lb_uint64 start; struct lb_uint64 size; @@ -186,7 +189,6 @@ struct lb_timestamp { uint32_t timestamp; }; - /* 0xe is taken by v3 */ struct lb_serial { @@ -306,7 +308,6 @@ struct lb_framebuffer { uint8_t orientation; }; - struct lb_gpio { uint32_t port; uint32_t polarity; @@ -349,11 +350,11 @@ struct lb_x86_rom_mtrr { uint32_t index; }; - -struct lb_strapping_id { - uint32_t tag; +/* Memory map windows to translate addresses between SPI flash space and host address space. */ +struct flash_mmap_window { + uint32_t flash_base; + uint32_t host_base; uint32_t size; - uint32_t id_code; }; struct lb_spi_flash { @@ -362,6 +363,13 @@ struct lb_spi_flash { uint32_t flash_size; uint32_t sector_size; uint32_t erase_cmd; + /* + * Number of mmap windows used by the platform to decode addresses between SPI flash + * space and host address space. This determines the number of entries in mmap_table. + */ + + uint32_t mmap_count; + struct flash_mmap_window mmap_table[0]; }; struct lb_boot_media_params { @@ -419,6 +427,16 @@ struct lb_macs { struct mac_address mac_addrs[0]; }; +struct lb_board_config { + uint32_t tag; + uint32_t size; + + struct lb_uint64 fw_config; + uint32_t board_id; + uint32_t ram_code; + uint32_t sku_id; +}; + #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the CMOS definitions table */ @@ -448,7 +466,6 @@ struct cmos_entries { variable length int aligned */ }; - /* CMOS enumerations record * This record is variable length. The text field may be * shorter than CMOS_MAX_TEXT_LENGTH. @@ -489,4 +506,43 @@ struct cmos_checksum { #define CHECKSUM_PCBIOS 1 }; +/* SMMSTOREv2 record + * This record contains information to use SMMSTOREv2. + */ + +struct lb_smmstorev2 { + uint32_t tag; + uint32_t size; + uint32_t num_blocks; /* Number of writeable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ +}; + +enum lb_tmp_ppi_tpm_version { + LB_TPM_VERSION_UNSPEC = 0, + LB_TPM_VERSION_TPM_VERSION_1_2, + LB_TPM_VERSION_TPM_VERSION_2, +}; + +/* + * Handoff buffer for TPM Physical Presence Interface. + * * ppi_address Pointer to PPI buffer shared with ACPI + * The layout of the buffer matches the QEMU virtual memory device + * that is generated by QEMU. + * See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' + * for details. + * * tpm_version TPM version: 1 for TPM1.2, 2 for TPM2.0 + * * ppi_version BCD encoded version of TPM PPI interface + */ +struct lb_tpm_physical_presence { + uint32_t tag; + uint32_t size; + uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ + uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ + uint8_t ppi_version; /* BCD encoded */ +} __packed; #endif diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index b9a984f171..4d095b731d 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -6,6 +6,7 @@ #include #include #include +#include #include /* @@ -210,14 +211,33 @@ void mmap_helper_device_init(struct mmap_helper_region_device *mdev, void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t); int mmap_helper_rdev_munmap(const struct region_device *, void *); -/* A translated region device provides the ability to publish a region device - * in one address space and use an access mechanism within another address - * space. The sub region is the window within the 1st address space and - * the request is modified prior to accessing the second address space - * provided by access_dev. */ -struct xlate_region_device { +/* + * A translated region device provides the ability to publish a region device in one address + * space and use an access mechanism within another address space. The sub region is the window + * within the 1st address space and the request is modified prior to accessing the second + * address space provided by access_dev. + * + * Each xlate_region_device can support multiple translation windows described using + * xlate_window structure. The windows need not be contiguous in either address space. However, + * this poses restrictions on the operations being performed i.e. callers cannot perform + * operations across multiple windows of a translated region device. It is possible to support + * readat/writeat/eraseat by translating them into multiple calls one to access device in each + * window. However, mmap support is tricky because the caller expects that the memory mapped + * region is contiguous in both address spaces. Thus, to keep the semantics consistent for all + * region ops, xlate_region_device does not support any operations across the window + * boundary. + * + * Note: The platform is expected to ensure that the fmap description does not place any + * section (that will be operated using the translated region device) across multiple windows. + */ +struct xlate_window { const struct region_device *access_dev; struct region sub_region; +}; + +struct xlate_region_device { + size_t window_count; + const struct xlate_window *window_arr; struct region_device rdev; }; @@ -225,38 +245,31 @@ extern const struct region_device_ops xlate_rdev_ro_ops; extern const struct region_device_ops xlate_rdev_rw_ops; -#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_, ops_) \ +#define XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, ops_) \ { \ - .access_dev = access_dev_, \ - .sub_region = { \ - .offset = (sub_offset_), \ - .size = (sub_size_), \ - }, \ + .window_count = ARRAY_SIZE(window_arr_), \ + .window_arr = window_arr_, \ .rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \ } -#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_ro_ops), \ +#define XLATE_REGION_DEV_RO_INIT(window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_ro_ops) -#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_rw_ops), \ +#define XLATE_REGION_DEV_RW_INIT(window_count_, window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_rw_ops) /* Helper to dynamically initialize xlate region device. */ void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); +void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev, + size_t sub_region_offset, size_t sub_region_size); + /* This type can be used for incoherent access where the read and write * operations are backed by separate drivers. An example is x86 systems * with memory mapped media for reading but use a spi flash driver for diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index b1e58c9780..a5721506d0 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -52,6 +52,8 @@ enum timestamp_id { TS_SELFBOOT_JUMP = 99, TS_START_POSTCAR = 100, TS_END_POSTCAR = 101, + TS_DELAY_START = 110, + TS_DELAY_END = 111, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -177,6 +179,8 @@ static const struct timestamp_id_to_name { { TS_LOAD_PAYLOAD, "load payload" }, { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, { TS_SELFBOOT_JUMP, "selfboot jump" }, + { TS_DELAY_START, "Forced delay start" }, + { TS_DELAY_END, "Forced delay end" }, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, @@ -185,7 +189,7 @@ static const struct timestamp_id_to_name { { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" }, { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" }, { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " }, - { TS_DONE_LOADING, "finished loading body (ignore for x86)" }, + { TS_DONE_LOADING, "finished loading body" }, { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, { TS_START_TPMPCR, "starting TPM PCR extend" }, diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 00bfb1e28b..a10702a6c5 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -188,33 +188,37 @@ void region_device_init(struct region_device *rdev, static void xlate_region_device_init(struct xlate_region_device *xdev, const struct region_device_ops *ops, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { memset(xdev, 0, sizeof(*xdev)); - xdev->access_dev = access_dev; - xdev->sub_region.offset = sub_offset; - xdev->sub_region.size = sub_size; + xdev->window_count = window_count; + xdev->window_arr = window_arr; region_device_init(&xdev->rdev, ops, 0, parent_size); } void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_ro_ops, window_count, window_arr, + parent_size); } void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_rw_ops, window_count, window_arr, + parent_size); +} + +void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev, + size_t sub_region_offset, size_t sub_region_size) +{ + window->access_dev = access_dev; + window->sub_region.offset = sub_region_offset; + window->sub_region.size = sub_region_size; } static void *mdev_mmap(const struct region_device *rd, size_t offset, @@ -321,6 +325,21 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping) return 0; } +static const struct xlate_window *xlate_find_window(const struct xlate_region_device *xldev, + const struct region *req) +{ + size_t i; + const struct xlate_window *xlwindow; + + for (i = 0; i < xldev->window_count; i++) { + xlwindow = &xldev->window_arr[i]; + if (region_is_subregion(&xlwindow->sub_region, req)) + return xlwindow; + } + + return NULL; +} + static void *xlate_mmap(const struct region_device *rd, size_t offset, size_t size) { @@ -329,24 +348,29 @@ static void *xlate_mmap(const struct region_device *rd, size_t offset, .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return NULL; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_mmap(xldev->access_dev, offset, size); + return rdev_mmap(xlwindow->access_dev, offset, size); } -static int xlate_munmap(const struct region_device *rd, void *mapping) +static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused) { - const struct xlate_region_device *xldev; - - xldev = container_of(rd, __typeof__(*xldev), rdev); - - return rdev_munmap(xldev->access_dev, mapping); + /* + * xlate_region_device does not keep track of the access device that was used to service + * a mmap request. So, munmap does not do anything. If munmap functionality is required, + * then xlate_region_device will have to be updated to accept some pre-allocated space + * from caller to keep track of the mapping requests. Since xlate_region_device is only + * used for memory mapped boot media on the backend right now, skipping munmap is fine. + */ + return 0; } static ssize_t xlate_readat(const struct region_device *rd, void *b, @@ -356,16 +380,18 @@ static ssize_t xlate_readat(const struct region_device *rd, void *b, .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_readat(xldev->access_dev, b, offset, size); + return rdev_readat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_writeat(const struct region_device *rd, const void *b, @@ -375,16 +401,18 @@ static ssize_t xlate_writeat(const struct region_device *rd, const void *b, .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_writeat(xldev->access_dev, b, offset, size); + return rdev_writeat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_eraseat(const struct region_device *rd, @@ -394,16 +422,18 @@ static ssize_t xlate_eraseat(const struct region_device *rd, .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_eraseat(xldev->access_dev, offset, size); + return rdev_eraseat(xlwindow->access_dev, offset, size); } const struct region_device_ops xlate_rdev_ro_ops = { @@ -420,7 +450,6 @@ const struct region_device_ops xlate_rdev_rw_ops = { .eraseat = xlate_eraseat, }; - static void *incoherent_mmap(const struct region_device *rd, size_t offset, size_t size) { diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 4ca98dfff7..b27f3425dd 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -265,7 +265,6 @@ int sd_set_bus_width(struct storage_media *media) return 0; } - int sd_set_partition(struct storage_media *media, unsigned int partition_number) { diff --git a/src/console/Kconfig b/src/console/Kconfig index bad6c564fc..548b701d9f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -58,6 +58,14 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL +config OVERRIDE_UART_FOR_CONSOLE + bool + help + Set to "y" when the platform overrides the index of uart port by providing + a get_uart_for_console routine. + +if !OVERRIDE_UART_FOR_CONSOLE + config UART_FOR_CONSOLE int prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE @@ -87,6 +95,8 @@ depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2 comment "Serial port base address = 0x2e8" depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3 +endif + config UART_OVERRIDE_BAUDRATE bool help @@ -294,9 +304,9 @@ config CONSOLE_QEMU_DEBUGCON_PORT depends on CONSOLE_QEMU_DEBUGCON default 0x402 -config SPI_CONSOLE - bool "SPI debug console output" - depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH +config EM100PRO_SPI_CONSOLE + bool "EM100Pro SPI debug console output" + depends on HAVE_EM100PRO_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH help Enable support for the debug console on the Dediprog EM100Pro. This is currently working only in ramstage due to how the spi diff --git a/src/console/console.c b/src/console/console.c index 2f544a80f2..67da10794e 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -69,7 +69,6 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) console_tx_byte(*buffer++); } - #if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) void gdb_hw_init(void) { diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad664..c59807785c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -8,40 +8,25 @@ #include #include -/* Mutable console log level only allowed when RAM comes online. */ -#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION +#define FIRST_CONSOLE (ENV_BOOTBLOCK || (CONFIG(NO_BOOTBLOCK_CONSOLE) && ENV_ROMSTAGE)) static int console_inited; -static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +static int console_loglevel; static inline int get_log_level(void) { if (console_inited == 0) return -1; - if (CONSOLE_LEVEL_CONST) - return get_console_loglevel(); return console_loglevel; } -static inline void set_log_level(int new_level) -{ - if (CONSOLE_LEVEL_CONST) - return; - - console_loglevel = new_level; -} - static void init_log_level(void) { - int debug_level = get_console_loglevel(); + console_loglevel = get_console_loglevel(); - if (CONSOLE_LEVEL_CONST) - return; - - get_option(&debug_level, "debug_level"); - - set_log_level(debug_level); + if (!FIRST_CONSOLE) + get_option(&console_loglevel, "debug_level"); } int console_log_level(int msg_level) diff --git a/src/console/printk.c b/src/console/printk.c index c5e5f97aab..85d9bfb1e6 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,8 +10,6 @@ #include #include #include -#include -#include #include DECLARE_SPIN_LOCK(console_lock) @@ -82,7 +80,6 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) if (log_this < CONSOLE_LOG_FAST) return 0; - DISABLE_TRACE; spin_lock(&console_lock); console_time_run(); @@ -97,7 +94,6 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) console_time_stop(); spin_unlock(&console_lock); - ENABLE_TRACE; return i; } diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index d0c569bf59..06b9e494a4 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -2,7 +2,6 @@ #include #include -#include struct vsnprintf_context { char *str_buf; @@ -24,16 +23,12 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) int i; struct vsnprintf_context ctx; - DISABLE_TRACE; - ctx.str_buf = buf; ctx.buf_limit = size ? size - 1 : 0; i = vtxprintf(str_tx_byte, fmt, args, &ctx); if (size) *ctx.str_buf = '\0'; - ENABLE_TRACE; - return i; } diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 273bc7ed72..c7bb585181 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -99,7 +99,6 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), return count; } - int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data) { diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 92e47aa3a2..a072a8b232 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,7 +1,6 @@ ################################################################################ ## Subdirectories ################################################################################ -subdirs-y += allwinner subdirs-y += amd subdirs-y += armltd subdirs-y += intel diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b276..b144fc1ca1 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -6,10 +6,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC @@ -17,7 +14,6 @@ config CPU_AMD_AGESA select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index de5bcdcad0..942539cac2 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -52,7 +52,7 @@ static void model_14_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index c2406d850c..83efb44693 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -51,7 +51,7 @@ static void model_15_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2f4fd63a7a..c1c75775e0 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -49,7 +49,7 @@ static void model_16_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc deleted file mode 100644 index f409d1f158..0000000000 --- a/src/cpu/amd/microcode/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-y += microcode.c -romstage-y += microcode.c diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig deleted file mode 100644 index 1cdfb1d7be..0000000000 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config CPU_AMD_PI_00660F01 - bool - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_PI_00660F01 - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc deleted file mode 100644 index 69635fc1f2..0000000000 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += fixme.c -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_15_init.c - -subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr -subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl deleted file mode 100644 index ede5021e03..0000000000 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Processor Object - * - */ -Scope (\_SB) { /* define processor scope */ - - Device (P000) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - - Device (P001) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - - Device (P002) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - - Device (P003) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - - Device (P004) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - - Device (P005) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - - Device (P006) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - - Device (P007) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } -} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c deleted file mode 100644 index 06fa4442ec..0000000000 --- a/src/cpu/amd/pi/00660F01/chip_name.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -struct chip_operations cpu_amd_pi_00660F01_ops = { - CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh") -}; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c deleted file mode 100644 index 9b208ecc4c..0000000000 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -void amd_initcpuio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; - /* set NP (non-posted) bit */ - PciData |= 1 << 7; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -} diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c deleted file mode 100644 index 142afbd27e..0000000000 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -void PSPProgBar3Msr(void *Buffer); - -void PSPProgBar3Msr(void *Buffer) -{ - u32 Bar3Addr; - u64 Tmp64; - /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig(0x20); - Tmp64 = Bar3Addr; - printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); -} - -static void model_15_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - u8 i; - msr_t msr; - int num_banks; - int msrno; -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - x86_mtrr_check(); - x86_enable_cache(); - - /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - - /* Enable the local CPU APICs */ - setup_lapic(); - -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - PSPProgBar3Msr(NULL); - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index 11e2531e2b..ccf64684aa 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -115,8 +115,7 @@ void amd_update_microcode_from_cbfs(void) size_t ucode_len; uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); - ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &ucode_len); + ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len); if (!ucode) { printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); return; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507ed06..d3a94a8c21 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -4,12 +4,8 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 - default y if CPU_AMD_PI_00660F01 default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC @@ -17,7 +13,6 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_PI @@ -49,4 +44,3 @@ endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" source "src/cpu/amd/pi/00730F01/Kconfig" -source "src/cpu/amd/pi/00660F01/Kconfig" diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 969434700e..dc9fd6b2bd 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -2,4 +2,3 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 -subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19a3e..01913de312 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,9 +10,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x +subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax +subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc new file mode 100644 index 0000000000..857e039952 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#if ENV_X86_64 +#define uintptr_t quad +#else +#define uintptr_t long +#endif + +rom_mtrr_mask: +.uintptr_t _rom_mtrr_mask + +rom_mtrr_base: +.uintptr_t _rom_mtrr_base + +car_mtrr_mask: +.uintptr_t _car_mtrr_mask + +car_mtrr_start: +.uintptr_t _car_mtrr_start diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c8c9..2c67207154 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include #include +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d08736585d..0451bb4dd5 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -7,8 +7,11 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e +.section .init .global bootblock_pre_c_entry +#include + .code32 _cache_as_ram_setup: @@ -83,11 +86,10 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $_car_mtrr_start, %eax + movl car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr @@ -96,20 +98,20 @@ addrsize_set_high: /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -207,8 +209,19 @@ end_microcode_update: /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp +#if ENV_X86_64 + + #include + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi + +#else + subl $4, %esp /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -216,6 +229,7 @@ end_microcode_update: pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e344778f..887bb22477 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,7 @@ #include #include +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538414..103d9e97f9 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,6 +8,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index a955d8c3c7..4b4a4abef3 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 0f2a65238c..7f9033cf65 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -19,14 +19,22 @@ config SET_IA32_FC_LOCK_BIT However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V. -config CPU_INTEL_COMMON_TIMEBASE - bool +config SET_MSR_AESNI_LOCK_BIT + bool "Lock the AES-NI enablement state" + default y + help + This config sets the AES-NI lock bit, if available, to prevent any + further change of AES-NI enablement. This may be disabled for e.g. + testing or debugging. -config CPU_INTEL_COMMON_HYPERTHREADING +config CPU_INTEL_COMMON_TIMEBASE bool endif +config CPU_INTEL_COMMON_VOLTAGE + bool + config CPU_INTEL_COMMON_SMM bool default y if CPU_INTEL_COMMON diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 161201244c..530ecee009 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,6 @@ ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c -ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 57a5fe602c..fdacd1f74b 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -3,7 +3,7 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H -#include +#include void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); @@ -17,9 +17,32 @@ void set_feature_ctrl_lock(void); struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); +/* + * Returns true if CPU supports Hyper-Threading. + */ +bool intel_ht_supported(void); + /* * Returns true if it's not thread 0 on a hyperthreading enabled core. */ bool intel_ht_sibling(void); +/* + * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes + * to the enablement state as suggested in Intel document 325384-070US. + */ +void set_aesni_lock(void); + +/* Enable local CPU APIC TPR (Task Priority Register) updates */ +void enable_lapic_tpr(void); + +/* Enable DCA (Direct Cache Access) */ +void configure_dca_cap(void); + +/* + * Set EPB (Energy Performance Bias) + * Possible values are 0 (performance) to 15 (powersave). + */ +void set_energy_perf_bias(u8 policy); + #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index f2c386db4c..c5f43ef22e 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -3,9 +3,13 @@ #include #include #include +#include +#include #include #include "common.h" +#define CPUID_6_ECX_EPB (1 << 3) + void set_vmx_and_lock(void) { set_feature_ctrl_vmx(); @@ -103,7 +107,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 8, .bit_offset = 0, - .access_size = 4, + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, .addrl = 0, .addrh = 0, }; @@ -111,7 +115,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) .space_id = ACPI_ADDRESS_SPACE_MEMORY, .bit_width = 0, .bit_offset = 0, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0, .addrh = 0, }; @@ -126,13 +130,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) */ config->regs[CPPC_HIGHEST_PERF] = msr; - /* - * Nominal Performance -> Guaranteed Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_NOMINAL_PERF] = msr; - /* * Lowest Nonlinear Performance -> Most Efficient Performance: * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, @@ -154,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; + msr.addrl = MSR_PLATFORM_INFO; + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_NOMINAL_PERF] = msr; + msr.addrl = IA32_HWP_REQUEST; /* @@ -235,11 +241,23 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) if (version >= 2) { /* Autonomous Selection Enable is populated below */ - /* Autonomous Activity Window Register */ - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + msr.addrl = IA32_HWP_REQUEST; - /* Energy Performance Preference Register */ - config->regs[CPPC_PERF_PREF] = unsupported; + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + msr.bit_width = 10; + msr.bit_offset = 32; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; /* Reference Performance */ config->regs[CPPC_REF_PERF] = unsupported; @@ -259,8 +277,51 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; msr.bit_width = 32; msr.bit_offset = 0; - msr.access_size = 0; + msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; msr.addrl = 1; config->regs[CPPC_AUTO_SELECT] = msr; } } + +void set_aesni_lock(void) +{ + msr_t msr; + + if (!CONFIG(SET_MSR_AESNI_LOCK_BIT)) + return; + + if (!(cpu_get_feature_flags_ecx() & CPUID_AES)) + return; + + /* Only run once per core as specified in the MSR datasheet */ + if (intel_ht_sibling()) + return; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if (msr.lo & AESNI_LOCK) + return; + + msr_set(MSR_FEATURE_CONFIG, AESNI_LOCK); +} + +void enable_lapic_tpr(void) +{ + msr_unset(MSR_PIC_MSG_CONTROL, TPR_UPDATES_DISABLE); +} + +void configure_dca_cap(void) +{ + if (cpu_get_feature_flags_ecx() & CPUID_DCA) + msr_set(IA32_PLATFORM_DCA_CAP, DCA_TYPE0_EN); +} + +void set_energy_perf_bias(u8 policy) +{ + u8 epb = policy & ENERGY_POLICY_MASK; + + if (!(cpuid_ecx(6) & CPUID_6_ECX_EPB)) + return; + + msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb); + printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb); +} diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 7772171f0d..3d46bbc4b9 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -45,6 +45,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index d68614974f..fce7576673 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -3,6 +3,13 @@ #include #include #include +#include + +bool intel_ht_supported(void) +{ + /* Is HyperThreading supported? */ + return !!(cpuid_edx(1) & CPUID_FEAURE_HTT); +} /* * Return true if running thread does not have the smallest lapic ID @@ -13,8 +20,7 @@ bool intel_ht_sibling(void) struct cpuid_result result; unsigned int core_ids, apic_ids, threads; - /* Is Hyper-Threading supported */ - if (!(cpuid_edx(1) & CPUID_FEAURE_HTT)) + if (!intel_ht_supported()) return false; apic_ids = 1; diff --git a/src/cpu/intel/common/voltage.c b/src/cpu/intel/common/voltage.c new file mode 100644 index 0000000000..38951a06db --- /dev/null +++ b/src/cpu/intel/common/voltage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* This is not an architectural MSR. */ +#define MSR_PERF_STATUS 0x198 + +unsigned int smbios_cpu_get_voltage(void) +{ + return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192; +} diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index fa10802926..9ea867e579 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,7 +5,7 @@ config CPU_INTEL_FIRMWARE_INTERFACE_TABLE config CPU_INTEL_NUM_FIT_ENTRIES int - default 16 if INTEL_TXT + default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 4b540ba5df..8d8f07d750 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -1 +1,27 @@ bootblock-y += fit.S + +FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG)) + +ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) + +$(call add_intermediate, add_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL)) + @printf " UPDATE-FIT Microcode\n" + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT + +# Second FIT in TOP_SWAP bootblock +ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) + +$(call add_intermediate, add_ts_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL)) + @printf " UPDATE-FIT Top Swap: Microcode\n" +ifneq ($(FIT_ENTRY),) + $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT +endif # FIT_ENTRY + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT + +endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK + +endif # CONFIG_CPU_MICROCODE_CBFS_NONE + +endif # CONFIG_UPDATE_IMAGE diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S index 3b7396c5ce..afecacdcd8 100644 --- a/src/cpu/intel/fit/fit.S +++ b/src/cpu/intel/fit/fit.S @@ -6,7 +6,6 @@ fit_pointer: .long fit_table .long 0 -.previous .section .text .align 16 @@ -29,4 +28,3 @@ fit_table: .byte 0x7d .fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 fit_table_end: -.previous diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld deleted file mode 100644 index 2e8749bb12..0000000000 --- a/src/cpu/intel/fit/fit.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = 0xffffffc0; - .fit_pointer (.): { - KEEP(*(.fit_pointer)) - } -} diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 54cb99fb9e..0d3d132006 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,11 +6,8 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC @@ -22,6 +19,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select HAVE_ASAN_IN_ROMSTAGE + select CPU_INTEL_COMMON_VOLTAGE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 676acce9dd..7c99df36c0 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,18 @@ #include +static int cstate_set_lp[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT, +}; + +static int cstate_set_trad[3] = { + C_STATE_C1, + C_STATE_C3, + C_STATE_C6_LONG_LAT, +}; + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -30,85 +42,6 @@ static int get_cores_per_package(void) return cores; } -static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - -static void generate_C_state_entries(void) -{ - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -161,6 +94,37 @@ static void generate_T_state_entries(int core, int cores_per_package) ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static void generate_C_state_entries(void) +{ + acpi_cstate_t map[3]; + int *set; + int i; + + struct cpu_info *info; + struct cpu_driver *cpu; + + /* Find CPU map of supported C-states */ + info = cpu_info(); + if (!info) + return; + cpu = find_cpu_driver(info->cpu); + if (!cpu || !cpu->cstates) + return; + + if (haswell_is_ult()) + set = cstate_set_lp; + else + set = cstate_set_trad; + + for (i = 0; i < ARRAY_SIZE(map); i++) { + map[i] = cpu->cstates[set[i]]; + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); +} + static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; @@ -209,7 +173,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * HASWELL_BCLK; + clock_max = ratio_max * CPU_BCLK; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -273,7 +237,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * HASWELL_BCLK; + clock = ratio * CPU_BCLK; acpigen_write_PSS_package( clock, /*MHz*/ @@ -307,19 +271,19 @@ void generate_cpu_entries(const struct device *device) /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, + (cpuID - 1) * cores_per_package+coreID - 1, pcontrol_blk, plen); /* Generate P-state tables */ generate_P_state_entries( - coreID-1, cores_per_package); + coreID - 1, cores_per_package); /* Generate C-state tables */ generate_C_state_entries(); /* Generate T-state tables */ generate_T_state_entries( - cpuID-1, cores_per_package); + cpuID - 1, cores_per_package); acpigen_pop_len(); } diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2abad..7066637f24 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "haswell.h" @@ -50,6 +51,10 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(TPM1) || CONFIG(TPM2)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 7d41461388..16f1079c32 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,16 +3,35 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC -struct cpu_intel_haswell_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ +#include +#include - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; - int tcc_offset; /* TCC Activation Offset */ + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + +struct cpu_intel_haswell_config { + int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1f84b821a9..3bf9225a1f 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include "haswell.h" void intel_cpu_haswell_finalize_smm(void) { + /* Lock memory configuration to protect SMM */ + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index b336e4c2c6..5084cd3bef 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -18,26 +18,32 @@ #define HASWELL_STEPPING_ULT_C0 1 /* Haswell bus clock is fixed at 100MHz */ -#define HASWELL_BCLK 100 +#define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 - -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 - +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -54,7 +60,7 @@ #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) -/* long duration in low dword, short duration in high dword */ +/* Long duration in low dword, short duration in high dword */ #define MSR_PKG_POWER_LIMIT 0x610 #define PKG_POWER_LIMIT_MASK 0x7fff #define PKG_POWER_LIMIT_EN (1 << 15) @@ -77,33 +83,34 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bit definitions */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + +/* Intel suggested latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base) * 5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" @@ -118,6 +125,27 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif +/* + * List of supported C-states for Haswell and Broadwell. + * Only the ULT parts support C8, C9, and C10. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6_SHORT_LAT = 4, + C_STATE_C6_LONG_LAT = 5, + C_STATE_C7_SHORT_LAT = 6, + C_STATE_C7_LONG_LAT = 7, + C_STATE_C7S_SHORT_LAT = 8, + C_STATE_C7S_LONG_LAT = 9, + C_STATE_C8 = 10, + C_STATE_C9 = 11, + C_STATE_C10 = 12, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); @@ -126,8 +154,9 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); /* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638da0..fa2f3f631c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,41 +20,6 @@ #include "haswell.h" #include "chip.h" -/* Intel suggested latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -186,29 +151,8 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +191,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -259,7 +203,7 @@ static void calibrate_24mhz_bclk(void) return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } @@ -284,8 +228,17 @@ static u32 pcode_mailbox_read(u32 command) static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr; + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n"); /* Configure VR_CURRENT_CONFIG. */ @@ -295,7 +248,7 @@ static void initialize_vr_config(void) msr.hi &= 0xc0000000; msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ if (haswell_is_ult()) msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ @@ -315,24 +268,35 @@ static void initialize_vr_config(void) msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } + if (!haswell_is_ult()) + return; + + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ + msr.lo |= 0x006f; + wrmsr(MSR_VR_MISC_CONFIG2, msr); } static void configure_pch_power_sharing(void) @@ -403,8 +367,7 @@ void set_power_limits(u8 power_limit_1_time) u8 power_limit_1_val; if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - - 1; + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -481,12 +444,6 @@ static void configure_c_states(void) /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0xffff; - msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); @@ -512,26 +469,24 @@ static void configure_c_states(void) msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - /* Haswell ULT only supoprts the 3-5 latency response registers.*/ - if (haswell_is_ult()) { - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + /* Only Haswell ULT supports the 3-5 latency response registers */ + if (!haswell_is_ult()) + return; - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); - } + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } static void configure_thermal_target(void) @@ -577,29 +532,6 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -607,7 +539,10 @@ static void set_max_ratio(void) perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; @@ -618,28 +553,8 @@ static void set_max_ratio(void) } wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "haswell: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); -} - -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", - policy); + printk(BIOS_DEBUG, "CPU: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } static void configure_mca(void) @@ -659,7 +574,7 @@ static void configure_mca(void) } /* All CPUs including BSP will run the following function. */ -static void haswell_init(struct device *cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -686,9 +601,6 @@ static void haswell_init(struct device *cpu) /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -704,10 +616,11 @@ static void pre_mp_init(void) initialize_vr_config(); - if (haswell_is_ult()) { - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); - } + if (!haswell_is_ult()) + return; + + calibrate_24mhz_bclk(); + configure_pch_power_sharing(); } static int get_cpu_count(void) @@ -743,6 +656,9 @@ static void per_cpu_smm_trigger(void) static void post_mp_init(void) { + /* Set Max Ratio */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); @@ -769,7 +685,7 @@ void mp_init_cpus(struct bus *cpu_bus) } static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = cpu_core_init, }; static const struct cpu_device_id cpu_table[] = { @@ -778,6 +694,8 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 0f7585ae69..9e3554f9e3 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,24 +17,6 @@ #include #include "haswell.h" -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - - - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) @@ -111,7 +93,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur @@ -158,7 +140,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; - u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -199,7 +180,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->uncore_prmrr_base.lo = prmrr_base; params->uncore_prmrr_base.hi = 0; params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + MTRR_PHYS_MASK_VALID; params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } @@ -284,6 +265,5 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 329b693140..ef3367d019 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -52,7 +52,6 @@ void intel_sibling_init(struct device *cpu) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 8080545d39..0f362d4b35 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -126,9 +126,7 @@ const void *intel_microcode_find(void) unsigned int x86_model, x86_family; msr_t msr; - ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, - µcode_len); + ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, µcode_len); if (ucode_updates == NULL) return NULL; diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a5ed..28705230a2 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,7 +43,8 @@ * if the revision of the update is newer than what is installed */ -.section .text +.code32 +.section .init .global update_bsp_microcode update_bsp_microcode: diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 79dda288b6..777eff6180 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e040e0d698..3e4de1fa31 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -9,7 +9,7 @@ #include #include #include -#include + #include "chip.h" static void init_timer(void) @@ -166,6 +166,8 @@ static void configure_emttm_tables(void) wrmsr(MSR_EMTTM_CR_TABLE(5), msr); } +#define IA32_PECI_CTL 0x5a0 + static void configure_misc(const int eist, const int tm2, const int emttm) { msr_t msr; @@ -208,6 +210,13 @@ static void configure_misc(const int eist, const int tm2, const int emttm) msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); } + + /* Enable PECI + WARNING: due to Erratum AW67 described in Intel document #318733 + the microcode must be updated before this MSR is written to. */ + msr = rdmsr(IA32_PECI_CTL); + msr.lo |= 1; + wrmsr(IA32_PECI_CTL, msr); } #define PIC_SENS_CFG 0x1aa @@ -233,7 +242,6 @@ static void model_1067x_init(struct device *cpu) { char processor_name[49]; - /* Gather some information: */ const struct cpuid_result cpuid1 = cpuid(1); @@ -256,10 +264,6 @@ static void model_1067x_init(struct device *cpu) /* Test for TM2 only if EIST is available. */ const char tm2 = eist && (cpuid1.ecx & (1 << 8)); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); @@ -292,7 +296,7 @@ static struct device_operations cpu_dev_ops = { }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x10676 }, { X86_VENDOR_INTEL, 0x10677 }, { X86_VENDOR_INTEL, 0x1067A }, { 0, 0 }, diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 3404e7fb4a..ff6cbec8dc 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -33,7 +33,7 @@ static int get_cpu_count(void) static void get_microcode_info(const void **microcode, int *parallel) { *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL @@ -63,7 +63,7 @@ static void per_cpu_smm_trigger(void) } else { if (!CONFIG(SET_IA32_FC_LOCK_BIT)) printk(BIOS_INFO, - "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); + "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); } diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 1ba8894940..bf9256af45 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_106CX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 927bebbbf2..278d8dea81 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -64,9 +63,6 @@ static void model_106cx_init(struct device *cpu) { char processor_name[49]; - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 39beb227bd..04b9e6785b 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -5,11 +5,8 @@ if CPU_INTEL_MODEL_2065X config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 21f75a3f56..d9b1057324 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -4,8 +4,6 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_model_2065x_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index d530fba5e7..e1fa968d9c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,12 +14,8 @@ void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); - - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); + msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15)); /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); } diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 1e3d41835a..566f82ed89 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,6 @@ #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 3208e10849..f1a2150d71 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -110,7 +110,6 @@ int cpu_config_tdp_levels(void) return (platform_info.hi >> 1) & 3; } - static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; @@ -149,16 +148,6 @@ static void configure_misc(void) wrmsr(IA32_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -196,9 +185,6 @@ static void model_2065x_init(struct device *cpu) { char processor_name[49]; - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Clear out pending MCEs */ configure_mca(); @@ -218,6 +204,8 @@ static void model_2065x_init(struct device *cpu) /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); + set_aesni_lock(); + /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); @@ -260,7 +248,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) @@ -282,7 +270,6 @@ static void post_mp_init(void) smm_lock(); } - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c6a50207c5..5098ac76d5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -5,11 +5,8 @@ if CPU_INTEL_MODEL_206AX config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9ff0673ece..beb2fbc579 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -9,23 +8,15 @@ #include #include #include +#include + #include "model_206ax.h" #include "chip.h" -static int get_cores_per_package(void) +static int get_logical_cores_per_package(void) { - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; + msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT); + return msr.lo & 0xffff; } static void generate_cstate_entries(acpi_cstate_t *cstates, @@ -40,8 +31,6 @@ static void generate_cstate_entries(acpi_cstate_t *cstates, ++cstate_count; if (c3 > 0) ++cstate_count; - if (!cstate_count) - return; acpigen_write_package(cstate_count + 1); acpigen_write_byte(cstate_count); @@ -87,20 +76,8 @@ static void generate_C_state_entries(void) return; acpigen_write_method("_CST", 0); - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); + acpigen_emit_byte(RETURN_OP); + generate_cstate_entries(cpu->cstates, conf->acpi_c1, conf->acpi_c2, conf->acpi_c3); acpigen_pop_len(); } @@ -287,7 +264,7 @@ void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); + int cores_per_package = get_logical_cores_per_package(); int numcpus = totalcores/cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 4e40830f94..4fff04a705 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -4,15 +4,9 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_model_206ax_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ + int acpi_c1; /* ACPI C1 */ + int acpi_c2; /* ACPI C2 */ + int acpi_c3; /* ACPI C3 */ int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index c7579f1764..2298684421 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include "model_206ax.h" /* MSR Documentation based on @@ -12,13 +12,9 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); - /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index e24993ceb4..04e463934a 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -3,8 +3,37 @@ #ifndef _CPU_INTEL_MODEL_206AX_H #define _CPU_INTEL_MODEL_206AX_H +#include #include +/* SandyBridge CPU stepping */ +#define SNB_STEP_B2 2 +#define SNB_STEP_C0 3 +#define SNB_STEP_D0 5 /* Also J0 */ +#define SNB_STEP_D1 6 +#define SNB_STEP_D2 7 /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 0 +#define IVB_STEP_B0 2 +#define IVB_STEP_C0 4 +#define IVB_STEP_K0 5 +#define IVB_STEP_D0 6 +#define IVB_STEP_E0 8 +#define IVB_STEP_E1 9 + +#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) +#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) +#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) +#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) +#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) + +#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) +#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) +#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) +#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) +#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) + /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 @@ -15,7 +44,6 @@ #define FLEX_RATIO_EN (1 << 16) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) @@ -89,4 +117,9 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); int get_platform_id(void); +static inline u8 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + #endif diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index e69d4fa8da..31099fd486 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -18,6 +18,7 @@ #include "chip.h" #include #include +#include /* * List of supported C-states in this processor @@ -338,29 +339,6 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -383,18 +361,23 @@ static void set_max_ratio(void) ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } -static void set_energy_perf_bias(u8 policy) +unsigned int smbios_cpu_get_max_speed_mhz(void) { msr_t msr; + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; +} - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; +} - printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); +unsigned int smbios_processor_external_clock(void) +{ + return SANDYBRIDGE_BCLK; } static void configure_mca(void) @@ -442,9 +425,6 @@ static void model_206ax_report(void) static void model_206ax_init(struct device *cpu) { - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Clear out pending MCEs */ configure_mca(); @@ -470,6 +450,8 @@ static void model_206ax_init(struct device *cpu) /* Thermal throttle activation offset */ configure_thermal_target(); + set_aesni_lock(); + /* Enable Direct Cache Access */ configure_dca_cap(); @@ -512,7 +494,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) @@ -534,7 +516,6 @@ static void post_mp_init(void) smm_lock(); } - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 6a1d09c35f..2eaa55e5dc 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_65X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 283927ff60..7fdb67f6c8 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_67X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 4f5d1acd2e..1b57dfc9df 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -2,8 +2,5 @@ config CPU_INTEL_MODEL_68X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index eb4b6751cd..a87228c7f4 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_6BX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 3af52722f3..31897ad7aa 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_6EX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 43d4599fc6..16c6866f45 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index e3d327ca02..1911ebc6c3 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index f1d64b7454..f6f838de39 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,5 @@ subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-y += ../smm/gen1 -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) \ + 3rdparty/intel-microcode/intel-ucode/06-16-01 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index b81eca4cfb..d0987b4a63 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -147,7 +146,6 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x10661 }, /* Intel Core 2 Celeron Conroe-L */ - { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */ { 0, 0 }, }; diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index d00fc2436a..18844d13a9 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_6XX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index dcf94415d0..afa93711b8 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,11 +1,6 @@ config CPU_INTEL_MODEL_F2X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1caf..61923b8165 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b51cd..d146dd494d 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,8 +1,4 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index ce3634b667..57d1fd4af0 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -189,7 +189,6 @@ int calculate_l2_latency(void) return 0; } - /* Setup address, data_high:data_low into the L2 * control registers and then issue command with correct cache way */ diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d17fe0ca69..36884a1b1c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -25,7 +25,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ @@ -60,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params) printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72e53..7a303af08c 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config C_ENV_BOOTBLOCK_SIZE hex - default 0x4000 + default 0x8000 config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index fba5df2f86..9235272002 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -104,7 +104,6 @@ void speedstep_gen_pstates(sst_table_t *const table) /* Gather speedstep limits. */ speedstep_get_limits(¶ms); - /*\ First, find the number of normal states: \*/ /* Calculate with doubled values to work @@ -130,7 +129,6 @@ void speedstep_gen_pstates(sst_table_t *const table) if (states < 2) /* Report at least two normal states. */ states = 2; - /*\ Now, fill the table: \*/ table->num_states = 0; diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 21ada02a5d..641cea815c 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -2,12 +2,60 @@ config CPU_QEMU_X86 bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + +if CPU_QEMU_X86 + +# coreboot i440fx does not support SMM +choice + prompt "AP init" + default CPU_QEMU_X86_LAPIC_INIT + +config CPU_QEMU_X86_LAPIC_INIT + bool "Legacy serial LAPIC init" + +config CPU_QEMU_X86_PARALLEL_MP + bool "Parallel MP init" + select PARALLEL_MP + +endchoice + +choice + prompt "SMM support" + default CPU_QEMU_X86_ASEG_SMM + depends on BOARD_EMULATION_QEMU_X86_Q35 + +config CPU_QEMU_X86_NO_SMM + bool "No SMM" + select NO_SMM + +config CPU_QEMU_X86_ASEG_SMM + bool "SMM in ASEG" + depends on !PARALLEL_MP select SMM_ASEG + +#config CPU_QEMU_X86_TSEG_SMM +# bool "SMM in TSEG" +# select SMM_TSEG + +endchoice + +config MAX_CPUS + int + default 4 if SMM_ASEG + default 32 + +config CPU_QEMU_X86_64 + bool "Experimental 64bit support" + select ARCH_ALL_STAGES_X86_64 + select ARCH_POSTCAR_X86_64 + +config CPU_QEMU_X86_32 + bool + default n if CPU_QEMU_X86_64 + default y + select ARCH_ALL_STAGES_X86_32 + select ARCH_POSTCAR_X86_32 +endif diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index fb560d6b7c..3f27e8b247 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c +bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S romstage-y += ../intel/car/romstage.c diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 30f9f9ceb2..07f848a019 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -2,6 +2,15 @@ #include +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) + +.section .init, "ax", @progbits +.code32 + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -22,18 +31,65 @@ cache_as_ram: post_code(0x21) +#if defined(__x86_64__) + /* + * Copy page tables to final location in DRAM. This prevents some strange + * bugs when running KVM enabled: + * Accessing MMX instructions in long mode causes an abort + * Some physical addresses aren't properly translated + * Emulation fault on every instruction fetched due to page tables in ROM + * Enabling or disabling paging causes a fault + * + * First, find page tables in CBFS: + */ + lea pagetables_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmpl $0, %eax + je .Lhlt + + /* Test if page tables are memory-mapped and skip relocation */ + cmpl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + je pages_done + + movl CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + addl %eax, %ebx + movl %ebx, %esi + + movl CBFS_FILE_LEN(%eax), %ecx + bswap %ecx + shr $2, %ecx + + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %edi + +loop: + movl (%esi), %eax + movl %eax, (%edi) + addl $4, %esi + addl $4, %edi + decl %ecx + jnz loop +pages_done: +#endif + movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) - movd %mm1, %rdi - shld %rdi, 32 + movd %mm2, %rdi + shlq $32, %rdi movd %mm1, %rsi or %rsi, %rdi - movd %mm2, %rsi + + movd %mm0, %rsi #else sub $4, %esp @@ -54,3 +110,6 @@ before_c_entry: post_code(POST_DEAD_CODE) hlt jmp .Lhlt + +pagetables_name: + .string "pagetables" diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig deleted file mode 100644 index 119e84bfc1..0000000000 --- a/src/cpu/ti/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/cpu/ti/am335x/Kconfig" diff --git a/src/cpu/ti/Makefile.inc b/src/cpu/ti/Makefile.inc deleted file mode 100644 index 64b22f62f2..0000000000 --- a/src/cpu/ti/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_TI_AM335X) += am335x diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c deleted file mode 100644 index 985e1a1a0b..0000000000 --- a/src/cpu/ti/am335x/bootblock.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include -#include - -void bootblock_soc_init(void) -{ - uint32_t sctlr; - - /* enable dcache */ - sctlr = read_sctlr(); - sctlr |= SCTLR_C; - write_sctlr(sctlr); -} diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/cpu/ti/am335x/dmtimer.c deleted file mode 100644 index b3aa7a18ba..0000000000 --- a/src/cpu/ti/am335x/dmtimer.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "dmtimer.h" - -void dmtimer_start(int num) -{ -} - -uint64_t dmtimer_raw_value(int num) -{ - return 0; -} diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/cpu/ti/am335x/dmtimer.h deleted file mode 100644 index 7e93a0c8f6..0000000000 --- a/src/cpu/ti/am335x/dmtimer.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __CPU_TI_AM335X_DMTIMER_H__ -#define __CPU_TI_AM335X_DMTIMER_H__ - -#include - -#define OSC_HZ 24000000 - -void dmtimer_start(int num); -uint64_t dmtimer_raw_value(int num); - -#endif diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c deleted file mode 100644 index b57258b6c8..0000000000 --- a/src/cpu/ti/am335x/monotonic_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -#include "dmtimer.h" - -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint64_t last_value; -} mono_counter; - -static const uint32_t clocks_per_usec = OSC_HZ/1000000; - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t current_tick; - uint64_t usecs_elapsed; - - if (!mono_counter.initialized) { - init_timer(); - mono_counter.last_value = dmtimer_raw_value(0); - mono_counter.initialized = 1; - } - - current_tick = dmtimer_raw_value(0); - usecs_elapsed = (current_tick - mono_counter.last_value) / - clocks_per_usec; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12beb66..5e90da1413 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -108,7 +108,7 @@ _start16bit: movw $nullidt_offset, %bx subw %ax, %bx lidt %cs:(%bx) - movw $gdtptr16_offset, %bx + movw $gdtptr_offset, %bx subw %ax, %bx lgdtl %cs:(%bx) @@ -124,14 +124,11 @@ _start16bit: ljmpl $ROM_CODE_SEG, $__protected_start /** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment + * The gdt is defined in gdt_init.S, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ -.align 4 -.globl gdtptr16 -gdtptr16: - .word gdt_end - gdt -1 /* compute the table limit */ - .long gdt /* we know the offset */ +__gdtptr: + .long gdtptr .align 4 .globl nullidt @@ -139,7 +136,3 @@ nullidt: .word 0 /* limit */ .long 0 .word 0 - -.globl _estart16bit -_estart16bit: - .code32 diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld deleted file mode 100644 index bc456e7cb0..0000000000 --- a/src/cpu/x86/16bit/entry16.ld +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -gdtptr16_offset = gdtptr16 & 0xffff; -nullidt_offset = nullidt & 0xffff; - -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. - */ -#if CONFIG(SIPI_VECTOR_IN_ROM) -_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); -ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; -#endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld deleted file mode 100644 index b90dd04992..0000000000 --- a/src/cpu/x86/16bit/reset16.ld +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* _RESET_VECTOR: typically the top of the ROM */ - -SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - - . = CONFIG_X86_RESET_VECTOR; - .reset . : { - *(.reset); - . = 15; - BYTE(0x00); - } -} diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index be67b534cb..873a809616 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -4,33 +4,14 @@ #include #include -#include .code32 /* - * When we come here we are in protected mode. We expand - * the stack and copies the data segment from ROM to the - * memory. - * - * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. - * + * When we come here we are in protected mode. * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. - * - * In the bootblock there is already a ljmp to __protected_start and - * the reset vector jumps to symbol _start16bit in entry16.inc from - * the reset vectors's symbol which is _start. Therefore, don't - * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK -.globl _start -_start: -#endif - - lgdt %cs:gdtptr - ljmp $ROM_CODE_SEG, $__protected_start __protected_start: /* Save the BIST value */ diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc929..70255173f1 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -16,7 +16,12 @@ #endif #include +#if defined(__RAMSTAGE__) +#include +#else #include +#endif + setup_longmode: /* Get page table address */ @@ -42,7 +47,12 @@ setup_longmode: movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ +#if defined(__RAMSTAGE__) + ljmp $RAM_CODE_SEG64, $__longmode_start +#else ljmp $ROM_CODE_SEG64, $__longmode_start + +#endif .code64 __longmode_start: diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 48837d96a9..91cccb535e 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -12,14 +12,23 @@ #include #include +#if defined(__RAMSTAGE__) +#include +#define CODE_SEG RAM_CODE_SEG +#define DATA_SEG RAM_DATA_SEG +#else #include +#define CODE_SEG ROM_CODE_SEG +#define DATA_SEG ROM_DATA_SEG +#endif drop_longmode: +#if !ENV_CACHE_AS_RAM /* Ensure cache is clean. */ wbinvd - +#endif /* Set 32-bit code segment and ss */ - mov $ROM_CODE_SEG, %rcx + mov $CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ call SetCodeSelector32 @@ -54,7 +63,7 @@ __longmode_compatibility: /* Running in 32-bit compatibility mode */ /* Use flat data segment */ - movl $ROM_DATA_SEG, %eax + movl $DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S new file mode 100644 index 0000000000..eea104bcf3 --- /dev/null +++ b/src/cpu/x86/64bit/mode_switch.S @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.text +.code64 + .section ".text.protected_mode_call", "ax", @progbits + .globl protected_mode_call_narg +protected_mode_call_narg: + + push %rbp + mov %rsp, %rbp + /* Preserve registers */ + push %rbx + push %r12 + push %r13 + push %r14 + push %r15 + + /* Arguments to stack */ + push %rdi + push %rsi + push %rdx + push %rcx + + #include + + movl -48(%ebp), %eax /* Argument count */ + movl -64(%ebp), %edx /* Argument 0 */ + movl -72(%ebp), %ecx /* Argument 1 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + test %eax, %eax + je 1f /* Zero arguments */ + + subl $1, %eax + test %eax, %eax + je 2f /* One argument */ + + /* Two arguments */ + subl $8, %esp + pushl %ecx /* Argument 1 */ + pushl %edx /* Argument 0 */ + jmp 1f +2: + subl $12, %esp + pushl %edx /* Argument 0 */ + +1: + movl -56(%ebp), %ebx /* Function to call */ + call *%ebx + movl %eax, %ebx + + /* Preserves ebx */ + #include + + /* Place return value in rax */ + movl %ebx, %eax + + /* Restore registers */ + mov -40(%rbp), %r15 + mov -32(%rbp), %r14 + mov -24(%rbp), %r13 + mov -16(%rbp), %r12 + mov -8(%rbp), %rbx + + /* Restore stack pointer */ + mov %rbp, %rsp + pop %rbp + + ret diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5394cd023d..b3a16bcf63 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -121,6 +121,14 @@ config SMM_STUB_STACK_SIZE endif +config X86_SMM_LOADER_VERSION2 + bool + default n + depends on HAVE_SMI_HANDLER + help + This option enables SMM module loader that works with server + platforms which may contain more than 32 CPU threads. + config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7581..cd73b72fe3 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,7 @@ subdirs-y += pae + +all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S + subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52a6d..07e63f42de 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -7,6 +7,7 @@ #include +.code32 .section .text .global check_mtrr diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 04ce2261de..988d664c94 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -3,7 +3,7 @@ #include #include -void do_lapic_init(void) +void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 8a44112943..073e6b485b 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -33,7 +33,11 @@ _secondary_start: _secondary_gdt_addr: gdtaddr: .word 0 /* the table limit */ +#if ENV_X86_64 + .quad 0 +#else .long 0 /* we know the offset */ +#endif _secondary_start_end: @@ -54,14 +58,23 @@ __ap_protected_start: /* Load the Interrupt descriptor table */ lidt idtarg +#if ENV_X86_64 + /* entry64.inc preserves ebx. */ + #include + mov secondary_stack, %rsp + andl $0xfffffff0, %esp + mov secondary_cpu_index, %rdi +#else /* Set the stack pointer, and flag that we are done */ xorl %eax, %eax movl secondary_stack, %esp + andl $0xfffffff0, %esp sub $12, %esp /* maintain 16-byte alignment for the call below */ movl secondary_cpu_index, %edi pushl %edi movl %eax, secondary_stack +#endif call secondary_cpu_init 1: hlt diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4005..c691c4882b 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -106,14 +106,13 @@ struct saved_msr { uint32_t hi; } __packed; - /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ extern char _binary_sipi_vector_start[]; /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -339,16 +338,16 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params) setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) - sp->microcode_lock = 0; - else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + else + sp->microcode_lock = 0; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); @@ -435,7 +434,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -452,7 +451,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -463,7 +462,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -478,7 +477,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -489,14 +488,14 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", + if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { + printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return -1; } @@ -726,12 +725,21 @@ static void asmlinkage smm_do_relocation(void *arg) * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ +#if CONFIG(X86_SMM_LOADER_VERSION2) + perm_smbase = smm_get_cpu_smbase(cpu); + mp_state.perm_smbase = perm_smbase; + if (!perm_smbase) { + printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); + return; + } +#else perm_smbase = mp_state.perm_smbase; perm_smbase -= cpu * runtime->save_state_size; - - printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); +#endif /* Setup code checks this callback for validity. */ + printk(BIOS_INFO, "%s : curr_smbase 0x%x perm_smbase 0x%x, cpu = %d\n", + __func__, (int)curr_smbase, (int)perm_smbase, cpu); mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); if (CONFIG(STM)) { @@ -758,9 +766,17 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) static int install_relocation_handler(int num_cpus, size_t save_state_size) { + int cpus = num_cpus; +#if CONFIG(X86_SMM_LOADER_VERSION2) + /* Default SMRAM size is not big enough to concurrently + * handle relocation for more than ~32 CPU threads + * therefore, relocate 1 by 1. */ + cpus = 1; +#endif + struct smm_loader_params smm_params = { .per_cpu_stack_size = CONFIG_SMM_STUB_STACK_SIZE, - .num_concurrent_stacks = num_cpus, + .num_concurrent_stacks = cpus, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = 1, .handler = smm_do_relocation, @@ -770,9 +786,10 @@ static int install_relocation_handler(int num_cpus, size_t save_state_size) if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 0); - if (smm_setup_relocation_handler(&smm_params)) + if (smm_setup_relocation_handler(&smm_params)) { + printk(BIOS_ERR, "%s: smm setup failed\n", __func__); return -1; - + } adjust_smm_apic_id_map(&smm_params); return 0; @@ -781,8 +798,13 @@ static int install_relocation_handler(int num_cpus, size_t save_state_size) static int install_permanent_handler(int num_cpus, uintptr_t smbase, size_t smsize, size_t save_state_size) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to 1KiB. */ + /* + * All the CPUs will relocate to permanaent handler now. Set parameters + * needed for all CPUs. The placement of each CPUs entry point is + * determined by the loader. This code simply provides the beginning of + * SMRAM region, the number of CPUs who will use the handler, the stack + * size and save state size for each CPU. + */ struct smm_loader_params smm_params = { .per_cpu_stack_size = CONFIG_SMM_MODULE_STACK_SIZE, .num_concurrent_stacks = num_cpus, @@ -794,7 +816,7 @@ static int install_permanent_handler(int num_cpus, uintptr_t smbase, if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 1); - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); + printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); if (smm_load_module((void *)smbase, smsize, &smm_params)) return -1; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7907..cb7ecdc963 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -104,9 +104,7 @@ static void enable_var_mtrr(unsigned char deftype) #define MTRR_VERBOSE_LEVEL BIOS_NEVER -/* MTRRs are at a 4KiB granularity. Therefore all address calculations can - * be done with 32-bit numbers. This allows for the MTRR code to handle - * up to 2^44 bytes (16 TiB) of address space. */ +/* MTRRs are at a 4KiB granularity. */ #define RANGE_SHIFT 12 #define ADDR_SHIFT_TO_RANGE_SHIFT(x) \ (((x) > RANGE_SHIFT) ? ((x) - RANGE_SHIFT) : RANGE_SHIFT) @@ -115,18 +113,18 @@ static void enable_var_mtrr(unsigned char deftype) #define NUM_FIXED_MTRRS (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR) /* Helpful constants. */ -#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20) -#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) +#define RANGE_1MB PHYS_TO_RANGE_ADDR(1ULL << 20) +#define RANGE_4GB (1ULL << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) #define MTRR_ALGO_SHIFT (8) #define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1) -static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_base_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_base(r)); } -static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_end_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } @@ -402,7 +400,7 @@ static void clear_var_mtrr(int index) } static void prep_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { struct var_mtrr_regs *regs; resource_t rbase; @@ -444,24 +442,51 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state, regs->mask.hi = rsize >> 32; } +/* + * fls64: find least significant bit set in a 64-bit word + * As samples, fls64(0x0) = 64; fls64(0x4400) = 10; + * fls64(0x40400000000) = 34. + */ +static uint32_t fls64(uint64_t x) +{ + uint32_t lo = (uint32_t)x; + if (lo) + return fls(lo); + uint32_t hi = x >> 32; + return fls(hi) + 32; +} + +/* + * fms64: find most significant bit set in a 64-bit word + * As samples, fms64(0x0) = 0; fms64(0x4400) = 14; + * fms64(0x40400000000) = 42. + */ +static uint32_t fms64(uint64_t x) +{ + uint32_t hi = (uint32_t)(x >> 32); + if (!hi) + return fms((uint32_t)x); + return fms(hi) + 32; +} + static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { while (size != 0) { uint32_t addr_lsb; uint32_t size_msb; - uint32_t mtrr_size; + uint64_t mtrr_size; - addr_lsb = fls(base); - size_msb = fms(size); + addr_lsb = fls64(base); + size_msb = fms64(size); /* All MTRR entries need to have their base aligned to the mask * size. The maximum size is calculated by a function of the * min base bit set and maximum size bit set. */ if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; + mtrr_size = 1ULL << size_msb; else - mtrr_size = 1 << addr_lsb; + mtrr_size = 1ULL << addr_lsb; if (var_state->prepare_msrs) prep_var_mtrr(var_state, base, mtrr_size, mtrr_type); @@ -472,8 +497,8 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, } } -static uint32_t optimize_var_mtrr_hole(const uint32_t base, - const uint32_t hole, +static uint64_t optimize_var_mtrr_hole(const uint64_t base, + const uint64_t hole, const uint64_t limit, const int carve_hole) { @@ -531,7 +556,7 @@ static uint32_t optimize_var_mtrr_hole(const uint32_t base, static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, struct range_entry *r) { - uint32_t a1, a2, b1, b2; + uint64_t a1, a2, b1, b2; int mtrr_type, carve_hole; /* @@ -671,6 +696,7 @@ static void __calc_var_mtrrs(struct memranges *addr_space, wb_deftype_count += var_state.mtrr_index; } } + *num_def_wb_mtrrs = wb_deftype_count; *num_def_uc_mtrrs = uc_deftype_count; } diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7de6..e1b90890ed 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -5,6 +5,8 @@ #include #include +#define __RAMSTAGE__ + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -82,10 +84,9 @@ _start: mov idt_ptr, %ebx lidt (%ebx) - /* Obtain CPU number. */ - movl ap_count, %eax 1: - movl %eax, %ecx + /* Obtain CPU number. */ + movl ap_count, %ecx inc %ecx lock cmpxchg %ecx, ap_count jnz 1b @@ -101,6 +102,13 @@ _start: /* Save CPU number. */ mov %ecx, %esi + /* + * The following code only needs to run on Intel platforms and thus the caller + * doesn't provide a microcode_ptr if not on Intel. + * On Intel platforms which update microcode using FIT the version check will + * also skip the microcode update. + */ + /* Determine if one should check microcode versions. */ mov microcode_ptr, %edi test %edi, %edi @@ -115,13 +123,23 @@ _start: test %edx, %edx jnz microcode_done + /* + * Intel SDM and various BWGs specify to use a semaphore to update microcode + * on one thread per core on Hyper-Threading enabled CPUs. Due to this complex + * code would be necessary to determine the core #ID, initializing and picking + * the right semaphore out of CONFIG_MAX_CPUS / 2. + * Instead of the per core approachm, as recommended, use one global spinlock. + * Assuming that only pre-FIT platforms with Hyper-Threading enabled and at + * most 8 threads will ever run into this condition, the boot delay is negligible. + */ + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode /* Protect microcode loading. */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: @@ -192,11 +210,24 @@ load_msr: mov %eax, %cr4 #endif +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ +#include + + mov %rsi, %rdi /* cpu_num */ + + movl c_handler, %eax + call *%rax +#else /* c_handler(cpu_num), preserve proper stack alignment */ sub $12, %esp push %esi /* cpu_num */ + mov c_handler, %eax call *%eax +#endif + + halt_jump: hlt jmp halt_jump diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a8a2..1ed018d1be 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,6 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_X86_SMM_LOADER_VERSION2),y) +ramstage-y += smm_module_loaderv2.c +else ramstage-y += smm_module_loader.c +endif ramstage-y += smi_trigger.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -13,10 +17,10 @@ endif smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ -smm-c-deps:=$$(OPTION_TABLE_H) +smm-c-deps+=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -28,6 +32,8 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c @@ -72,8 +78,10 @@ $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c new file mode 100644 index 0000000000..bb08f86414 --- /dev/null +++ b/src/cpu/x86/smm/save_state.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* These are weakly linked such that platforms can link only the save state + ops they actually require. */ +const struct smm_save_state_ops *legacy_ops __weak = NULL; +const struct smm_save_state_ops *em64t100_ops __weak = NULL; +const struct smm_save_state_ops *em64t101_ops __weak = NULL; +const struct smm_save_state_ops *amd64_ops __weak = NULL; + +static const struct smm_save_state_ops *save_state; + +/* Returns -1 on failure, 0 on success */ +static int init_save_state(void) +{ + const uint32_t revision = smm_revision(); + int i; + static bool initialized = false; + const struct smm_save_state_ops *save_state_ops[] = { + legacy_ops, + em64t100_ops, + em64t101_ops, + amd64_ops, + }; + + if (initialized) + return 0; + + for (i = 0; i < ARRAY_SIZE(save_state_ops); i++) { + const struct smm_save_state_ops *ops = save_state_ops[i]; + const uint32_t *rev; + + if (ops == NULL) + continue; + + for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++) + if (*rev == revision) { + save_state = ops; + initialized = true; + return 0; + } + } + + return -1; +} + +int get_apmc_node(u8 cmd) +{ + if (init_save_state()) + return -1; + + return save_state->apmc_node(cmd); +} + +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + if (init_save_state()) + return -1; + + if (node > CONFIG_MAX_CPUS) + return -1; + + return save_state->get_reg(reg, node, out, length); +} + +int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + if (init_save_state()) + return -1; + + if (node > CONFIG_MAX_CPUS) + return -1; + + return save_state->set_reg(reg, node, in, length); +} diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index 4b637450b7..7e3ddb1613 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include -static void set_smm_gnvs_ptr(void); - int apm_control(u8 cmd) { if (!CONFIG(HAVE_SMI_HANDLER)) @@ -23,9 +20,6 @@ int apm_control(u8 cmd) case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); break; - case APM_CNT_GNVS_UPDATE: - set_smm_gnvs_ptr(); - return 0; case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "Finalizing SMM.\n"); break; @@ -45,32 +39,3 @@ int apm_control(u8 cmd) printk(BIOS_DEBUG, "APMC done.\n"); return 0; } - -static void set_smm_gnvs_ptr(void) -{ - uintptr_t gnvs_address; - - if (CONFIG(ACPI_NO_SMI_GNVS)) { - printk(BIOS_WARNING, "%s() is not implemented\n", __func__); - return; - } - - gnvs_address = (uintptr_t)acpi_get_gnvs(); - if (!gnvs_address) - return; - - /* - * Issue SMI to set the gnvs pointer in SMM. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" (gnvs_address), - "d" (APM_CNT) - ); -} diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 8fd95bb563..0d9131e429 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -14,23 +14,6 @@ #include #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -120,6 +103,32 @@ static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) return (void *)base; } +/* This returns the SMM revision from the savestate of CPU0, + which is assumed to be the same for all CPU's. See the memory + map in smmhandler.S */ +uint32_t smm_revision(void) +{ + return *(uint32_t *)(SMM_BASE + SMM_ENTRY_OFFSET * 2 - SMM_REVISION_OFFSET_FROM_TOP); +} + +void *smm_get_save_state(int cpu) +{ + switch (smm_revision()) { + case 0x00030002: + case 0x00030007: + return smm_save_state(SMM_BASE, SMM_LEGACY_ARCH_OFFSET, cpu); + case 0x00030100: + return smm_save_state(SMM_BASE, SMM_EM64T100_ARCH_OFFSET, cpu); + case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ + return smm_save_state(SMM_BASE, SMM_EM64T101_ARCH_OFFSET, cpu); + case 0x00020064: + case 0x00030064: + return smm_save_state(SMM_BASE, SMM_AMD64_ARCH_OFFSET, cpu); + } + + return NULL; +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {SMM_BASE, SMM_DEFAULT_SIZE}; @@ -133,11 +142,9 @@ bool smm_region_overlaps_handler(const struct region *r) * @param smm_revision revision of the smm state save map */ -void smi_handler(u32 smm_revision) +void smi_handler(void) { unsigned int node; - smm_state_save_area_t state_save; - u32 smm_base = SMM_BASE; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -163,36 +170,10 @@ void smi_handler(u32 smm_revision) printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_revision) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + /* Use smm_get_save_state() to see if the smm revision is supported */ + if (smm_get_save_state(node) == NULL) { + printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); + printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index af5968d9d5..e232028e4b 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -2,6 +2,9 @@ /* Maximum number of CPUs/cores */ CPUS = 4; + +_ = ASSERT(CPUS >= CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); + ENTRY(smm_handler_start); SECTIONS diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 02682b4191..8532d59b9d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -69,7 +69,6 @@ static void smi_set_eos(void) southbridge_smi_set_eos(); } - static u32 pci_orig; /** @@ -88,7 +87,6 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } - static const struct smm_runtime *smm_runtime; struct global_nvs *gnvs; @@ -99,13 +97,20 @@ void *smm_get_save_state(int cpu) /* This function assumes all save states start at top of default * SMRAM size space and are staggered down by save state size. */ - base = (void *)smm_runtime->smbase; + base = (void *)(uintptr_t)smm_runtime->smbase; base += SMM_DEFAULT_SIZE; base -= (cpu + 1) * smm_runtime->save_state_size; return base; } +uint32_t smm_revision(void) +{ + const uintptr_t save_state = (uintptr_t)(smm_get_save_state(0)); + + return *(uint32_t *)(save_state + smm_runtime->save_state_size - SMM_REVISION_OFFSET_FROM_TOP); +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {smm_runtime->smbase, smm_runtime->smm_size}; @@ -129,8 +134,10 @@ asmlinkage void smm_handler_start(void *arg) /* Make sure to set the global runtime. It's OK to race as the value * will be the same across CPUs as well as multiple SMIs. */ - if (smm_runtime == NULL) + if (smm_runtime == NULL) { smm_runtime = runtime; + gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; + } if (cpu >= CONFIG_MAX_CPUS) { console_init(); diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index fc1e1b3062..876fde6733 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -209,6 +209,12 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size, smm_stub_size = rmodule_memory_size(&smm_stub); stub_entry_offset = rmodule_entry_offset(&smm_stub); + if (smm_stub_size > params->per_cpu_save_state_size) { + printk(BIOS_ERR, "SMM Module: SMM stub size larger than save state size\n"); + printk(BIOS_ERR, "SMM Module: Staggered entry points will overlap stub\n"); + return -1; + } + /* Assume the stub is always small enough to live within upper half of * SMRAM region after the save state space has been allocated. */ smm_stub_loc = &base[SMM_ENTRY_OFFSET]; diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c new file mode 100644 index 0000000000..23495da520 --- /dev/null +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define FXSAVE_SIZE 512 +#define SMM_CODE_SEGMENT_SIZE 0x10000 +/* FXSAVE area during relocation. While it may not be strictly needed the + SMM stub code relies on the FXSAVE area being non-zero to enable SSE + instructions within SMM mode. */ +static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] +__attribute__((aligned(16))); + +/* + * Components that make up the SMRAM: + * 1. Save state - the total save state memory used + * 2. Stack - stacks for the CPUs in the SMM handler + * 3. Stub - SMM stub code for calling into handler + * 4. Handler - C-based SMM handler. + * + * The components are assumed to consist of one consecutive region. + */ + +/* These parameters are used by the SMM stub code. A pointer to the params + * is also passed to the C-base handler. */ +struct smm_stub_params { + u32 stack_size; + u32 stack_top; + u32 c_handler; + u32 c_handler_arg; + u32 fxsave_area; + u32 fxsave_area_size; + struct smm_runtime runtime; +} __packed; + +/* + * The stub is the entry point that sets up protected mode and stacks for each + * CPU. It then calls into the SMM handler module. It is encoded as an rmodule. + */ +extern unsigned char _binary_smmstub_start[]; + +/* Per CPU minimum stack size. */ +#define SMM_MINIMUM_STACK_SIZE 32 + +struct cpu_smm_info { + uint8_t active; + uintptr_t smbase; + uintptr_t entry; + uintptr_t ss_start; + uintptr_t code_start; + uintptr_t code_end; +}; +struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; + +/* + * This method creates a map of all the CPU entry points, save state locations + * and the beginning and end of code segments for each CPU. This map is used + * during relocation to properly align as many CPUs that can fit into the SMRAM + * region. For more information on how SMRAM works, refer to the latest Intel + * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the + * following regions: + * +-----------------+ Top of SMRAM + * | | <- MSEG, FXSAVE + * +-----------------+ + * | common | + * | smi handler | 64K + * | | + * +-----------------+ + * | CPU 0 code seg | + * +-----------------+ + * | CPU 1 code seg | + * +-----------------+ + * | CPU x code seg | + * +-----------------+ + * | | + * | | + * +-----------------+ + * | stacks | + * +-----------------+ <- START of SMRAM + * + * The code below checks when a code segment is full and begins placing the remainder + * CPUs in the lower segments. The entry point for each CPU is smbase + 0x8000 + * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state + * area grows downward into the CPUs entry point. Therefore staggering too many + * CPUs in one 32K block will corrupt CPU0's entry code as the save states move + * downward. + * input : smbase of first CPU (all other CPUs + * will go below this address) + * input : num_cpus in the system. The map will + * be created from 0 to num_cpus. + */ +static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, + const struct smm_loader_params *params) +{ + unsigned int i; + struct rmodule smm_stub; + unsigned int ss_size = params->per_cpu_save_state_size, stub_size; + unsigned int smm_entry_offset = params->smm_main_entry_offset; + unsigned int seg_count = 0, segments = 0, available; + unsigned int cpus_in_segment = 0; + unsigned int base = smbase; + + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); + return 0; + } + + stub_size = rmodule_memory_size(&smm_stub); + /* How many CPUs can fit into one 64K segment? */ + available = 0xFFFF - smm_entry_offset - ss_size - stub_size; + if (available > 0) { + cpus_in_segment = available / ss_size; + /* minimum segments needed will always be 1 */ + segments = num_cpus / cpus_in_segment + 1; + printk(BIOS_DEBUG, + "%s: cpus allowed in one segment %d\n", __func__, cpus_in_segment); + printk(BIOS_DEBUG, + "%s: min # of segments needed %d\n", __func__, segments); + } else { + printk(BIOS_ERR, "%s: not enough space in SMM to setup all CPUs\n", __func__); + printk(BIOS_ERR, " save state & stub size need to be reduced\n"); + printk(BIOS_ERR, " or increase SMRAM size\n"); + return 0; + } + + if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) { + printk(BIOS_ERR, + "%s: increase MAX_CPUS in Kconfig\n", __func__); + return 0; + } + + if (stub_size > ss_size) { + printk(BIOS_ERR, "%s: Save state larger than SMM stub size\n", __func__); + printk(BIOS_ERR, " Decrease stub size or increase the size allocated for the save state\n"); + return 0; + } + + for (i = 0; i < num_cpus; i++) { + cpus[i].smbase = base; + cpus[i].entry = base + smm_entry_offset; + cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); + cpus[i].code_start = cpus[i].entry; + cpus[i].code_end = cpus[i].entry + stub_size; + cpus[i].active = 1; + base -= ss_size; + seg_count++; + if (seg_count >= cpus_in_segment) { + base -= smm_entry_offset; + seg_count = 0; + } + } + + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + seg_count = 0; + for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); + printk(BIOS_DEBUG, + " smbase %zx entry %zx\n", + cpus[i].smbase, cpus[i].entry); + printk(BIOS_DEBUG, + " ss_start %zx code_end %zx\n", + cpus[i].ss_start, cpus[i].code_end); + seg_count++; + if (seg_count >= cpus_in_segment) { + printk(BIOS_DEBUG, + "-------------NEW CODE SEGMENT --------------\n"); + seg_count = 0; + } + } + } + return 1; +} + +/* + * This method expects the smm relocation map to be complete. + * This method does not read any HW registers, it simply uses a + * map that was created during SMM setup. + * input: cpu_num - cpu number which is used as an index into the + * map to return the smbase + */ +u32 smm_get_cpu_smbase(unsigned int cpu_num) +{ + if (cpu_num < CONFIG_MAX_CPUS) { + if (cpus[cpu_num].active) + return cpus[cpu_num].smbase; + } + return 0; +} + +/* + * This method assumes that at least 1 CPU has been set up from + * which it will place other CPUs below its smbase ensuring that + * save state does not clobber the first CPUs init code segment. The init + * code which is the smm stub code is the same for all CPUs. They enter + * smm, setup stacks (based on their apic id), enter protected mode + * and then jump to the common smi handler. The stack is allocated + * at the beginning of smram (aka tseg base, not smbase). The stack + * pointer for each CPU is calculated by using its apic id + * (code is in smm_stub.s) + * Each entry point will now have the same stub code which, sets up the CPU + * stack, enters protected mode and then jumps to the smi handler. It is + * important to enter protected mode before the jump because the "jump to + * address" might be larger than the 20bit address supported by real mode. + * SMI entry right now is in real mode. + * input: smbase - this is the smbase of the first cpu not the smbase + * where tseg starts (aka smram_start). All CPUs code segment + * and stack will be below this point except for the common + * SMI handler which is one segment above + * input: num_cpus - number of cpus that need relocation including + * the first CPU (though its code is already loaded) + * input: top of stack (stacks work downward by default in Intel HW) + * output: return -1, if runtime smi code could not be installed. In + * this case SMM will not work and any SMI's generated will + * cause a CPU shutdown or general protection fault because + * the appropriate smi handling code was not installed + */ + +static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, + uintptr_t stack_top, const struct smm_loader_params *params) +{ + unsigned int i; + unsigned int size; + if (smm_create_map(smbase, num_cpus, params)) { + /* + * Ensure there was enough space and the last CPUs smbase + * did not encroach upon the stack. Stack top is smram start + * + size of stack. + */ + if (cpus[num_cpus].active) { + if (cpus[num_cpus - 1].smbase + + params->smm_main_entry_offset < stack_top) { + printk(BIOS_ERR, "%s: stack encroachment\n", __func__); + printk(BIOS_ERR, "%s: smbase %zx, stack_top %lx\n", + __func__, cpus[num_cpus].smbase, stack_top); + return 0; + } + } + } else { + printk(BIOS_ERR, "%s: unable to place smm entry code\n", __func__); + return 0; + } + + printk(BIOS_INFO, "%s: smbase %zx, stack_top %lx\n", + __func__, cpus[num_cpus-1].smbase, stack_top); + + /* start at 1, the first CPU stub code is already there */ + size = cpus[0].code_end - cpus[0].code_start; + for (i = 1; i < num_cpus; i++) { + memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); + printk(BIOS_DEBUG, + "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", + cpus[i].code_start, i); + printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", + __func__, cpus[0].code_start, cpus[i].code_start, size); + } + return 1; +} + +/* + * Place stacks in base -> base + size region, but ensure the stacks don't + * overlap the staggered entry points. + */ +static void *smm_stub_place_stacks(char *base, size_t size, + struct smm_loader_params *params) +{ + size_t total_stack_size; + char *stacks_top; + + /* If stack space is requested assume the space lives in the lower + * half of SMRAM. */ + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + printk(BIOS_DEBUG, "%s: cpus: %zx : stack space: needed -> %zx\n", + __func__, params->num_concurrent_stacks, + total_stack_size); + printk(BIOS_DEBUG, " available -> %zx : per_cpu_stack_size : %zx\n", + size, params->per_cpu_stack_size); + + /* There has to be at least one stack user. */ + if (params->num_concurrent_stacks < 1) + return NULL; + + /* Total stack size cannot fit. */ + if (total_stack_size > size) + return NULL; + + /* Stacks extend down to SMBASE */ + stacks_top = &base[total_stack_size]; + printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); + + return stacks_top; +} + +/* + * Place the staggered entry points for each CPU. The entry points are + * staggered by the per CPU SMM save state size extending down from + * SMM_ENTRY_OFFSET. + */ +static int smm_stub_place_staggered_entry_points(char *base, + const struct smm_loader_params *params, const struct rmodule *smm_stub) +{ + size_t stub_entry_offset; + int rc = 1; + stub_entry_offset = rmodule_entry_offset(smm_stub); + /* Each CPU now has its own stub code, which enters protected mode, + * sets up the stack, and then jumps to common SMI handler + */ + if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { + rc = smm_place_entry_code((uintptr_t)base, + params->num_concurrent_save_states, + (uintptr_t)params->stack_top, params); + } + return rc; +} + +/* + * The stub setup code assumes it is completely contained within the + * default SMRAM size (0x10000) for the default SMI handler (entry at + * 0x30000), but no assumption should be made for the permanent SMI handler. + * The placement of CPU entry points for permanent handler are determined + * by the number of CPUs in the system and the amount of SMRAM. + * There are potentially 3 regions to place + * within the default SMRAM size: + * 1. Save state areas + * 2. Stub code + * 3. Stack areas + * + * The save state and smm stack are treated as contiguous for the number of + * concurrent areas requested. The save state always lives at the top of the + * the CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain + * number of CPUs with staggered entry points until the save state area comes + * down far enough to overwrite/corrupt the entry code (stub code). Therefore, + * an SMM map is created to avoid this corruption, see smm_create_map() above. + * This module setup code works for the default (0x30000) SMM handler setup and the + * permanent SMM handler. + */ +static int smm_module_setup_stub(void *smbase, size_t smm_size, + struct smm_loader_params *params, + void *fxsave_area) +{ + size_t total_save_state_size; + size_t smm_stub_size; + size_t stub_entry_offset; + char *smm_stub_loc; + void *stacks_top; + size_t size; + char *base; + size_t i; + struct smm_stub_params *stub_params; + struct rmodule smm_stub; + unsigned int total_size_all; + base = smbase; + size = smm_size; + + /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { + printk(BIOS_ERR, "%s: not enough stacks\n", __func__); + return -1; + } + + /* Fail if can't parse the smm stub rmodule. */ + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to parse smm stub\n", __func__); + return -1; + } + + /* Adjust remaining size to account for save state. */ + total_save_state_size = params->per_cpu_save_state_size * + params->num_concurrent_save_states; + if (total_save_state_size > size) { + printk(BIOS_ERR, + "%s: more state save space needed:need -> %zx:available->%zx\n", + __func__, total_save_state_size, size); + return -1; + } + + size -= total_save_state_size; + + /* The save state size encroached over the first SMM entry point. */ + if (size <= params->smm_main_entry_offset) { + printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", + __func__, size, params->smm_main_entry_offset); + return -1; + } + + /* Need a minimum stack size and alignment. */ + if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || + (params->per_cpu_stack_size & 3) != 0) { + printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); + return -1; + } + + smm_stub_loc = NULL; + smm_stub_size = rmodule_memory_size(&smm_stub); + stub_entry_offset = rmodule_entry_offset(&smm_stub); + + /* Put the stub at the main entry point */ + smm_stub_loc = &base[params->smm_main_entry_offset]; + + /* Stub is too big to fit. */ + if (smm_stub_size > (size - params->smm_main_entry_offset)) { + printk(BIOS_ERR, "%s: stub is too big to fit\n", __func__); + return -1; + } + + /* The stacks, if requested, live in the lower half of SMRAM space + * for default handler, but for relocated handler it lives at the beginning + * of SMRAM which is TSEG base + */ + const size_t total_stack_size = params->num_concurrent_stacks * + params->per_cpu_stack_size; + stacks_top = smm_stub_place_stacks((char *)params->smram_start, total_stack_size, + params); + if (stacks_top == NULL) { + printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__); + printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__, + base, total_stack_size); + return -1; + } + params->stack_top = stacks_top; + /* Load the stub. */ + if (rmodule_load(smm_stub_loc, &smm_stub)) { + printk(BIOS_ERR, "%s: load module failed\n", __func__); + return -1; + } + + if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { + printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); + return -1; + } + + /* Setup the parameters for the stub code. */ + stub_params = rmodule_parameters(&smm_stub); + stub_params->stack_top = (uintptr_t)stacks_top; + stub_params->stack_size = params->per_cpu_stack_size; + stub_params->c_handler = (uintptr_t)params->handler; + stub_params->c_handler_arg = (uintptr_t)params->handler_arg; + stub_params->fxsave_area = (uintptr_t)fxsave_area; + stub_params->fxsave_area_size = FXSAVE_SIZE; + stub_params->runtime.smbase = (uintptr_t)smbase; + stub_params->runtime.smm_size = smm_size; + stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + stub_params->runtime.num_cpus = params->num_concurrent_stacks; + stub_params->runtime.gnvs_ptr = (uintptr_t)acpi_get_gnvs(); + + printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", + __func__, stub_params->stack_top - total_stack_size); + printk(BIOS_DEBUG, + "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); + printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", + __func__, stub_params->stack_size); + printk(BIOS_DEBUG, "%s: runtime.smbase = 0x%x\n", + __func__, stub_params->runtime.smbase); + printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, + stub_params->runtime.start32_offset); + printk(BIOS_DEBUG, "%s: runtime.smm_size = 0x%zx\n", + __func__, smm_size); + printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", + __func__, stub_params->runtime.save_state_size); + printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", + __func__, (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus)); + total_size_all = stub_params->stack_size + + (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_size_all = 0x%x\n", __func__, + total_size_all); + + /* Initialize the APIC id to CPU number table to be 1:1 */ + for (i = 0; i < params->num_concurrent_stacks; i++) + stub_params->runtime.apic_id_to_cpu[i] = i; + + /* Allow the initiator to manipulate SMM stub parameters. */ + params->runtime = &stub_params->runtime; + + printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", + smm_stub_loc, params->handler, params->handler_arg); + return 0; +} + +/* + * smm_setup_relocation_handler assumes the callback is already loaded in + * memory. i.e. Another SMM module isn't chained to the stub. The other + * assumption is that the stub will be entered from the default SMRAM + * location: 0x30000 -> 0x40000. + */ +int smm_setup_relocation_handler(struct smm_loader_params *params) +{ + void *smram = (void *)(SMM_DEFAULT_BASE); + printk(BIOS_SPEW, "%s: enter\n", __func__); + /* There can't be more than 1 concurrent save state for the relocation + * handler because all CPUs default to 0x30000 as SMBASE. */ + if (params->num_concurrent_save_states > 1) + return -1; + + /* A handler has to be defined to call for relocation. */ + if (params->handler == NULL) + return -1; + + /* Since the relocation handler always uses stack, adjust the number + * of concurrent stack users to be CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks == 0) + params->num_concurrent_stacks = CONFIG_MAX_CPUS; + + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + params->smram_start = SMM_DEFAULT_BASE; + params->smram_end = SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE; + return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, + params, fxsave_area_relocation); + printk(BIOS_SPEW, "%s: exit\n", __func__); +} + +/* + *The SMM module is placed within the provided region in the following + * manner: + * +-----------------+ <- smram + size + * | BIOS resource | + * | list (STM) | + * +-----------------+ + * | fxsave area | + * +-----------------+ + * | smi handler | + * | ... | + * +-----------------+ <- cpu0 + * | stub code | <- cpu1 + * | stub code | <- cpu2 + * | stub code | <- cpu3, etc + * | | + * | | + * | | + * | stacks | + * +-----------------+ <- smram start + + * It should be noted that this algorithm will not work for + * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm + * expects a region large enough to encompass the handler and stacks + * as well as the SMM_DEFAULT_SIZE. + */ +int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) +{ + struct rmodule smm_mod; + size_t total_stack_size; + size_t handler_size; + size_t module_alignment; + size_t alignment_size; + size_t fxsave_size; + void *fxsave_area; + size_t total_size = 0; + char *base; + + if (size <= SMM_DEFAULT_SIZE) + return -1; + + /* Load main SMI handler at the top of SMRAM + * everything else will go below + */ + base = smram; + base += size; + params->smram_start = (uintptr_t)smram; + params->smram_end = params->smram_start + size; + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + + /* Fail if can't parse the smm rmodule. */ + if (rmodule_parse(&_binary_smm_start, &smm_mod)) + return -1; + + /* Clear SMM region */ + if (CONFIG(DEBUG_SMI)) + memset(smram, 0xcd, size); + + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + total_size += total_stack_size; + /* Stacks are the base of SMRAM */ + params->stack_top = smram + total_stack_size; + + /* MSEG starts at the top of SMRAM and works down */ + if (CONFIG(STM)) { + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + } + + /* FXSAVE goes below MSEG */ + if (CONFIG(SSE)) { + fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; + fxsave_area = base - fxsave_size; + base -= fxsave_size; + total_size += fxsave_size; + } else { + fxsave_size = 0; + fxsave_area = NULL; + } + + handler_size = rmodule_memory_size(&smm_mod); + base -= handler_size; + total_size += handler_size; + module_alignment = rmodule_load_alignment(&smm_mod); + alignment_size = module_alignment - + ((uintptr_t)base % module_alignment); + if (alignment_size != module_alignment) { + handler_size += alignment_size; + base += alignment_size; + } + + printk(BIOS_DEBUG, + "%s: total_smm_space_needed %zx, available -> %zx\n", + __func__, total_size, size); + + /* Does the required amount of memory exceed the SMRAM region size? */ + if (total_size > size) { + printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); + return -1; + } + if (handler_size > SMM_CODE_SEGMENT_SIZE) { + printk(BIOS_ERR, "%s: increase SMM_CODE_SEGMENT_SIZE: handler_size = %zx\n", + __func__, handler_size); + return -1; + } + + if (rmodule_load(base, &smm_mod)) + return -1; + + params->handler = rmodule_entry(&smm_mod); + params->handler_arg = rmodule_parameters(&smm_mod); + + printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", + __func__, smram); + printk(BIOS_DEBUG, "%s: smram_end: %p\n", + __func__, smram + size); + printk(BIOS_DEBUG, "%s: stack_top: %p\n", + __func__, params->stack_top); + printk(BIOS_DEBUG, "%s: handler start %p\n", + __func__, params->handler); + printk(BIOS_DEBUG, "%s: handler_size %zx\n", + __func__, handler_size); + printk(BIOS_DEBUG, "%s: handler_arg %p\n", + __func__, params->handler_arg); + printk(BIOS_DEBUG, "%s: fxsave_area %p\n", + __func__, fxsave_area); + printk(BIOS_DEBUG, "%s: fxsave_size %zx\n", + __func__, fxsave_size); + printk(BIOS_DEBUG, "%s: CONFIG_MSEG_SIZE 0x%x\n", + __func__, CONFIG_MSEG_SIZE); + printk(BIOS_DEBUG, "%s: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x%x\n", + __func__, CONFIG_BIOS_RESOURCE_LIST_SIZE); + + /* CPU 0 smbase goes first, all other CPUs + * will be staggered below + */ + base -= SMM_CODE_SEGMENT_SIZE; + printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", + __func__, base); + params->smm_entry = (uintptr_t)base + params->smm_main_entry_offset; + return smm_module_setup_stub(base, size, params, fxsave_area); +} diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 425724d559..45f634d0c9 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -10,6 +10,7 @@ */ #include +#include .code32 .section ".module_parameters", "aw", @progbits @@ -90,7 +91,7 @@ smm_relocate_gdt: /* gdt selector 0x18, flat code segment (64-bit) */ .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 + .byte 0x00, 0x9b, 0xaf, 0x00 /* gdt selector 0x20 tss segment */ .word 0xffff, 0x0000 @@ -143,13 +144,16 @@ smm_trampoline32: movl stack_size, %eax subl %eax, %ebx /* %ebx(stack_top) - size = %ebx(stack_bottom) */ movl %ebx, (%ebx) +#if ENV_X86_64 + movl $0, 4(%ebx) +#endif /* Create stack frame by pushing a NULL stack base pointer */ pushl $0x0 mov %esp, %ebp - /* Allocate locals (fxsave) */ - subl $0x4, %esp + /* Allocate locals (fxsave, efer_backup) */ + subl $0xc, %esp /* calculate fxsave location */ mov fxsave_area, %edi @@ -177,22 +181,65 @@ smm_trampoline32: /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#ifdef __x86_64__ + mov %ecx, %edi + /* Backup IA32_EFER. Preserves ebx. */ + movl $(IA32_EFER), %ecx + rdmsr + movl %eax, -0x8(%ebp) + movl %edx, -0xc(%ebp) + + /* entry64.inc preserves ebx, esi, edi */ +#include + mov %edi, %ecx + +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ +#ifdef __x86_64__ + push %rbx /* uintptr_t *canary */ + push $(smm_runtime) + push %rcx /* size_t cpu */ + push c_handler_arg /* void *arg */ + + mov %rsp, %rdi /* *arg */ + + movl c_handler, %eax + call *%rax + + /* + * The only reason to go back to protected mode is that RSM doesn't restore + * MSR registers and MSR IA32_EFER was modified by entering long mode. + * Drop to protected mode to safely operate on the IA32_EFER MSR. + */ + + /* Disable long mode. */ + #include + + /* Restore IA32_EFER as RSM doesn't restore MSRs. */ + movl $(IA32_EFER), %ecx + rdmsr + movl -0x8(%ebp), %eax + movl -0xc(%ebp), %edx + + wrmsr + +#else push $0x0 /* Padding */ push $0x0 /* Padding */ push $0x0 /* Padding */ push %ebx /* uintptr_t *canary */ push $(smm_runtime) - push %ecx /* int cpu */ + push %ecx /* size_t cpu */ push c_handler_arg /* void *arg */ push %esp /* smm_module_params *arg (allocated on stack). */ mov c_handler, %eax call *%eax - +#endif /* Retrieve fxsave location. */ mov -4(%ebp), %edi test %edi, %edi diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 340840f685..4cbfbfdfb1 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -46,9 +46,9 @@ #if defined(__x86_64__) .bss ia32efer_backup_eax: -.long +.long 0 ia32efer_backup_edx: -.long +.long 0 #endif /* initially SMM is some sort of real mode. Let gcc know @@ -165,10 +165,6 @@ untampered_lapic: addl $SMM_STACK_SIZE, %ebx movl %ebx, %esp - /* Get SMM revision */ - movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ - subl %ebp, %ebx /* subtract core X offset */ - #if defined(__x86_64__) /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx @@ -179,13 +175,7 @@ untampered_lapic: /* Enable long mode. Preserves ebx. */ #include - mov (%ebx), %rdi - -#else - movl (%ebx), %eax - pushl %eax #endif - /* Call C handler */ call smi_handler diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 893d41dc3b..9607c2c6eb 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include -#include #include #include diff --git a/src/device/Kconfig b/src/device/Kconfig index d0d72f9a77..bb4e913f35 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -46,6 +46,12 @@ config MAINBOARD_FORCE_NATIVE_VGA_INIT Selected by mainboards / chipsets whose graphics driver can't or shouldn't be disabled. +config VGA_ROM_RUN_DEFAULT + def_bool n + help + Selected by mainboards whose graphics initialization depends on VGA OpROM. + coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX. + config MAINBOARD_HAS_LIBGFXINIT def_bool n help @@ -54,8 +60,8 @@ config MAINBOARD_HAS_LIBGFXINIT choice prompt "Graphics initialization" - default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS - default VGA_ROM_RUN if VGA_BIOS + default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS + default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT default MAINBOARD_DO_NATIVE_VGA_INIT default MAINBOARD_USE_LIBGFXINIT default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT @@ -491,18 +497,6 @@ config MMCONF_SUPPORT bool default !NO_MMCONF_SUPPORT -config HYPERTRANSPORT_PLUGIN_SUPPORT - bool - default n - -config HT_CHAIN_UNITID_BASE - int - default 0 - -config HT_CHAIN_END_UNITID_BASE - int - default 0 - config PCIX_PLUGIN_SUPPORT bool default y @@ -519,6 +513,41 @@ config PCIEXP_PLUGIN_SUPPORT bool default y +config PCI_ALLOW_BUS_MASTER + bool "Allow coreboot to set optional PCI bus master bits" + default y + help + For security reasons, bus mastering should be enabled as late as + possible. In coreboot, it's usually not necessary and payloads + should only enable it for devices they use. Since not all payloads + enable bus mastering properly yet, this option gives some sort of + "backwards compatibility" and is enabled by default to keep the + traditional behaviour for now. This is currently necessary, for + instance, for libpayload based payloads as the drivers don't enable + bus mastering for PCI bridges. + +if PCI_ALLOW_BUS_MASTER + +config PCI_SET_BUS_MASTER_PCI_BRIDGES + bool "PCI bridges" + default y + help + Let coreboot configure bus mastering for PCI bridges. Enabling bus + mastering for a PCI bridge also allows it to forward requests from + downstream devices. Currently, payloads ignore this and only enable + bus mastering for the downstream device. Hence, this option is needed + for compatibility until payloads are fixed. + +config PCI_ALLOW_BUS_MASTER_ANY_DEVICE + bool "Any devices" + default y + select PCI_SET_BUS_MASTER_PCI_BRIDGES + help + Allow coreboot to enable PCI bus mastering for any device. The actual + selection of devices depends on the various PCI drivers in coreboot. + +endif # PCI_ALLOW_BUS_MASTER + endif # PCI if PCIEXP_PLUGIN_SUPPORT @@ -650,6 +679,9 @@ config SUBSYSTEM_VENDOR_ID This config option will override the devicetree settings for PCI Subsystem Vendor ID. + Note: This option is not meant for a board's Kconfig; use the + devicetree setting `subsystemid` instead. + config SUBSYSTEM_DEVICE_ID hex "Override PCI Subsystem Device ID" depends on PCI @@ -658,9 +690,13 @@ config SUBSYSTEM_DEVICE_ID This config option will override the devicetree settings for PCI Subsystem Device ID. + Note: This option is not meant for a board's Kconfig; use the + devicetree setting `subsystemid` instead. + config VGA_BIOS bool "Add a VGA BIOS image" depends on ARCH_X86 + select VGA_ROM_RUN_DEFAULT help Select this option if you have a VGA BIOS image that you would like to add to your ROM. diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2fae44ab24..808648d4b4 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -8,7 +8,7 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/hda_verb.c) endif bootblock-y += device_const.c @@ -35,7 +35,6 @@ postcar-y += pci_ops.c ramstage-y += pci_ops.c smm-y += pci_ops.c -ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c @@ -64,3 +63,5 @@ ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c ramstage-$(CONFIG_XHCI_UTILS) += xhci.c + +ramstage-y += gpio.c diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 1e0cf2f5cb..e1899f13c0 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -7,11 +7,7 @@ #include #include -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - -static int set_bits(void *port, u32 mask, u32 val) +int azalia_set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -23,9 +19,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -40,19 +34,30 @@ static int set_bits(void *port, u32 mask, u32 val) return 0; } +int azalia_enter_reset(u8 *base) +{ + /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); +} + +int azalia_exit_reset(u8 *base) +{ + /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST); +} + static int codec_detect(u8 *base) { u32 reg32; int count; - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (azalia_exit_reset(base) < 0) goto no_codec; - /* clear STATESTS bits (BAR + 0xE)[2:0] */ - reg32 = read32(base + 0x0E); + /* clear STATESTS bits (BAR + 0xe)[2:0] */ + reg32 = read32(base + HDA_STATESTS_REG); reg32 |= 7; - write32(base + 0x0E, reg32); + write32(base + HDA_STATESTS_REG, reg32); /* Wait for readback of register to * match what was just written to it @@ -61,22 +66,20 @@ static int codec_detect(u8 *base) do { /* Wait 1ms based on BKDG wait time */ mdelay(1); - reg32 = read32(base + 0x0E); + reg32 = read32(base + HDA_STATESTS_REG); } while ((reg32 != 0) && --count); /* Timeout occurred */ if (!count) goto no_codec; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (azalia_enter_reset(base) < 0) goto no_codec; - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (azalia_exit_reset(base) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -86,25 +89,48 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) +/* + * Find a specific entry within a verb table + * + * @param verb_table: verb table data + * @param verb_table_bytes: verb table size in bytes + * @param viddid: vendor/device to search for + * @param verb: pointer to entry within table + * + * Returns size of the entry within the verb table, + * Returns 0 if the entry is not found + * + * The HDA verb table is composed of dwords. A set of 4 dwords is + * grouped together to form a "jack" descriptor. + * Bits 31:28 - Codec Address + * Bits 27:20 - NID + * Bits 19:8 - Verb ID + * Bits 7:0 - Payload + * + * coreboot groups different codec verb tables into a single table + * and prefixes each with a specific header consisting of 3 + * dword entries: + * 1 - Codec Vendor/Device ID + * 2 - Subsystem ID + * 3 - Number of jacks (groups of 4 dwords) for this codec + */ +u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb) { - printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); - printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); - int idx = 0; - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { + while (idx < (verb_table_bytes / sizeof(u32))) { + /* Header contains the number of jacks, aka groups of 4 dwords */ + u32 verb_size = 4 * verb_table[idx + 2]; + if (verb_table[idx] != viddid) { idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx + 3]; + *verb = &verb_table[idx + 3]; return verb_size; } @@ -112,16 +138,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -134,29 +158,29 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 25; - write32(base + HDA_ICII_REG, - HDA_ICII_VALID | HDA_ICII_BUSY); + /* Send the verb to the codec */ + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); + while (timeout--) { udelay(1); } timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -174,20 +198,23 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; - - reg32 = read32(base + 0x64); + } /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); @@ -197,12 +224,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); @@ -224,19 +251,18 @@ void azalia_audio_init(struct device *dev) struct resource *res; u32 codec_mask; - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", - codec_mask); + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index cbe0c724fb..b014946144 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -51,23 +51,6 @@ static void cardbus_record_bridge_resource(struct device *dev, resource_t moving resource->size = min_size; } -static void cardbus_size_bridge_resource(struct device *dev, unsigned int index) -{ - struct resource *resource; - resource_t min_size; - - resource = find_resource(dev, index); - if (resource) { - min_size = resource->size; - /* - * Always allocate at least the minimum size to a - * cardbus bridge in case a new card is plugged in. - */ - if (resource->size < min_size) - resource->size = min_size; - } -} - void cardbus_read_resources(struct device *dev) { resource_t moving_base, moving_limit, moving; @@ -88,7 +71,6 @@ void cardbus_read_resources(struct device *dev) /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, PCI_CB_IO_BASE_0, IORESOURCE_IO); - cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); /* See which bridge I/O resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); @@ -118,8 +100,6 @@ void cardbus_read_resources(struct device *dev) type |= IORESOURCE_PREFETCH; cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_0, type); - if (type & IORESOURCE_PREFETCH) - cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); /* See which bridge memory resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); @@ -129,7 +109,6 @@ void cardbus_read_resources(struct device *dev) /* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); - cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); compact_resources(dev); } @@ -140,7 +119,6 @@ void cardbus_enable_resources(struct device *dev) ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link_list->bridge_ctrl & ( - PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); diff --git a/src/device/device_const.c b/src/device/device_const.c index 12d5386d22..5288a743b6 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -162,6 +162,9 @@ static int path_eq(const struct device_path *path1, case DEVICE_PATH_LPC: equal = (path1->lpc.addr == path2->lpc.addr); break; + case DEVICE_PATH_GPIO: + equal = (path1->gpio.id == path2->gpio.id); + break; default: printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; @@ -184,7 +187,7 @@ DEVTREE_CONST struct device *find_dev_path( DEVTREE_CONST struct device *child; if (!parent) { - assert(0); + BUG(); /* Return NULL in case asserts are considered non-fatal. */ return NULL; } @@ -196,6 +199,33 @@ DEVTREE_CONST struct device *find_dev_path( return child; } +/** + * Find the device structure given an array of nested device paths, + * + * @param parent The parent bus to start the search on. + * @param nested_path An array of relative paths from the parent bus to the target device. + * @param nested_path_length Number of path elements in nested_path array. + * @return Pointer to a device structure for the device at nested path + * or 0/NULL if no device is found. + */ +DEVTREE_CONST struct device *find_dev_nested_path( + const struct bus *parent, const struct device_path nested_path[], + size_t nested_path_length) +{ + DEVTREE_CONST struct device *child; + + if (!parent || !nested_path || !nested_path_length) + return NULL; + + child = find_dev_path(parent, nested_path); + + /* Terminate recursion at end of nested path or child not found */ + if (nested_path_length == 1 || !child) + return child; + + return find_dev_nested_path(child->link_list, nested_path + 1, nested_path_length - 1); +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -255,7 +285,7 @@ DEVTREE_CONST struct device *pcidev_path_behind_pci2pci_bridge( pci_devfn_t devfn) { if (!bridge || (bridge->path.type != DEVICE_PATH_PCI)) { - assert(0); + BUG(); /* Return NULL in case asserts are non-fatal. */ return NULL; } diff --git a/src/device/device_util.c b/src/device/device_util.c index 22c3db1c44..0bce26a99e 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -130,6 +130,9 @@ u32 dev_path_encode(const struct device *dev) case DEVICE_PATH_USB: ret |= dev->path.usb.port_type << 8 | dev->path.usb.port_id; break; + case DEVICE_PATH_GPIO: + ret |= dev->path.gpio.id; + break; case DEVICE_PATH_NONE: case DEVICE_PATH_MMIO: /* don't care */ default: @@ -223,6 +226,9 @@ const char *dev_path(const struct device *dev) snprintf(buffer, sizeof(buffer), "LPC: %08lx", dev->path.lpc.addr); break; + case DEVICE_PATH_GPIO: + snprintf(buffer, sizeof(buffer), "GPIO: %d", dev->path.gpio.id); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); @@ -519,7 +525,7 @@ void report_resource_stored(struct device *dev, struct resource *resource, end = resource_end(resource); buf[0] = '\0'; - if (resource->flags & IORESOURCE_PCI_BRIDGE) { + if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), "bus %02x ", dev->link_list->secondary); } diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index f397a534f2..f7118dbbc2 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,3 @@ romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c + +ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index c6d6442da8..0eba0e384c 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -653,7 +653,7 @@ static void print_us(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 3c433a931e..ab6d828b1d 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -493,7 +493,6 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, return ret; } - /** * Fill cbmem with information for SMBIOS type 17. * @@ -593,7 +592,7 @@ static void print_ns(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 429a9d271a..e670b20f72 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -9,6 +9,69 @@ #include #include +enum ddr4_speed_grade { + DDR4_1600, + DDR4_1866, + DDR4_2133, + DDR4_2400, + DDR4_2666, + DDR4_2933, + DDR4_3200 +}; + +struct ddr4_speed_attr { + uint32_t min_clock_mhz; // inclusive + uint32_t max_clock_mhz; // inclusive + uint32_t reported_mts; +}; + +/** + * DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170 + * + * min_clock_mhz = 1000/max_tCk_avg(ns) + 1 + * Adding 1 to make minimum inclusive + * max_clock_mhz = 1000/min_tCk_avg(ns) + * reported_mts = Standard reported DDR4 speed in MT/s + * May be 1 less than the actual max MT/s + */ +static const struct ddr4_speed_attr ddr4_speeds[] = { + [DDR4_1600] = { + .min_clock_mhz = 668, + .max_clock_mhz = 800, + .reported_mts = 1600 + }, + [DDR4_1866] = { + .min_clock_mhz = 801, + .max_clock_mhz = 934, + .reported_mts = 1866 + }, + [DDR4_2133] = { + .min_clock_mhz = 935, + .max_clock_mhz = 1067, + .reported_mts = 2133 + }, + [DDR4_2400] = { + .min_clock_mhz = 1068, + .max_clock_mhz = 1200, + .reported_mts = 2400 + }, + [DDR4_2666] = { + .min_clock_mhz = 1201, + .max_clock_mhz = 1333, + .reported_mts = 2666 + }, + [DDR4_2933] = { + .min_clock_mhz = 1334, + .max_clock_mhz = 1466, + .reported_mts = 2933 + }, + [DDR4_3200] = { + .min_clock_mhz = 1467, + .max_clock_mhz = 1600, + .reported_mts = 3200 + } +}; + typedef enum { BLOCK_0, /* Base Configuration and DRAM Parameters */ BLOCK_1, @@ -68,6 +131,21 @@ static bool block_exists(spd_block_type type, u8 dimm_type) } } +/** + * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +{ + for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) { + const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed]; + if (speed_mhz >= speed_attr->min_clock_mhz && + speed_mhz <= speed_attr->max_clock_mhz) { + return speed_attr->reported_mts; + } + } + printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range", speed_mhz); + return 0; +} /** * \brief Decode the raw SPD data diff --git a/src/device/gpio.c b/src/device/gpio.c new file mode 100644 index 0000000000..5e71497024 --- /dev/null +++ b/src/device/gpio.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const struct gpio_operations *dev_get_gpio_ops(struct device *dev) +{ + if (!dev) { + printk(BIOS_ERR, "Could not get gpio operations, device is NULL."); + return NULL; + } else if (!dev->ops) { + printk(BIOS_ERR, "Could not get gpio operations, dev->ops is NULL."); + return NULL; + } else if (!dev->ops->ops_gpio) { + printk(BIOS_ERR, "Could not get gpio operations, ops_gpio is NULL."); + return NULL; + } + + return dev->ops->ops_gpio; +} diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c deleted file mode 100644 index a9f922fdf3..0000000000 --- a/src/device/hypertransport.c +++ /dev/null @@ -1,500 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -struct ht_link { - struct device *dev; - unsigned int pos; - unsigned char ctrl_off, config_off, freq_off, freq_cap_off; -}; - -static struct device *ht_scan_get_devs(struct device **old_devices) -{ - struct device *first, *last; - - first = *old_devices; - last = first; - - /* - * Extract the chain of devices to (first through last) for the next - * hypertransport device. - */ - while (last && last->sibling && - (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) - { - last = last->sibling; - } - - if (first) { - struct device *child; - - /* Unlink the chain from the list of old devices. */ - *old_devices = last->sibling; - last->sibling = 0; - - /* Now add the device to the list of devices on the bus. */ - /* Find the last child of our parent. */ - for (child = first->bus->children; child && child->sibling;) - child = child->sibling; - - /* Place the chain on the list of children of their parent. */ - if (child) - child->sibling = first; - else - first->bus->children = first; - } - return first; -} - -static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos) -{ - struct ht_link cur[1]; - int linkb_to_host; - - /* Set the hypertransport link width and frequency. */ - - /* - * See which side of the device our previous write to set the unitid - * came from. - */ - cur->dev = dev; - cur->pos = pos; - linkb_to_host = - (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1; - - if (!linkb_to_host) { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } else { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } - - /* - * Remember the current link as the previous link, but look at the - * other offsets. - */ - prev->dev = cur->dev; - prev->pos = cur->pos; - if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } else { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } - - return 0; -} - -static unsigned int ht_lookup_slave_capability(struct device *dev) -{ - unsigned int pos; - - pos = 0; - do { - pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos); - if (pos) { - u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - printk(BIOS_SPEW, "flags: 0x%04x\n", flags); - if ((flags >> 13) == 0) { - /* Entry is a slave secondary, success... */ - break; - } - } - } while (pos); - - return pos; -} - -static void ht_collapse_early_enumeration(struct bus *bus, - unsigned int offset_unitid) -{ - unsigned int devfn; - struct ht_link prev; - u16 ctrl; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); - - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) - return; - - /* Has the link failed? */ - if (ctrl & (1 << 4)) { - /* - * Either the link has failed, or we have a CRC error. - * Sometimes this can happen due to link retrain, so - * lets knock it down and see if its transient. - */ - ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */ - pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, - ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "Hypertransport link\n"); - return; - } - } - } while ((ctrl & (1 << 5)) == 0); - - /* Actually, only for one HT device HT chain, and unitid is 0. */ -#if !CONFIG_HT_CHAIN_UNITID_BASE - if (offset_unitid) - return; -#endif - - /* Check if is already collapsed. */ - if ((!offset_unitid) || (offset_unitid - && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) - && (CONFIG_HT_CHAIN_END_UNITID_BASE - < CONFIG_HT_CHAIN_UNITID_BASE))))) { - - struct device dummy; - u32 id; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = PCI_DEVFN(0, 0); - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (!((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000))) { - return; - } - } - - /* Spin through the devices and collapse any early HT enumeration. */ - for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) { - struct device dummy; - u32 id; - unsigned int pos, flags; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = devfn; - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if ((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000)) { - continue; - } - - dummy.vendor = id & 0xffff; - dummy.device = (id >> 16) & 0xffff; - dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE); - - pos = ht_lookup_slave_capability(&dummy); - if (!pos) - continue; - - /* Clear the unitid. */ - flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); - printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); - } -} - -static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, - unsigned int *ht_unitid_base, - unsigned int offset_unitid) -{ - /* - * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this - * function, because of end_of_chain check. Also, we need it to - * optimize link. - */ - unsigned int next_unitid, last_unitid, min_unitid, max_unitid; - struct device *old_devices, *dev, *func, *last_func = NULL; - struct ht_link prev; - int ht_dev_num = 0; - - printk(BIOS_SPEW, "%s for bus %02x\n", __func__, bus->secondary); - - min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - /* - * Let's record the device of last HT device, so we can set the unitid - * to CONFIG_HT_CHAIN_END_UNITID_BASE. - */ - unsigned int real_last_unitid = 0, end_used = 0; - u8 real_last_pos = 0; - struct device *real_last_dev = NULL; -#endif - - /* Restore the hypertransport chain to it's uninitialized state. */ - ht_collapse_early_enumeration(bus, offset_unitid); - - /* See which static device nodes I have. */ - old_devices = bus->children; - bus->children = 0; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* If present, assign unitid to a hypertransport chain. */ - max_unitid = next_unitid = min_unitid; - do { - u8 pos; - u16 flags, ctrl; - unsigned int count, static_count; - - last_unitid = next_unitid; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - - /* End of chain? */ - if (ctrl & (1 << 6)) - goto end_of_chain; - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have a CRC - * error. Sometimes this can happen due to link - * retrain, so lets knock it down and see if - * it's transient. - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC - pci_write_config16(prev.dev, - prev.pos + prev.ctrl_off, ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "hypertransport link\n"); - goto end_of_chain; - } - } - } while ((ctrl & (1 << 5)) == 0); - - - /* Get and setup the device_structure. */ - dev = ht_scan_get_devs(&old_devices); - - /* See if a device is present and setup the device structure. */ - dev = pci_probe_dev(dev, bus, 0); - if (!dev || !dev->enabled) - break; - - /* Find the hypertransport link capability. */ - pos = ht_lookup_slave_capability(dev); - if (pos == 0) { - printk(BIOS_ERR, "%s Hypertransport link capability " - "not found", dev_path(dev)); - break; - } - - /* Update the unitid of the current device. */ - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - - /* - * If the device has a unitid set and is at devfn 0 we are - * done. This can happen with shadow hypertransport devices, - * or if we have reached the bottom of a HT device chain. - */ - if (flags & 0x1f) - break; - - flags &= ~0x1f; /* Mask out base Unit ID. */ - - count = (flags >> 5) & 0x1f; /* Het unit count. */ - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */ - if (next_unitid > (max_devfn >> 3)) { - if (!end_used) { - next_unitid = - CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto end_of_chain; - } - } - } -#endif - - flags |= next_unitid & 0x1f; - pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); - - /* Update the unitid in the device structure. */ - static_count = 1; - for (func = dev; func; func = func->sibling) { - func->path.pci.devfn += (next_unitid << 3); - static_count = (func->path.pci.devfn >> 3) - - (dev->path.pci.devfn >> 3) + 1; - last_func = func; - } - - /* Compute the number of unitids consumed. */ - printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", - dev_path(dev), count, static_count); - if (count < static_count) - count = static_count; - - /* Update the unitid of the next device. */ - ht_unitid_base[ht_dev_num] = next_unitid; - ht_dev_num++; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - real_last_pos = pos; - real_last_unitid = next_unitid; - real_last_dev = dev; - } -#endif - next_unitid += count; - if (next_unitid > max_unitid) - max_unitid = next_unitid; - - /* Setup the hypertransport link. */ - bus->reset_needed |= ht_setup_link(&prev, dev, pos); - - printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", - dev_path(dev), dev->vendor, dev->device, - (dev->enabled? "enabled" : "disabled"), next_unitid); - - } while (last_unitid != next_unitid); - -end_of_chain: - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid && (ht_dev_num > 1) - && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) - && !end_used) { - u16 flags; - flags = pci_read_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_write_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS, flags); - - for (func = real_last_dev; func; func = func->sibling) { - func->path.pci.devfn -= ((real_last_unitid - - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3); - last_func = func; - } - - /* Update last one. */ - ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; - - printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", - real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); - } -#endif - next_unitid = max_unitid; - - if (next_unitid > 0x20) - next_unitid = 0x20; - - if ((bus->secondary == 0) && (next_unitid > 0x18)) - next_unitid = 0x18; /* Avoid K8 on bus 0. */ - - /* - * Die if any leftover static devices are are found. There's probably - * a problem in devicetree.cb. - */ - if (old_devices) { - struct device *left; - for (left = old_devices; left; left = left->sibling) - printk(BIOS_DEBUG, "%s\n", dev_path(left)); - - printk(BIOS_ERR, "HT: Leftover static devices. " - "Check your devicetree.cb\n"); - - /* - * Put back the leftover static device, and let pci_scan_bus() - * disable it. - */ - if (last_func && !last_func->sibling) - last_func->sibling = old_devices; - } - - return next_unitid; -} - -/** - * Scan a PCI bridge and the buses behind the bridge. - * - * Determine the existence of buses behind the bridge. Set up the bridge - * according to the result of the scan. - * - * This function is the default scan_bus() method for PCI bridge devices. - * - * @param bus TODO - * @param min_devfn TODO - * @param max_devfn TODO - */ -static void hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn) -{ - unsigned int ht_unitid_base[4]; - unsigned int offset_unitid = 1; - - unsigned int next_unitid = do_hypertransport_scan_chain(bus, min_devfn, max_devfn, - ht_unitid_base, offset_unitid); - - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); -} - -static void ht_scan_bridge(struct device *dev) -{ - do_pci_scan_bridge(dev, hypertransport_scan_chain_x); -} - -/** Default device operations for hypertransport bridges */ -static struct pci_operations ht_bus_ops_pci = { - .set_subsystem = 0, -}; - -struct device_operations default_ht_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = ht_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &ht_bus_ops_pci, -}; diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5215934ed5..6b80ac5f62 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -12,6 +12,7 @@ #include #include #include +#include /* we use x86emu's register file representation */ #include @@ -130,7 +131,7 @@ static void setup_interrupt_handlers(void) { /* If the mainboard_interrupt_handler isn't called first. */ - if(!intXX_handler[i]) + if (!intXX_handler[i]) { /* Now set the default functions that are actually * needed to initialize the option roms. This is @@ -208,11 +209,6 @@ static void setup_realmode_idt(void) static vbe_mode_info_t mode_info; static int mode_info_valid; -static int vbe_mode_info_valid(void) -{ - return mode_info_valid; -} - const vbe_mode_info_t *vbe_mode_info(void) { if (!mode_info_valid || !mode_info.vesa.phys_base_ptr) @@ -351,6 +347,24 @@ void vbe_set_graphics(void) } vbe_set_mode(&mode_info); + const struct lb_framebuffer fb = { + .physical_address = mode_info.vesa.phys_base_ptr, + .x_resolution = le16_to_cpu(mode_info.vesa.x_resolution), + .y_resolution = le16_to_cpu(mode_info.vesa.y_resolution), + .bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline), + .bits_per_pixel = mode_info.vesa.bits_per_pixel, + .red_mask_pos = mode_info.vesa.red_mask_pos, + .red_mask_size = mode_info.vesa.red_mask_size, + .green_mask_pos = mode_info.vesa.green_mask_pos, + .green_mask_size = mode_info.vesa.green_mask_size, + .blue_mask_pos = mode_info.vesa.blue_mask_pos, + .blue_mask_size = mode_info.vesa.blue_mask_size, + .reserved_mask_pos = mode_info.vesa.reserved_mask_pos, + .reserved_mask_size = mode_info.vesa.reserved_mask_size, + .orientation = LB_FB_ORIENTATION_NORMAL, + }; + + fb_add_framebuffer_info_ex(&fb); } void vbe_textmode_console(void) @@ -362,34 +376,6 @@ void vbe_textmode_console(void) die("\nError: In %s function\n", __func__); } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - framebuffer->physical_address = mode_info.vesa.phys_base_ptr; - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = - le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; -} - #endif void run_bios(struct device *dev, unsigned long addr) diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index 9e216e9df6..ab55198d23 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -170,7 +170,7 @@ void x86emu_decode_printf (const char *x) void x86emu_decode_printf2 (const char *x, int y) { char temp[100]; - snprintf(temp, sizeof (temp), x,y); + snprintf(temp, sizeof(temp), x,y); strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,temp); M.x86.enc_str_pos += strlen(temp); } diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index 3b7bde727a..06d7f314fe 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -1122,7 +1122,6 @@ unsigned int decode_rm10_address( return 0; /* SHOULD NOT HAPPEN */ } - /**************************************************************************** PARAMETERS: mod - modifier diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 3c4a8caf5b..d794ecb46c 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -129,7 +129,6 @@ static u32 x86emu_parity_tab[8] = /*----------------------------- Implementation ----------------------------*/ - /*--------- Side effects helper functions -------*/ /**************************************************************************** diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 06f240c5a7..538660894f 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -199,8 +199,6 @@ void X86API wrl(u32 addr, u32 val) DB(if (DEBUG_MEM_TRACE()) printf("%#08x 4 <- %#x\n", addr, val);) - - } /**************************************************************************** diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h index ce910f7e69..8cec44fe97 100644 --- a/src/device/oprom/yabel/compat/of.h +++ b/src/device/oprom/yabel/compat/of.h @@ -31,7 +31,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #ifndef OF_H #define OF_H #define p32 int @@ -48,7 +47,6 @@ typedef struct unsigned int args[16]; } of_arg_t; - phandle_t of_finddevice (const char *); phandle_t of_peer(phandle_t); phandle_t of_child(phandle_t); @@ -56,7 +54,6 @@ phandle_t of_parent(phandle_t); int of_getprop(phandle_t, const char *, void *, int); void *of_call_method_3(const char *, ihandle_t, int); - ihandle_t of_open(const char *); void of_close(ihandle_t); int of_read(ihandle_t, void *, int); diff --git a/src/device/oprom/yabel/compat/rtas.h b/src/device/oprom/yabel/compat/rtas.h index ccad9e958b..021f51e723 100644 --- a/src/device/oprom/yabel/compat/rtas.h +++ b/src/device/oprom/yabel/compat/rtas.h @@ -31,7 +31,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #ifndef RTAS_H #define RTAS_H diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 4a50068faf..2c98578c7d 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -32,7 +32,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #include "device.h" #include "compat/rtas.h" #include @@ -150,7 +149,6 @@ biosemu_dev_get_addr_info(void) void translate_address_dev(u64 *, phandle_t); u64 get_puid(phandle_t node); - // scan all addresses assigned to the device ("assigned-addresses" and "reg") // store in translate_address_array for faster translation using dev_translate_address void diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 0fe9e00abe..37440a8051 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -40,7 +40,6 @@ #include "compat/of.h" #include "debug.h" - // a Expansion Header Struct as defined in Plug and Play BIOS Spec 1.0a Chapter 3.2 typedef struct { char signature[4]; // signature diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 338156f8ed..968e471992 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -48,7 +48,6 @@ #include #include - //setup to run the code at the address, that the Interrupt Vector points to... static void setupInt(int intNum) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736fa93..5f03e19261 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -33,6 +33,7 @@ *****************************************************************************/ #include +#include #include #include @@ -163,11 +164,6 @@ vbe_info(vbe_info_t * info) static int mode_info_valid; -static int vbe_mode_info_valid(void) -{ - return mode_info_valid; -} - // VBE Function 01h static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info) @@ -747,33 +743,25 @@ void vbe_set_graphics(void) mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -} -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; + const struct lb_framebuffer fb = { + .physical_address = mode_info.vesa.phys_base_ptr, + .x_resolution = le16_to_cpu(mode_info.vesa.x_resolution), + .y_resolution = le16_to_cpu(mode_info.vesa.y_resolution), + .bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline), + .bits_per_pixel = mode_info.vesa.bits_per_pixel, + .red_mask_pos = mode_info.vesa.red_mask_pos, + .red_mask_size = mode_info.vesa.red_mask_size, + .green_mask_pos = mode_info.vesa.green_mask_pos, + .green_mask_size = mode_info.vesa.green_mask_size, + .blue_mask_pos = mode_info.vesa.blue_mask_pos, + .blue_mask_size = mode_info.vesa.blue_mask_size, + .reserved_mask_pos = mode_info.vesa.reserved_mask_pos, + .reserved_mask_size = mode_info.vesa.reserved_mask_size, + .orientation = LB_FB_ORIENTATION_NORMAL, + }; - framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr); - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; + fb_add_framebuffer_info_ex(&fb); } void vbe_textmode_console(void) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 3623c3b564..f41689e24a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -19,13 +19,11 @@ #include #include #include -#include #include #include #include #include - u8 pci_moving_config8(struct device *dev, unsigned int reg) { u8 value, ones, zeroes; @@ -543,7 +541,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource) dev->command |= PCI_COMMAND_MEMORY; if (resource->flags & IORESOURCE_IO) dev->command |= PCI_COMMAND_IO; - if (resource->flags & IORESOURCE_PCI_BRIDGE) + if (resource->flags & IORESOURCE_PCI_BRIDGE && + CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES)) dev->command |= PCI_COMMAND_MASTER; } @@ -862,19 +861,6 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev) return &default_pcix_ops_bus; } #endif -#if CONFIG(HYPERTRANSPORT_PLUGIN_SUPPORT) - unsigned int htpos = 0; - while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { - u16 flags; - flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); - if ((flags >> 13) == 1) { - /* Host or Secondary Interface */ - printk(BIOS_DEBUG, "%s subordinate bus HT\n", - dev_path(dev)); - return &default_ht_ops_bus; - } - } -#endif #if CONFIG(PCIEXP_PLUGIN_SUPPORT) unsigned int pciexpos; pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); @@ -954,13 +940,16 @@ static void set_pci_ops(struct device *dev) if ((driver->vendor == dev->vendor) && device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; - printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", - dev_path(dev), driver->vendor, driver->device, - (driver->ops->scan_bus ? "bus " : "")); - return; + break; } } + if (dev->ops) { + printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev), + driver->vendor, driver->device, (driver->ops->scan_bus ? "bus " : "")); + return; + } + /* If I don't have a specific driver use the default operations. */ switch (dev->hdr_type & 0x7f) { /* Header type */ case PCI_HEADER_TYPE_NORMAL: @@ -978,7 +967,7 @@ static void set_pci_ops(struct device *dev) dev->ops = &default_cardbus_ops_bus; break; #endif -default: + default: bad: if (dev->enabled) { printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown " @@ -1007,16 +996,11 @@ static struct device *pci_scan_get_dev(struct bus *bus, unsigned int devfn) prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { - if (dev->path.type == DEVICE_PATH_PCI) { - if (dev->path.pci.devfn == devfn) { - /* Unlink from the list. */ - *prev = dev->sibling; - dev->sibling = NULL; - break; - } - } else { - printk(BIOS_ERR, "child %s not a PCI device\n", - dev_path(dev)); + if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == devfn) { + /* Unlink from the list. */ + *prev = dev->sibling; + dev->sibling = NULL; + break; } prev = &dev->sibling; } @@ -1134,7 +1118,8 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus, dev->class = class >> 8; /* Architectural/System devices always need to be bus masters. */ - if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) + if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM && + CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) dev->command |= PCI_COMMAND_MASTER; /* @@ -1284,6 +1269,16 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { + + /* + * If static device is not PCI then enable it here and don't + * treat it as a leftover device. + */ + if (dev->path.type != DEVICE_PATH_PCI) { + enable_static_device(dev); + continue; + } + /* * The device is only considered leftover if it is not hidden * and it has a Vendor ID of 0 (the default for a device that diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 90f45bf21a..aaa9f95fb1 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -78,3 +78,21 @@ void __noreturn pcidev_die(void) { die("PCI: dev is NULL!\n"); } + +bool pci_dev_is_wake_source(const struct device *dev) +{ + unsigned int pm_cap; + uint16_t pmcs; + + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!pm_cap) + return false; + + pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL); + + /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ + return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); +} diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index bb616d91f1..4224c651f3 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -264,8 +264,8 @@ void pci_rom_ssdt(const struct device *device) { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865152..8d4bb9849d 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -180,6 +180,8 @@ static void pciexp_enable_ltr(struct device *dev) for (bus = dev->link_list ; bus ; bus = bus->next) { for (child = bus->children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI) + continue; pciexp_configure_ltr(child); if (child->ops && child->ops->scan_bus) pciexp_enable_ltr(child); @@ -478,6 +480,8 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI) + continue; if ((child->path.pci.devfn < min_devfn) || (child->path.pci.devfn > max_devfn)) { continue; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index cd7adf32bc..259d449752 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -56,7 +56,7 @@ void pnp_set_enable(struct device *dev, int enable) { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; @@ -66,14 +66,14 @@ void pnp_set_enable(struct device *dev, int enable) else tmp &= ~(1 << bitpos); - pnp_write_config(dev, 0x30, tmp); + pnp_write_config(dev, PNP_IDX_EN, tmp); } int pnp_read_enable(struct device *dev) { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; @@ -249,6 +249,8 @@ static void get_resources(struct device *dev, struct pnp_info *info) pnp_get_ioresource(dev, PNP_IDX_IO2, info->io2); if (info->flags & PNP_IO3) pnp_get_ioresource(dev, PNP_IDX_IO3, info->io3); + if (info->flags & PNP_IO4) + pnp_get_ioresource(dev, PNP_IDX_IO4, info->io4); if (info->flags & PNP_IRQ0) { resource = new_resource(dev, PNP_IDX_IRQ0); diff --git a/src/device/root_device.c b/src/device/root_device.c index 640ea505d4..1f51786153 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -7,6 +7,18 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; +void enable_static_device(struct device *dev) +{ + if (dev->chip_ops && dev->chip_ops->enable_dev) + dev->chip_ops->enable_dev(dev); + + if (dev->ops && dev->ops->enable) + dev->ops->enable(dev); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(dev), + dev->enabled ? "enabled" : "disabled"); +} + /** * Enable devices on static buses. * @@ -32,15 +44,7 @@ void enable_static_devices(struct device *bus) for (link = bus->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); + enable_static_device(child); } } } @@ -58,18 +62,9 @@ void scan_generic_bus(struct device *bus) link->secondary = ++bus_max; for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - + enable_static_device(child); printk(BIOS_DEBUG, "bus: %s[%d]->", dev_path(child->bus->dev), child->bus->link_num); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); } } diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 6d80c4c6c3..246ed8bac0 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += def_callouts.c ramstage-y += eventlog.c ramstage-y += heapmanager.c ramstage-y += acpi_tables.c +ramstage-y += nvs.c romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 4ef3f40208..df9876a84a 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29b3c..33940cb489 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include #include +.section .init + .code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end + .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 07f717324e..5f52ca0904 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -121,9 +121,7 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr) AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = cbfs_map("pci"CONFIG_VGA_BIOS_ID".rom", NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 8aa1c93120..c1fac0dadb 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include diff --git a/src/drivers/amd/agesa/nvs.c b/src/drivers/amd/agesa/nvs.c new file mode 100644 index 0000000000..5bde9d53fc --- /dev/null +++ b/src/drivers/amd/agesa/nvs.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +size_t gnvs_size_of_array(void) +{ + return 0; +} diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 6ae7d999d6..31db0b6b4c 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include @@ -31,8 +30,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader) const void *agesa, *image; size_t file_size; - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); + agesa = cbfs_map((const char *)CONFIG_AGESA_CBFS_NAME, &file_size); if (agesa == NULL) return; diff --git a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c index a93826551d..b5be31d038 100644 --- a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c +++ b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c @@ -21,6 +21,11 @@ static void i2s_machine_dev_fill_ssdt(const struct device *dev) dmic_select_gpio = &cfg->dmic_select_gpio; + if (scope == NULL) { + printk(BIOS_ERR, "%s: ERROR: ACPI I2S scope not found\n", dev_path(dev)); + return; + } + if (cfg->hid == NULL) { printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); return; diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index ee98fd4df9..9f0b2e1f2c 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -737,7 +737,6 @@ static int anx7625_power_on_init(uint8_t bus) } ANXINFO("Init interface.\n"); - anx7625_disable_pd_protocol(bus); anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version); anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision); diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 460b85801e..924ca57d9d 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -331,7 +331,6 @@ static bool ast_init_dvo(struct drm_device *dev) return true; } - static void ast_init_analog(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index e275108602..423ba37c28 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -11,7 +11,6 @@ #define PCI_CHIP_AST2100 0x2010 #define PCI_CHIP_AST1180 0x1180 - enum ast_chip { AST2000, AST2100, @@ -64,6 +63,11 @@ struct ast_private { int next_cursor; bool support_wide_screen; + enum { + ast_use_p2a, + ast_use_dt, + ast_use_defaults + } config_mode; enum ast_tx_chip tx_chip_type; u8 dp501_maxclk; diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 5143e6d0eb..89194ad0be 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -4,6 +4,7 @@ */ #include +#include #include "ast_drv.h" #include "ast_dram_tables.h" @@ -36,17 +37,79 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, return ret; } +static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) +{ + struct ast_private *ast = dev->dev_private; + uint32_t data, jregd0, jregd1; + + /* Defaults */ + ast->config_mode = ast_use_defaults; + *scu_rev = 0xffffffff; + + /* Not all families have a P2A bridge */ + if (dev->pdev->device != PCI_CHIP_AST2000) + return; + + /* + * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge + * is disabled. We force using P2A if VGA only mode bit + * is set D[7] + */ + jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); + if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Double check it's actually working */ + data = ast_read32(ast, 0xf004); + if (data != 0xFFFFFFFF) { + /* P2A works, grab silicon revision */ + ast->config_mode = ast_use_p2a; + + DRM_INFO("Using P2A bridge for configuration\n"); + + /* Read SCU7c (silicon revision register) */ + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + *scu_rev = ast_read32(ast, 0x1207c); + return; + } + } + + /* We have a P2A bridge but it's disabled */ + DRM_INFO("P2A bridge disabled, using default configuration\n"); +} static int ast_detect_chip(struct drm_device *dev, bool *need_post) { struct ast_private *ast = dev->dev_private; - uint32_t data, jreg; + uint32_t jreg, scu_rev; + + /* + * If VGA isn't enabled, we need to enable now or subsequent + * access to the scratch registers will fail. We also inform + * our caller that it needs to POST the chip + * (Assumption: VGA not enabled -> need to POST) + */ + if (!ast_is_vga_enabled(dev)) { + ast_enable_vga(dev); + DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); + *need_post = true; + } else + *need_post = false; + + + /* Enable extended register access */ + ast_enable_mmio(dev); ast_open_key(ast); + /* Find out whether P2A works or whether to use device-tree */ + ast_detect_config_mode(dev, &scu_rev); + + /* Identify chipset */ if (dev->pdev->device == PCI_CHIP_AST1180) { ast->chip = AST1100; DRM_INFO("AST 1180 detected\n"); } else { + uint32_t data; pci_read_config_dword(ast->dev->pdev, 0x08, &data); uint8_t revision = data & 0xff; if (revision >= 0x40) { @@ -59,11 +122,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->chip = AST2300; DRM_INFO("AST 2300 detected\n"); } else if (revision >= 0x10) { - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - - data = ast_read32(ast, 0x1207c); - switch (data & 0x0300) { + switch (scu_rev & 0x0300) { case 0x0200: ast->chip = AST1100; DRM_INFO("AST 1100 detected\n"); @@ -88,20 +147,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) } } - /* - * If VGA isn't enabled, we need to enable now or subsequent - * access to the scratch registers will fail. We also inform - * our caller that it needs to POST the chip - * (Assumption: VGA not enabled -> need to POST) - */ - if (!ast_is_vga_enabled(dev)) { - ast_enable_vga(dev); - ast_enable_mmio(dev); - DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); - *need_post = true; - } else - *need_post = false; - /* Check if we support wide screen */ switch (ast->chip) { case AST1180: @@ -118,16 +163,14 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->support_wide_screen = true; else { ast->support_wide_screen = false; - /* Read SCU7c (silicon revision register) */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - data = ast_read32(ast, 0x1207c); - data &= 0x300; - if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ + if (ast->chip == AST2300 && + (scu_rev & 0x300) == 0x0) /* ast1300 */ ast->support_wide_screen = true; - if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ + if (ast->chip == AST2400 && + (scu_rev & 0x300) == 0x100) /* ast1400 */ ast->support_wide_screen = true; - if (ast->chip == AST2500 && data == 0x100) /* ast2510 */ + if (ast->chip == AST2500 && + scu_rev == 0x100) /* ast2510 */ ast->support_wide_screen = true; } break; @@ -193,34 +236,44 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) static int ast_get_dram_info(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; - uint8_t i; - uint32_t data, data2; - uint32_t denum, num, div, ref_pll; + uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; + uint32_t denum, num, div, ref_pll, dsel; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - - - ast_write32(ast, 0x10000, 0xfc600309); - - /* Wait up to 2.5 seconds for device initialization / register unlock */ - for (i = 0; i < 250; i++) { - if (ast_read32(ast, 0x10000) == 0x01) - break; - mdelay(10); + switch (ast->config_mode) { + case ast_use_dt: + /* + * If some properties are missing, use reasonable + * defaults for AST2400 + */ + mcr_cfg = 0x00000577; + mcr_scu_mpll = 0x000050C0; + mcr_scu_strap = 0; + break; + case ast_use_p2a: + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + mcr_cfg = ast_read32(ast, 0x10004); + mcr_scu_mpll = ast_read32(ast, 0x10120); + mcr_scu_strap = ast_read32(ast, 0x10170); + break; + case ast_use_defaults: + default: + ast->dram_bus_width = 16; + ast->dram_type = AST_DRAM_1Gx16; + if (ast->chip == AST2500) + ast->mclk = 800; + else + ast->mclk = 396; + return 0; } - if (ast_read32(ast, 0x10000) != 0x01) - dev_err(dev->pdev, "Unable to unlock SDRAM control registers\n"); - data = ast_read32(ast, 0x10004); - - if (data & 0x40) + if (mcr_cfg & 0x40) ast->dram_bus_width = 16; else ast->dram_bus_width = 32; if (ast->chip == AST2500) { - switch (data & 0x03) { + switch (mcr_cfg & 0x03) { case 0: ast->dram_type = AST_DRAM_1Gx16; break; @@ -236,7 +289,7 @@ static int ast_get_dram_info(struct drm_device *dev) break; } } else if (ast->chip == AST2300 || ast->chip == AST2400) { - switch (data & 0x03) { + switch (mcr_cfg & 0x03) { case 0: ast->dram_type = AST_DRAM_512Mx16; break; @@ -252,13 +305,13 @@ static int ast_get_dram_info(struct drm_device *dev) break; } } else { - switch (data & 0x0c) { + switch (mcr_cfg & 0x0c) { case 0: case 4: ast->dram_type = AST_DRAM_512Mx16; break; case 8: - if (data & 0x40) + if (mcr_cfg & 0x40) ast->dram_type = AST_DRAM_1Gx16; else ast->dram_type = AST_DRAM_512Mx32; @@ -269,17 +322,15 @@ static int ast_get_dram_info(struct drm_device *dev) } } - data = ast_read32(ast, 0x10120); - data2 = ast_read32(ast, 0x10170); - if (data2 & 0x2000) + if (mcr_scu_strap & 0x2000) ref_pll = 14318; else ref_pll = 12000; - denum = data & 0x1f; - num = (data & 0x3fe0) >> 5; - data = (data & 0xc000) >> 14; - switch (data) { + denum = mcr_scu_mpll & 0x1f; + num = (mcr_scu_mpll & 0x3fe0) >> 5; + dsel = (mcr_scu_mpll & 0xc000) >> 14; + switch (dsel) { case 3: div = 0x4; break; @@ -311,6 +362,19 @@ static u32 ast_get_vram_info(struct drm_device *dev) case 3: vram_size = AST_VIDMEM_SIZE_64M; break; } + jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); + switch (jreg & 0x03) { + case 1: + vram_size -= 0x100000; + break; + case 2: + vram_size -= 0x200000; + break; + case 3: + vram_size -= 0x400000; + break; + } + return vram_size; } @@ -329,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, 0x14); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -343,7 +407,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, 0x18); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); if (!res) { dev_err(dev->pdev, "BAR2 resource not found.\n"); ret = -EIO; @@ -374,15 +438,19 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast_detect_chip(dev, &need_post); - if (ast->chip != AST1180) { - ast_get_dram_info(dev); - ast->vram_size = ast_get_vram_info(dev); - DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); - } - if (need_post) ast_post_gpu(dev); + if (ast->chip != AST1180) { + ret = ast_get_dram_info(dev); + if (ret) + goto out_free; + ast->vram_size = ast_get_vram_info(dev); + DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", + ast->mclk, ast->dram_type, + ast->dram_bus_width, ast->vram_size); + } + return 0; out_free: kfree(ast); diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c index 465d8866a9..e5832e772e 100644 --- a/src/drivers/aspeed/common/ast_mode.c +++ b/src/drivers/aspeed/common/ast_mode.c @@ -6,7 +6,6 @@ #include "ast_drv.h" #include "ast_tables.h" - static inline void ast_load_palette_index(struct ast_private *ast, u8 index, u8 red, u8 green, u8 blue) diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2a033a028b..b25d742f01 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -2,7 +2,11 @@ /* * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ + +#include #include +#include +#include #include "ast_drv.h" @@ -18,7 +22,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) struct drm_framebuffer *fb = crtc->primary->fb; /* PCI BAR 0 */ - struct resource *res = find_resource(crtc->dev->pdev, 0x10); + struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_ERR, "BAR0 resource not found.\n"); return -EIO; @@ -29,7 +33,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) return -ENOMEM; } - fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095); ast_set_offset_reg(crtc); ast_set_start_address_crt1(ast, fb->mmio_addr); @@ -95,7 +99,11 @@ static int ast_select_mode(struct drm_connector *connector, ast_software_i2c_read(ast, raw); if (decode_edid(raw, sizeof(raw), edid) != EDID_CONFORMANT) { - dev_err(dev->pdev, "Failed to decode EDID\n"); + /* + * Servers often run headless, so a missing EDID is not an error. + * We still need to initialize a framebuffer for KVM, though. + */ + dev_info(dev->pdev, "Failed to decode EDID\n"); printk(BIOS_DEBUG, "Assuming VGA for KVM\n"); memset(edid, 0, sizeof(*edid)); @@ -193,7 +201,7 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags) return ret; } - /* Updated edid for set_vbe_mode_info_valid */ + /* Updated edid for fb_fill_framebuffer_info */ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; @@ -220,10 +228,10 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags) ast_hide_cursor(&crtc); /* Advertise new mode */ - set_vbe_mode_info_valid(&edid, fb.mmio_addr); + fb_new_framebuffer_info_from_edid(&edid, fb.mmio_addr); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); return 0; } diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index b3b7d6196c..e644d910f7 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -2,6 +2,7 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 +#include #include #include "ast_drv.h" @@ -25,7 +26,6 @@ void ast_enable_mmio(struct drm_device *dev) ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); } - bool ast_is_vga_enabled(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; @@ -208,7 +208,6 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw) return 1; } - static void cbrdlli_ast2150(struct ast_private *ast, int busw) { u32 dll_min[4], dll_max[4], dlli, data, passcnt; @@ -239,8 +238,6 @@ cbr_start: ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); } - - static void ast_init_dram_reg(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; @@ -370,14 +367,20 @@ void ast_post_gpu(struct drm_device *dev) ast_enable_mmio(dev); ast_set_def_ext_reg(dev); - if (ast->chip == AST2500) - ast_post_chip_2500(dev); - else if (ast->chip == AST2300 || ast->chip == AST2400) - ast_post_chip_2300(dev); - else - ast_init_dram_reg(dev); + if (ast->config_mode == ast_use_p2a) { + if (ast->chip == AST2500) + ast_post_chip_2500(dev); + else if (ast->chip == AST2300 || ast->chip == AST2400) + ast_post_chip_2300(dev); + else + ast_init_dram_reg(dev); - ast_init_3rdtx(dev); + ast_init_3rdtx(dev); + } else { + if (ast->tx_chip_type != AST_TX_NONE) + /* Enable DVO */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); + } } /* AST 2300 DRAM settings */ @@ -473,7 +476,6 @@ static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) return data; } - static bool mmc_test_burst(struct ast_private *ast, u32 datagen) { return mmc_test(ast, datagen, 0xc1); @@ -1225,7 +1227,6 @@ ddr3_init_start: ast_moutdwm(ast, 0x1E6E0050, 0x00000000); #endif - } static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1240,7 +1241,6 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa trap_AC2 += 0x00110000; trap_MRS = 0x00000040 | (trap << 4); - param->reg_MADJ = 0x00034C4C; param->reg_SADJ = 0x00001800; param->reg_DRV = 0x000000F0; diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index fb13da803f..bfd8f52ce0 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -220,7 +220,6 @@ static const struct ast_vbios_enhtable res_800x600[] = { (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, }; - static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, @@ -280,7 +279,6 @@ static const struct ast_vbios_enhtable res_1920x1080[] = { AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; - /* 16:10 */ static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ diff --git a/src/drivers/camera/Kconfig b/src/drivers/camera/Kconfig new file mode 100644 index 0000000000..1c0c0a3634 --- /dev/null +++ b/src/drivers/camera/Kconfig @@ -0,0 +1,7 @@ +config CHROMEOS_CAMERA + bool + default n + help + Camera with identifiers following Chrome OS Camera Info. The info is + usually available on MIPI camera EEPROM for identifying correct + drivers and config. diff --git a/src/drivers/camera/Makefile.inc b/src/drivers/camera/Makefile.inc new file mode 100644 index 0000000000..1a6e609465 --- /dev/null +++ b/src/drivers/camera/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_CHROMEOS_CAMERA) += cros_camera.c diff --git a/src/drivers/camera/cros_camera.c b/src/drivers/camera/cros_camera.c new file mode 100644 index 0000000000..ff39678033 --- /dev/null +++ b/src/drivers/camera/cros_camera.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "cros_camera.h" + +int check_cros_camera_info(const struct cros_camera_info *info) +{ + if (memcmp(info->magic, CROS_CAMERA_INFO_MAGIC, sizeof(info->magic))) { + printk(BIOS_ERR, "Invalid magic in camera info\n"); + return -1; + } + + const uint8_t *ptr = (void *)(&info->crc16 + 1); + uint16_t crc16 = 0; + while (ptr < (uint8_t *)info + sizeof(struct cros_camera_info)) + crc16 = crc16_byte(crc16, *ptr++); + + if (info->crc16 != crc16) { + printk(BIOS_ERR, "Incorrect CRC16: expected %#06x, got %#06x\n", + crc16, info->crc16); + return -1; + } + + if (info->version != CROS_CAMERA_INFO_VERSION) { + printk(BIOS_ERR, "Unknown camera info version: %u\n", + info->version); + return -1; + } + if (info->size < CROS_CAMERA_INFO_SIZE_MIN) { + printk(BIOS_ERR, "Size of camera info is too small: %u\n", + info->size); + return -1; + } + + return 0; +} diff --git a/src/drivers/camera/cros_camera.h b/src/drivers/camera/cros_camera.h new file mode 100644 index 0000000000..f69e77d3e5 --- /dev/null +++ b/src/drivers/camera/cros_camera.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H +#define __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H + +#include + +#define CROS_CAMERA_INFO_MAGIC "CrOS" +#define CROS_CAMERA_INFO_VERSION 1 +#define CROS_CAMERA_INFO_SIZE_MIN 0x0a + +struct cros_camera_info { + uint8_t magic[4]; /* CROS_CAMERA_INFO_MAGIC */ + uint16_t crc16; + uint8_t version; + uint8_t size; + uint16_t data_format; + uint16_t module_pid; + uint8_t module_vid[2]; + uint8_t sensor_vid[2]; + uint16_t sensor_pid; +}; + +/* Returns 0 on success, non-zero on errors. */ +int check_cros_camera_info(const struct cros_camera_info *info); + +#endif diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 9d12690def..800d1457f4 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -30,7 +30,6 @@ static const char *tis_get_dev_name(struct tpm2_info *info) return "Unknown"; } - int tis_open(void) { if (tpm_is_open) { @@ -79,7 +78,6 @@ int tis_init(void) return 0; } - int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 6436725d69..fcefe96448 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include @@ -44,10 +43,11 @@ static void crb_readControlArea(void) control_area.cancel = read32(CRB_REG(cur_loc, CRB_REG_CANCEL)); control_area.interrupt_control = read64(CRB_REG(cur_loc, CRB_REG_INT_CTRL)); control_area.command_size = read32(CRB_REG(cur_loc, CRB_REG_CMD_SIZE)); - control_area.command_bfr = (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR)); + control_area.command_bfr = + (void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR)); control_area.response_size = read32(CRB_REG(cur_loc, CRB_REG_RESP_SIZE)); control_area.response_bfr = - (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR)); + (void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR)); } /* Wait for Reg to be expected Value */ @@ -122,7 +122,6 @@ static uint8_t crb_activate_locality(void) if (rc) write8(CRB_REG(locality, CRB_REG_LOC_CTRL), LOC_CTRL_REQ_ACCESS); - rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, LOC_STATE_LOC_ASSIGN, LOC_STATE_LOC_ASSIGN); if (rc) { @@ -138,7 +137,6 @@ static uint8_t crb_activate_locality(void) return 0; } - return locality; } @@ -177,7 +175,6 @@ static int crb_switch_to_ready(void) int tpm2_init(void) { - if (crb_probe()) { printk(BIOS_ERR, "TPM: Probe failed.\n"); return -1; diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index 449d02fb6b..c43beb6843 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -6,7 +6,7 @@ #define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS #define CRB_REG(LOCTY, REG) \ - (void *)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG) + (void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG) /* hardware registers */ #define CRB_REG_LOC_STATE 0x00 @@ -39,7 +39,6 @@ #define CRB_INTF_REG_INTF_SEL (1<<17) #define CRB_INTF_REG_INTF_LOCK (1<<19) - /*REQUEST Register related */ #define CRB_REG_REQUEST_CMD_RDY 0x01 #define CRB_REG_REQUEST_GO_IDLE 0x02 @@ -58,7 +57,6 @@ struct tpm2_info { uint16_t revision; }; - int tpm2_init(void); void tpm2_get_info(struct tpm2_info *tpm2_info); size_t tpm2_process_command(const void *tpm2_command, size_t command_size, diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index bc25d1cebb..19b33318c4 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -23,12 +23,6 @@ config ELOG_CBMEM but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log. -config ELOG_PRERAM - bool - default n - help - This option will enable event logging from the preram stage. - config ELOG_GSMI depends on HAVE_SMI_HANDLER bool "SMI interface to write and clear event log" diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d6d7..370eef44d1 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ -bootblock-$(CONFIG_ELOG_PRERAM) += elog.c -verstage-$(CONFIG_ELOG_PRERAM) += elog.c -romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +bootblock-$(CONFIG_ELOG) += elog.c +verstage-$(CONFIG_ELOG) += elog.c +romstage-$(CONFIG_ELOG) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 01fa9cce65..818355b5b9 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -17,7 +17,6 @@ #include #include "elog_internal.h" - #if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) #else diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 5a6603ee1e..73fa19e2ca 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -10,6 +9,7 @@ #include #include #include +#include /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_IOPORT_INDEX 0x01CE @@ -82,7 +82,6 @@ static struct resource res_legacy = { static void bochs_init_linear_fb(struct device *dev) { - struct edid edid; struct resource *res_fb, *res_io; int id, mem, bar; @@ -139,13 +138,8 @@ static void bochs_init_linear_fb(struct device *dev) bochs_vga_write(res_io, 0, 0x20); /* disable blanking */ - /* setup coreboot framebuffer */ - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, res_fb->base); + /* Advertise new mode */ + fb_add_framebuffer_info(res_fb->base, width, height, 4 * width, 32); } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c8d373a46e..d9e0e1bd14 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include #include #include #include +#include static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; @@ -299,14 +299,7 @@ static void cirrus_init_linear_fb(struct device *dev) vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - - struct edid edid; - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + fb_add_framebuffer_info(addr, width, height, 4 * width, 32); } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 88ee34da7b..26da09b264 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -17,7 +17,7 @@ static void adau7002_fill_ssdt(const struct device *dev) struct drivers_generic_adau7002_config *config; struct acpi_dp *dp; - if (!dev || !dev->enabled) + if (!dev) return; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 2e3e37d1ac..9f8aaa80f9 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -5,7 +5,6 @@ #include #include - #define MAX_SERIAL_LENGTH 0x100 const char *smbios_mainboard_serial_number(void) diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 80ac407904..3d273a030f 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -57,7 +57,7 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev) const char *drv_string = config->is_polled ? "gpio-keys-polled" : "gpio-keys"; - if (!dev->enabled || !scope || !path || !config->gpio.pin_count) + if (!scope || !path || !config->gpio.pin_count) return; /* Device */ diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 44f8802490..9ae4bf4658 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -18,7 +18,7 @@ static void max98357a_fill_ssdt(const struct device *dev) const char *path; struct acpi_dp *dp; - if (!dev->enabled || !config) + if (!config) return; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/genesyslogic/gl9755/Kconfig b/src/drivers/genesyslogic/gl9755/Kconfig new file mode 100644 index 0000000000..5bccb9b490 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/Kconfig @@ -0,0 +1,7 @@ +config DRIVERS_GENESYSLOGIC_GL9755 + bool "Genesys Logic GL9755" + help + GL9755 is a PCI Express Rev. 2.1 compliant card reader controller + which integrates PCI Express PHY, UHS-II PHY, memory card access + interface, regulators (3.3V-to-1.8V and 3.3V-to-1.2V) and card + power switch. diff --git a/src/drivers/genesyslogic/gl9755/Makefile.inc b/src/drivers/genesyslogic/gl9755/Makefile.inc new file mode 100644 index 0000000000..995cfd30f6 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9755) += gl9755.c diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c new file mode 100644 index 0000000000..6dfac47293 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9755 */ + +#include +#include +#include +#include +#include +#include +#include "gl9755.h" + +static void gl9755_enable(struct device *dev) +{ + uint32_t reg; + + printk(BIOS_INFO, "GL9755: configure ASPM and LTR\n"); + + /* Set Vendor Config to be configurable */ + pci_or_config32(dev, CFG, CFG_EN); + + /* Set LTR value */ + pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); + + /* Adjust L1 exit latency to enable ASPM */ + reg = pci_read_config32(dev, CFG2); + reg &= ~CFG2_LAT_L1_MASK; + reg |= CFG2_LAT_L1_64US; + pci_write_config32(dev, CFG2, reg); + + /* Set Vendor Config to be non-configurable */ + pci_and_config32(dev, CFG, ~CFG_EN); +} + +static struct device_operations gl9755_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .enable = gl9755_enable +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9755, + 0 +}; + +static const struct pci_driver genesyslogic_gl9755 __pci_driver = { + .ops = &gl9755_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_gl9755_ops = { + CHIP_NAME("Genesys Logic GL9755") +}; diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h new file mode 100644 index 0000000000..aa20a527f2 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_GENESYSLOGIC_GL9755_H +#define DRIVERS_GENESYSLOGIC_GL9755_H + +/* Definitions for Genesys Logic GL9755 */ + +#define CFG 0x800 +#define CFG_EN 0x1 +#define CFG2 0x48 +#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3)) +#define CFG2_LAT_L1_64US ((0x6 << 12) | (0x6 << 3)) +#define LTR 0x5C +#define SNOOP_VALUE 0x25 +#define SNOOP_SCALE (0x3 << 10) +#define NO_SNOOP_VALUE (0x25 << 16) +#define NO_SNOOP_SCALE (0x3 << 26) + +#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */ diff --git a/src/drivers/genesyslogic/gl9763e/Kconfig b/src/drivers/genesyslogic/gl9763e/Kconfig new file mode 100644 index 0000000000..c254707f66 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENESYSLOGIC_GL9763E + bool diff --git a/src/drivers/genesyslogic/gl9763e/Makefile.inc b/src/drivers/genesyslogic/gl9763e/Makefile.inc new file mode 100644 index 0000000000..61a63e6231 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9763E) += gl9763e.c diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c new file mode 100644 index 0000000000..cd581b9380 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9763E */ + +#include +#include +#include +#include +#include +#include +#include "gl9763e.h" + +static void gl9763e_init(struct device *dev) +{ + uint32_t ver; + + printk(BIOS_INFO, "GL9763E: init\n"); + pci_dev_init(dev); + + /* Set VHS (Vendor Header Space) to be writable */ + pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_W); + /* Set single AXI request */ + pci_or_config32(dev, SCR, SCR_AXI_REQ); + /* Disable L0s support */ + pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S); + /* Set SSC to 30000 ppm */ + pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); + /* Enable SSC */ + pci_or_config32(dev, PLL_CTL, PLL_CTL_SSC); + /* Check chip version */ + ver = pci_read_config32(dev, HW_VER_2); + if ((ver & HW_VER_MASK) == REVISION_03) { + /* Set clock source for RX path */ + pci_update_config32(dev, SD_CLKRX_DLY, ~CLK_SRC_MASK, AFTER_OUTPUT_BUFF); + } + /* Modify DS delay */ + pci_update_config32(dev, SD_CLKRX_DLY, ~HS400_RX_DELAY_MASK, HS400_RX_DELAY); + /* Disable Slow mode */ + pci_and_config32(dev, EMMC_CTL, ~SLOW_MODE); + /* Set VHS to read-only */ + pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R); +} + +static struct device_operations gl9763e_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = gl9763e_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9763E, + 0 +}; + +static const struct pci_driver genesyslogic_gl9763e __pci_driver = { + .ops = &gl9763e_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_ops = { + CHIP_NAME("Genesys Logic GL9763E") +}; diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h new file mode 100644 index 0000000000..7f5dbf9c05 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Definitions for Genesys Logic GL9763E */ + +#include + +#define VHS 0x884 +#define VHS_REV_MASK (0xF << 16) +#define VHS_REV_R (0x0 << 16) +#define VHS_REV_M (0x1 << 16) +#define VHS_REV_W (0x2 << 16) +#define SCR 0x8E0 +#define SCR_AXI_REQ BIT(9) + +#define CFG_REG_2 0x8A4 +#define CFG_REG_2_L0S BIT(11) + +#define PLL_CTL 0x938 +#define PLL_CTL_SSC BIT(19) + +#define EMMC_CTL 0x960 +#define SLOW_MODE BIT(3) + +#define PLL_CTL_2 0x93C +#define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16) +#define MAX_SSC_30000PPM (0xF5C3 << 16) + +#define HW_VER_2 0x8F8 +#define HW_VER_MASK 0xFFFF +#define REVISION_03 0x0011 + +#define SD_CLKRX_DLY 0x934 +#define CLK_SRC_MASK (0x3 << 24) +#define AFTER_OUTPUT_BUFF (0x0 << 24) +#define HS400_RX_DELAY_MASK (0xF << 28) +#define HS400_RX_DELAY (0x5 << 28) diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 546f30bead..d3a4518d40 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -106,7 +106,7 @@ static void gfx_fill_ssdt_generator(const struct device *dev) const char *scope = acpi_device_scope(dev); - if (!scope || !dev->enabled) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index afadc6fd53..bc01969b5a 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -45,7 +45,7 @@ static void at24rf08c_read_string_dev(struct device *dev, u8 start, int t = at24rf08c_read_byte(dev, start + i); if (t < 0x20 || t > 0x7f) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } result[i] = t; @@ -60,7 +60,7 @@ static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) dev = at24rf08c_find_bank(bank); if (dev == NULL) { printk(BIOS_WARNING, "EEPROM not found\n"); - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } @@ -75,7 +75,7 @@ const char *smbios_mainboard_serial_number(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x2e, 7, result); already_read = 1; @@ -90,7 +90,7 @@ const char *lenovo_mainboard_partnumber(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x27, 7, result); already_read = 1; @@ -113,13 +113,12 @@ void smbios_system_set_uuid(u8 *uuid) 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 }; - if (already_read) { memcpy(uuid, result, 16); return; } - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); dev = dev_find_slot_on_smbus(1, 0x56); if (dev == NULL) { @@ -141,7 +140,7 @@ void smbios_system_set_uuid(u8 *uuid) break; } if (t < 0) { - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); break; } result[remap[i]] = t; @@ -162,17 +161,17 @@ const char *smbios_mainboard_version(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); dev = at24rf08c_find_bank(2); if (dev == NULL) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } len = at24rf08c_read_byte(dev, 0x26) - 2; if (len < 0 || len > sizeof(result) - 1) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index e83d3e35ed..58eaec657a 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -31,7 +31,6 @@ static void ck505_init(struct device *dev) nregs = MIN(MIN(dev_nregs, config->nregs == 0 ? SMBUS_BLOCK_SIZE : config->nregs), ARRAY_SIZE(config->mask)); - printk(BIOS_DEBUG, "Changing %d of the %d ck505 config bytes.\n", nregs, dev_nregs); diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 1d98023ff5..0423460049 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -27,7 +27,7 @@ static void da7219_fill_ssdt(const struct device *dev) }; struct acpi_dp *dsd, *aad; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 00865e3f6e..c0212c3e27 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -419,6 +419,15 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, /* Read to clear INTR_STAT_STOP_DET */ read32(®s->clear_stop_det_intr); + /* Check TX abort */ + if (read32(®s->raw_intr_stat) & INTR_STAT_TX_ABORT) { + printk(BIOS_ERR, "I2C TX abort detected (%08x)\n", + read32(®s->tx_abort_source)); + /* clear INTR_STAT_TX_ABORT */ + read32(®s->clear_tx_abrt_intr); + goto out; + } + /* Wait for the bus to go idle */ if (dw_i2c_wait_for_bus_idle(regs)) { printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); @@ -698,7 +707,6 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, return 0; } - /* * Initialize this bus controller and set the speed. * @@ -748,8 +756,8 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) write32(®s->rx_thresh, 0); write32(®s->tx_thresh, 0); - /* Enable stop detection interrupt */ - write32(®s->intr_mask, INTR_STAT_STOP_DET); + /* Enable stop detection and TX abort interrupt */ + write32(®s->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT); printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); @@ -825,9 +833,6 @@ void dw_i2c_acpi_fill_ssdt(const struct device *dev) const char *path; unsigned int speed; - if (!dev->enabled) - return; - bus = dw_i2c_soc_dev_to_bus(dev); if (bus < 0) diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 45f305e3b2..e20a5d1d7e 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -17,7 +17,7 @@ /* * Timing values are in units of clock period, with the clock speed - * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ + * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ * Automatic configuration is done based on requested speed, but the * values may need tuned depending on the board and the number of * devices present on the bus. diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 18fd55cd58..1c7267e897 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -57,7 +57,7 @@ void i2c_generic_fill_ssdt(const struct device *dev, int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1; const char *path = acpi_device_path(dev); - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { @@ -72,7 +72,8 @@ void i2c_generic_fill_ssdt(const struct device *dev, if (config->cid) acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); - acpigen_write_name_string("_DDN", config->desc); + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(acpi_device_status(dev)); /* Resources */ diff --git a/src/drivers/i2c/gpiomux/Kconfig b/src/drivers/i2c/gpiomux/Kconfig new file mode 100644 index 0000000000..f09a641eb7 --- /dev/null +++ b/src/drivers/i2c/gpiomux/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_GPIO_MUX + bool + default n + depends on HAVE_ACPI_TABLES + help + When enabled, add identifiers in ACPI tables for GPIO based I2C multiplexer. diff --git a/src/drivers/i2c/gpiomux/Makefile.inc b/src/drivers/i2c/gpiomux/Makefile.inc new file mode 100644 index 0000000000..5c328cba40 --- /dev/null +++ b/src/drivers/i2c/gpiomux/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus diff --git a/src/drivers/i2c/gpiomux/bus/Makefile.inc b/src/drivers/i2c/gpiomux/bus/Makefile.inc new file mode 100644 index 0000000000..1c462dc094 --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus.c diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c new file mode 100644 index 0000000000..0bcf36a3f4 --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *i2c_gpiomux_bus_acpi_name(const struct device *dev) +{ + static char name[ACPI_NAME_BUFFER_SIZE]; + + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MXA%01.1X", dev->path.generic.id); + return name; +} + +static void i2c_gpiomux_bus_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + + if (!dev || !scope || !path) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_ADR(dev->path.generic.id); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_bus_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_bus_fill_ssdt, +}; + +static void i2c_gpiomux_bus_enable(struct device *dev) +{ + if (!dev) + return; + + dev->ops = &i2c_gpiomux_bus_ops; +} + +struct chip_operations drivers_i2c_gpiomux_bus_ops = { + CHIP_NAME("I2C GPIO MUX Bus Device") + .enable_dev = i2c_gpiomux_bus_enable +}; diff --git a/src/drivers/i2c/gpiomux/bus/chip.h b/src/drivers/i2c/gpiomux/bus/chip.h new file mode 100644 index 0000000000..2baf334a6c --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_BUS_CHIP_H__ +#define __I2C_GPIOMUX_BUS_CHIP_H__ + +struct drivers_i2c_gpiomux_bus_config { +}; + +#endif /* __I2C_GPIOMUX_BUS_CHIP_H__ */ diff --git a/src/drivers/i2c/gpiomux/mux/Makefile.inc b/src/drivers/i2c/gpiomux/mux/Makefile.inc new file mode 100644 index 0000000000..e51f706eda --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux.c diff --git a/src/drivers/i2c/gpiomux/mux/chip.h b/src/drivers/i2c/gpiomux/mux/chip.h new file mode 100644 index 0000000000..9906b258db --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/chip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_MUX_CHIP_H__ +#define __I2C_GPIOMUX_MUX_CHIP_H__ + +#include +#include + +#define MAX_NUM_MUX_GPIOS 4 + +struct drivers_i2c_gpiomux_mux_config { + /* GPIOs used to select the mux lines */ + uint32_t mux_gpio_count; + struct acpi_gpio mux_gpio[MAX_NUM_MUX_GPIOS]; +}; + +#endif /* __I2C_GPIOMUX_MUX_CHIP_H__ */ diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c new file mode 100644 index 0000000000..c1ae758226 --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *i2c_gpiomux_mux_acpi_name(const struct device *dev) +{ + static char name[ACPI_NAME_BUFFER_SIZE]; + + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MUX%01.1X", dev->path.generic.id); + return name; +} + +static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + struct drivers_i2c_gpiomux_mux_config *config = config_of(dev); + struct acpi_dp *dsd = NULL; + const char *compat_string = "i2c-mux-gpio"; + struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS]; + int i; + + if (!scope || !path) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + for (i = 0; i < config->mux_gpio_count; i++) { + acpi_device_write_gpio(&config->mux_gpio[i]); + param[i].ref = path; + param[i].index = i; + param[i].pin = 0; + param[i].active_low = config->mux_gpio[i].active_low; + } + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "compatible", compat_string); + acpi_dp_add_gpio_array(dsd, "mux-gpios", param, config->mux_gpio_count); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_mux_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_mux_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_mux_fill_ssdt, +}; + +static void i2c_gpiomux_mux_enable(struct device *dev) +{ + if (!dev) + return; + + dev->ops = &i2c_gpiomux_mux_ops; +} + +struct chip_operations drivers_i2c_gpiomux_mux_ops = { + CHIP_NAME("I2C GPIO MUX Device") + .enable_dev = i2c_gpiomux_mux_enable +}; diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 0755852d94..2d213eb74e 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -28,6 +28,10 @@ static void i2c_hid_fill_ssdt_generator(const struct device *dev) static const char *i2c_hid_acpi_name(const struct device *dev) { static char name[5]; + struct drivers_i2c_hid_config *config = dev->chip_info; + if (config->generic.name) + return config->generic.name; + snprintf(name, sizeof(name), "H%03.3X", dev->path.i2c.device); name[4] = '\0'; return name; diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 0557f421ca..b078674ef0 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -24,8 +24,8 @@ static void max98373_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) { - printk(BIOS_ERR, "%s: dev not enabled", __func__); + if (!scope) { + printk(BIOS_ERR, "%s: dev not enabled\n", __func__); return; } diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 24c500bd2e..c216391e04 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -28,7 +28,7 @@ static void max98390_fill_ssdt(const struct device *dev) struct acpi_dp *dp; uint64_t r0_value, temp_value; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 9429e4aa0d..642eccfd36 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -24,7 +24,7 @@ static void max98927_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index e995ebd06d..a0769d0422 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -30,7 +30,7 @@ static void nau8825_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp = NULL; - if (!dev->enabled || !scope) + if (!scope) return; if (config->sar_threshold_num > NAU8825_MAX_BUTTONS) return; diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 925dca1eae..03c464af82 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -7,6 +7,15 @@ #define NCT7802Y_PECI_CNT 2 #define NCT7802Y_FAN_CNT 3 +#define NCT7802Y_RTD_CNT 3 + +/* Remote temperature diode sensors mode */ +enum nct7802y_rtd_mode { + RTD_CLOSED = 0, + RTD_CURRENT_MODE, + RTD_THERMISTOR_MODE, + RTD_VOLTAGE_MODE, +}; enum nct7802y_peci_mode { PECI_DISABLED = 0, @@ -53,6 +62,11 @@ enum nct7802y_temp_source { TEMP_SOURCE_PROGRAMMABLE_1, }; +struct nct7802y_sensors_config { + bool local_enable; + enum nct7802y_rtd_mode rtd[NCT7802Y_RTD_CNT]; +}; + struct nct7802y_fan_smartconfig { enum nct7802y_fan_smartmode mode; enum nct7802y_fan_speed speed; @@ -76,6 +90,7 @@ struct nct7802y_fan_config { struct drivers_i2c_nct7802y_config { struct nct7802y_peci_config peci[NCT7802Y_PECI_CNT]; struct nct7802y_fan_config fan[NCT7802Y_FAN_CNT]; + struct nct7802y_sensors_config sensors; enum nct7802y_fan_pecierror on_pecierror; u8 pecierror_minduty; }; diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index 5057890c6b..bb52a3fd0b 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -2,10 +2,24 @@ #include #include +#include #include "nct7802y.h" #include "chip.h" +static void nct7802y_init_sensors(struct device *const dev) +{ + const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; + unsigned int i; + u8 value = 0; + + for (i = 0; i < NCT7802Y_RTD_CNT; ++i) + value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]); + if (config->sensors.local_enable) + value |= MODE_SELECTION_LTD_EN; + nct7802y_write(dev, MODE_SELECTION, value); +} + static void nct7802y_init(struct device *const dev) { if (!dev->chip_info) { @@ -15,6 +29,7 @@ static void nct7802y_init(struct device *const dev) } nct7802y_init_peci(dev); + nct7802y_init_sensors(dev); nct7802y_init_fan(dev); } diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h index aa07e7082e..d9b5878c67 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.h +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -11,6 +11,9 @@ #define BANK_SELECT 0x00 /* Bank 0 */ +#define MODE_SELECTION 0x22 +#define MODE_SELECTION_LTD_EN (1 << 6) +#define MODE_SELECTION_RTDx(x, val) ((val) << (x) * 2) #define PECI_ENABLE 0x23 #define PECI_ENABLE_AGENTx(x) (1 << (x)) diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index 7771b78808..bfe3a91a30 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -68,7 +68,7 @@ void nct7802y_init_fan(struct device *const dev) { const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; unsigned int i; - u8 set; + u8 value; if (nct7802y_select_bank(dev, 0) != CB_SUCCESS) return; @@ -80,19 +80,18 @@ void nct7802y_init_fan(struct device *const dev) switch (config->on_pecierror) { case PECI_ERROR_KEEP: - set = CLOSE_LOOP_FAN_PECI_ERR_CURR; + value = CLOSE_LOOP_FAN_PECI_ERR_CURR; break; case PECI_ERROR_VALUE: - set = CLOSE_LOOP_FAN_PECI_ERR_VALUE; + value = CLOSE_LOOP_FAN_PECI_ERR_VALUE; break; case PECI_ERROR_FULLSPEED: - set = CLOSE_LOOP_FAN_PECI_ERR_MAX; + value = CLOSE_LOOP_FAN_PECI_ERR_MAX; break; default: - set = 0; + value = 0; break; } - nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, - CLOSE_LOOP_FAN_PECI_ERR_MASK, set); + nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, CLOSE_LOOP_FAN_PECI_ERR_MASK, value); nct7802y_write(dev, FAN_DUTY_ON_PECI_ERROR, config->pecierror_minduty); } diff --git a/src/drivers/i2c/pca9538/chip.h b/src/drivers/i2c/pca9538/chip.h index bde08a6f5c..96fd02f905 100644 --- a/src/drivers/i2c/pca9538/chip.h +++ b/src/drivers/i2c/pca9538/chip.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - struct drivers_i2c_pca9538_config { unsigned char in_out; /* Use bit as input(1) or output (0). */ unsigned char invert; /* If a bit is 1, the input will be inverted. */ diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 3bdcba6eed..98a343228e 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h index e5dee97159..84a73dcc83 100644 --- a/src/drivers/i2c/rt1011/chip.h +++ b/src/drivers/i2c/rt1011/chip.h @@ -4,7 +4,6 @@ * Realtek RT1011 audio codec devicetree bindings */ - struct drivers_i2c_rt1011_config { const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index d1732f7440..70f1881b6c 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -28,7 +28,7 @@ static void rt1011_fill_ssdt(const struct device *dev) struct acpi_dp *dp; uint64_t r0_value, temp_value; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 272cf78319..565e3bb29c 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -27,7 +27,7 @@ static void rt5663_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index 46ef7f1e3a..4df95806ac 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -3,6 +3,7 @@ #include "rx6110sa.h" struct drivers_i2c_rx6110sa_config { + unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz)*/ /* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index ca39bdb1bc..210444ebc4 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include +#include #include +#include +#include #include #include #include @@ -163,11 +166,70 @@ static void rx6110sa_init(struct device *dev) rx6110sa_write(dev, CTRL_REG, reg); } +#if CONFIG(HAVE_ACPI_TABLES) +static void rx6110sa_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_rx6110sa_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + enum i2c_speed bus_speed; + + if (!scope) + return; + + switch (config->bus_speed) { + case I2C_SPEED_STANDARD: + case I2C_SPEED_FAST: + bus_speed = config->bus_speed; + break; + default: + printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n", + dev_path(dev), I2C_SPEED_STANDARD / 1000); + bus_speed = I2C_SPEED_STANDARD; + break; + } + + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = bus_speed, + .resource = scope, + }; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_DDN", RX6110SA_HID_DESC); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + dev->chip_ops->name, dev_path(dev)); +} + +static const char *rx6110sa_acpi_name(const struct device *dev) +{ + return RX6110SA_ACPI_NAME; +} +#endif + static struct device_operations rx6110sa_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = rx6110sa_init, - .final = rx6110sa_final + .final = rx6110sa_final, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = rx6110sa_acpi_name, + .acpi_fill_ssdt = rx6110sa_fill_ssdt, +#endif }; static void rx6110sa_enable(struct device *dev) diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 187bad424f..fc0109db2a 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -3,9 +3,8 @@ #ifndef _I2C_RX6110SA_H_ #define _I2C_RX6110SA_H_ -/* The address of this RTC is fixed. */ -#define RX6110SA_SLAVE_ADR 0x32 -#define RX6110SA_I2C_CONTROLLER 0 +#define RX6110SA_ACPI_NAME "ERX6" +#define RX6110SA_HID_DESC "Real Time Clock" /* Register layout */ #define SECOND_REG 0x10 diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index c12e4ea524..8dc57a2d98 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -28,7 +28,7 @@ static void i2c_sx9310_fill_ssdt(const struct device *dev) }; struct acpi_dp *dsd; - if (!dev->enabled || !scope || !config) + if (!scope || !config) return; if (config->speed) diff --git a/src/drivers/i2c/sx9324/Kconfig b/src/drivers/i2c/sx9324/Kconfig new file mode 100644 index 0000000000..77f6967b7e --- /dev/null +++ b/src/drivers/i2c/sx9324/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_SX9324 + bool + default n + depends on HAVE_ACPI_TABLES + help + Board has a Semtech SX9324 proximity sensor. diff --git a/src/drivers/i2c/sx9324/Makefile.inc b/src/drivers/i2c/sx9324/Makefile.inc new file mode 100644 index 0000000000..8811c996b0 --- /dev/null +++ b/src/drivers/i2c/sx9324/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_SX9324) += sx9324.c diff --git a/src/drivers/i2c/sx9324/chip.h b/src/drivers/i2c/sx9324/chip.h new file mode 100644 index 0000000000..9c9dd3cf35 --- /dev/null +++ b/src/drivers/i2c/sx9324/chip.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_I2C_SX9324_CHIP_H__ +#define __DRIVERS_I2C_SX9324_CHIP_H__ + +#include +#include + +#define REGISTER(NAME) uint8_t NAME + +struct drivers_i2c_sx9324_config { + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; +#include "registers.h" +}; + +#undef REGISTER + +#endif /* __DRIVERS_I2C_SX9324_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h new file mode 100644 index 0000000000..7d00261787 --- /dev/null +++ b/src/drivers/i2c/sx9324/registers.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef REGISTER +#error "define REGISTER(NAME) before including this file" +#endif + +REGISTER(reg_adv_ctrl0); +REGISTER(reg_adv_ctrl1); +REGISTER(reg_adv_ctrl2); +REGISTER(reg_adv_ctrl3); +REGISTER(reg_adv_ctrl4); +REGISTER(reg_adv_ctrl5); +REGISTER(reg_adv_ctrl6); +REGISTER(reg_adv_ctrl7); +REGISTER(reg_adv_ctrl8); +REGISTER(reg_adv_ctrl9); +REGISTER(reg_adv_ctrl10); +REGISTER(reg_adv_ctrl11); +REGISTER(reg_adv_ctrl12); +REGISTER(reg_adv_ctrl13); +REGISTER(reg_adv_ctrl14); +REGISTER(reg_adv_ctrl15); +REGISTER(reg_adv_ctrl16); +REGISTER(reg_adv_ctrl17); +REGISTER(reg_adv_ctrl18); +REGISTER(reg_adv_ctrl19); +REGISTER(reg_adv_ctrl20); + +REGISTER(reg_afe_ctrl0); +REGISTER(reg_afe_ctrl1); +REGISTER(reg_afe_ctrl2); +REGISTER(reg_afe_ctrl3); +REGISTER(reg_afe_ctrl4); +REGISTER(reg_afe_ctrl5); +REGISTER(reg_afe_ctrl6); +REGISTER(reg_afe_ctrl7); +REGISTER(reg_afe_ctrl8); +REGISTER(reg_afe_ctrl9); + +REGISTER(reg_afe_ph0); +REGISTER(reg_afe_ph1); +REGISTER(reg_afe_ph2); +REGISTER(reg_afe_ph3); + +REGISTER(reg_gnrl_ctrl0); +REGISTER(reg_gnrl_ctrl1); + +REGISTER(reg_irq_msk); +REGISTER(reg_irq_cfg0); +REGISTER(reg_irq_cfg2); + +REGISTER(reg_prox_ctrl0); +REGISTER(reg_prox_ctrl1); +REGISTER(reg_prox_ctrl2); +REGISTER(reg_prox_ctrl3); +REGISTER(reg_prox_ctrl4); +REGISTER(reg_prox_ctrl5); +REGISTER(reg_prox_ctrl6); +REGISTER(reg_prox_ctrl7); diff --git a/src/drivers/i2c/sx9324/sx9324.c b/src/drivers/i2c/sx9324/sx9324.c new file mode 100644 index 0000000000..2ca9f36345 --- /dev/null +++ b/src/drivers/i2c/sx9324/sx9324.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define I2C_SX9324_ACPI_ID "STH9324" +#define I2C_SX9324_CHIP_NAME "Semtech SX9324" + +#define REGISTER(NAME) acpi_dp_add_integer(dsd, \ + I2C_SX9324_ACPI_ID "," #NAME, \ + config->NAME) + +static void i2c_sx9324_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + + if (!scope || !config) + return; + + if (config->speed) + i2c.speed = config->speed; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", I2C_SX9324_ACPI_ID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); +#include "registers.h" + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +#undef REGISTER + +static const char *i2c_sx9324_acpi_name(const struct device *dev) +{ + static char name[5]; + + snprintf(name, sizeof(name), "SX%02.2X", dev->path.i2c.device); + return name; +} + +static struct device_operations i2c_sx9324_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = i2c_sx9324_acpi_name, + .acpi_fill_ssdt = i2c_sx9324_fill_ssdt, +}; + +static void i2c_sx9324_enable(struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + + if (!config) { + dev->enabled = 0; + return; + } + + dev->ops = &i2c_sx9324_ops; + + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_sx9324_ops = { + CHIP_NAME(I2C_SX9324_CHIP_NAME) + .enable_dev = i2c_sx9324_enable +}; diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index 6a27224031..df622f079d 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -41,8 +41,7 @@ config DRIVER_TPM_I2C_ADDR depends on I2C_TPM config DRIVER_I2C_TPM_ACPI - depends on I2C_TPM - bool "Generate I2C TPM ACPI device" + bool "Generate I2C TPM ACPI device" if I2C_TPM default y if ARCH_X86 && I2C_TPM default n diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 2baec423f1..07791c33a4 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -20,7 +20,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) .resource = scope, }; - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 78ac224eda..4321757705 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -15,7 +15,6 @@ * Version: 2.1.1 */ - #include #include #include @@ -425,11 +424,6 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, uint8_t *buf, size_t len) if (burstcnt > (len-1-count)) burstcnt = len-1-count; -#ifdef CONFIG_TPM_I2C_BURST_LIMITATION - if (burstcnt > CONFIG_TPM_I2C_BURST_LIMITATION) - burstcnt = CONFIG_TPM_I2C_BURST_LIMITATION; -#endif /* CONFIG_TPM_I2C_BURST_LIMITATION */ - if (iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), burstcnt) == 0) count += burstcnt; diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 6068693675..19aa6dae6f 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -365,7 +365,6 @@ int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern) return -1; } - #define LP55231_I2C_BASE_ADDR 0x32 static void ww_ring_init(unsigned int i2c_bus) diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index 880b32ad9c..c3af32036c 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -1,5 +1,5 @@ config DRIVERS_INTEL_DPTF - bool "Support runtime generation of Intel DPTF ACPI tables" + bool depends on HAVE_ACPI_TABLES default n help @@ -7,10 +7,11 @@ config DRIVERS_INTEL_DPTF Intel DPTF Tables at runtime in the SSDT. config DPTF_USE_EISA_HID - bool "If selected, use 'old' 7 character EISA IDs for DPTF _HID" + bool depends on DRIVERS_INTEL_DPTF default n help - When selected, all DPTF devices will use the "old" style of - _HIDs, which are 7-character EISA IDs. Otherwise, it will use - the "new" style, which are regular 8-character _HIDs. + Prior to Tiger Lake, all DPTF devices used 7-character EISA + IDs. If selected, the 7-character _HIDs will be emitted, + otherwise, it will use the "new" style, which are regular + 8-character _HIDs. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index a13f6d0443..0f1cc9c400 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -209,9 +209,11 @@ static void write_options(const struct drivers_intel_dptf_config *config) int i; /* Fan options */ + dptf_write_scope(DPTF_FAN); dptf_write_fan_options(config->options.fan.fine_grained_control, config->options.fan.step_size, config->options.fan.low_speed_notify); + acpigen_pop_len(); /* Scope */ /* TSR options */ for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 86d1f2f760..b5dd3c3810 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -4,11 +4,12 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) verstage-y += car.c verstage-y += fsp_util.c -verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S +bootblock-y += fsp_report.c romstage-y += car.c romstage-y += fsp_util.c @@ -17,7 +18,6 @@ romstage-y += raminit.c romstage-y += romstage.c romstage-$(CONFIG_MMA) += mma_core.c -ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580aac..e20d5277ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -14,6 +14,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: /* @@ -132,8 +134,8 @@ CAR_init_done: cmp $0, %eax jne halt2 - /* Setup bootloader stack */ - movl %edx, %esp + /* Setup bootblock stack */ + movl $_ecar_stack, %esp /* * ebp: FSP_INFO_HEADER address @@ -145,16 +147,28 @@ CAR_init_done: * mm1: high 32-bits of TSC value */ - /* coreboot assumes stack/heap region will be zero */ + /* + * temp_memory_start/end reside in the .bss section, which gets cleared + * below. Save the FSP return value to the stack before writing those + * variables. + */ + push %ecx + push %edx + + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c deleted file mode 100644 index 4fcf1e3701..0000000000 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - VOID *hob_list_ptr; - hob_list_ptr = get_hob_list(); - const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; - u32 *vbt_hob; - EFI_PEI_GRAPHICS_INFO_HOB *vbt_gop; - vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr); - if (vbt_hob == NULL) { - printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n"); - return -1; - } - printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); - vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - - framebuffer->physical_address = vbt_gop->FrameBufferBase; - framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution; - framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution; - framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine - * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = 16; - framebuffer->red_mask_size = 8; - framebuffer->green_mask_pos = 8; - framebuffer->green_mask_size = 8; - framebuffer->blue_mask_pos = 0; - framebuffer->blue_mask_size = 8; - framebuffer->reserved_mask_pos = 24; - framebuffer->reserved_mask_size = 8; - - return 0; -} diff --git a/src/drivers/intel/fsp1_1/fsp_report.c b/src/drivers/intel/fsp1_1/fsp_report.c new file mode 100644 index 0000000000..884218d7f7 --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fsp_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt DCACHE_RAM_BASE and DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d968..570648c373 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -174,7 +174,6 @@ struct fsp_runtime { uint32_t hob_list; } __packed; - void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list) { struct fsp_runtime *fspr; diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 23f92899e8..cab867a68d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -31,6 +31,7 @@ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_resource_hob(const EFI_GUID *guid); void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); +void report_fsp_output(void); /* Return version of FSP associated with fih. */ static inline uint32_t fsp_version(FSP_INFO_HEADER *fih) @@ -85,7 +86,6 @@ void *get_first_hob(uint16_t type); void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_guid_hob(const EFI_GUID *guid); - asmlinkage void chipset_teardown_car_main(void); #endif /* FSP1_1_UTIL_H */ diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index feec434cdf..bcaf15715f 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -13,8 +13,8 @@ const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index cd4a1e665e..eb226dbb65 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -116,6 +117,28 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) gfx_set_init_done(1); #endif + if (CONFIG(RUN_FSP_GOP)) { + const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; + u32 *vbt_hob; + + void *hob_list_ptr = get_hob_list(); + vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr); + if (vbt_hob == NULL) { + printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n"); + } else { + EFI_PEI_GRAPHICS_INFO_HOB *gop; + + printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); + gop = GET_GUID_HOB_DATA(vbt_hob); + + fb_add_framebuffer_info(gop->FrameBufferBase, + gop->GraphicsMode.HorizontalResolution, + gop->GraphicsMode.VerticalResolution, + gop->GraphicsMode.PixelsPerScanLine * 4, + 32); + } + } + display_hob_info(fsp_info_header); soc_after_silicon_init(); } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 46df1c8697..5129dc696b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -23,7 +23,7 @@ static void raminit_common(struct romstage_params *params) { bool s3wake; - struct region_device rdev; + size_t mrc_size; post_code(0x32); @@ -41,23 +41,24 @@ static void raminit_common(struct romstage_params *params) params->saved_data_size = 0; params->saved_data = NULL; if (!params->disable_saved_data) { - if (vboot_recovery_mode_enabled()) { - /* Recovery mode does not use MRC cache */ - printk(BIOS_DEBUG, - "Recovery mode: not using MRC cache.\n"); - } else if (CONFIG(CACHE_MRC_SETTINGS) - && (!mrc_cache_get_current(MRC_TRAINING_DATA, - params->fsp_version, - &rdev))) { + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + params->saved_data = NULL; + if (CONFIG(CACHE_MRC_SETTINGS)) + params->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + params->fsp_version, + &mrc_size); + if (params->saved_data) { /* MRC cache found */ - params->saved_data_size = region_device_sz(&rdev); - params->saved_data = rdev_mmap_full(&rdev); - /* Assume boot device is memory mapped. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + params->saved_data_size = mrc_size; + } else if (s3wake) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); + "No MRC cache " + "found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); /* FIXME: A "system" reset is likely enough: */ full_reset(); @@ -283,13 +284,6 @@ __weak void mainboard_add_dimm_info( { } -/* Get the memory configuration data */ -__weak int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev) -{ - return -1; -} - /* Save the memory configuration data */ __weak int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3caa04ac25..96ae282522 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -41,6 +41,7 @@ config HAVE_INTEL_FSP_REPO config FSP_USE_REPO bool "Use binaries of the Intel FSP repository on GitHub" depends on HAVE_INTEL_FSP_REPO + select FSP_FULL_FD default y help Select this option to use the default FSP headers and binaries @@ -55,13 +56,6 @@ config FSP_HEADER_PATH help Include directory with the FSP ABI header files. -config FSP_FD_PATH - string - depends on FSP_USE_REPO - help - Path to the FSP FD file that contains the individual FSP-T, FSP-M - and FSP-S binaries. - config ADD_FSP_BINARIES bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO default y if FSP_USE_REPO @@ -81,31 +75,45 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_FULL_FD + bool "Use a combined FSP FD file" if !FSP_USE_REPO + depends on ADD_FSP_BINARIES + help + Use a combined FSP FD file instead of specifying individual, already split + binaries and split the file at build-time. + +config FSP_FD_PATH + string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO + help + Path to the FSP FD file that contains the individual FSP-T, FSP-M + and FSP-S binaries. The file gets split at build-time. + config FSP_T_FILE - string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES depends on FSP_CAR - default "\$(obj)/Fsp_T.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-T binary for this platform. config FSP_M_FILE - string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES - default "\$(obj)/Fsp_M.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE - string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES - default "\$(obj)/Fsp_S.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-S binary for this platform. config FSP_CAR bool default n + select NO_CBFS_MCACHE help Use FSP APIs to initialize & Tear Down the Cache-As-Ram @@ -132,29 +140,14 @@ config FSP_USES_CB_STACK config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK help - The amount of anticipated heap usage in CAR by FSP to setup HOB. - This configuration is applicable for FSP specification using shared - stack with coreboot/bootloader. - Sync this value with Platform FSP integration guide recommendation. - -config FSP2_0_USES_TPM_MRC_HASH - bool - depends on TPM1 || TPM2 - depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK - default y if HAS_RECOVERY_MRC_CACHE - default n - select VBOOT_HAS_REC_HASH_SPACE - help - Store hash of trained recovery MRC cache in NVRAM space in TPM. - Use the hash to validate recovery MRC cache before using it. - This hash needs to be updated every time recovery mode training - is recomputed, or if the hash does not match recovery MRC cache. - Selecting this option requires that TPM already be setup by this - point in time. Thus it is only compatible when the option - VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and - TPM setup to occur prior to memory initialization. + The amount of memory coreboot reserves for the FSP to use. In the + case of FSP 2.1 and newer that share the stack with coreboot instead + of having its own stack, this is the amount of anticipated heap usage + in CAR by FSP to setup HOB and needs to be the recommended value from + the Platform FSP integration guide. In the case of the FSP having its + own stack that will be placed in DRAM and not in CAR, this is the + amount of memory the FSP needs for its stack and heap. config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS bool @@ -211,6 +204,58 @@ config FSP_M_ADDR help The address FSP-M will be relocated to during build time +config FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_4 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET + hex + depends on SOC_INTEL_COMMON_FSP_RESET + default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 + default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + default 0xffffffff + help + If global reset is supported by SoC then select the correct status value for global + reset type from SoC Kconfig based on available Kconfig options + FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported. + +config SOC_INTEL_COMMON_FSP_RESET + bool + help + Common code block to handle platform reset request raised by FSP. The FSP + will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that + a reset is required. + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index e954a462a1..25e284679b 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +bootblock-$(CONFIG_FSP_CAR) += fspt_report.c + romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c @@ -14,6 +16,7 @@ romstage-$(CONFIG_MMA) += mma_core.c romstage-y += cbmem.c ramstage-y += debug.c +ramstage-$(CONFIG_USE_INTEL_FSP_MP_INIT) += fsp_mpinit.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c @@ -69,8 +72,8 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif -ifeq ($(CONFIG_FSP_USE_REPO),y) -$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) +ifeq ($(CONFIG_FSP_FULL_FD),y) +$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462b40..5388b8912a 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,7 +6,14 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; + uint8_t *tolum_base; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum); + + /* + * The TOLUM range may have other memory regions (such as APEI + * BERT region on top of CBMEM (IMD root and IMD small) region. + */ + return tolum_base + cbmem_overhead_size(); } diff --git a/src/drivers/intel/fsp2_0/fsp_mpinit.c b/src/drivers/intel/fsp2_0/fsp_mpinit.c new file mode 100644 index 0000000000..cda9269cb8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/fsp_mpinit.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * As per FSP integration guide: + * If bootloader needs to take control of APs back, a full AP re-initialization is + * required after FSP-S is completed and control has been transferred back to bootloader + */ +void do_mpinit_after_fsp(void) +{ + init_cpus(); +} diff --git a/src/drivers/intel/fsp2_0/fspt_report.c b/src/drivers/intel/fsp2_0/fspt_report.c new file mode 100644 index 0000000000..7fa3205e3d --- /dev/null +++ b/src/drivers/intel/fsp2_0/fspt_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fspt_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index f6686c4f57..ddf8f0b857 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -2,9 +2,11 @@ #include #include +#include #include #include #include +#include enum pixel_format { pixel_rgbx_8bpc = 0, @@ -46,75 +48,54 @@ static const struct fsp_framebuffer { [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) + +void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar) { size_t size; const struct hob_graphics_info *ginfo; const struct fsp_framebuffer *fbinfo; + /* + * Pci enumeration happens after silicon init. + * After enumeration graphic framebuffer base may be relocated. + */ + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR invalid\n"); + return; + } + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); if (!ginfo) { printk(BIOS_ALERT, "Graphics hand-off block not found\n"); - return CB_ERR; + return; } if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", ginfo->pixel_format); - return CB_ERR; + return; } fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; - framebuffer->physical_address = ginfo->framebuffer_base; - framebuffer->x_resolution = ginfo->horizontal_resolution; - framebuffer->y_resolution = ginfo->vertical_resolution; - framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = fbinfo->red.pos; - framebuffer->red_mask_size = fbinfo->red.size; - framebuffer->green_mask_pos = fbinfo->green.pos; - framebuffer->green_mask_size = fbinfo->green.size; - framebuffer->blue_mask_pos = fbinfo->blue.pos; - framebuffer->blue_mask_size = fbinfo->blue.size; - framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; - framebuffer->reserved_mask_size = fbinfo->rsvd.pos; + const struct lb_framebuffer fb = { + .physical_address = framebuffer_bar, + .x_resolution = ginfo->horizontal_resolution, + .y_resolution = ginfo->vertical_resolution, + .bytes_per_line = ginfo->pixels_per_scanline * 4, + .bits_per_pixel = fbinfo->rsvd.size + fbinfo->red.size + + fbinfo->green.size + fbinfo->blue.size, + .red_mask_pos = fbinfo->red.pos, + .red_mask_size = fbinfo->red.size, + .green_mask_pos = fbinfo->green.pos, + .green_mask_size = fbinfo->green.size, + .blue_mask_pos = fbinfo->blue.pos, + .blue_mask_size = fbinfo->blue.size, + .reserved_mask_pos = fbinfo->rsvd.pos, + .reserved_mask_size = fbinfo->rsvd.size, + .orientation = LB_FB_ORIENTATION_NORMAL, + }; - return CB_SUCCESS; -} - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - enum cb_err ret; - uintptr_t framebuffer_bar; - - /* Pci enumeration happens after silicon init. - * After enumeration graphic framebuffer base may be relocated. - * Get framebuffer base from soc. - */ - framebuffer_bar = fsp_soc_get_igd_bar(); - - if (!framebuffer_bar) { - printk(BIOS_ALERT, "Framebuffer BAR invalid\n"); - return -1; - } - - ret = fsp_fill_lb_framebuffer(framebuffer); - if (ret != CB_SUCCESS) { - printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); - return -1; - } - - /* Resource allocator can move the BAR around after FSP configures it */ - framebuffer->physical_address = framebuffer_bar; - printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", - framebuffer->physical_address); - - return 0; -} - -__weak uintptr_t fsp_soc_get_igd_bar(void) -{ - return 0; + fb_add_framebuffer_info_ex(&fb); } diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index fdc92a7cbf..60ab7cb3ec 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -207,7 +207,7 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) return NULL; } -static void display_fsp_version_info_hob(const void *hob, size_t size) +static void display_fsp_version_info_hob(const void *hob) { #if CONFIG(DISPLAY_FSP_VERSION_INFO) const FIRMWARE_VERSION_INFO *fvi; @@ -218,8 +218,7 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) fvi = (void *)&fvih[1]; str_ptr = (char *)((uintptr_t)fvi + - (fvih->Count * sizeof (FIRMWARE_VERSION_INFO))); - size -= sizeof(SMBIOS_STRUCTURE); + (fvih->Count * sizeof(FIRMWARE_VERSION_INFO))); for (index = 0; index < fvih->Count; index++) { cnt = strlen(str_ptr); @@ -279,7 +278,7 @@ void fsp_display_fvi_version_hob(void) if (fsp_guid_compare(hob_uuid, uuid_fv_info)) { size = hob->length - (HOB_HEADER_LEN + 16); - display_fsp_version_info_hob(hob, size); + display_fsp_version_info_hob(hob); } } } diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 57e13b5354..b45b4d8a7c 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -5,15 +5,7 @@ void fsp_print_header_info(const struct fsp_header *hdr) { - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; + union fsp_revision revision; revision.val = hdr->fsp_revision; diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e850d..9bfb0f15a9 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,9 +43,16 @@ void fsp_verify_memory_init_hobs(void) die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } + + if (CONFIG(ACPI_BERT) && + range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) { + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n", + range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE); + die("Space between cbmem_top and APEI BERT!\n"); + } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index d2c556f916..97e2fea34d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -31,7 +31,6 @@ enum fsp_notify_phase { END_OF_FIRMWARE = 0xF0 }; - /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); @@ -74,6 +73,13 @@ const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd); void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); +/* + * As per FSP integration guide: + * If bootloader needs to take control of APs back, a full AP re-initialization is + * required after FSP-S is completed and control has been transferred back to bootloader + */ +void do_mpinit_after_fsp(void); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index ccb66cbeb5..e3d19180f0 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -24,7 +24,7 @@ void fsp_verify_memory_init_hobs(void); void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file - * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + * that is conditionally build with CONFIG(DISPLAY_UPD_DATA). */ void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd); @@ -32,7 +32,7 @@ void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd); /* Callbacks for displaying HOBs - place in a separate file that is - * conditionally build with CONFIG_DISPLAY_HOBS. + * conditionally build with CONFIG(DISPLAY_HOBS). */ const char *soc_get_hob_type_name(const struct hob_header *hob); const char *soc_get_guid_name(const uint8_t *guid); diff --git a/src/drivers/intel/fsp2_0/include/fsp/graphics.h b/src/drivers/intel/fsp2_0/include/fsp/graphics.h new file mode 100644 index 0000000000..2d8138332f --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/graphics.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _FSP2_0_GRAPHICS_H_ +#define _FSP2_0_GRAPHICS_H_ + +#include + +/* + * Report the fsp_graphics_info_guid HOB to framebuffer info. + * + * Must be called after PCI enumeration to make sure that the BAR + * doesn't change any more. + */ +void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar); + +#endif /* _FSP2_0_GRAPHICS_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h deleted file mode 100644 index e100efbeaa..0000000000 --- a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _FSP2_0_MEMORY_INIT_H_ -#define _FSP2_0_MEMORY_INIT_H_ - -#include - -/* - * Updates mrc cache hash if it differs. - */ -void mrc_cache_update_hash(const uint8_t *data, size_t size); - -/* - * Verifies mrc cache hash which is stored somewhere. - * return 1 verification was successful and 0 for error. - */ -int mrc_cache_verify_hash(const uint8_t *data, size_t size); - -#endif /* _FSP2_0_MEMORY_INIT_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 93e54b15bc..8781bde8d8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -31,7 +31,6 @@ #include #endif - #pragma pack(pop) #endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f154a34a34..7393305f0b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -42,6 +42,16 @@ struct hob_resource { uint64_t length; } __packed; +union fsp_revision { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; +}; + #if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, @@ -78,7 +88,6 @@ const void *fsp_get_hob_list(void); void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); void fsp_find_reserved_memory(struct range_entry *re); @@ -89,6 +98,8 @@ bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]); void fsp_find_bootloader_tolum(struct range_entry *re); void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); +void report_fspt_output(void); +void soc_validate_fsp_version(const struct fsp_header *hdr); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, @@ -111,9 +122,6 @@ struct fsp_load_descriptor { * header object will be validated and filled in on successful load. */ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_header *hdr); -/* Get igd framebuffer bar from SoC */ -uintptr_t fsp_soc_get_igd_bar(void); - /* * Handle FSP reboot request status. Chipset/soc is expected to provide * chipset_handle_reset() that deals with reset type codes specific to given diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index 0d430a19ac..314616b296 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -13,8 +13,8 @@ const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389592..bddd07f33c 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -21,16 +21,11 @@ #include #include #include -#include #include +#include static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); -/* TPM MRC hash functionality depends on vboot starting before memory init. */ -_Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || - CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), - "for TPM MRC hash functionality, vboot must start in bootblock"); - static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -54,9 +49,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - - if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) - mrc_cache_update_hash(mrc_data, mrc_data_size); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -93,45 +85,26 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) { - struct region_device rdev; void *data; + size_t mrc_size; arch_upd->NvsBufferPtr = NULL; if (!CONFIG(CACHE_MRC_SETTINGS)) return; - /* - * In recovery mode, force retraining: - * 1. Recovery cache is not supported, or - * 2. Memory retrain switch is set. - */ - if (vboot_recovery_mode_enabled()) { - if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) - return; - if (get_recovery_mode_retrain_switch()) - return; - } - - if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0) - return; - /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - data = rdev_mmap_full(&rdev); + data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, fsp_version, + &mrc_size); if (data == NULL) return; - if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && - !mrc_cache_verify_hash(data, region_device_sz(&rdev))) - return; - /* MRC cache found */ arch_upd->NvsBufferPtr = data; - printk(BIOS_SPEW, "MRC cache found, size %zx\n", - region_device_sz(&rdev)); + printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size); } static enum cb_err check_region_overlap(const struct memranges *ranges, @@ -184,8 +157,9 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, * top and does not reinitialize stack pointer. The parameters passed * as StackBase and StackSize are actually for temporary RAM and HOBs * and are not related to FSP stack at all. + * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. */ - if (CONFIG(FSP_USES_CB_STACK)) { + if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { arch_upd->StackBase = temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { @@ -278,6 +252,21 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + /* + * If ACPI APEI BERT region size is defined, reserve memory for it. + * +------------------------+ range_entry_top(tolum) + * | Other reserved regions | + * | APEI BERT region | + * +------------------------+ cbmem_top() + * | CBMEM IMD ROOT | + * | CBMEM IMD SMALL | + * +------------------------+ range_entry_base(tolum), TOLUM + * | CBMEM FSP MEMORY | + * | Other CBMEM regions... | + */ + if (CONFIG(ACPI_BERT)) + arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; + /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) @@ -308,7 +297,13 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); - status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); + if (ENV_X86_64) + status = protected_mode_call_2arg(fsp_raminit, + (uintptr_t)&fspm_upd, + (uintptr_t)fsp_get_hob_list_ptr()); + else + status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); + post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf1281e..8a51c0bad7 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -5,6 +5,7 @@ #include #include #include +#include static void fsp_notify(enum fsp_notify_phase phase) { @@ -30,7 +31,10 @@ static void fsp_notify(enum fsp_notify_phase phase) post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE); } - ret = fspnotify(¬ify_params); + if (ENV_X86_64) + ret = protected_mode_call_1arg(fspnotify, (uintptr_t)¬ify_params); + else + ret = fspnotify(¬ify_params); if (phase == AFTER_PCI_ENUM) { timestamp_add_now(TS_FSP_AFTER_ENUMERATE); @@ -57,7 +61,7 @@ static void fsp_notify(enum fsp_notify_phase phase) static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 5b964d51fb..03184e16ca 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -10,6 +10,7 @@ #include #define BSP_CPU_SLOT 0 +#define SINGLE_CHIP_PACKAGE 0 static efi_return_status_t mp_get_number_of_processors(const efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, @@ -31,6 +32,8 @@ static efi_return_status_t mp_get_processor_info(const efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { + unsigned int num_virt_cores, num_phys_cores; + if (cpu_index() < 0) return FSP_DEVICE_ERROR; @@ -48,7 +51,14 @@ static efi_return_status_t mp_get_processor_info(const if (processor_number == BSP_CPU_SLOT) processor_info_buffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; - /* TODO: Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + /* Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + cpu_read_topology(&num_phys_cores, &num_virt_cores); + + /* FSP will add one to the value in this Package field */ + processor_info_buffer->Location.Package = SINGLE_CHIP_PACKAGE; + processor_info_buffer->Location.Core = num_phys_cores; + processor_info_buffer->Location.Thread = num_virt_cores; + return FSP_SUCCESS; } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 663b1d7cfd..a4ffbda4cc 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -13,6 +13,7 @@ #include #include #include +#include struct fsp_header fsps_hdr; @@ -117,7 +118,14 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_SILICON_INIT_START); post_code(POST_FSP_SILICON_INIT); - status = silicon_init(upd); + + if (ENV_X86_64) + status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); + else + status = silicon_init(upd); + + printk(BIOS_ERR, "FSPS returned %x\n", status); + timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); @@ -127,6 +135,10 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); + /* Reinitialize CPUs if FSP-S has done MP Init */ + if (CONFIG(USE_INTEL_FSP_MP_INIT)) + do_mpinit_after_fsp(); + if (!CONFIG(PLATFORM_USES_FSP2_2)) return; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index cfa83d7e0e..866db586e2 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include @@ -86,6 +85,9 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, return CB_ERR; } + if (ENV_ROMSTAGE) + soc_validate_fsp_version(hdr); + return CB_SUCCESS; } @@ -214,15 +216,7 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea void fsp_get_version(char *buf) { struct fsp_header *hdr = &fsps_hdr; - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; + union fsp_revision revision; revision.val = hdr->fsp_revision; snprintf(buf, FSP_VER_LEN, "%u.%u-%u.%u.%u.%u", (hdr->spec_version >> 4), @@ -244,3 +238,7 @@ void lb_string_platform_blob_version(struct lb_header *header) rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); memcpy(rec->string, fsp_version, len+1); } + +__weak void soc_validate_fsp_version(const struct fsp_header *hdr) +{ +} diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 635de1c87a..b001fd3e4d 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -59,6 +59,10 @@ config INTEL_GMA_SWSMISCI config INTEL_GMA_LIBGFXINIT_EDID bool +config VBT_DATA_SIZE_KB + int + default 8 + config GFX_GMA_ANALOG_I2C_HDMI_B bool @@ -68,6 +72,14 @@ config GFX_GMA_ANALOG_I2C_HDMI_C config GFX_GMA_ANALOG_I2C_HDMI_D bool +config GFX_GMA_IGNORE_PRESENCE_STRAPS + def_bool n + depends on MAINBOARD_HAS_LIBGFXINIT + help + libgfxinit uses the GPU presence straps to determine if a display port + is present/enabled. Select this option if a board doesn't correctly implement + these straps, causing libgfxinit to fail to detect an attached panel. + config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ @@ -75,7 +87,7 @@ config GFX_GMA || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ - || SOC_INTEL_WHISKEYLAKE + || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -102,11 +114,21 @@ config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ - SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE || \ + SOC_INTEL_COMETLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X +config GFX_GMA_PCH + string + default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE + default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE + default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "No_PCH" + config GFX_GMA_PANEL_1_PORT string default "eDP" if GFX_GMA_PANEL_1_ON_EDP @@ -127,11 +149,4 @@ config GFX_GMA_ANALOG_I2C_PORT digital displays. In that case, the EDID for a VGA display has to be read over the I2C interface of the coupled digital port. -config GFX_GMA_IGNORE_PRESENCE_STRAPS - def_bool n - help - libgfxinit uses the GPU presence straps to determine if a display port - is present/enabled. Select this option if a board doesn't correctly implement - these straps, causing libgfxinit to fail to detect an attached panel. - endif diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/drivers/intel/gma/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/drivers/intel/gma/acpi/gfx.asl diff --git a/src/drivers/intel/gma/acpi/gma.asl b/src/drivers/intel/gma/acpi/gma.asl index c4ee2db826..2282110fb9 100644 --- a/src/drivers/intel/gma/acpi/gma.asl +++ b/src/drivers/intel/gma/acpi/gma.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) Field (GFXC, DWordAcc, NoLock, Preserve) { @@ -20,6 +18,9 @@ Device (GFX0) { Offset (CONFIG_INTEL_GMA_BCLV_OFFSET), BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH, + } + Field (GFRG, DWordAcc, NoLock, Preserve) + { Offset (CONFIG_INTEL_GMA_BCLM_OFFSET), BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH } diff --git a/src/drivers/intel/gma/drm_dp_helper.h b/src/drivers/intel/gma/drm_dp_helper.h deleted file mode 100644 index f2e06c33f3..0000000000 --- a/src/drivers/intel/gma/drm_dp_helper.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -/* From the VESA DisplayPort spec */ - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) - -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) - -/* AUX CH addresses */ -/* DPCD */ -#define DP_DPCD_REV 0x000 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 - -/* link configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_PSR_EN_CFG 0x170 -# define DP_PSR_ENABLE (1 << 0) -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) -# define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_EDP_CONFIGURATION_SET 0x10a - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads index 84c4a5b6db..4998d3312e 100644 --- a/src/drivers/intel/gma/gma-gfx_init.ads +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -13,28 +13,14 @@ is ---------------------------------------------------------------------------- - type lb_framebuffer is record - tag : word32; - size : word32; + function c_fb_add_framebuffer_info + (fb_addr: Interfaces.C.size_t; + x_resolution : word32; + y_resolution : word32; + bytes_per_line : word32; + bits_per_pixel : word8) + return Interfaces.C.size_t; - physical_address : word64; - x_resolution : word32; - y_resolution : word32; - bytes_per_line : word32; - bits_per_pixel : word8; - red_mask_pos : word8; - red_mask_size : word8; - green_mask_pos : word8; - green_mask_size : word8; - blue_mask_pos : word8; - blue_mask_size : word8; - reserved_mask_pos : word8; - reserved_mask_size : word8; - end record; - - function fill_lb_framebuffer - (framebuffer : in out lb_framebuffer) - return Interfaces.C.int; - pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer"); + pragma import (C, c_fb_add_framebuffer_info, "fb_add_framebuffer_info"); end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h index d7a336c537..a39198c006 100644 --- a/src/drivers/intel/gma/gma.h +++ b/src/drivers/intel/gma/gma.h @@ -11,11 +11,31 @@ struct i915_gpu_controller_info { u32 did[5]; }; +/* Devicetree panel configuration */ +struct i915_gpu_panel_config { + unsigned int up_delay_ms; + unsigned int down_delay_ms; + unsigned int cycle_delay_ms; + unsigned int backlight_on_delay_ms; + unsigned int backlight_off_delay_ms; + unsigned int backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } backlight_polarity; +}; + #define GMA_STATIC_DISPLAYS(ssc) { \ .use_spread_spectrum_clock = (ssc), \ .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ } +/* Shortcut for one internal panel at port A */ +#define GMA_DEFAULT_PANEL(ssc) { \ + .use_spread_spectrum_clock = (ssc), \ + .ndid = 1, .did = { 0x0400 } \ +} + void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); #endif diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 92d3a16963..b213030b2b 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -18,56 +18,29 @@ with GMA.Mainboard; package body GMA.GFX_Init is - fb_valid : boolean := false; - - linear_fb_addr : word64; - - fb : Framebuffer_Type; - - function fill_lb_framebuffer - (framebuffer : in out lb_framebuffer) - return Interfaces.C.int - is - use type word32; - use type Interfaces.C.int; - begin - if fb_valid then - framebuffer := - (tag => 0, - size => 0, - physical_address => linear_fb_addr, - x_resolution => word32 (fb.Width), - y_resolution => word32 (fb.Height), - bytes_per_line => 4 * word32 (fb.Stride), - bits_per_pixel => 32, - reserved_mask_pos => 24, - reserved_mask_size => 8, - red_mask_pos => 16, - red_mask_size => 8, - green_mask_pos => 8, - green_mask_size => 8, - blue_mask_pos => 0, - blue_mask_size => 8); - return 0; - else - return -1; - end if; - end fill_lb_framebuffer; - ---------------------------------------------------------------------------- procedure gfxinit (lightup_ok : out Interfaces.C.int) is use type pos32; use type word64; + use type word32; + use type Interfaces.C.size_t; ports : Port_List; configs : Pipe_Configs; success : boolean; + linear_fb_addr : word64; + + fb : Framebuffer_Type; + min_h : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_WIDTH; min_v : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_HEIGHT; + + fbinfo : Interfaces.C.size_t; + begin lightup_ok := 0; @@ -108,9 +81,17 @@ is HW.GFX.GMA.Update_Outputs (configs); HW.GFX.GMA.Map_Linear_FB (linear_fb_addr, fb); - fb_valid := linear_fb_addr /= 0; - - lightup_ok := (if fb_valid then 1 else 0); + if linear_fb_addr /= 0 then + fbinfo := c_fb_add_framebuffer_info + (fb_addr => Interfaces.C.size_t (linear_fb_addr), + x_resolution => word32 (fb.Width), + y_resolution => word32 (fb.Height), + bytes_per_line => word32 (fb.Stride) * 4, + bits_per_pixel => 32); + if fbinfo /= 0 then + lightup_ok := 1; + end if; + end if; end if; end if; end if; diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 670ea6efa1..8e9fc904f2 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -4,7 +4,6 @@ #define INTEL_I915_H 1 #include -#include #include #include diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index b4face49fb..f65c53290d 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -27,7 +27,6 @@ #define IVB_GMCH_GMS_SHIFT 4 #define IVB_GMCH_GMS_MASK 0xf - /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ @@ -296,7 +295,6 @@ #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ - /* * Reset registers */ @@ -551,7 +549,6 @@ #define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 -#define ESR 0x020b8 #define GM45_ERROR_PAGE_TABLE (1<<5) #define GM45_ERROR_MEM_PRIV (1<<4) #define I915_ERROR_PAGE_TABLE (1<<4) @@ -791,7 +788,6 @@ #define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21) - /* * Framebuffer compression for Sandybridge * @@ -801,7 +797,6 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104 - /* * GPIO regs */ @@ -1213,7 +1208,6 @@ HSW_CXT_RENDER_SIZE(ctx_reg) + \ GEN7_CXT_VFSTATE_SIZE(ctx_reg)) - /* * Overlay regs */ @@ -1254,7 +1248,6 @@ #define _BCLRPAT_B 0x61020 #define _VSYNCSHIFT_B 0x61028 - #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) @@ -1311,7 +1304,6 @@ #define ADPA_DPMS_STANDBY (2<<10) #define ADPA_DPMS_OFF (3<<10) - /* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 #define HDMIB_HOTPLUG_INT_EN (1 << 29) @@ -1673,6 +1665,33 @@ #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254 +#define UTIL_PIN_CTL 0x48400 +#define UTIL_PIN_ENABLE (1 << 31) + +#define UTIL_PIN_PIPE(x) ((x) << 29) +#define UTIL_PIN_PIPE_MASK (3 << 29) +#define UTIL_PIN_MODE_PWM (1 << 24) +#define UTIL_PIN_MODE_MASK (0xf << 24) +#define UTIL_PIN_POLARITY (1 << 22) + +/* BXT backlight register definition. */ +#define _BXT_BLC_PWM_CTL1 0xC8250 +#define BXT_BLC_PWM_ENABLE (1 << 31) +#define BXT_BLC_PWM_POLARITY (1 << 29) +#define _BXT_BLC_PWM_FREQ1 0xC8254 +#define _BXT_BLC_PWM_DUTY1 0xC8258 + +#define _BXT_BLC_PWM_CTL2 0xC8350 +#define _BXT_BLC_PWM_FREQ2 0xC8354 +#define _BXT_BLC_PWM_DUTY2 0xC8358 + +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \ + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \ + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \ + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) + /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ @@ -2781,7 +2800,6 @@ #define _PIPEB_FRMCOUNT_GM45 0x71040 #define _PIPEB_FLIPCOUNT_GM45 0x71044 - /* Display B control */ #define _DSPBCNTR 0x71180 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) @@ -2984,7 +3002,6 @@ #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff - #define _PIPEA_DATA_M1 0x60030 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ #define TU_SIZE_MASK 0x7e000000 @@ -3538,7 +3555,6 @@ #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) #define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) - #define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index ab49604bf1..a7f3fdc18a 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -98,7 +98,6 @@ int intel_vga_int15_handler(void) return res; } - void install_intel_vga_int15_handler(int active_lfp_, int pfit_, int display_, int panel_type_) { active_lfp = active_lfp_; diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index 559ec22ab1..cddd4ac6b8 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -27,7 +27,6 @@ enum { GMA_INT15_ACTIVE_LFP_EDP = 0x03, }; - #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type); diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 3df72c71fb..558dae6aba 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -396,7 +396,6 @@ struct bdb_sdvo_lvds_options { u8 panel_misc_bits_4; } __packed; - #define BDB_DRIVER_FEATURE_NO_LVDS 0 #define BDB_DRIVER_FEATURE_INT_LVDS 1 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 7682af199b..4e9f94d013 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -19,7 +19,7 @@ const char *mainboard_vbt_filename(void) return "vbt.bin"; } -static char vbt_data[8 * KiB]; +static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB]; static size_t vbt_data_sz; void *locate_vbt(size_t *vbt_size) @@ -34,8 +34,7 @@ void *locate_vbt(size_t *vbt_size) const char *filename = mainboard_vbt_filename(); - size_t file_size = cbfs_boot_load_file(filename, - vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW); + size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data)); if (file_size == 0) return NULL; diff --git a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb index 04ef30a465..d27385247e 100644 --- a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb @@ -13,17 +13,6 @@ with GMA.Mainboard; package body GMA.GFX_Init is - function fill_lb_framebuffer - (framebuffer : in out lb_framebuffer) - return Interfaces.C.int - is - use type Interfaces.C.int; - begin - return -1; - end fill_lb_framebuffer; - - ---------------------------------------------------------------------------- - procedure gfxinit (lightup_ok : out Interfaces.C.int) is ports : Port_List; diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index f1ad265b9f..b42c52d02c 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -15,31 +15,31 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf, { u8 *ptr; - memset(head, 0, sizeof (*head)); + memset(head, 0, sizeof(*head)); - memset(head->signature, ' ', sizeof (head->signature)); + memset(head->signature, ' ', sizeof(head->signature)); memcpy(head->signature, idstr, - MIN(strlen(idstr), sizeof (head->signature))); + MIN(strlen(idstr), sizeof(head->signature))); head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); + head->header_size = sizeof(*head); + head->bdb_offset = sizeof(*head); struct bdb_header *const bdb_head = (struct bdb_header *)(head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); + memset(bdb_head, 0, sizeof(*bdb_head)); memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); + bdb_head->header_size = sizeof(*bdb_head); ptr = (u8 *)(bdb_head + 1); ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (struct bdb_general_features); - ptr[2] = sizeof (struct bdb_general_features) >> 8; + ptr[1] = sizeof(struct bdb_general_features); + ptr[2] = sizeof(struct bdb_general_features) >> 8; ptr += 3; struct bdb_general_features *const genfeat = (struct bdb_general_features *)ptr; - memset(genfeat, 0, sizeof (*genfeat)); + memset(genfeat, 0, sizeof(*genfeat)); genfeat->panel_fitting = 3; genfeat->flexaim = 1; genfeat->download_ext_vbt = 1; @@ -50,7 +50,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf, genfeat->int_crt_support = 1; genfeat->dp_ssc_enb = 1; - ptr += sizeof (*genfeat); + ptr += sizeof(*genfeat); bdb_head->bdb_size = ptr - (u8 *)bdb_head; head->vbt_size = ptr - (u8 *)head; diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 852f368e5c..8caa194a9e 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -206,17 +206,17 @@ static void init(struct device *dev) return; } -static void set_resources(struct device *dev) +static void enable_bus_master(struct device *dev) { - pci_dev_set_resources(dev); - dev->command |= PCI_COMMAND_MASTER; + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } static struct device_operations i210_ops = { .read_resources = pci_dev_read_resources, - .set_resources = set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = init, + .final = enable_bus_master, }; static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 }; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index 46e9788905..1cc6a28a0b 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -16,7 +16,6 @@ #define I210_DONE 0x02 /* command done bit */ #define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum */ - /*define some other useful values here */ #define I210_POLL_TIMEOUT_US 300000 /* 300 ms */ /*Define some error states here*/ @@ -28,9 +27,10 @@ #define I210_CHECKSUM_ERROR 0x00000010 #define I210_FLASH_UPDATE_ERROR 0x00000020 +#define MAC_ADDR_LEN 6 + /* We need one function we can call to get a MAC address to use */ /* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(struct device *dev, - uint8_t mac[6]); +extern enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]); #endif /* _INTEL_I210_H_ */ diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index f82f7fc7f6..19cbd82fa5 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -13,7 +13,7 @@ static void ish_fill_ssdt_generator(const struct device *dev) struct device *root = dev->bus->dev; struct acpi_dp *dsd; - if (!dev->enabled || !config || !config->firmware_name) + if (!config || !config->firmware_name) return; acpigen_write_scope(acpi_device_path(root)); diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index f32f744f8f..7dfd6502f5 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -18,6 +18,59 @@ #define CIO2_PCI_DEV 0x14 #define CIO2_PCI_FN 0x3 #define POWER_RESOURCE_NAME "PRIC" +#define GUARD_VARIABLE_FORMAT "RES%1d" +#define ENABLE_METHOD_FORMAT "ENB%1d" +#define DISABLE_METHOD_FORMAT "DSB%1d" +#define UNKNOWN_METHOD_FORMAT "UNK%1d" +#define CLK_ENABLE_METHOD "MCON" +#define CLK_DISABLE_METHOD "MCOF" + +static struct camera_resource_manager res_mgr; + +static void resource_set_action_type(struct resource_config *res_config, + enum action_type action) +{ + if (res_config) + res_config->action = action; +} + +static enum action_type resource_get_action_type(const struct resource_config *res_config) +{ + return res_config ? res_config->action : UNKNOWN_ACTION; +} + +static enum ctrl_type resource_get_ctrl_type(const struct resource_config *res_config) +{ + return res_config ? res_config->type : UNKNOWN_CTRL; +} + +static void resource_set_clk_config(struct resource_config *res_config, + const struct clk_config *clk_conf) +{ + if (res_config) { + res_config->type = IMGCLK; + res_config->clk_conf = clk_conf; + } +} + +static const struct clk_config *resource_clk_config(const struct resource_config *res_config) +{ + return res_config ? res_config->clk_conf : NULL; +} + +static void resource_set_gpio_config(struct resource_config *res_config, + const struct gpio_config *gpio_conf) +{ + if (res_config) { + res_config->type = GPIO; + res_config->gpio_conf = gpio_conf; + } +} + +static const struct gpio_config *resource_gpio_config(const struct resource_config *res_config) +{ + return res_config ? res_config->gpio_conf : NULL; +} /* * This implementation assumes there is only 1 endpoint at each end of every data port. It also @@ -399,7 +452,12 @@ static void camera_fill_sensor(const struct device *dev) static void camera_fill_nvm(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + struct acpi_dp *dsd; + + if (!config->nvm_compat) + return; + + dsd = acpi_dp_new_table("_DSD"); /* It might be possible to default size or width based on type. */ if (!config->disable_nvm_defaults && !config->nvm_pagesize) @@ -420,6 +478,7 @@ static void camera_fill_nvm(const struct device *dev) if (config->nvm_width) acpi_dp_add_integer(dsd, "address-width", config->nvm_width); + acpi_dp_add_string(dsd, "compatible", config->nvm_compat); acpi_dp_write(dsd); } @@ -436,53 +495,271 @@ static void camera_fill_vcm(const struct device *dev) acpi_dp_write(dsd); } -static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, - struct operation_seq *seq) +static int get_resource_index(const struct resource_config *res_config) +{ + enum ctrl_type type = resource_get_ctrl_type(res_config); + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + unsigned int i; + uint8_t res_id; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + res_id = clk_config->clknum; + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + res_id = gpio_config->gpio_num; + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work", type); + return -1; + } + + for (i = 0; i < res_mgr.cnt; i++) + if (res_mgr.resource[i].type == type && res_mgr.resource[i].id == res_id) + return i; + + return -1; +} + +static void add_guarded_method_namestring(struct resource_config *res_config, int res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + enum action_type action = resource_get_action_type(res_config); + + switch (action) { + case ENABLE: + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + break; + case DISABLE: + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + break; + default: + snprintf(method_name, sizeof(method_name), UNKNOWN_METHOD_FORMAT, res_index); + printk(BIOS_ERR, "Unsupported resource action: %x\n", action); + } + + acpigen_emit_namestring(method_name); +} + +static void call_guarded_method(struct resource_config *res_config) +{ + int res_index; + + if (res_config == NULL) + return; + + res_index = get_resource_index(res_config); + + if (res_index != -1) + add_guarded_method_namestring(res_config, res_index); +} + +static void add_clk_op(const struct clk_config *clk_config, enum action_type action) +{ + if (clk_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_ENABLE_METHOD); + acpigen_emit_namestring(CLK_ENABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_write_integer(clk_config->freq); + acpigen_pop_len(); /* CondRefOf */ + break; + case DISABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_DISABLE_METHOD); + acpigen_emit_namestring(CLK_DISABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_pop_len(); /* CondRefOf */ + break; + default: + acpigen_write_debug_string("Unsupported clock action"); + printk(BIOS_ERR, "Unsupported clock action: %x\n" + "OS camera driver will likely not work", action); + } +} + +static void add_gpio_op(const struct gpio_config *gpio_config, enum action_type action) +{ + if (gpio_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_soc_set_tx_gpio(gpio_config->gpio_num); + break; + case DISABLE: + acpigen_soc_clear_tx_gpio(gpio_config->gpio_num); + break; + default: + acpigen_write_debug_string("Unsupported GPIO action"); + printk(BIOS_ERR, "Unsupported GPIO action: %x\n" + "OS camera driver will likely not work\n", action); + } +} + +static void add_power_operation(const struct resource_config *res_config) +{ + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + enum ctrl_type type = resource_get_ctrl_type(res_config); + enum action_type action = resource_get_action_type(res_config); + + if (res_config == NULL) + return; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + add_clk_op(clk_config, action); + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + add_gpio_op(gpio_config, action); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", type); + break; + } +} + +static void write_guard_variable(uint8_t res_index) +{ + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + acpigen_write_name_integer(varname, 0); +} + +static void write_enable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, ENABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* method_name */ +} + +static void write_disable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(varname); + acpigen_write_integer(0x0); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* if */ + + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, DISABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + acpigen_pop_len(); /* method_name */ +} + +static void add_guarded_operations(const struct drivers_intel_mipi_camera_config *config, + const struct operation_seq *seq) { unsigned int i; uint8_t index; - uint8_t gpio_num; + uint8_t res_id; + struct resource_config res_config; + int res_index; - for (i = 0; i < seq->ops_cnt; i++) { + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; switch (seq->ops[i].type) { case IMGCLK: - index = seq->ops[i].index; - if (seq->ops[i].action == ENABLE) { - acpigen_emit_namestring("MCON"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - acpigen_write_byte(config->clk_panel.clks[index].freq); - } else if (seq->ops[i].action == DISABLE) { - acpigen_emit_namestring("MCOF"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - } else { - acpigen_write_debug_string("Unsupported clock action"); - printk(BIOS_ERR, "Unsupported clock action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->clk_panel.clks[index].clknum; + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); break; case GPIO: - index = seq->ops[i].index; - gpio_num = config->gpio_panel.gpio[index].gpio_num; - if (seq->ops[i].action == ENABLE) { - acpigen_soc_set_tx_gpio(gpio_num); - } else if (seq->ops[i].action == DISABLE) { - acpigen_soc_clear_tx_gpio(gpio_num); - } else { - acpigen_write_debug_string("Unsupported GPIO action"); - printk(BIOS_ERR, "Unsupported GPIO action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->gpio_panel.gpio[index].gpio_num; + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); break; default: - printk(BIOS_ERR, "Unsupported power operation: %x\n", seq->ops[i].type); - printk(BIOS_ERR, "OS camera driver will likely not work"); - break; + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; } + res_index = get_resource_index(&res_config); + + if (res_index == -1) { + if (res_mgr.cnt >= MAX_GUARDED_RESOURCES) { + printk(BIOS_ERR, "Unable to add guarded camera resource\n" + "OS camera driver will likely not work\n"); + return; + } + + res_mgr.resource[res_mgr.cnt].id = res_id; + res_mgr.resource[res_mgr.cnt].type = seq->ops[i].type; + + write_guard_variable(res_mgr.cnt); + write_enable_method(&res_config, res_mgr.cnt); + write_disable_method(&res_config, res_mgr.cnt); + + res_mgr.cnt++; + } + } +} + +static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, + struct operation_seq *seq) +{ + struct resource_config res_config; + unsigned int i; + uint8_t index; + + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; + + switch (seq->ops[i].type) { + case IMGCLK: + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); + break; + case GPIO: + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; + } + + resource_set_action_type(&res_config, seq->ops[i].action); + call_guarded_method(&res_config); if (seq->ops[i].delay_ms) acpigen_write_sleep(seq->ops[i].delay_ms); } @@ -490,8 +767,6 @@ static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *con static void write_pci_camera_device(const struct device *dev) { - struct drivers_intel_mipi_camera_config *config = dev->chip_info; - if (dev->path.type != DEVICE_PATH_PCI) { printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); return; @@ -499,8 +774,7 @@ static void write_pci_camera_device(const struct device *dev) acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR_pci_device(dev); - acpigen_write_name_string("_DDN", config->device_type == INTEL_ACPI_CAMERA_CIO2 ? - "Camera and Imaging Subsystem" : "Imaging Unit"); + acpigen_write_name_string("_DDN", "Camera and Imaging Subsystem"); } static void write_i2c_camera_device(const struct device *dev, const char *scope) @@ -513,11 +787,6 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope) .resource = scope, }; - if (dev->path.type != DEVICE_PATH_I2C) { - printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); - return; - } - acpigen_write_device(acpi_device_name(dev)); /* add power resource */ @@ -559,10 +828,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope) if (config->acpi_hid) acpigen_write_name_string("_HID", config->acpi_hid); - else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + else if (config->device_type == INTEL_ACPI_CAMERA_VCM || + config->device_type == INTEL_ACPI_CAMERA_NVM) acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); - else if (config->device_type == INTEL_ACPI_CAMERA_NVM) - acpigen_write_name_string("_HID", "INT3499"); acpigen_write_name_integer("_UID", config->acpi_uid); acpigen_write_name_string("_DDN", config->chip_name); @@ -638,19 +906,47 @@ static void write_camera_device_common(const struct device *dev) static void camera_fill_ssdt(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + const char *scope = NULL; + const struct device *pdev; - if (!dev->enabled || !scope) - return; + if (config->has_power_resource) { + pdev = dev->bus->dev; + if (!pdev || !pdev->enabled) + return; - /* Device */ - acpigen_write_scope(scope); + scope = acpi_device_scope(pdev); + if (!scope) + return; - if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || - config->device_type == INTEL_ACPI_CAMERA_IMGU) - write_pci_camera_device(dev); - else + acpigen_write_scope(scope); + add_guarded_operations(config, &config->on_seq); + add_guarded_operations(config, &config->off_seq); + acpigen_pop_len(); /* Guarded power resource operations scope */ + } + + switch (dev->path.type) { + case DEVICE_PATH_I2C: + scope = acpi_device_scope(dev); + if (!scope) + return; + + acpigen_write_scope(scope); write_i2c_camera_device(dev, scope); + break; + case DEVICE_PATH_GENERIC: + pdev = dev->bus->dev; + scope = acpi_device_scope(pdev); + if (!scope) + return; + + acpigen_write_scope(scope); + write_pci_camera_device(pdev); + break; + default: + printk(BIOS_ERR, "Unsupported device type: %x\n" + "OS camera driver will likely not work\n", dev->path.type); + return; + } write_camera_device_common(dev); @@ -669,7 +965,7 @@ static void camera_fill_ssdt(const struct device *dev) static const char *camera_acpi_name(const struct device *dev) { const char *prefix = NULL; - static char name[5]; + static char name[ACPI_NAME_BUFFER_SIZE]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; if (config->acpi_name) diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index d133f7df86..28f8464ec2 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -13,6 +13,7 @@ #define MAX_CLK_CONFIGS 2 #define MAX_GPIO_CONFIGS 4 #define MAX_PWR_OPS 5 +#define MAX_GUARDED_RESOURCES 10 #define SEQ_OPS_CLK_ENABLE(ind, delay) \ { .type = IMGCLK, .index = (ind), .action = ENABLE, .delay_ms = (delay) } @@ -70,15 +71,36 @@ enum intel_power_action_type { }; enum ctrl_type { - IMGCLK = 1, + UNKNOWN_CTRL, + IMGCLK, GPIO }; enum action_type { - ENABLE = 1, + UNKNOWN_ACTION, + ENABLE, DISABLE }; +struct camera_resource { + uint8_t type; + uint8_t id; +}; + +struct camera_resource_manager { + uint8_t cnt; + struct camera_resource resource[MAX_GUARDED_RESOURCES]; +}; + +struct resource_config { + enum action_type action; + enum ctrl_type type; + union { + const struct clk_config *clk_conf; + const struct gpio_config *gpio_conf; + }; +}; + struct clk_config { /* IMGCLKOUT_x being used for a port */ uint8_t clknum; @@ -219,6 +241,7 @@ struct drivers_intel_mipi_camera_config { uint32_t nvm_pagesize; uint32_t nvm_readonly; uint32_t nvm_width; + const char *nvm_compat; /* Settings specific to vcm */ const char *vcm_compat; diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index 16d113bcb1..9fd85431f3 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -32,9 +32,6 @@ static void conn_fill_ssdt(const struct device *dev) const char *scope; const char *name; - if (!dev->enabled) - return; - /* Reference the existing scope and write CONx device */ scope = acpi_device_scope(dev); name = acpi_device_name(dev); diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index 34ecd86021..c7e84a5339 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -50,7 +50,7 @@ static void intel_soundwire_fill_ssdt(const struct device *dev) struct intel_soundwire_controller *controller; const char *scope = acpi_device_scope(dev); - if (!dev->enabled || !scope) + if (!scope) return; if (soc_fill_soundwire_controller(&controller) < 0 || !controller) diff --git a/src/drivers/intel/soundwire/soundwire.h b/src/drivers/intel/soundwire/soundwire.h index 3e2addfcbf..6ee1fad7c0 100644 --- a/src/drivers/intel/soundwire/soundwire.h +++ b/src/drivers/intel/soundwire/soundwire.h @@ -4,7 +4,7 @@ #define __DRIVERS_INTEL_SOUNDWIRE_H__ #include -#include +#include /** * enum intel_soundwire_quirk - Quirks for controller master links. diff --git a/src/drivers/intel/usb4/retimer/Kconfig b/src/drivers/intel/usb4/retimer/Kconfig new file mode 100644 index 0000000000..eee8fe1bed --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_INTEL_USB4_RETIMER + bool + depends on HAVE_ACPI_TABLES + help + A retimer is a device that retransmits a fresh copy of the signal it + receives, by doing CDR and retransmitting the data (i.e., it is + protocol-aware). If your mainboard has a USB4 retimer (usually + located close to the USB4 ports), then select this driver. diff --git a/src/drivers/intel/usb4/retimer/Makefile.inc b/src/drivers/intel/usb4/retimer/Makefile.inc new file mode 100644 index 0000000000..bca23aa3bf --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_RETIMER) += retimer.c diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h new file mode 100644 index 0000000000..789d824a81 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_RETIMER_H__ +#define __DRIVERS_INTEL_USB4_RETIMER_H__ + +#include + +struct drivers_intel_usb4_retimer_config { + /* GPIO used to control power of retimer device. */ + struct acpi_gpio power_gpio; +}; + +#endif /* __DRIVERS_INTEL_USB4_RETIMER_H__ */ diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c new file mode 100644 index 0000000000..7a693ff531 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* Unique ID for the retimer _DSM. */ +#define INTEL_USB4_RETIMER_DSM_UUID "61788900-C470-42BB-80F0-23A313864593" + +/* + * Arg0: UUID + * Arg1: Revision ID (set to 1) + * Arg2: Function Index + * 0: Query command implemented + * 1: Query force power enable state + * 2: Set force power state + * Arg3: A package containing parameters for the function specified + * by the UUID, revision ID and function index. + */ + +static void usb4_retimer_cb_standard_query(void *arg) +{ + /* + * ToInteger (Arg1, Local2) + * If (Local2 == 1) { + * Return(Buffer() {0x07}) + * } + * Return (Buffer() {0x01}) + */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + + /* Revision 1 supports 2 Functions beyond the standard query */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0x07); + acpigen_pop_len(); /* If */ + + /* Other revisions support no additional functions */ + acpigen_write_return_singleton_buffer(0); +} + +static void usb4_retimer_cb_get_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Read power gpio into Local0 + * Store (\_SB.PCI0.GTXS (power_gpio), Local0) + * Return (Local0) + */ + acpigen_get_tx_gpio(power_gpio); + acpigen_write_return_op(LOCAL0_OP); +} + +static void usb4_retimer_cb_set_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Get argument for on/off from Arg3[0] + * Local0 = DeRefOf (Arg3[0]) + */ + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); + + /* + * If (Local0 == 0) { + * // Turn power off + * \_SB.PCI0.CTXS (power_gpio) + * } + */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + acpigen_disable_tx_gpio(power_gpio); + acpigen_pop_len(); /* If */ + + /* + * Else { + * // Turn power on + * \_SB.PCI0.STXS (power_gpio) + * } + */ + acpigen_write_else(); + acpigen_enable_tx_gpio(power_gpio); + acpigen_pop_len(); + + /* Return (Zero) */ + acpigen_write_return_integer(0); +} + +static void (*usb4_retimer_callbacks[3])(void *) = { + usb4_retimer_cb_standard_query, /* Function 0 */ + usb4_retimer_cb_get_power_state, /* Function 1 */ + usb4_retimer_cb_set_power_state, /* Function 2 */ +}; + +static void usb4_retimer_fill_ssdt(const struct device *dev) +{ + const struct drivers_intel_usb4_retimer_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + + if (!scope || !config) + return; + + if (!config->power_gpio.pin_count) { + printk(BIOS_ERR, "%s: Power GPIO required for %s\n", __func__, dev_path(dev)); + return; + } + + /* Write the _DSM that toggles power with provided GPIO. */ + acpigen_write_scope(scope); + acpigen_write_dsm(INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, + ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->power_gpio); + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static struct device_operations usb4_retimer_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_retimer_fill_ssdt, +}; + +static void usb4_retimer_enable(struct device *dev) +{ + dev->ops = &usb4_retimer_dev_ops; +} + +struct chip_operations drivers_intel_usb4_retimer_ops = { + CHIP_NAME("Intel USB4 Retimer") + .enable_dev = usb4_retimer_enable +}; diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig deleted file mode 100644 index fb60c6fbe1..0000000000 --- a/src/drivers/intel/wifi/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config DRIVERS_INTEL_WIFI - bool "Support Intel PCI-e WiFi adapters" - depends on PCI - default y if PCIEXP_PLUGIN_SUPPORT - select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES - help - When enabled, add identifiers in ACPI and SMBIOS tables to - make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h deleted file mode 100644 index 966573f2f4..0000000000 --- a/src/drivers/intel/wifi/chip.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _INTEL_WIFI_CHIP_H_ -#define _INTEL_WIFI_CHIP_H_ - -struct drivers_intel_wifi_config { - unsigned int wake; /* Wake pin for ACPI _PRW */ -}; - -#endif /* _INTEL_WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c deleted file mode 100644 index 9fcd7ba8af..0000000000 --- a/src/drivers/intel/wifi/wifi.c +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "drivers/wifi/generic_wifi.h" - -#define PMCS_DR 0xcc -#define PME_STS (1 << 15) - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int smbios_write_wifi(struct device *dev, int *handle, - unsigned long *current) -{ - struct smbios_type_intel_wifi { - u8 type; - u8 length; - u16 handle; - u8 str; - u8 eos[2]; - } __packed; - - struct smbios_type_intel_wifi *t = - (struct smbios_type_intel_wifi *)*current; - int len = sizeof(struct smbios_type_intel_wifi); - - memset(t, 0, sizeof(struct smbios_type_intel_wifi)); - t->type = 0x85; - t->length = len - 2; - t->handle = *handle; - /* - * Intel wifi driver expects this string to be in the table 0x85 - * with PCI IDs enumerated below. - */ - t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); - - len = t->length + smbios_string_table_len(t->eos); - *current += len; - *handle += 1; - return len; -} -#endif - -#if CONFIG(HAVE_ACPI_TABLES) -static void intel_wifi_fill_ssdt(const struct device *dev) -{ - struct drivers_intel_wifi_config *config = dev->chip_info; - struct generic_wifi_config generic_config; - - if (config) { - generic_config.wake = config->wake; - /* By default, all intel wifi chips wake from S3 */ - generic_config.maxsleep = 3; - } - generic_wifi_fill_ssdt(dev, config ? &generic_config : NULL); -} -#endif - -static void wifi_pci_dev_init(struct device *dev) -{ - pci_dev_init(dev); - - if (CONFIG(ELOG)) { - uint32_t val; - val = pci_read_config16(dev, PMCS_DR); - if (val & PME_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); - } -} - -struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = wifi_pci_dev_init, -#if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = smbios_write_wifi, -#endif - .ops_pci = &pci_dev_ops_pci, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = generic_wifi_acpi_name, - .acpi_fill_ssdt = intel_wifi_fill_ssdt, -#endif -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_1000_SERIES_WIFI, - PCI_DEVICE_ID_6005_SERIES_WIFI, - PCI_DEVICE_ID_6005_I_SERIES_WIFI, - PCI_DEVICE_ID_1030_SERIES_WIFI, - PCI_DEVICE_ID_6030_I_SERIES_WIFI, - PCI_DEVICE_ID_6030_SERIES_WIFI, - PCI_DEVICE_ID_6150_SERIES_WIFI, - PCI_DEVICE_ID_2030_SERIES_WIFI, - PCI_DEVICE_ID_2000_SERIES_WIFI, - PCI_DEVICE_ID_0135_SERIES_WIFI, - PCI_DEVICE_ID_0105_SERIES_WIFI, - PCI_DEVICE_ID_6035_SERIES_WIFI, - PCI_DEVICE_ID_5300_SERIES_WIFI, - PCI_DEVICE_ID_5100_SERIES_WIFI, - PCI_DEVICE_ID_6000_SERIES_WIFI, - PCI_DEVICE_ID_6000_I_SERIES_WIFI, - PCI_DEVICE_ID_5350_SERIES_WIFI, - PCI_DEVICE_ID_5150_SERIES_WIFI, - /* Wilkins Peak 2 */ - PCI_DEVICE_ID_WP_7260_SERIES_1_WIFI, - PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI, - /* Stone Peak 2 */ - PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI, - PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI, - /* Stone Field Peak */ - PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI, - PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, - /* Windstorm Peak */ - PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, - /* Jefferson Peak */ - PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, - /* Thunder Peak 2 */ - PCI_DEVICE_ID_TP_9260_SERIES_WIFI, - /* Harrison Peak */ - PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, - PCI_DEVICE_ID_HrP_6SERIES_WIFI, - /* Cyclone Peak */ - PCI_DEVICE_ID_CyP_6SERIES_WIFI, - /* Typhoon Peak */ - PCI_DEVICE_ID_TyP_6SERIES_WIFI, - /* Garfiled Peak */ - PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, - PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, - 0 -}; - -static const struct pci_driver pch_intel_wifi __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -static void intel_wifi_enable(struct device *dev) -{ - dev->ops = &device_ops; -} - -struct chip_operations drivers_intel_wifi_ops = { - CHIP_NAME("Intel WiFi") - .enable_dev = intel_wifi_enable -}; diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 44ed17e548..012f67887c 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -33,3 +33,23 @@ config BMC_KCS_BASE help The PNP base address of BMC KCS. It must be equal to the pnp port value defined in devicetree for chip drivers/ipmi. + +config IPMI_KCS_TIMEOUT_MS + int + default 5000 + depends on IPMI_KCS + help + The time unit is millisecond for each IPMI KCS transfer. + IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or + greater is recommended. + +config DRIVERS_IPMI_SUPERMICRO_OEM + bool "Supermicro IPMI OEM BMC support" + depends on IPMI_KCS + default n + help + Tested on X11SSH only. Different BMCs might not support these OEM + commands. + The following features are implemented: + * Communicates the BIOS version to the BMC + * Communicates the BIOS date to the BMC diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 06a3433ae0..e4bcf313eb 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c +ramstage-$(CONFIG_DRIVERS_IPMI_SUPERMICRO_OEM) += supermicro_oem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs_ops_premem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index f561bcd893..fb5d4d921f 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #ifndef _IMPI_CHIP_H_ #define _IPMI_CHIP_H_ +#include + struct drivers_ipmi_config { u8 bmc_i2c_address; u8 have_nv_storage; @@ -11,6 +15,16 @@ struct drivers_ipmi_config { u8 gpe_interrupt; u8 have_apic; u32 apic_interrupt; + /* Device to use for GPIO operations */ + DEVTREE_CONST struct device *gpio_dev; + /* + * Jumper GPIO for enabling / disabling BMC/IPMI + * If present, the jumper overrides the devicetree. + */ + u32 bmc_jumper_gpio; + /* "POST complete" GPIO and polarity */ + u32 post_complete_gpio; + bool post_complete_invert; /* * Wait for BMC to boot. * This can be used if the BMC takes a long time to boot after PoR: diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 1d6b71cee9..dcad8627ce 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include "ipmi_kcs.h" #define IPMI_KCS_STATE(_x) ((_x) >> 6) @@ -35,30 +35,24 @@ static unsigned char ipmi_kcs_status(int port) static int wait_ibf_timeout(int port) { - int timeout = 1000; - do { - if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF)) - return 0; - udelay(100); - } while (timeout--); - printk(BIOS_ERR, "wait_ibf timeout!\n"); - return timeout; + if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, !(ipmi_kcs_status(port) & IPMI_KCS_IBF))) { + printk(BIOS_ERR, "wait_ibf timeout!\n"); + return 1; + } else { + return 0; + } } static int wait_obf_timeout(int port) { - int timeout = 1000; - do { - if ((ipmi_kcs_status(port) & IPMI_KCS_OBF)) - return 0; - udelay(100); - } while (timeout--); - - printk(BIOS_ERR, "wait_obf timeout!\n"); - return timeout; + if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, (ipmi_kcs_status(port) & IPMI_KCS_OBF))) { + printk(BIOS_ERR, "wait_obf timeout!\n"); + return 1; + } else { + return 0; + } } - static int ipmi_kcs_send_data_byte(int port, const unsigned char byte) { unsigned char status; diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 501e5dd8c6..33ddd5f016 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -33,6 +33,8 @@ extern int ipmi_kcs_message(int port, int netfn, int lun, int cmd, * returns CB_SUCCESS on success and CB_ERR if an error occurred. */ enum cb_err ipmi_kcs_premem_init(const u16 port, const u16 device); +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision); + struct ipmi_rsp { uint8_t lun; uint8_t cmd; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3df5..9d1cac8715 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -8,8 +8,11 @@ * end */ +#include +#include #include #include +#include #include #if CONFIG(HAVE_ACPI_TABLES) #include @@ -22,12 +25,18 @@ #include #include #include "ipmi_kcs.h" +#include "ipmi_supermicro_oem.h" #include "chip.h" /* 4 bit encoding */ static u8 ipmi_revision_major = 0x1; static u8 ipmi_revision_minor = 0x0; +static u8 bmc_revision_major = 0x0; +static u8 bmc_revision_minor = 0x0; + +static struct boot_state_callback bscb_post_complete; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -68,24 +77,66 @@ static int ipmi_get_bmc_self_test_result(struct device *dev, struct ipmi_selftes return 0; } +static void bmc_set_post_complete_gpio_callback(void *arg) +{ + struct drivers_ipmi_config *conf = arg; + const struct gpio_operations *gpio_ops; + + if (!conf || !conf->post_complete_gpio) + return; + + gpio_ops = dev_get_gpio_ops(conf->gpio_dev); + if (!gpio_ops) { + printk(BIOS_WARNING, "IPMI: specified gpio device is missing gpio ops!\n"); + return; + } + + /* Set POST Complete pin. The `invert` field controls the polarity. */ + gpio_ops->output(conf->post_complete_gpio, conf->post_complete_invert ^ 1); + + printk(BIOS_DEBUG, "BMC: POST complete gpio set\n"); +} + static void ipmi_kcs_init(struct device *dev) { struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; - struct drivers_ipmi_config *conf = NULL; - struct ipmi_selftest_rsp selftestrsp; + struct drivers_ipmi_config *conf = dev->chip_info; + const struct gpio_operations *gpio_ops; + struct ipmi_selftest_rsp selftestrsp = {0}; uint8_t retry_count; + if (!conf) { + printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n"); + return; + } + + if (conf->bmc_jumper_gpio) { + gpio_ops = dev_get_gpio_ops(conf->gpio_dev); + if (!gpio_ops) { + printk(BIOS_WARNING, "IPMI: gpio device is missing gpio ops!\n"); + } else { + /* Get jumper value and set device state accordingly */ + dev->enabled = gpio_ops->get(conf->bmc_jumper_gpio); + if (!dev->enabled) + printk(BIOS_INFO, "IPMI: Disabled by jumper\n"); + } + } + if (!dev->enabled) return; printk(BIOS_DEBUG, "IPMI: PNP KCS 0x%x\n", dev->path.pnp.port); - if (dev->chip_info) - conf = dev->chip_info; + /* Set up boot state callback for POST_COMPLETE# */ + if (conf->post_complete_gpio) { + bscb_post_complete.callback = bmc_set_post_complete_gpio_callback; + bscb_post_complete.arg = conf; + boot_state_sched_on_entry(&bscb_post_complete, BS_PAYLOAD_BOOT); + } /* Get IPMI version for ACPI and SMBIOS */ - if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { + if (conf->wait_for_bmc && conf->bmc_boot_timeout) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); @@ -144,6 +195,9 @@ static void ipmi_kcs_init(struct device *dev) ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); @@ -158,6 +212,12 @@ static void ipmi_kcs_init(struct device *dev) /* Don't write tables if communication failed */ dev->enabled = 0; } + + if (!dev->enabled) + return; + + if (CONFIG(DRIVERS_IPMI_SUPERMICRO_OEM)) + supermicro_ipmi_oem(dev->path.pnp.port); } #if CONFIG(HAVE_ACPI_TABLES) @@ -167,7 +227,7 @@ static unsigned long ipmi_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) { - struct drivers_ipmi_config *conf = NULL; + struct drivers_ipmi_config *conf = dev->chip_info; struct acpi_spmi *spmi; s8 gpe_interrupt = -1; u32 apic_interrupt = 0; @@ -197,33 +257,32 @@ ipmi_write_acpi_tables(const struct device *dev, unsigned long current, printk(BIOS_DEBUG, "ACPI: * SPMI at %lx\n", current); spmi = (struct acpi_spmi *)current; - if (dev->chip_info) - conf = dev->chip_info; - if (conf) { if (conf->have_gpe) gpe_interrupt = conf->gpe_interrupt; if (conf->have_apic) apic_interrupt = conf->apic_interrupt; + + /* Use command to get UID from ipmi_ssdt */ + acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) | + (ipmi_revision_minor << 4), &addr, + IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt, + conf->uid); + + acpi_add_table(rsdp, spmi); + + current += spmi->header.length; + } else { + printk(BIOS_WARNING, "IPMI: chip_info is missing!\n"); } - /* Use command to get UID from ipmi_ssdt */ - acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) | - (ipmi_revision_minor << 4), &addr, - IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt, - conf->uid); - - acpi_add_table(rsdp, spmi); - - current += spmi->header.length; - return current; } static void ipmi_ssdt(const struct device *dev) { const char *scope = acpi_device_scope(dev); - struct drivers_ipmi_config *conf = NULL; + struct drivers_ipmi_config *conf = dev->chip_info; if (!scope) { printk(BIOS_ERR, "IPMI: Missing ACPI scope for %s\n", @@ -231,8 +290,10 @@ static void ipmi_ssdt(const struct device *dev) return; } - if (dev->chip_info) - conf = dev->chip_info; + if (!conf) { + printk(BIOS_WARNING, "IPMI: chip_info is missing!\n"); + return; + } /* Use command to pass UID to ipmi_write_acpi_tables */ conf->uid = uid_cnt++; @@ -250,11 +311,9 @@ static void ipmi_ssdt(const struct device *dev) acpigen_write_io16(dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING, dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING, 1, 1, 1); - if (conf) { - // FIXME: is that correct? - if (conf->have_apic) - acpigen_write_irq(1 << conf->apic_interrupt); - } + // FIXME: is that correct? + if (conf->have_apic) + acpigen_write_irq(1 << conf->apic_interrupt); acpigen_write_resourcetemplate_footer(); @@ -272,20 +331,29 @@ static void ipmi_ssdt(const struct device *dev) } #endif +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + if (!bmc_revision_major || !bmc_revision_minor) { + printk(BIOS_ERR, "IPMI: BMC revision missing\n"); + *ipmi_bmc_major_revision = 0; + *ipmi_bmc_minor_revision = 0; + } else { + *ipmi_bmc_major_revision = bmc_revision_major; + *ipmi_bmc_minor_revision = bmc_revision_minor; + } +} + #if CONFIG(GENERATE_SMBIOS_TABLES) static int ipmi_smbios_data(struct device *dev, int *handle, unsigned long *current) { - struct drivers_ipmi_config *conf = NULL; + struct drivers_ipmi_config *conf = dev->chip_info; u8 nv_storage = 0xff; u8 i2c_address = 0; u8 register_spacing; int len = 0; - if (dev->chip_info) - conf = dev->chip_info; - if (conf) { if (conf->have_nv_storage) nv_storage = conf->nv_storage_device_address; diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c index d799be1310..e1ae0dc3e5 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops_premem.c +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/drivers/ipmi/ipmi_supermicro_oem.h b/src/drivers/ipmi/ipmi_supermicro_oem.h new file mode 100644 index 0000000000..5babadb13f --- /dev/null +++ b/src/drivers/ipmi/ipmi_supermicro_oem.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IPMI_SUPERMICRO_OEM_H +#define __IPMI_SUPERMICRO_OEM_H + +#include + +void supermicro_ipmi_oem(const uint16_t kcs_port); + +#endif /* __IPMI_SUPERMICRO_OEM_H */ diff --git a/src/drivers/ipmi/ocp/Kconfig b/src/drivers/ipmi/ocp/Kconfig new file mode 100644 index 0000000000..26503efb8d --- /dev/null +++ b/src/drivers/ipmi/ocp/Kconfig @@ -0,0 +1,10 @@ +config IPMI_OCP + bool + default n + help + This implements OCP specific IPMI command + +config IPMI_OCP_MANU_ID + hex + default 0x0 + depends on IPMI_OCP diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc new file mode 100644 index 0000000000..8291f82677 --- /dev/null +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c new file mode 100644 index 0000000000..07628ee1ff --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Place in devicetree.cb: + * + * chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + * end + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipmi_ocp.h" + +static int ipmi_set_processor_information_param1(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param1_req req1 = {0}; + struct ipmi_rsp rsp; + int mfid = CONFIG_IPMI_OCP_MANU_ID; + + memcpy(&req1.data.manufacturer_id, &mfid, 3); + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req1.data.manufacturer_id[2], req1.data.manufacturer_id[1], + req1.data.manufacturer_id[0]); + + req1.data.index = 0; + req1.data.parameter_selector = 1; + + /* Get processor name. */ + fill_processor_name(req1.product_name); + printk(BIOS_DEBUG, "IPMI BMC CPU NAME: %s.\n", req1.product_name); + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req1, + sizeof(req1), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI BMC: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static int ipmi_set_processor_information_param2(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param2_req req2 = {0}; + struct ipmi_rsp rsp; + uint8_t stepping_id; + int mfid = CONFIG_IPMI_OCP_MANU_ID; + unsigned int core_count, thread_count; + struct cpuinfo_x86 c; + + memcpy(&req2.data.manufacturer_id, &mfid, 3); + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req2.data.manufacturer_id[2], req2.data.manufacturer_id[1], + req2.data.manufacturer_id[0]); + + req2.data.index = 0; + req2.data.parameter_selector = 2; + + /* Get core number and thread number. */ + cpu_read_topology(&core_count, &thread_count); + req2.core_number = core_count; + req2.thread_number = thread_count; + printk(BIOS_DEBUG, "IPMI BMC CPU has %u cores, %u threads enabled.\n", + req2.core_number, req2.thread_number); + + /* Get processor frequency. */ + req2.processor_freq = 100 * cpu_get_max_ratio(); + printk(BIOS_DEBUG, "IPMI BMC CPU frequency is %u MHz.\n", + req2.processor_freq); + + /* Get revision. */ + get_fms(&c, cpuid_eax(1)); + stepping_id = c.x86_mask; + printk(BIOS_DEBUG, "IPMI BMC CPU stepping id is %x.\n", stepping_id); + switch (stepping_id) { + /* TBD */ + case 0x0a: + req2.revision[0] = 'A'; + req2.revision[1] = '0'; + break; + default: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + } + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req2, + sizeof(req2), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static void ipmi_set_processor_information(struct device *dev) +{ + if (ipmi_set_processor_information_param1(dev)) + printk(BIOS_ERR, "IPMI BMC set param 1 processor info failed\n"); + + if (ipmi_set_processor_information_param2(dev)) + printk(BIOS_ERR, "IPMI BMC set param 2 processor info failed\n"); +} + +static void ipmi_ocp_init(struct device *dev) +{ + /* Add OCP specific IPMI command */ +} + +static void ipmi_ocp_final(struct device *dev) +{ + /* Add OCP specific IPMI command */ + + /* Send processor information */ + ipmi_set_processor_information(dev); +} + +static void ipmi_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void ipmi_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ops = { + .read_resources = ipmi_read_resources, + .set_resources = ipmi_set_resources, + .init = ipmi_ocp_init, + .final = ipmi_ocp_final, +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", + dev_path(dev)); + else if (dev->path.pnp.port & 1) + printk(BIOS_ERR, "%s: Base address needs to be aligned to 2\n", + dev_path(dev)); + else + dev->ops = &ops; +} + +struct chip_operations drivers_ipmi_ocp_ops = { + CHIP_NAME("IPMI OCP") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h new file mode 100644 index 0000000000..96b0086298 --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __IPMI_OCP_H +#define __IPMI_OCP_H + +#include +#include +#include "drivers/ipmi/ipmi_kcs.h" + +#define IPMI_NETFN_OEM_COMMON 0x36 +#define IPMI_BMC_SET_PROCESSOR_INFORMATION 0x10 +#define IPMI_BMC_GET_PROCESSOR_INFORMATION 0x11 + +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce + +struct ipmi_processor_info_req { + uint8_t manufacturer_id[3]; + uint8_t index; + uint8_t parameter_selector; +} __packed; + +struct ipmi_processor_info_param1_req { + struct ipmi_processor_info_req data; + char product_name[48]; +} __packed; + +struct ipmi_processor_info_param2_req { + struct ipmi_processor_info_req data; + uint8_t core_number; + uint16_t thread_number; + uint16_t processor_freq; + char revision[2]; +} __packed; + +#endif diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c new file mode 100644 index 0000000000..87b7fe243a --- /dev/null +++ b/src/drivers/ipmi/supermicro_oem.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include +#include +#include +#include +#include "ipmi_supermicro_oem.h" + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_LUN0_AC_SET_BIOS_VER 0x100 +#define IPMI_LUN0_AC_SET_BIOS_DATE 0x101 +#define IPMI_LUN0_SET_BIOS_STRING 0xac + +struct ipmi_oem_set_bios_str { + uint16_t ver; + char str[16]; // NULL terminated string +} __packed; + +static void set_coreboot_ver(const uint16_t kcs_port) +{ + const char *coreboot_ver = COREBOOT_VERSION; + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + size_t i; + + /* Only 8 charactars are visible in UI. Cut of on first dash */ + for (i = 0; i < 15; i++) { + if (coreboot_ver[i] == '-') + break; + bios_ver.str[i] = coreboot_ver[i]; + } + bios_ver.str[i] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +static void set_coreboot_date(const uint16_t kcs_port) +{ + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + + strncpy(bios_ver.str, COREBOOT_DMI_DATE, 15); + bios_ver.str[15] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +void supermicro_ipmi_oem(const uint16_t kcs_port) +{ + set_coreboot_ver(kcs_port); + set_coreboot_date(kcs_port); +} diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 79cc205a9d..df6973b0a4 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -17,11 +17,6 @@ config HAS_RECOVERY_MRC_CACHE bool default n -config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - bool - depends on VBOOT_STARTS_IN_BOOTBLOCK - default n - config MRC_SETTINGS_VARIABLE_DATA bool default n @@ -35,4 +30,26 @@ config MRC_WRITE_NV_LATE normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY. +config MRC_STASH_TO_CBMEM + bool + default y if MRC_WRITE_NV_LATE || BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + default n + help + Instead of writing back MRC_CACHE training data back to the + MRC_CACHE right away, stash the data into cbmem. This data + will be written back later to MRC_CACHE. This is selected + for platforms which either do not support writes to SPI + flash in early stages + (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) or the platforms + that need to write back the MRC data in late ramstage boot + states (MRC_WRITE_NV_LATE). + +config MRC_SAVE_HASH_IN_TPM + bool "Save a hash of the MRC_CACHE data in TPM NVRAM" + depends on VBOOT_STARTS_IN_BOOTBLOCK && TPM2 && !TPM1 + default y + help + Store a hash of the MRC_CACHE training data in a TPM NVRAM + space to ensure that it cannot be tampered with. + endif # CACHE_MRC_SETTINGS diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3a005db357..8b26ea5905 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include @@ -44,6 +46,7 @@ struct cache_region { uint32_t cbmem_id; int type; int elog_slot; + uint32_t tpm_hash_index; int flags; }; @@ -52,6 +55,7 @@ static const struct cache_region recovery_training = { .cbmem_id = CBMEM_ID_MRCDATA, .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, + .tpm_hash_index = MRC_REC_HASH_NV_INDEX, #if CONFIG(HAS_RECOVERY_MRC_CACHE) .flags = RECOVERY_FLAG, #else @@ -64,7 +68,21 @@ static const struct cache_region normal_training = { .cbmem_id = CBMEM_ID_MRCDATA, .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + .tpm_hash_index = MRC_RW_HASH_NV_INDEX, +#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE) + /* + * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that + * memory training happens before vboot (in RO) and the + * mrc_cache data is always safe to use. + */ .flags = NORMAL_FLAG | RECOVERY_FLAG, +#else + /* + * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after + * vboot (in RW code) and is never safe to use in recovery. + */ + .flags = NORMAL_FLAG, +#endif }; static const struct cache_region variable_data = { @@ -72,7 +90,21 @@ static const struct cache_region variable_data = { .cbmem_id = CBMEM_ID_VAR_MRCDATA, .type = MRC_VARIABLE_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, + .tpm_hash_index = 0, +#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE) + /* + * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that + * memory training happens before vboot (in RO) and the + * mrc_cache data is always safe to use. + */ .flags = NORMAL_FLAG | RECOVERY_FLAG, +#else + /* + * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after + * vboot (in RW code) and is never safe to use in recovery. + */ + .flags = NORMAL_FLAG, +#endif }; /* Order matters here for priority in matching. */ @@ -82,6 +114,11 @@ static const struct cache_region *cache_regions[] = { &variable_data, }; +/* TPM MRC hash functionality depends on vboot starting before memory init. */ +_Static_assert(!CONFIG(MRC_SAVE_HASH_IN_TPM) || + CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), + "for TPM MRC hash functionality, vboot must start in bootblock"); + static int lookup_region_by_name(const char *name, struct region *r) { if (fmap_locate_area(name, r) == 0) @@ -109,41 +146,6 @@ static const struct cache_region *lookup_region_type(int type) return NULL; } -int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size) -{ - const struct cache_region *cr; - size_t cbmem_size; - struct mrc_metadata *md; - - cr = lookup_region_type(type); - if (cr == NULL) { - printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n", - type); - return -1; - } - - cbmem_size = sizeof(*md) + size; - - md = cbmem_add(cr->cbmem_id, cbmem_size); - - if (md == NULL) { - printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", - cr->name); - return -1; - } - - memset(md, 0, sizeof(*md)); - md->signature = MRC_DATA_SIGNATURE; - md->data_size = size; - md->version = version; - md->data_checksum = compute_ip_checksum(data, size); - md->header_checksum = compute_ip_checksum(md, sizeof(*md)); - memcpy(&md[1], data, size); - - return 0; -} - static const struct cache_region *lookup_region(struct region *r, int type) { const struct cache_region *cr; @@ -152,7 +154,7 @@ static const struct cache_region *lookup_region(struct region *r, int type) if (cr == NULL) { printk(BIOS_ERR, "MRC: failed to locate region type %d.\n", - type); + type); return NULL; } @@ -204,33 +206,37 @@ static int mrc_header_valid(struct region_device *rdev, struct mrc_metadata *md) return 0; } -static int mrc_data_valid(const struct region_device *rdev, - const struct mrc_metadata *md) +static int mrc_data_valid(int type, const struct mrc_metadata *md, + void *data, size_t data_size) { - void *data; uint16_t checksum; - const size_t md_size = sizeof(*md); - const size_t data_size = md->data_size; + const struct cache_region *cr = lookup_region_type(type); + uint32_t hash_idx; - data = rdev_mmap(rdev, md_size, data_size); - if (data == NULL) { - printk(BIOS_ERR, "MRC: mmap failure on data verification.\n"); + if (cr == NULL) return -1; - } - checksum = compute_ip_checksum(data, data_size); - - rdev_munmap(rdev, data); - if (md->data_checksum != checksum) { - printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", - md->data_checksum, checksum); + if (md->data_size != data_size) return -1; + + hash_idx = cr->tpm_hash_index; + if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM)) { + if (!mrc_cache_verify_hash(hash_idx, data, data_size)) + return -1; + } else { + checksum = compute_ip_checksum(data, data_size); + + if (md->data_checksum != checksum) { + printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", + md->data_checksum, checksum); + return -1; + } } return 0; } -static int mrc_cache_latest(const char *name, +static int mrc_cache_get_latest_slot_info(const char *name, const struct region_device *backing_rdev, struct mrc_metadata *md, struct region_file *cache_file, @@ -260,27 +266,28 @@ static int mrc_cache_latest(const char *name, return fail_bad_data ? -1 : 0; } - /* Validate Data */ - if (mrc_data_valid(rdev, md) < 0) { - printk(BIOS_ERR, "MRC: invalid data in '%s'\n", name); - return fail_bad_data ? -1 : 0; - } - return 0; } -int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev) +static int mrc_cache_find_current(int type, uint32_t version, + struct region_device *rdev, + struct mrc_metadata *md) { const struct cache_region *cr; struct region region; struct region_device read_rdev; struct region_file cache_file; - struct mrc_metadata md; size_t data_size; - const size_t md_size = sizeof(md); + const size_t md_size = sizeof(*md); const bool fail_bad_data = true; + /* + * In recovery mode, force retraining if the memory retrain + * switch is set. + */ + if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch()) + return -1; + cr = lookup_region(®ion, type); if (cr == NULL) @@ -289,34 +296,100 @@ int mrc_cache_get_current(int type, uint32_t version, if (boot_device_ro_subregion(®ion, &read_rdev) < 0) return -1; - if (mrc_cache_latest(cr->name, &read_rdev, &md, &cache_file, rdev, - fail_bad_data) < 0) + if (mrc_cache_get_latest_slot_info(cr->name, + &read_rdev, + md, + &cache_file, + rdev, + fail_bad_data) < 0) return -1; - if (version != md.version) { + if (version != md->version) { printk(BIOS_INFO, "MRC: version mismatch: %x vs %x\n", - md.version, version); + md->version, version); return -1; } /* Re-size rdev to only contain the data. i.e. remove metadata. */ - data_size = md.data_size; + data_size = md->data_size; return rdev_chain(rdev, rdev, md_size, data_size); } -static bool mrc_cache_needs_update(const struct region_device *rdev, - const struct cbmem_entry *to_be_updated) +ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer, + size_t buffer_size) { - void *mapping; - size_t size = region_device_sz(rdev); + struct region_device rdev; + struct mrc_metadata md; + ssize_t data_size; + + if (mrc_cache_find_current(type, version, &rdev, &md) < 0) + return -1; + + data_size = region_device_sz(&rdev); + if (buffer_size < data_size) + return -1; + + if (rdev_readat(&rdev, buffer, 0, data_size) != data_size) + return -1; + + if (mrc_data_valid(type, &md, buffer, data_size) < 0) + return -1; + + return data_size; +} + +void *mrc_cache_current_mmap_leak(int type, uint32_t version, + size_t *data_size) +{ + struct region_device rdev; + void *data; + size_t region_device_size; + struct mrc_metadata md; + + if (mrc_cache_find_current(type, version, &rdev, &md) < 0) + return NULL; + + region_device_size = region_device_sz(&rdev); + if (data_size) + *data_size = region_device_size; + data = rdev_mmap_full(&rdev); + + if (data == NULL) { + printk(BIOS_INFO, "MRC: mmap failure.\n"); + return NULL; + } + + if (mrc_data_valid(type, &md, data, region_device_size) < 0) + return NULL; + + return data; +} + +static bool mrc_cache_needs_update(const struct region_device *rdev, + const struct mrc_metadata *new_md, + const void *new_data, size_t new_data_size) +{ + void *mapping, *data_mapping; + size_t old_data_size = region_device_sz(rdev) - sizeof(struct mrc_metadata); bool need_update = false; - if (cbmem_entry_size(to_be_updated) != size) + if (new_data_size != old_data_size) return true; mapping = rdev_mmap_full(rdev); + if (mapping == NULL) { + printk(BIOS_ERR, "MRC: cannot mmap existing cache.\n"); + return true; + } + data_mapping = mapping + sizeof(struct mrc_metadata); - if (memcmp(cbmem_entry_start(to_be_updated), mapping, size)) + /* we need to compare the md and the data separately */ + /* check the mrc_metadata */ + if (memcmp(new_md, mapping, sizeof(struct mrc_metadata))) + need_update = true; + + /* check the data */ + if (!need_update && memcmp(new_data, data_mapping, new_data_size)) need_update = true; rdev_munmap(rdev, mapping); @@ -351,7 +424,10 @@ static void log_event_cache_update(uint8_t slot, enum result res) * read and write. The read assumes a memory-mapped boot device that can be used * to quickly locate and compare the up-to-date data. However, when an update * is required it uses the writeable region access to perform the update. */ -static void update_mrc_cache_by_type(int type) +static void update_mrc_cache_by_type(int type, + struct mrc_metadata *new_md, + const void *new_data, + size_t new_data_size) { const struct cache_region *cr; struct region region; @@ -359,24 +435,17 @@ static void update_mrc_cache_by_type(int type) struct region_device write_rdev; struct region_file cache_file; struct mrc_metadata md; - const struct cbmem_entry *to_be_updated; struct incoherent_rdev backing_irdev; const struct region_device *backing_rdev; struct region_device latest_rdev; const bool fail_bad_data = false; + uint32_t hash_idx; cr = lookup_region(®ion, type); if (cr == NULL) return; - to_be_updated = cbmem_entry_find(cr->cbmem_id); - if (to_be_updated == NULL) { - printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", - cr->name); - return; - } - printk(BIOS_DEBUG, "MRC: Checking cached data update for '%s'.\n", cr->name); @@ -392,11 +461,21 @@ static void update_mrc_cache_by_type(int type) if (backing_rdev == NULL) return; - if (mrc_cache_latest(cr->name, backing_rdev, &md, &cache_file, - &latest_rdev, fail_bad_data) < 0) + /* Note that mrc_cache_get_latest_slot_info doesn't check the + * validity of the current slot. If the slot is invalid, + * we'll overwrite it anyway when we update the mrc_cache. + */ + if (mrc_cache_get_latest_slot_info(cr->name, + backing_rdev, + &md, + &cache_file, + &latest_rdev, + fail_bad_data) < 0) + return; - if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) { + if (!mrc_cache_needs_update(&latest_rdev, + new_md, new_data, new_data_size)) { printk(BIOS_DEBUG, "MRC: '%s' does not need update.\n", cr->name); log_event_cache_update(cr->elog_slot, ALREADY_UPTODATE); return; @@ -404,14 +483,25 @@ static void update_mrc_cache_by_type(int type) printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); - if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) { - printk(BIOS_DEBUG, "MRC: failed to update '%s'.\n", cr->name); + struct update_region_file_entry entries[] = { + [0] = { + .size = sizeof(struct mrc_metadata), + .data = new_md, + }, + [1] = { + .size = new_data_size, + .data = new_data, + }, + }; + if (region_file_update_data_arr(&cache_file, entries, ARRAY_SIZE(entries)) < 0) { + printk(BIOS_ERR, "MRC: failed to update '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); + hash_idx = cr->tpm_hash_index; + if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM)) + mrc_cache_update_hash(hash_idx, new_data, new_data_size); } } @@ -447,15 +537,13 @@ static int nvm_is_write_protected(void) /* Apply protection to a range of flash */ static int nvm_protect(const struct region *r) { - const struct spi_flash *flash = boot_device_spi_flash(); - if (!CONFIG(MRC_SETTINGS_PROTECT)) return 0; if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; - return spi_flash_ctrlr_protect_region(flash, r, WRITE_PROTECT); + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r, WRITE_PROTECT); } /* Protect mrc region with a Protected Range Register */ @@ -467,7 +555,7 @@ static int protect_mrc_cache(const char *name) return 0; if (lookup_region_by_name(name, ®ion) < 0) { - printk(BIOS_ERR, "MRC: Could not find region '%s'\n", name); + printk(BIOS_INFO, "MRC: Could not find region '%s'\n", name); return -1; } @@ -511,10 +599,24 @@ static void invalidate_normal_cache(void) const char *name = DEFAULT_MRC_CACHE; const uint32_t invalid = ~MRC_DATA_SIGNATURE; - /* Invalidate only on recovery mode with retraining enabled. */ + /* + * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is + * selected, this means that memory training occurs before + * verified boot (in RO), so normal mode cache does not need + * to be invalidated. + */ + if (!CONFIG(HAS_RECOVERY_MRC_CACHE) && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return; + + /* We only invalidate the normal cache in recovery mode. */ if (!vboot_recovery_mode_enabled()) return; - if (!get_recovery_mode_retrain_switch()) + + /* + * For platforms with a recovery mrc_cache, no need to + * invalidate when retrain switch is not set. + */ + if (CONFIG(HAS_RECOVERY_MRC_CACHE) && !get_recovery_mode_retrain_switch()) return; if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { @@ -535,26 +637,103 @@ static void invalidate_normal_cache(void) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +static void update_mrc_cache_from_cbmem(int type) { - update_mrc_cache_by_type(MRC_TRAINING_DATA); + const struct cache_region *cr; + struct region region; + const struct cbmem_entry *to_be_updated; - if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) - update_mrc_cache_by_type(MRC_VARIABLE_DATA); + cr = lookup_region(®ion, type); - if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) - invalidate_normal_cache(); + if (cr == NULL) { + printk(BIOS_INFO, "MRC: could not find cache_region type %d\n", type); + return; + } + + to_be_updated = cbmem_entry_find(cr->cbmem_id); + + if (to_be_updated == NULL) { + printk(BIOS_INFO, "MRC: No data in cbmem for '%s'.\n", + cr->name); + return; + } + + update_mrc_cache_by_type(type, + /* pointer to mrc_cache entry metadata header */ + cbmem_entry_start(to_be_updated), + /* pointer to start of mrc_cache entry data */ + cbmem_entry_start(to_be_updated) + + sizeof(struct mrc_metadata), + /* size of just data portion of the entry */ + cbmem_entry_size(to_be_updated) - + sizeof(struct mrc_metadata)); +} + +static void finalize_mrc_cache(void *unused) +{ + if (CONFIG(MRC_STASH_TO_CBMEM)) { + update_mrc_cache_from_cbmem(MRC_TRAINING_DATA); + + if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) + update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA); + } + + invalidate_normal_cache(); protect_mrc_region(); } +int mrc_cache_stash_data(int type, uint32_t version, const void *data, + size_t size) +{ + const struct cache_region *cr; + + struct mrc_metadata md = { + .signature = MRC_DATA_SIGNATURE, + .data_size = size, + .version = version, + .data_checksum = compute_ip_checksum(data, size), + }; + md.header_checksum = + compute_ip_checksum(&md, sizeof(struct mrc_metadata)); + + if (CONFIG(MRC_STASH_TO_CBMEM)) { + /* Store data in cbmem for use in ramstage */ + struct mrc_metadata *cbmem_md; + size_t cbmem_size; + cbmem_size = sizeof(*cbmem_md) + size; + + cr = lookup_region_type(type); + if (cr == NULL) { + printk(BIOS_INFO, "MRC: No region type found. Skip adding to cbmem for type %d.\n", + type); + return 0; + } + + cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size); + + if (cbmem_md == NULL) { + printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", + cr->name); + return -1; + } + + memcpy(cbmem_md, &md, sizeof(*cbmem_md)); + /* cbmem_md + 1 is the pointer to the mrc_cache data */ + memcpy(cbmem_md + 1, data, size); + } else { + /* Otherwise store to mrc_cache right away */ + update_mrc_cache_by_type(type, &md, data, size); + } + return 0; +} + /* * Ensures MRC training data is stored into SPI after PCI enumeration is done. * Some implementations may require this to be later than others. */ - #if CONFIG(MRC_WRITE_NV_LATE) -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL); #else -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, finalize_mrc_cache, NULL); #endif diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 620dab952e..971f31dd83 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -36,7 +36,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #include "ns8390.h" - #define ETH_ALEN 6 /* Size of Ethernet address */ #define ETH_HLEN 14 /* Size of ethernet header */ #define ETH_ZLEN 60 /* Minimum packet */ @@ -48,7 +47,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #define TX_START 64 #define RX_START (64 + D8390_TXBUF_SIZE) - static unsigned int get_count(unsigned int eth_nic_base) { unsigned int ret; @@ -146,7 +144,6 @@ static void str2mac(const char *str, unsigned char *mac) } while (c != '\0'); } - static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) { unsigned short chksum; diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c index 4e54af0b2a..d0ef11508d 100644 --- a/src/drivers/ocp/dmi/smbios.c +++ b/src/drivers/ocp/dmi/smbios.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "ocp_dmi.h" diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index b32ac707ad..914c9aed9c 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -77,7 +77,6 @@ unsigned long calibrate_tsc_with_pit(void) if (end.hi) goto bad_ctc; - /* Error: ECPUTOOSLOW */ if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc; diff --git a/src/drivers/pc80/pc/isa-dma.c b/src/drivers/pc80/pc/isa-dma.c index dbb2362836..5c3fe67920 100644 --- a/src/drivers/pc80/pc/isa-dma.c +++ b/src/drivers/pc80/pc/isa-dma.c @@ -32,7 +32,6 @@ #define DMA_AUTOINIT 0x10 - void isa_dma_init(void) { /* slave at 0x00 - 0x0f */ diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index ced544e178..9e457f7166 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -5,7 +5,6 @@ #define SPEAKER_PIT_FREQUENCY 0x1234dd - enum { PIT_COUNTER_0 = 0x40, PIT_COUNTER_1 = 0x41, @@ -14,7 +13,6 @@ enum { PIT_SPEAKER_PORT = 0x61, }; - enum { PIT_SPK_TMR2 = 0x01, PIT_SPK_DATA = 0x02, @@ -44,13 +42,11 @@ enum { PIT_CTRL_HARDSTROBE = 0x0a, - PIT_CTRL_COUNT_MASK = 0x01, PIT_CTRL_COUNT_BINARY = 0x00, PIT_CTRL_COUNT_BCD = 0x01 }; - static void make_tone(uint16_t freq_count, unsigned int duration) { diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index c0dd1275d8..5f6055e872 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -1,29 +1,14 @@ ifeq ($(CONFIG_ARCH_X86),y) -bootblock-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -verstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c +all-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -bootblock-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +all-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -bootblock-$(CONFIG_USE_OPTION_TABLE) += option.c -verstage-$(CONFIG_USE_OPTION_TABLE) += option.c -postcar-$(CONFIG_USE_OPTION_TABLE) += option.c -romstage-$(CONFIG_USE_OPTION_TABLE) += option.c -ramstage-$(CONFIG_USE_OPTION_TABLE) += option.c -smm-$(CONFIG_USE_OPTION_TABLE) += option.c +all-$(CONFIG_USE_OPTION_TABLE) += option.c +smm-$(CONFIG_USE_OPTION_TABLE) += option.c -bootblock-$(CONFIG_CMOS_POST) += post.c -verstage-$(CONFIG_CMOS_POST) += post.c -postcar-$(CONFIG_CMOS_POST) += post.c -romstage-$(CONFIG_CMOS_POST) += post.c -ramstage-$(CONFIG_CMOS_POST) += post.c +all-$(CONFIG_CMOS_POST) += post.c ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3227510941..21d3c009fa 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -144,7 +143,7 @@ static void cmos_init_vbnv(bool invalid) uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; /* __cmos_init() will clear vbnv contents when a known rtc failure - occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may + occurred with !CONFIG(USE_OPTION_TABLE). However, __cmos_init() may clear vbnv data for other internal reasons. For that, always back up the vbnv contents and conditionally save them when __cmos_init() indicates CMOS was cleared. */ diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index fbcf387f63..550a6027c0 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 0a73cb3232..409f0efb3b 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -49,36 +49,28 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(void) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - static struct cbfsf fh; + static struct cmos_option_table *ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -86,16 +78,9 @@ enum cb_err cmos_get_option(void *dest, const char *name) /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -108,19 +93,15 @@ enum cb_err cmos_get_option(void *dest, const char *name) } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); + return CB_SUCCESS; } @@ -168,7 +149,6 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -177,16 +157,9 @@ enum cb_err cmos_set_option(const char *name, void *value) /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -199,7 +172,6 @@ enum cb_err cmos_set_option(const char *name, void *value) } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -208,18 +180,13 @@ enum cb_err cmos_set_option(const char *name, void *value) length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } @@ -228,7 +195,6 @@ int cmos_lb_cks_valid(void) return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } - void sanitize_cmos(void) { const unsigned char *cmos_default; @@ -238,8 +204,7 @@ void sanitize_cmos(void) size_t i; if (CONFIG(TPM_MEASURED_BOOT) || cmos_need_reset) { - cmos_default = cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); + cmos_default = cbfs_map("cmos.default", &length); if (!cmos_default || !cmos_need_reset) return; diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 27d238ce75..48e529ad9f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -21,13 +21,11 @@ #include #include #include +#include #include "chip.h" #define PREFIX "lpc_tpm: " -/* TCG Physical Presence Interface */ -#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" -/* TCG Memory Clear Interface */ -#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ if (CONFIG(DEBUG_TPM)) { \ @@ -777,104 +775,9 @@ static void lpc_tpm_set_resources(struct device *dev) } #if CONFIG(HAVE_ACPI_TABLES) - -static void tpm_ppi_func0_cb(void *arg) -{ - /* Functions 1-8. */ - u8 buf[] = {0xff, 0x01}; - acpigen_write_return_byte_buffer(buf, 2); -} - -static void tpm_ppi_func1_cb(void *arg) -{ - if (CONFIG(TPM2)) - /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); - else - /* Interface version: 1.2 */ - acpigen_write_return_string("1.2"); -} - -static void tpm_ppi_func2_cb(void *arg) -{ - /* Submit operations: drop on the floor and return success. */ - acpigen_write_return_byte(0); -} - -static void tpm_ppi_func3_cb(void *arg) -{ - /* Pending operation: none. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(2); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func4_cb(void *arg) -{ - /* Pre-OS transition method: reboot. */ - acpigen_write_return_byte(2); -} -static void tpm_ppi_func5_cb(void *arg) -{ - /* Operation response: no operation executed. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(3); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func6_cb(void *arg) -{ - /* - * Set preferred user language: deprecated and must return 3 aka - * "not implemented". - */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func7_cb(void *arg) -{ - /* Submit operations: deny. */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func8_cb(void *arg) -{ - /* All actions are forbidden. */ - acpigen_write_return_byte(1); -} -static void (*tpm_ppi_callbacks[])(void *) = { - tpm_ppi_func0_cb, - tpm_ppi_func1_cb, - tpm_ppi_func2_cb, - tpm_ppi_func3_cb, - tpm_ppi_func4_cb, - tpm_ppi_func5_cb, - tpm_ppi_func6_cb, - tpm_ppi_func7_cb, - tpm_ppi_func8_cb, -}; - -static void tpm_mci_func0_cb(void *arg) -{ - /* Function 1. */ - acpigen_write_return_singleton_buffer(0x3); -} -static void tpm_mci_func1_cb(void *arg) -{ - /* Just return success. */ - acpigen_write_return_byte(0); -} - -static void (*tpm_mci_callbacks[])(void *) = { - tpm_mci_func0_cb, - tpm_mci_func1_cb, -}; - static void lpc_tpm_fill_ssdt(const struct device *dev) { const char *path = acpi_device_path(dev->bus->dev); - u32 arg; if (!path) { path = "\\_SB_.PCI0.LPCB"; @@ -938,31 +841,12 @@ static void lpc_tpm_fill_ssdt(const struct device *dev) acpi_device_write_interrupt(&tpm_irq); } + acpigen_write_resourcetemplate_footer(); - if (!CONFIG(CHROMEOS)) { - /* - * _DSM method - */ - struct dsm_uuid ids[] = { - /* Physical presence interface. - * This is used to submit commands like "Clear TPM" to - * be run at next reboot provided that user confirms - * them. Spec allows user to cancel all commands and/or - * configure BIOS to reject commands. So we pretend that - * user did just this: cancelled everything. If user - * really wants to clear TPM the only option now is to - * do it manually in payload. - */ - DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], - ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), - /* Memory clearing on boot: just a dummy. */ - DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], - ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), - }; + if (!CONFIG(CHROMEOS)) + tpm_ppi_acpi_fill_ssdt(dev); - acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 7ee8676014..ba8268e378 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -6,6 +6,18 @@ config SMMSTORE default y if PAYLOAD_TIANOCORE select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP +config SMMSTORE_V2 + bool "Use version 2 of SMMSTORE API" + depends on SMMSTORE + default n + help + Version 2 of SMMSTORE allows secure communication with SMM and + makes no assumptions on the structure of the data stored within. + It splits the store into chunks to allows fault tolerant writes. + + By using version 2 you cannot make use of software that expects + a version 1 SMMSTORE. + config SMMSTORE_IN_CBFS bool default n diff --git a/src/drivers/smmstore/Makefile.inc b/src/drivers/smmstore/Makefile.inc index 1cafe3a3cf..90bcdece9d 100644 --- a/src/drivers/smmstore/Makefile.inc +++ b/src/drivers/smmstore/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_SMMSTORE) += store.c +ramstage-$(CONFIG_SMMSTORE_V2) += ramstage.c smm-$(CONFIG_SMMSTORE) += store.c smi.c diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c new file mode 100644 index 0000000000..ef80e221bc --- /dev/null +++ b/src/drivers/smmstore/ramstage.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smmstore_params_info info; + +void lb_smmstorev2(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_smmstorev2 *store; + const struct cbmem_entry *e; + + e = cbmem_entry_find(CBMEM_ID_SMM_COMBUFFER); + if (!e) + return; + + rec = lb_new_record(header); + store = (struct lb_smmstorev2 *)rec; + + store->tag = LB_TAG_SMMSTOREV2; + store->size = sizeof(*store); + store->com_buffer = (uintptr_t)cbmem_entry_start(e); + store->com_buffer_size = cbmem_entry_size(e); + store->mmap_addr = info.mmap_addr; + store->num_blocks = info.num_blocks; + store->block_size = info.block_size; + store->apm_cmd = APM_CNT_SMMSTORE; +} + +static void init_store(void *unused) +{ + struct smmstore_params_init args; + uint32_t eax = ~0; + uint32_t ebx; + + if (smmstore_get_info(&info) < 0) { + printk(BIOS_INFO, "SMMSTORE: Failed to get meta data\n"); + return; + } + + void *ptr = cbmem_add(CBMEM_ID_SMM_COMBUFFER, info.block_size); + if (!ptr) { + printk(BIOS_ERR, "SMMSTORE: Failed to add com buffer\n"); + return; + } + + args.com_buffer = (uintptr_t)ptr; + args.com_buffer_size = info.block_size; + ebx = (uintptr_t)&args; + + printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n"); + + /* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */ + __asm__ __volatile__ ( + "outb %%al, %%dx" + : "=a" (eax) + : "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE), + "b" (ebx), + "d" (APM_CNT) + : "memory"); + + if (eax != SMMSTORE_RET_SUCCESS) { + printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n"); + return; + } +} + +/* The SMI APM handler is installed at DEV_INIT phase */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, init_store, NULL); diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index b21423e90e..b90338c619 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -23,8 +23,7 @@ static int range_check(void *start, size_t size) return 0; } -/* Param is usually EBX, ret in EAX */ -uint32_t smmstore_exec(uint8_t command, void *param) +static uint32_t smmstorev1_exec(uint8_t command, void *param) { uint32_t ret = SMMSTORE_RET_FAILURE; @@ -66,13 +65,89 @@ uint32_t smmstore_exec(uint8_t command, void *param) ret = SMMSTORE_RET_SUCCESS; break; } - default: printk(BIOS_DEBUG, - "Unknown SMM store command: 0x%02x\n", command); + "Unknown SMM store v1 command: 0x%02x\n", command); ret = SMMSTORE_RET_UNSUPPORTED; break; } return ret; } + +static uint32_t smmstorev2_exec(uint8_t command, void *param) +{ + uint32_t ret = SMMSTORE_RET_FAILURE; + + switch (command) { + case SMMSTORE_CMD_INIT: { + printk(BIOS_DEBUG, "Init SMM store\n"); + struct smmstore_params_init *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + void *buf = (void *)(uintptr_t)params->com_buffer; + + if (range_check(buf, params->com_buffer_size) != 0) + break; + + if (smmstore_init(buf, params->com_buffer_size) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_READ: { + printk(BIOS_DEBUG, "Raw read from SMM store, param = %p\n", param); + struct smmstore_params_raw_read *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawread_region(params->block_id, params->bufoffset, + params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_WRITE: { + printk(BIOS_DEBUG, "Raw write to SMM store, param = %p\n", param); + struct smmstore_params_raw_write *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawwrite_region(params->block_id, params->bufoffset, + params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_CLEAR: { + printk(BIOS_DEBUG, "Raw clear SMM store, param = %p\n", param); + struct smmstore_params_raw_clear *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawclear_region(params->block_id) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + default: + printk(BIOS_DEBUG, + "Unknown SMM store v2 command: 0x%02x\n", command); + ret = SMMSTORE_RET_UNSUPPORTED; + break; + } + + return ret; +} + +uint32_t smmstore_exec(uint8_t command, void *param) +{ + if (!param) + return SMMSTORE_RET_FAILURE; + + if (CONFIG(SMMSTORE_V2)) + return smmstorev2_exec(command, param); + else + return smmstorev1_exec(command, param); +} diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index e183e6317c..bae7f333e1 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -265,6 +265,203 @@ int smmstore_clear_region(void) return 0; } + +/* Implementation of Version 2 */ + +static bool store_initialized; +static struct mem_region_device mdev_com_buf; + +static int smmstore_rdev_chain(struct region_device *rdev) +{ + if (!store_initialized) + return -1; + + return rdev_chain_full(rdev, &mdev_com_buf.rdev); +} + +/** + * Call once before using the store. In SMM this must be called through an + * APM SMI handler providing the communication buffer address and length. + */ +int smmstore_init(void *buf, size_t len) +{ + if (!buf || len < SMM_BLOCK_SIZE) + return -1; + + if (store_initialized) + return -1; + + mem_region_device_rw_init(&mdev_com_buf, buf, len); + + store_initialized = true; + + return 0; +} + +#if ENV_RAMSTAGE +/** + * Provide metadata for the coreboot tables. + * Must only be called in ramstage, but not in SMM. + */ +int smmstore_get_info(struct smmstore_params_info *out) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_ERR, "smm store: lookup of store failed\n"); + return -1; + } + + if (!IS_ALIGNED(region_device_offset(&store), SMM_BLOCK_SIZE)) { + printk(BIOS_ERR, "smm store: store not aligned to block size\n"); + return -1; + } + + out->block_size = SMM_BLOCK_SIZE; + out->num_blocks = region_device_sz(&store) / SMM_BLOCK_SIZE; + + /* FIXME: Broken EDK2 always assumes memory mapped Firmware Block Volumes */ + out->mmap_addr = (uintptr_t)rdev_mmap_full(&store); + + printk(BIOS_DEBUG, "smm store: %d # blocks with size 0x%x\n", + out->num_blocks, out->block_size); + + return 0; +} +#endif + +/* Returns -1 on error, 0 on success */ +static int lookup_block_in_store(struct region_device *store, uint32_t block_id) +{ + if (lookup_store(store) < 0) { + printk(BIOS_ERR, "smm store: lookup of store failed\n"); + return -1; + } + + if ((block_id * SMM_BLOCK_SIZE) >= region_device_sz(store)) { + printk(BIOS_ERR, "smm store: block ID out of range\n"); + return -1; + } + + return 0; +} + +/* Returns NULL on error, pointer from rdev_mmap on success */ +static void *mmap_com_buf(struct region_device *com_buf, uint32_t offset, uint32_t bufsize) +{ + if (smmstore_rdev_chain(com_buf) < 0) { + printk(BIOS_ERR, "smm store: lookup of com buffer failed\n"); + return NULL; + } + + if (offset >= region_device_sz(com_buf)) { + printk(BIOS_ERR, "smm store: offset out of range\n"); + return NULL; + } + + void *ptr = rdev_mmap(com_buf, offset, bufsize); + if (!ptr) + printk(BIOS_ERR, "smm store: not enough space for new data\n"); + + return ptr; +} + +/** + * Reads the specified block of the SMMSTORE and places it in the communication + * buffer. + * @param block_id The id of the block to operate on + * @param offset Offset within the block. + * Must be smaller than the block size. + * @param bufsize Size of chunk to read within the block. + * Must be smaller than the block size. + + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawread_region(uint32_t block_id, uint32_t offset, uint32_t bufsize) +{ + struct region_device store; + struct region_device com_buf; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + void *ptr = mmap_com_buf(&com_buf, offset, bufsize); + if (!ptr) + return -1; + + printk(BIOS_DEBUG, "smm store: reading %p block %d, offset=0x%x, size=%x\n", + ptr, block_id, offset, bufsize); + + ssize_t ret = rdev_readat(&store, ptr, block_id * SMM_BLOCK_SIZE + offset, bufsize); + rdev_munmap(&com_buf, ptr); + if (ret < 0) + return -1; + + return 0; +} + +/** + * Writes the specified block of the SMMSTORE by reading it from the communication + * buffer. + * @param block_id The id of the block to operate on + * @param offset Offset within the block. + * Must be smaller than the block size. + * @param bufsize Size of chunk to read within the block. + * Must be smaller than the block size. + + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawwrite_region(uint32_t block_id, uint32_t offset, uint32_t bufsize) +{ + struct region_device store; + struct region_device com_buf; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + if (rdev_chain(&store, &store, block_id * SMM_BLOCK_SIZE + offset, bufsize)) { + printk(BIOS_ERR, "smm store: not enough space for new data\n"); + return -1; + } + + void *ptr = mmap_com_buf(&com_buf, offset, bufsize); + if (!ptr) + return -1; + + printk(BIOS_DEBUG, "smm store: writing %p block %d, offset=0x%x, size=%x\n", + ptr, block_id, offset, bufsize); + + ssize_t ret = rdev_writeat(&store, ptr, 0, bufsize); + rdev_munmap(&com_buf, ptr); + if (ret < 0) + return -1; + + return 0; +} + +/** + * Erases the specified block of the SMMSTORE. The communication buffer remains untouched. + * + * @param block_id The id of the block to operate on + * + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawclear_region(uint32_t block_id) +{ + struct region_device store; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + ssize_t ret = rdev_eraseat(&store, block_id * SMM_BLOCK_SIZE, SMM_BLOCK_SIZE); + if (ret != SMM_BLOCK_SIZE) { + printk(BIOS_ERR, "smm store: erasing block failed\n"); + return -1; + } + + return 0; +} + static void clear_store_on_reset(void *unused) { int preserve = 1; diff --git a/src/drivers/soundwire/alc5682/alc5682.c b/src/drivers/soundwire/alc5682/alc5682.c index 79ed610ab8..e15ecd421a 100644 --- a/src/drivers/soundwire/alc5682/alc5682.c +++ b/src/drivers/soundwire/alc5682/alc5682.c @@ -128,7 +128,7 @@ static void soundwire_alc5682_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; - if (!dev->enabled || !scope) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/soundwire/alc711/Kconfig b/src/drivers/soundwire/alc711/Kconfig new file mode 100644 index 0000000000..bdc02a9324 --- /dev/null +++ b/src/drivers/soundwire/alc711/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_ALC711 + bool diff --git a/src/drivers/soundwire/alc711/Makefile.inc b/src/drivers/soundwire/alc711/Makefile.inc new file mode 100644 index 0000000000..78e4d1b7fe --- /dev/null +++ b/src/drivers/soundwire/alc711/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC711) += alc711.c diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c new file mode 100644 index 0000000000..44a9e98deb --- /dev/null +++ b/src/drivers/soundwire/alc711/alc711.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static struct soundwire_address alc711_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC711, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave alc711_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(2), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode alc711_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ + .bus_frequency_configs_count = 12, + .bus_frequency_configs = { + 9600 * KHz, + 4800 * KHz, + 2400 * KHz, + 1200 * KHz, + 12000 * KHz, + 6000 * KHz, + 3000 * KHz, + 1500 * KHz, + 12288 * KHz, + 6144 * KHz, + 3072 * KHz, + 1536 * KHz + }, + /* Support 16 KHz to 192 KHz sampling frequency */ + .sampling_frequency_configs_count = 9, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + 192 * KHz + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc711_dp = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc711_codec = { + .slave = &alc711_slave, + .audio_mode = { &alc711_audio_mode }, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc711_dp + }, + { + /* Data Output for DSP Path */ + .port = 2, + .source = &alc711_dp + } + } + +}; + +static void soundwire_alc711_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc711_address.link_id = dev->path.generic.id; + alc711_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc711_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc711_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc711_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc711_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc711_acpi_name, + .acpi_fill_ssdt = soundwire_alc711_fill_ssdt, +}; + +static void soundwire_alc711_enable(struct device *dev) +{ + dev->ops = &soundwire_alc711_ops; +} + +struct chip_operations drivers_soundwire_alc711_ops = { + CHIP_NAME("Realtek ALC711 SoundWire Codec") + .enable_dev = soundwire_alc711_enable +}; diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h new file mode 100644 index 0000000000..6d317fddfe --- /dev/null +++ b/src/drivers/soundwire/alc711/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ + +struct drivers_soundwire_alc711_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/drivers/soundwire/max98373/max98373.c b/src/drivers/soundwire/max98373/max98373.c index 231385cd57..28796c06bc 100644 --- a/src/drivers/soundwire/max98373/max98373.c +++ b/src/drivers/soundwire/max98373/max98373.c @@ -114,7 +114,7 @@ static void soundwire_max98373_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; - if (!dev->enabled || !scope) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4fce..13a73b8df2 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,20 @@ config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP Provide common implementation of the RW boot device that doesn't provide mmap() operations. +config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For platforms who do not allow writes to SPI flash in early + stages like romstage. Not selecting this config will result + in the auto-selection of + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform. + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help @@ -152,5 +164,5 @@ config SPI_FLASH_HAS_VOLATILE_GROUP endif # SPI_FLASH -config HAVE_SPI_CONSOLE_SUPPORT +config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT def_bool n diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 6dbc43a6d7..56ee44bd47 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,7 +2,7 @@ subdirs-y += tpm -ifeq ($(CONFIG_SPI_CONSOLE),y) +ifeq ($(CONFIG_EM100PRO_SPI_CONSOLE),y) ramstage-y += spiconsole.c smm-y += spiconsole.c endif diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index c0e776eee1..b23bc9d7a9 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -77,7 +77,7 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev) int reset_gpio_index = -1; int enable_gpio_index = -1; - if (!dev->enabled || !scope) + if (!scope) return; if (spi_acpi_get_bus(dev) == -1) { diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 654177f6d3..d5c4382101 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -75,7 +75,8 @@ void flashconsole_tx_byte(unsigned char c) size_t region_size = region_device_sz(rdev_ptr); - line_buffer[line_offset++] = c; + if (line_offset < LINE_BUFFER_SIZE) + line_buffer[line_offset++] = c; if (line_offset >= LINE_BUFFER_SIZE || offset + line_offset >= region_size || c == '\n') { diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 372575e2d9..2406a90e52 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -373,7 +373,6 @@ static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_i [1] = id[1] & vi->match_id_mask[1], }; - for (i = 0; i < vi->nr_part_ids; i++) { const struct spi_flash_part_id *part = &vi->ids[i]; @@ -664,8 +663,15 @@ void lb_spi_flash(struct lb_header *header) flash->sector_size = 64 * KiB; flash->erase_cmd = CMD_BLOCK_ERASE; } -} + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { + flash->mmap_count = 0; + } else { + struct flash_mmap_window *table = (struct flash_mmap_window *)(flash + 1); + flash->mmap_count = spi_flash_get_mmap_windows(table); + flash->size += flash->mmap_count * sizeof(*table); + } +} int spi_flash_ctrlr_protect_region(const struct spi_flash *flash, const struct region *region, diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index 5d0a71b4f5..a670111891 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -354,11 +354,12 @@ static int spi_sdcard_do_app_command(const struct spi_sdcard *card, uint32_t *out_register) { /* CMD55 */ - spi_sdcard_do_command(card, APP_CMD, 0, NULL); + if (spi_sdcard_do_command(card, APP_CMD, 0, NULL)) + return -1; + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); } - size_t spi_sdcard_size(const struct spi_sdcard *card) { int wait; diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 6849ea7bf0..2554cf717c 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -75,7 +75,6 @@ int tis_init(void) return 0; } - int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 24851d1c86..d65decda12 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -31,6 +31,15 @@ #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) +#define CR50_BOARD_CFG (TPM_LOCALITY_0_SPI_BASE + 0xfe0) + +#define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U +#define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU + +#define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U +#define CR50_BOARD_CFG_VALUE \ + (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ + ? CR50_BOARD_CFG_100US_READY_PULSE : 0) #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ @@ -39,12 +48,13 @@ static struct spi_slave spi_slave; /* Cached TPM device identification. */ static struct tpm2_info tpm_info; +static struct cr50_firmware_version cr50_firmware_version; /* - * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of + * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of * debug traces. Right now it is either 0 or 1. */ -static const int debug_level_ = CONFIG_DEBUG_TPM; +static const int debug_level_ = CONFIG(DEBUG_TPM); /* * SPI frame header for TPM transactions is 4 bytes in size, it is described @@ -338,7 +348,7 @@ static int read_tpm_sts(uint32_t *status) return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); } -static int write_tpm_sts(uint32_t status) +static int __must_check write_tpm_sts(uint32_t status) { return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); } @@ -421,12 +431,109 @@ static int tpm2_claim_locality(void) return 0; } +static int cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) +{ + int epoch, major, minor; + + char *number = strstr(version_str, " RW_A:"); + if (!number) + number = strstr(version_str, " RW_B:"); + if (!number) + return -1; + number += 6; /* Skip past the colon. */ + + epoch = skip_atoi(&number); + if (*number++ != '.') + return -2; + major = skip_atoi(&number); + if (*number++ != '.') + return -2; + minor = skip_atoi(&number); + + ver->epoch = epoch; + ver->major = major; + ver->minor = minor; + return 0; +} + +static int cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) +{ + /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 + * and onwards. */ + if (version->epoch > 0 || version->major >= 7 + || (version->major >= 5 && version->minor >= 5)) + return 1; + printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", + version->epoch, version->major, version->minor); + return 0; +} + +/** + * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. + */ +static void cr50_set_board_cfg(void) +{ + uint32_t board_cfg_value; + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return; + /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ + if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return; + } + if ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { + printk(BIOS_INFO, + "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + return; + } + if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) { + /* The high bit is set, meaning that the Cr50 is already locked on a particular + * value for the register, but not the one we wanted. */ + printk(BIOS_ERR, + "ERROR: Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + return; + } + printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + board_cfg_value = CR50_BOARD_CFG_VALUE; + if (!tpm2_write_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) + printk(BIOS_INFO, "Error writing to cr50\n"); +} + +/* + * Expose method to read the CR50_BOARD_CFG register, will return zero if + * register not supported by Cr50 firmware. + */ +static uint32_t cr50_get_board_cfg(void) +{ + uint32_t board_cfg_value; + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return 0; + if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return 0; + } + return board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK; +} + +bool cr50_is_long_interrupt_pulse_enabled(void) +{ + return cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE; +} + /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { 0x00281ae0, /* H1 based Cr50 security chip. */ 0x0000104a /* ST33HTPH2E32 */ }; +static int first_access_this_boot(void) +{ + return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); +} + int tpm2_init(struct spi_slave *spi_if) { uint32_t did_vid, status; @@ -471,7 +578,7 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, " done!\n"); // FIXME: Move this to tpm_setup() - if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT)) + if (first_access_this_boot()) /* * Claim locality 0, do it only during the first * initialization after reset. @@ -502,18 +609,10 @@ int tpm2_init(struct spi_slave *spi_if) tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); /* Let's report device FW version if available. */ - if (tpm_info.vendor_id == 0x1ae0) { + if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - size_t chunk_size; - /* - * let's read 50 bytes at a time; leave room for the trailing - * zero. - */ - char vstr[51]; - - chunk_size = sizeof(vstr) - 1; - - printk(BIOS_INFO, "Firmware version: "); + size_t chunk_size = 50; + char version_str[301]; /* * Does not really matter what's written, this just makes sure @@ -521,20 +620,28 @@ int tpm2_init(struct spi_slave *spi_if) */ tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); - /* Print it out in sizeof(vstr) - 1 byte chunks. */ - vstr[chunk_size] = 0; + /* + * Read chunk_size bytes at a time, last chunk will be zero padded. + */ do { - tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); - printk(BIOS_INFO, "%s", vstr); - - /* - * While string is not over, and is no longer than 300 - * characters. - */ - } while (vstr[chunk_size - 1] && - (chunk_count++ < (300 / chunk_size))); - - printk(BIOS_INFO, "\n"); + tpm2_read_reg(TPM_FW_VER, + version_str + chunk_count * chunk_size, + chunk_size); + if (!version_str[++chunk_count * chunk_size - 1]) + /* Zero padding detected: end of string. */ + break; + /* Check if there is enough room for reading one more chunk. */ + } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); + version_str[chunk_count * chunk_size] = '\0'; + printk(BIOS_INFO, "Firmware version: %s\n", version_str); + if (cr50_parse_fw_version(version_str, &cr50_firmware_version)) { + printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); + return -1; + } + if (CR50_BOARD_CFG_VALUE) { + if (first_access_this_boot()) + cr50_set_board_cfg(); + } } return 0; } @@ -581,9 +688,9 @@ union fifo_transfer_buffer { * Transfer requested number of bytes to or from TPM FIFO, accounting for the * current burst count value. */ -static void fifo_transfer(size_t transfer_size, - union fifo_transfer_buffer buffer, - enum fifo_transfer_direction direction) +static int __must_check fifo_transfer(size_t transfer_size, + union fifo_transfer_buffer buffer, + enum fifo_transfer_direction direction) { size_t transaction_size; size_t burst_count; @@ -604,18 +711,23 @@ static void fifo_transfer(size_t transfer_size, */ transaction_size = MIN(transaction_size, 64); - if (direction == fifo_receive) - tpm2_read_reg(TPM_DATA_FIFO_REG, - buffer.rx_buffer + handled_so_far, - transaction_size); - else - tpm2_write_reg(TPM_DATA_FIFO_REG, - buffer.tx_buffer + handled_so_far, - transaction_size); + if (direction == fifo_receive) { + if (!tpm2_read_reg(TPM_DATA_FIFO_REG, + buffer.rx_buffer + handled_so_far, + transaction_size)) + return 0; + } else { + if (!tpm2_write_reg(TPM_DATA_FIFO_REG, + buffer.tx_buffer + handled_so_far, + transaction_size)) + return 0; + } handled_so_far += transaction_size; } while (handled_so_far != transfer_size); + + return 1; } size_t tpm2_process_command(const void *tpm2_command, size_t command_size, @@ -648,7 +760,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, } /* Let the TPM know that the command is coming. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } /* * TPM commands and responses written to and read from the FIFO @@ -662,10 +777,17 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, * burst count or the maximum PDU size, whatever is smaller. */ fifo_buffer.tx_buffer = cmd_body; - fifo_transfer(command_size, fifo_buffer, fifo_transmit); + if (!fifo_transfer(command_size, fifo_buffer, fifo_transmit)) { + printk(BIOS_ERR, "fifo_transfer %zd command bytes failed\n", + command_size); + return 0; + } /* Now tell the TPM it can start processing the command. */ - write_tpm_sts(TPM_STS_GO); + if (!write_tpm_sts(TPM_STS_GO)) { + printk(BIOS_ERR, "TPM_STS_GO failed\n"); + return 0; + } /* Now wait for it to report that the response is ready. */ expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; @@ -708,7 +830,11 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, */ bytes_to_go = payload_size - 1 - HEADER_SIZE; fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; - fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); + if (!fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive)) { + printk(BIOS_ERR, "fifo_transfer %zd receive bytes failed\n", + bytes_to_go); + return 0; + } /* Verify that there is still data to read. */ read_tpm_sts(&status); @@ -733,7 +859,15 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, } /* Move the TPM back to idle state. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } return payload_size; } + +void cr50_get_firmware_version(struct cr50_firmware_version *version) +{ + memcpy(version, &cr50_firmware_version, sizeof(*version)); +} diff --git a/src/drivers/spi/tpm/tpm.h b/src/drivers/spi/tpm/tpm.h index be98ed05df..f48943e020 100644 --- a/src/drivers/spi/tpm/tpm.h +++ b/src/drivers/spi/tpm/tpm.h @@ -16,6 +16,13 @@ struct tpm2_info { uint16_t revision; }; +/* Structure describing the elements of Cr50 firmware version. */ +struct cr50_firmware_version { + int epoch; + int major; + int minor; +}; + /* * Initialize a TPM2 device: read its id, claim locality of zero, verify that * this indeed is a TPM2 device. Use the passed in handle to access the right @@ -25,7 +32,6 @@ struct tpm2_info { */ int tpm2_init(struct spi_slave *spi_if); - /* * Each command processing consists of sending the command to the TPM, by * writing it into the FIFO register, then polling the status register until @@ -41,4 +47,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, /* Get information about previously initialized TPM device. */ void tpm2_get_info(struct tpm2_info *info); +/* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ +bool cr50_is_long_interrupt_pulse_enabled(void); + +/* Get the cr50 firmware version information. */ +void cr50_get_firmware_version(struct cr50_firmware_version *version); + #endif /* ! __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H */ diff --git a/src/drivers/ti/sn65dsi86bridge/Kconfig b/src/drivers/ti/sn65dsi86bridge/Kconfig new file mode 100644 index 0000000000..b7abb34231 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_TI_SN65DSI86BRIDGE + bool + default n + help + TI SN65DSI86 eDP bridge driver diff --git a/src/drivers/ti/sn65dsi86bridge/Makefile.inc b/src/drivers/ti/sn65dsi86bridge/Makefile.inc new file mode 100644 index 0000000000..b146fe363c --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_TI_SN65DSI86BRIDGE) += sn65dsi86bridge.c diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c new file mode 100644 index 0000000000..44a80884aa --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -0,0 +1,489 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sn65dsi86bridge.h" + +#define BRIDGE_GETHIGHERBYTE(x) (uint8_t)((x & 0xff00) >> 8) +#define BRIDGE_GETLOWERBYTE(x) (uint8_t)((x & 0x00ff)) + +/* fudge factor required to account for 8b/10b encoding */ +#define DP_CLK_FUDGE_NUM 10 +#define DP_CLK_FUDGE_DEN 8 + +/* DPCD */ +#define DP_BRIDGE_DPCD_REV 0x700 +#define DP_BRIDGE_11 0x00 +#define DP_BRIDGE_12 0x01 +#define DP_BRIDGE_13 0x02 +#define DP_BRIDGE_14 0x03 +#define DP_BRIDGE_CONFIGURATION_SET 0x10a +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LANE_COUNT 0x002 +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ +#define DP_LANE_COUNT_MASK 0xf + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_1_62 0x06 +#define DP_LINK_BW_2_7 0x0a +#define DP_LINK_BW_5_4 0x14 + +#define AUX_CMD_SEND 0x1 +#define MIN_DSI_CLK_FREQ_MHZ 40 +#define MAX_DSI_CLK_FREQ_MHZ 750 + +enum bridge_regs { + SN_DPPLL_SRC_REG = 0x0A, + SN_PLL_ENABLE_REG = 0x0D, + SN_DSI_LANES_REG = 0x10, + SN_DSIA_CLK_FREQ_REG = 0x12, + SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG = 0x20, + SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG = 0x21, + SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG = 0x24, + SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG = 0x25, + SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG = 0x2C, + SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG = 0x2D, + SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG = 0x30, + SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG = 0x31, + SN_CHA_HORIZONTAL_BACK_PORCH_REG = 0x34, + SN_CHA_VERTICAL_BACK_PORCH_REG = 0x36, + SN_CHA_HORIZONTAL_FRONT_PORCH_REG = 0x38, + SN_CHA_VERTICAL_FRONT_PORCH_REG = 0x3A, + SN_COLOR_BAR_REG = 0x3C, + SN_ENH_FRAME_REG = 0x5A, + SN_DATA_FORMAT_REG = 0x5B, + SN_HPD_DISABLE_REG = 0x5C, + SN_I2C_CLAIM_ADDR_EN1 = 0x60, + SN_AUX_WDATA_REG_0 = 0x64, + SN_AUX_WDATA_REG_1 = 0x65, + SN_AUX_WDATA_REG_2 = 0x66, + SN_AUX_WDATA_REG_3 = 0x67, + SN_AUX_WDATA_REG_4 = 0x68, + SN_AUX_WDATA_REG_5 = 0x69, + SN_AUX_WDATA_REG_6 = 0x6A, + SN_AUX_WDATA_REG_7 = 0x6B, + SN_AUX_WDATA_REG_8 = 0x6C, + SN_AUX_WDATA_REG_9 = 0x6D, + SN_AUX_WDATA_REG_10 = 0x6E, + SN_AUX_WDATA_REG_11 = 0x6F, + SN_AUX_WDATA_REG_12 = 0x70, + SN_AUX_WDATA_REG_13 = 0x71, + SN_AUX_WDATA_REG_14 = 0x72, + SN_AUX_WDATA_REG_15 = 0x73, + SN_AUX_ADDR_19_16_REG = 0x74, + SN_AUX_ADDR_15_8_REG = 0x75, + SN_AUX_ADDR_7_0_REG = 0x76, + SN_AUX_LENGTH_REG = 0x77, + SN_AUX_CMD_REG = 0x78, + SN_AUX_RDATA_REG_0 = 0x79, + SN_AUX_RDATA_REG_1 = 0x7A, + SN_AUX_RDATA_REG_2 = 0x7B, + SN_AUX_RDATA_REG_3 = 0x7C, + SN_AUX_RDATA_REG_4 = 0x7D, + SN_AUX_RDATA_REG_5 = 0x7E, + SN_AUX_RDATA_REG_6 = 0x7F, + SN_AUX_RDATA_REG_7 = 0x80, + SN_AUX_RDATA_REG_8 = 0x81, + SN_AUX_RDATA_REG_9 = 0x82, + SN_AUX_RDATA_REG_10 = 0x83, + SN_AUX_RDATA_REG_11 = 0x84, + SN_AUX_RDATA_REG_12 = 0x85, + SN_AUX_RDATA_REG_13 = 0x86, + SN_AUX_RDATA_REG_14 = 0x87, + SN_AUX_RDATA_REG_15 = 0x88, + SN_SSC_CONFIG_REG = 0x93, + SN_DATARATE_CONFIG_REG = 0x94, + SN_ML_TX_MODE_REG = 0x96, + SN_AUX_CMD_STATUS_REG = 0xF4, +}; + +enum { + HPD_ENABLE = 0x0, + HPD_DISABLE = 0x1, +}; + +enum { + SOT_ERR_TOL_DSI = 0x0, + CHB_DSI_LANES = 0x1, + CHA_DSI_LANES = 0x2, + DSI_CHANNEL_MODE = 0x3, + LEFT_RIGHT_PIXELS = 0x4, +}; + +enum vstream_config { + VSTREAM_DISABLE = 0, + VSTREAM_ENABLE = 1, +}; + +enum i2c_over_aux { + I2C_OVER_AUX_WRITE_MOT_0 = 0x0, + I2C_OVER_AUX_READ_MOT_0 = 0x1, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4, + I2C_OVER_AUX_WRITE_MOT_1 = 0x5, + I2C_OVER_AUX_READ_MOT_1 = 0x6, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7, + NATIVE_AUX_WRITE = 0x8, + NATIVE_AUX_READ = 0x9, +}; + +enum ml_tx_mode { + MAIN_LINK_OFF = 0x0, + NORMAL_MODE = 0x1, + TPS1 = 0x2, + TPS2 = 0x3, + TPS3 = 0x4, + PRBS7 = 0x5, + HBR2_COMPLIANCE_EYE_PATTERN = 0x6, + SYMBOL_ERR_RATE_MEASUREMENT_PATTERN = 0x7, + CUTSOM_PATTERN = 0x8, + FAST_LINK_TRAINING = 0x9, + SEMI_AUTO_LINK_TRAINING = 0xa, + REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, +}; + +enum dpcd_request { + DPCD_READ = 0x0, + DPCD_WRITE = 0x1, +}; + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +/* + * LUT index corresponds to register value and LUT values corresponds + * to dp data rate supported by the bridge in Mbps unit. + */ +static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = { + 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 +}; + +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + int ret; + u8 edid[EDID_LENGTH * 2]; + int edid_size = EDID_LENGTH; + + /* Send I2C command to claim EDID I2c slave */ + i2c_writeb(bus, chip, SN_I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1); + + /* read EDID */ + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); + return CB_ERR; + } + + if (edid[EDID_EXTENSION_FLAG]) { + edid_size += EDID_LENGTH; + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, + &edid[EDID_LENGTH], EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "Failed to read EDID ext block.\n"); + return CB_ERR; + } + } + + if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { + printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static void sn65dsi86_bridge_dpcd_request(uint8_t bus, + uint8_t chip, + unsigned int dpcd_reg, + unsigned int len, + enum dpcd_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + + while (len) { + length = MIN(len, 16); + + i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF); + i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ + if (request == DPCD_WRITE) { + reg = SN_AUX_WDATA_REG_0; + for (i = 0; i < length; i++) + i2c_writeb(bus, chip, reg++, *data++); + + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4)); + } else { + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4)); + if (!wait_ms(100, + !i2c_readb(bus, chip, SN_AUX_CMD_REG, + &buf) && !(buf & AUX_CMD_SEND))) { + printk(BIOS_ERR, "ERROR: aux command send failed\n"); + } + + reg = SN_AUX_RDATA_REG_0; + for (i = 0; i < length; i++) { + i2c_readb(bus, chip, reg++, &buf); + *data++ = buf; + } + } + + len -= length; + } +} + +static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[]) +{ + unsigned int rate_per_200khz; + uint8_t dpcd_val; + int i, j; + + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); + if (dpcd_val >= DP_BRIDGE_14) { + /* eDP 1.4 devices must provide a custom table */ + uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, + sizeof(sink_rates), + DPCD_READ, (void *)sink_rates); + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + rate_per_200khz = le16_to_cpu(sink_rates[i]); + + if (!rate_per_200khz) + break; + + for (j = 0; + j < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + j++) { + if (sn65dsi86_bridge_dp_rate_lut[j] * (MHz / KHz) == + rate_per_200khz * 200) + rate_valid[j] = true; + } + } + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); i++) { + if (rate_valid[i]) + return; + } + + printk(BIOS_ERR, "No matching eDP rates in table; falling back\n"); + } + + /* On older versions best we can do is use DP_MAX_LINK_RATE */ + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + + switch (dpcd_val) { + default: + printk(BIOS_ERR, "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); + /* fall through */ + case DP_LINK_BW_5_4: + rate_valid[7] = 1; + /* fall through */ + case DP_LINK_BW_2_7: + rate_valid[4] = 1; + /* fall through */ + case DP_LINK_BW_1_62: + rate_valid[1] = 1; + break; + } +} + +static void sn65dsi86_bridge_set_dsi_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, + uint32_t num_of_lanes, uint32_t bpp) +{ + uint64_t pixel_clk_hz; + uint64_t stream_bit_rate_mhz; + uint64_t min_req_dsi_clk; + + pixel_clk_hz = edid->mode.pixel_clock * KHz; + stream_bit_rate_mhz = (pixel_clk_hz * bpp) / MHz; + + /* For TI the clock frequencies are half the bit rates */ + min_req_dsi_clk = stream_bit_rate_mhz / (num_of_lanes * 2); + + /* for each increment in val, frequency increases by 5MHz */ + min_req_dsi_clk = MAX(MIN_DSI_CLK_FREQ_MHZ, + MIN(MAX_DSI_CLK_FREQ_MHZ, min_req_dsi_clk)) / 5; + i2c_writeb(bus, chip, SN_DSIA_CLK_FREQ_REG, min_req_dsi_clk); +} + +static void sn65dsi86_bridge_set_dp_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lanes) +{ + uint64_t stream_bit_rate_khz; + bool rate_valid[ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)] = { }; + uint64_t dp_rate_mhz; + int dp_rate_idx, i; + + stream_bit_rate_khz = edid->mode.pixel_clock * 18; + + /* Calculate minimum DP data rate, taking 80% as per DP spec */ + dp_rate_mhz = DIV_ROUND_UP(stream_bit_rate_khz * DP_CLK_FUDGE_NUM, + KHz * num_of_lanes * DP_CLK_FUDGE_DEN); + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut) - 1; i++) + if (sn65dsi86_bridge_dp_rate_lut[i] > dp_rate_mhz) + break; + + sn65dsi86_bridge_valid_dp_rates(bus, chip, rate_valid); + + /* Train until we run out of rates */ + for (dp_rate_idx = i; + dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + dp_rate_idx++) + if (rate_valid[dp_rate_idx]) + break; + + if (dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)) + i2c_write_field(bus, chip, SN_DATARATE_CONFIG_REG, dp_rate_idx, 8, 5); + else + printk(BIOS_ERR, "ERROR: valid dp rate not found"); +} + +static void sn65dsi86_bridge_set_bridge_active_timing(uint8_t bus, + uint8_t chip, + struct edid *edid) +{ + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_BACK_PORCH_REG, + edid->mode.hbl - edid->mode.hso - edid->mode.hspw); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_BACK_PORCH_REG, + edid->mode.vbl - edid->mode.vso - edid->mode.vspw); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, + edid->mode.hso); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_FRONT_PORCH_REG, + edid->mode.vso); +} + +static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip) +{ + uint8_t buf; + + /* enable pll lock */ + i2c_writeb(bus, chip, SN_PLL_ENABLE_REG, 0x1); + + if (!wait_ms(500, + !(i2c_readb(bus, chip, SN_DPPLL_SRC_REG, &buf)) && + (buf & BIT(7)))) { + printk(BIOS_ERR, "ERROR: PLL lock failure\n"); + } + + /* + * The SN65DSI86 only supports ASSR Display Authentication method and + * this method is enabled by default. An eDP panel must support this + * authentication method. We need to enable this method in the eDP panel + * at DisplayPort address 0x0010A prior to link training. + */ + buf = 0x1; + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); + + int i; /* Kernel driver suggests to retry this up to 10 times if it fails. */ + for (i = 0; i < 10; i++) { + i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, SEMI_AUTO_LINK_TRAINING); + + if (!wait_ms(500, !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && + (buf == NORMAL_MODE || buf == MAIN_LINK_OFF))) { + printk(BIOS_ERR, "ERROR: unexpected link training state: %#x\n", buf); + return; + } + if (buf == NORMAL_MODE) + return; + } + + printk(BIOS_ERR, "ERROR: Link training failed 10 times\n"); +} + +static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable) +{ + if (enable) + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1, 3); + else + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_DISABLE, 1, 3); +} + +static int sn65dsi86_bridge_dp_lane_config(uint8_t bus, uint8_t chip) +{ + uint8_t lane_count; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); + lane_count &= DP_LANE_COUNT_MASK; + i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(lane_count, 3), 3, 4); + + return lane_count; +} + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk) +{ + /* disable HPD */ + i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0); + + /* set refclk to 19.2 MHZ */ + i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1); +} + +void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lanes, + uint32_t dsi_bpp) +{ + int dp_lanes; + + /* DSI Lanes config */ + i2c_write_field(bus, chip, SN_DSI_LANES_REG, (4 - num_of_lanes), 3, 3); + + /* DP Lane config */ + dp_lanes = sn65dsi86_bridge_dp_lane_config(bus, chip); + + sn65dsi86_bridge_set_dsi_clock_range(bus, chip, edid, num_of_lanes, dsi_bpp); + + sn65dsi86_bridge_set_dp_clock_range(bus, chip, edid, dp_lanes); + + /* Disable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 0); + sn65dsi86_bridge_link_training(bus, chip); + sn65dsi86_bridge_set_bridge_active_timing(bus, chip, edid); + + /* DP BPP config */ + i2c_writeb(bus, chip, SN_DATA_FORMAT_REG, 0x1); + + /* color bar disabled */ + i2c_writeb(bus, chip, SN_COLOR_BAR_REG, 0x5); + + /* Enable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 1); +} diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h new file mode 100644 index 0000000000..83b940bbb4 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TI_SN65DSI86BRIDGE_H +#define __TI_SN65DSI86BRIDGE_H + +#include + +enum dp_pll_clk_src { + SN65_SEL_12MHZ = 0x0, + SN65_SEL_19MHZ = 0x1, + SN65_SEL_26MHZ = 0x2, + SN65_SEL_27MHZ = 0x3, + SN65_SEL_38MHZ = 0x4, +}; + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk); +void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lines, + uint32_t dsi_bpp); +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out); + +#endif diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 8508210fc6..baf760b4b0 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -5,3 +5,14 @@ config TPM_INIT help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. + +config TPM_PPI + bool "Generate ACPI code to implement TPM physical presence interface" + depends on TPM1 || TPM2 + depends on HAVE_ACPI_TABLES + depends on !CHROMEOS + default y if PAYLOAD_TIANOCORE + help + This driver automatically generates ACPI tables for the Physical + Presence Interface defined by the TCG. If not activated only a stub + will be generated without any functionality. diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 4e80600ddf..af6e5a21c1 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1 +1,7 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c + +ifeq ($(CONFIG_TPM_PPI),y) +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi.c +else +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c +endif diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c new file mode 100644 index 0000000000..88dd649954 --- /dev/null +++ b/src/drivers/tpm/ppi.c @@ -0,0 +1,726 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tpm_ppi.h" + +#define BCD(x, y) (((x) << 4) | ((y) << 0)) + +static void set_package_element_op(const char *package_name, unsigned int element, + uint8_t src_op) +{ + acpigen_write_store(); + acpigen_emit_byte(src_op); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +static void set_package_element_name(const char *package_name, unsigned int element, + const char *src) +{ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +/* PPI function is passed in src_op. Converted to Local2. Clobbers Local1 and Local2 */ +static void verify_supported_ppi(uint8_t src_op) +{ + /* + * Old OSes incorrectly pass a Buffer instead of a Package. + * See TCG Physical Presence Interface Specification Chapter 8.1.2 for details. + */ + + /* If (ObjectType(Arg3) == Package) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 4); + acpigen_get_package_op_element(src_op, 0, LOCAL2_OP); + acpigen_pop_len(); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_to_integer(src_op, LOCAL2_OP); + acpigen_pop_len(); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + /* + * Note: Must fake success for 1-4, 6-13, 15-16, 19-20 + * see "Trusted Execution Environment ACPI Profile" + * + * Even if not available, the TPM 1.2 PPI must be advertised as + * supported. Tests showed that Windows relies on it, even when + * a TPM2.0 is present! + * The functions aren't actually used when a TPM2.0 is present... + * Without this the Windows TPM 2.0 stack refuses to work. + */ + + /* + * Check if we have TPM1.2 but a TPM2 PPI function was called + * or if we have TPM2.0 but a TPM1.2 PPI function was called. + */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ZERO_OP : ONE_OP); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer(PPI2_RET_SUCCESS); /* As per TPM spec */ + acpigen_pop_len(); + acpigen_write_return_integer(PPI2_RET_NOT_SUPPORTED); + + acpigen_pop_len(); +} + +/* TPM PPI functions */ + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, 2); +} + + /* + * PPI 1.0: 2.1.1 Get Physical Presence Interface Version + * + * Arg2 (Integer): Function Index = 1 + * Arg3 (Package): Arguments = Empty Package + * + * Returns: Type: String + */ +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +/* + * Submit TPM Operation Request to Pre-OS Environment [Windows optional] + * PPI 1.0: 2.1.3 Submit TPM Operation Request to Pre-OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 2 + * Arg3 (Package): Arguments = Package: Type: Integer + * Operation Value of the Request + * + * Returns: Type: Integer + * 0: Success + * 1: Operation Value of the Request Not Supported + * 2: General Failure + */ +static void tpm_ppi_func2_cb(void *arg) +{ + /* Revision 1 */ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^USER"); + + acpigen_write_return_integer(PPI2_RET_SUCCESS); + acpigen_pop_len(); + + acpigen_write_return_integer(PPI2_RET_GENERAL_FAILURE); +} + +/* + * PPI 1.0: 2.1.4 Get Pending TPM Operation Requested By the OS + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 3 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer (optional)) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Pending TPM operation requested by OS + * Integer 3: + * Pending TPM operation argument requested by OS + */ +static void tpm_ppi_func3_cb(void *arg) +{ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_GENERAL_FAILURE); + acpigen_emit_byte(LOCAL0_OP); + + /* ^TPM3 [0] = PPI3_RET_GENERAL_FAILURE */ + set_package_element_op("^TPM3", 0, LOCAL0_OP); + + /* ^TPM2 [0] = PPI3_RET_GENERAL_FAILURE */ + set_package_element_op("^TPM2", 0, LOCAL0_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM2 [0] = PPI3_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM2", 0, LOCAL1_OP); + + /* ^TPM2 [1] = ^CMDR */ + set_package_element_name("^TPM2", 1, "^CMDR"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM2"); + acpigen_pop_len(); + + /* + * A return value of {0, 23, 1} indicates that operation 23 + * with argument 1 is pending. + */ + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + + /* ^TPM3 [0] = PPI3_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + /* ^TPM3 [1] = ^CMDR */ + set_package_element_name("^TPM3", 1, "^CMDR"); + + /* ^TPM3 [2] = ^OARG */ + set_package_element_name("^TPM3", 2, "^OARG"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.0: 2.1.5 Get Platform-Specific Action to Transition to Pre-OS Environment + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 4 + * Arg3 (Package): Empty package + * + * Returns: Type: Integer + * 0: None + * 1: Shutdown + * 2: Reboot + * 3: Vendor specific + */ +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(PPI4_RET_REBOOT); +} + +/* + * PPI 1.0: 2.1.6 Return TPM Operation Response to OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Most recent TPM operation requested by OS + * Integer 3: + * Response to most recent TPM operation requested by OS + */ +static void tpm_ppi_func5_cb(void *arg) +{ + /* ^TPM3 [0] = PPI5_RET_GENERAL_FAILURE */ + acpigen_write_store(); + acpigen_write_integer(PPI5_RET_GENERAL_FAILURE); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM3 [0] = PPI5_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI5_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + /* ^TPM3 [1] = ^LCMD */ + set_package_element_name("^TPM3", 1, "^LCMD"); + + /* ^TPM3 [2] = ^RESU */ + set_package_element_name("^TPM3", 2, "^RESU"); + + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.2: 2.1.6 Submit preferred user language [Windows optional] + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + */ +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 aka + * "not implemented". + */ + acpigen_write_return_byte(PPI6_RET_NOT_IMPLEMENTED); +} + +/* + * PPI 1.2: 2.1.7 Submit TPM Operation Request to Pre-OS Environment 2 + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Success + * 1: Not implemented + * 2: General Failure + * 3: Blocked by current BIOS settings + */ +static void tpm_ppi_func7_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + + /* Enforce use of Revision 1 that doesn't take an optional argument. */ + + /* Local0 = One */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Zero */ + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + + acpigen_write_return_byte(PPI7_RET_SUCCESS); + acpigen_pop_len(); + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Arg3 [1] */ + acpigen_get_package_op_element(ARG3_OP, 1, LOCAL3_OP); + acpigen_write_store(); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_namestring("^OARG"); + + acpigen_write_return_byte(PPI7_RET_SUCCESS); + acpigen_pop_len(); + + acpigen_write_return_byte(PPI7_RET_GENERAL_FAILURE); +} + +/* + * PPI 1.2: 2.1.8 Get User Confirmation Status for Operation + * + * Returns if a command is supported and allowed by firmware + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Not implemented + * 1: BIOS only + * 2: Blocked for OS by BIOS settings + * 3: Allowed and physical present user required + * 4: Allowed and physical present user not required + */ +static void tpm_ppi_func8_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL2_OP); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + acpigen_write_return_byte(0); /* Not implemented */ + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + if (CONFIG(TPM1)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm1_funcs[] = { + TPM_NOOP, + TPM_SET_NOPPICLEAR_TRUE, + TPM_SET_NOPPIMAINTAINANCE_TRUE, + TPM_SET_NOPPIPROVISION_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm1_funcs[i]); + acpigen_write_return_integer(PPI8_RET_ALLOWED); + acpigen_pop_len(); /* Pop : If */ + } + } else if (CONFIG(TPM2)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm2_funcs[i]); + acpigen_write_return_integer(PPI8_RET_ALLOWED); + acpigen_pop_len(); /* Pop : If */ + } + } + acpigen_write_return_integer(PPI8_RET_ALLOWED_WITH_PP); + + acpigen_pop_len(); + + acpigen_write_return_integer(PPI8_RET_NOT_IMPLEMENTED); +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + struct cb_tpm_ppi_payload_handshake *ppib; + + static const struct fieldlist list[] = { + FIELDLIST_OFFSET(0x100),// FIXME: Add support for func + FIELDLIST_NAMESTR("PPIN", 8),// Not used + FIELDLIST_NAMESTR("PPIP", 32),// Not used + FIELDLIST_NAMESTR("RESU", 32),// Result of the last operation (TPM error code) + FIELDLIST_NAMESTR("CMDR", 32),// The command requested by OS. 0 for NOP + FIELDLIST_NAMESTR("OARG", 32),// The command optional argument requested by OS + FIELDLIST_NAMESTR("LCMD", 32),// The last command requested by OS. + FIELDLIST_NAMESTR("FRET", 32),// Not used + }; + static const u8 tpm1_funcs[] = { + TPM_NOOP, + TPM_ENABLE, + TPM_DISABLE, + TPM_ACTIVATE, + TPM_DEACTIVATE, + TPM_CLEAR, + TPM_ENABLE_ACTIVATE, + TPM_DEACTIVATE_DISABLE, + TPM_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE, + TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE, + TPM_CLEAR_ENABLE_ACTIVATE, + TPM_SET_NOPPIPROVISION_FALSE, + TPM_SET_NOPPIPROVISION_TRUE, + TPM_ENABLE_ACTIVE_CLEAR, + TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE, + }; + static const u8 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_ENABLE, + TPM2_DISABLE, + TPM2_CLEAR, + TPM2_CLEAR_ENABLE_ACTIVE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE, + TPM2_ENABLE_CLEAR, + TPM2_ENABLE_CLEAR2, + TPM2_SET_PCR_BANKS, + TPM2_CHANGE_EPS, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_LOG_ALL_DIGEST, + TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY, + TPM2_ENABLE_BLOCK_SID, + TPM2_DISABLE_BLOCK_SID, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE, + }; + + /* + * On hot reset/ACPI S3 the contents are preserved. + */ + ppib = (void *)cbmem_add(CBMEM_ID_TPM_PPI, sizeof(*ppib)); + if (!ppib) { + printk(BIOS_ERR, "PPI: Failed to add CBMEM\n"); + return; + } + printk(BIOS_DEBUG, "PPI: Pending OS request: 0x%x (0x%x)\n", ppib->pprq, ppib->pprm); + printk(BIOS_DEBUG, "PPI: OS response: CMD 0x%x = 0x%x\n", ppib->lppr, ppib->pprp); + + /* Clear unsupported fields */ + ppib->next_step = 0; + ppib->ppin = 1; // Not used by ACPI. Read by EDK-2, must be 1. + ppib->ppip = 0; + ppib->fret = 0; + ppib->next_step = 0; + + bool found = false; + /* Fill in defaults, the TPM command executor may overwrite this list */ + memset(ppib->func, 0, sizeof(ppib->func)); + if (CONFIG(TPM1)) { + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + ppib->func[tpm1_funcs[i]] = 1; + if (ppib->pprq == tpm1_funcs[i]) + found = true; + } + } else { + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + ppib->func[tpm2_funcs[i]] = 1; + if (ppib->pprq == tpm2_funcs[i]) + found = true; + } + } + if (!found) { + // Set sane defaults + ppib->pprq = 0; + ppib->pprm = 0; + ppib->pprp = 0; + } + + /* Physical Presence OpRegion */ + struct opregion opreg = OPREGION("PPOP", SYSTEMMEMORY, (uintptr_t)ppib, + sizeof(*ppib)); + + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_name("TPM2"); + acpigen_write_package(2); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + acpigen_write_name("TPM3"); + acpigen_write_package(3); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + /* + * Returns One if the firmware implements this function. + * + * Arg0: Integer PPI function + */ + acpigen_write_method_serialized("FUNC", 1); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(VENDOR_SPECIFIC_OFFSET); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + /* TPPF = CreateField("PPOP", Local0) */ + acpigen_emit_byte(CREATE_BYTE_OP); + acpigen_emit_namestring("PPOP"); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_namestring("TPPF"); + + /* Local0 = ToInteger("TPPF") */ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_namestring("TPPF"); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_return_op(LOCAL0_OP); + acpigen_pop_len(); /* Method */ + + /* + * Returns One if the PPI spec supports this functions. + * That doesn't necessarily mean that the firmware implemtents it, or the + * TPM can execute the function. + * + * Arg0: Integer PPI function + * Arg1: Integer TPMversion (0: TPM2, 1: TPM1.2) + */ + acpigen_write_method("FSUP", 2); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(VENDOR_SPECIFIC_OFFSET); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm1_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm2_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_return_integer(0); + acpigen_pop_len(); /* Method */ + + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. + */ + DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], + ARRAY_SIZE(tpm_ppi_callbacks), NULL), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], + ARRAY_SIZE(tpm_mci_callbacks), NULL), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} + +void lb_tpm_ppi(struct lb_header *header) +{ + struct lb_tpm_physical_presence *tpm_ppi; + void *ppib; + + ppib = cbmem_find(CBMEM_ID_TPM_PPI); + if (!ppib) + return; + + tpm_ppi = (struct lb_tpm_physical_presence *)lb_new_record(header); + tpm_ppi->tag = LB_TAG_TPM_PPI_HANDOFF; + tpm_ppi->size = sizeof(*tpm_ppi); + tpm_ppi->ppi_address = (uintptr_t)ppib; + tpm_ppi->tpm_version = CONFIG(TPM1) ? LB_TPM_VERSION_TPM_VERSION_1_2 : + LB_TPM_VERSION_TPM_VERSION_2; + + tpm_ppi->ppi_version = BCD(1, 3); +} diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c new file mode 100644 index 0000000000..1e3a7fcb27 --- /dev/null +++ b/src/drivers/tpm/ppi_stub.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "tpm_ppi.h" + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, sizeof(buf)); +} + +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +static void tpm_ppi_func2_cb(void *arg) +{ + /* Submit operations: drop on the floor and return success. */ + acpigen_write_return_byte(PPI2_RET_SUCCESS); +} + +static void tpm_ppi_func3_cb(void *arg) +{ + /* Pending operation: none. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(2); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} + +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(2); +} + +static void tpm_ppi_func5_cb(void *arg) +{ + /* Operation response: no operation executed. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(3); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} + +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 AKA + * "not implemented". + */ + acpigen_write_return_byte(PPI6_RET_NOT_IMPLEMENTED); +} + +static void tpm_ppi_func7_cb(void *arg) +{ + /* Submit operations: deny. */ + acpigen_write_return_byte(PPI7_RET_BLOCKED_BY_FIRMWARE); +} + +static void tpm_ppi_func8_cb(void *arg) +{ + /* All actions are forbidden. */ + acpigen_write_return_byte(PPI8_RET_FIRMWARE_ONLY); +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. Spec allows user to cancel all commands and/or + * configure BIOS to reject commands. So we pretend that + * user did just this: cancelled everything. If user + * really wants to clear TPM the only option now is to + * do it manually in payload. + */ + DSM_UUID(TPM_PPI_UUID, tpm_ppi_callbacks, + ARRAY_SIZE(tpm_ppi_callbacks), NULL), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, tpm_mci_callbacks, + ARRAY_SIZE(tpm_mci_callbacks), NULL), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h new file mode 100644 index 0000000000..4d468ba84d --- /dev/null +++ b/src/drivers/tpm/tpm_ppi.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _TPM_PPI_H_ +#define _TPM_PPI_H_ + +#include +#include + +#if CONFIG(HAVE_ACPI_TABLES) +void tpm_ppi_acpi_fill_ssdt(const struct device *dev); +#else +static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ +} +#endif + +/* Return codes */ +/* Function 2 */ +#define PPI2_RET_SUCCESS 0 +#define PPI2_RET_NOT_SUPPORTED 1 +#define PPI2_RET_GENERAL_FAILURE 2 + +/* Function 3 */ +#define PPI3_RET_SUCCESS 0 +#define PPI3_RET_GENERAL_FAILURE 1 + +/* Function 4 */ +#define PPI4_RET_NONE 0 +#define PPI4_RET_SHUTDOWN 1 +#define PPI4_RET_REBOOT 2 +#define PPI4_RET_OS_VENDOR_SPECIFIC 3 + +/* Function 5 */ +#define PPI5_RET_SUCCESS 0 +#define PPI5_RET_GENERAL_FAILURE 1 + +/* Function 6 */ +#define PPI6_RET_NOT_IMPLEMENTED 3 + +/* Function 7 */ +#define PPI7_RET_SUCCESS 0 +#define PPI7_RET_NOT_IMPLEMENTED 1 +#define PPI7_RET_GENERAL_FAILURE 2 +#define PPI7_RET_BLOCKED_BY_FIRMWARE 3 + +/* Function 8 */ +#define PPI8_RET_NOT_IMPLEMENTED 0 +#define PPI8_RET_FIRMWARE_ONLY 1 +#define PPI8_RET_BLOCKED_FOR_OS_BY_FW 2 +#define PPI8_RET_ALLOWED_WITH_PP 3 +#define PPI8_RET_ALLOWED 4 + +/* TCG Physical Presence Interface */ +#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TCG Memory Clear Interface */ +#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 1 Physical Presence Interface Operation Summary for TPM 1.2 + */ +#define TPM_NOOP 0 +#define TPM_ENABLE 1 +#define TPM_DISABLE 2 +#define TPM_ACTIVATE 3 +#define TPM_DEACTIVATE 4 +#define TPM_CLEAR 5 +#define TPM_ENABLE_ACTIVATE 6 +#define TPM_DEACTIVATE_DISABLE 7 +#define TPM_SETOWNERINSTALL_TRUE 8 +#define TPM_SETOWNERINSTALL_FALSE 9 +#define TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE 10 +#define TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11 +#define TPM_CLEAR_ENABLE_ACTIVATE 14 +#define TPM_SET_NOPPIPROVISION_FALSE 15 +#define TPM_SET_NOPPIPROVISION_TRUE 16 +#define TPM_SET_NOPPICLEAR_FALSE 17 +#define TPM_SET_NOPPICLEAR_TRUE 18 +#define TPM_SET_NOPPIMAINTAINANCE_FALSE 19 +#define TPM_SET_NOPPIMAINTAINANCE_TRUE 20 +#define TPM_ENABLE_ACTIVE_CLEAR 21 +#define TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE 22 + +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 2 Physical Presence Interface Operation Summary for TPM 2.0 + */ +#define TPM2_NOOP 0 +#define TPM2_ENABLE 1 +#define TPM2_DISABLE 2 +#define TPM2_CLEAR 5 +#define TPM2_CLEAR_ENABLE_ACTIVE 14 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18 +#define TPM2_ENABLE_CLEAR 21 +#define TPM2_ENABLE_CLEAR2 22 +#define TPM2_SET_PCR_BANKS 23 +#define TPM2_CHANGE_EPS 24 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32 +#define TPM2_LOG_ALL_DIGEST 33 +#define TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY 34 +#define TPM2_ENABLE_BLOCK_SID 96 +#define TPM2_DISABLE_BLOCK_SID 97 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE 98 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE 99 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE 100 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE 101 + +#define VENDOR_SPECIFIC_OFFSET 0x80 + + /* + * The layout of the buffer matches the QEMU virtual memory device that is generated + * by QEMU. See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' for details. + */ +struct cb_tpm_ppi_payload_handshake { + uint8_t func[256]; /* Firmware sets values for each supported operation. + * See defined values below. */ + uint8_t ppin; /* SMI interrupt to use. Set by firmware. + * Not supported. */ + uint32_t ppip; /* ACPI function index to pass to SMM code. + * Set by ACPI. Not supported. */ + uint32_t pprp; /* Result of last executed operation. + * Set by firmware. See function index 5 for values. */ + uint32_t pprq; /* Operation request number to execute. + * See 'Physical Presence Interface Operation Summary' + * tables in specs. Set by ACPI. */ + uint32_t pprm; /* Operation request optional parameter. + * Values depend on operation. Set by ACPI. */ + uint32_t lppr; /* Last executed operation request number. + * Copied from pprq field by firmware. */ + uint32_t fret; /* Result code from SMM function. Not supported. */ + uint8_t res1[0x040]; /* Reserved */ + uint8_t next_step; /* Operation to execute after reboot by firmware. + * Used by firmware. */ +} __packed; + +void lb_tpm_ppi(struct lb_header *header); + +#endif /* _TPM_PPI_H_ */ diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index f9d9d8fa19..d4b14aac04 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -46,7 +46,7 @@ static void uart_acpi_fill_ssdt(const struct device *dev) int reset_gpio_index = -1; int enable_gpio_index = -1; - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index d8a8b9167e..8ba39efc6d 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - struct resource *res = find_resource(dev, 0x10); + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; @@ -26,7 +26,6 @@ static void oxford_oxpcie_enable(struct device *dev) printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); } - static void oxford_oxpcie_set_resources(struct device *dev) { pci_dev_set_resources(dev); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b012c5a77a..ff7d0cfd8a 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -55,9 +55,9 @@ static int oxpcie_uart_active(void) return oxpcie_present; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { - if ((idx >= 0) && (idx < 8) && oxpcie_uart_active()) + if ((idx < 8) && oxpcie_uart_active()) return uart0_base + idx * 0x200; return 0; } diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2b81e76693..0a73d829ad 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -5,11 +5,11 @@ #include #include -void uart_init(int idx) +void uart_init(unsigned int idx) { } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -17,7 +17,7 @@ void uart_tx_byte(int idx, unsigned char data) uart_tx_flush(idx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -26,7 +26,7 @@ void uart_tx_flush(int idx) ; } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index d4d54c45f4..1f5f0f721b 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef __DRIVERS_UART_PL011_H #define __DRIVERS_UART_PL011_H diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 0c94c6aeaa..31181aa51f 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -45,7 +45,7 @@ static void sifive_uart_init(struct sifive_uart_registers *regs, int div) write32(®s->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0)); } -void uart_init(int idx) +void uart_init(unsigned int idx) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), @@ -58,7 +58,7 @@ static bool uart_can_tx(struct sifive_uart_registers *regs) return !(read32(®s->txdata) & TXDATA_FULL); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); @@ -68,7 +68,7 @@ void uart_tx_byte(int idx, unsigned char data) write32(®s->txdata, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t ip; @@ -79,7 +79,7 @@ void uart_tx_flush(int idx) } while (!(ip & IP_TXWM)); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t rxdata; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 22b79e8b6b..aa8c969530 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */ @@ -54,7 +53,6 @@ static unsigned char uart8250_rx_byte(unsigned int base_port) static void uart8250_init(unsigned int base_port, unsigned int divisor) { - DISABLE_TRACE; /* Disable interrupts */ outb(0x0, base_port + UART8250_IER); /* Enable FIFOs */ @@ -72,19 +70,18 @@ static void uart8250_init(unsigned int base_port, unsigned int divisor) /* Set to 3 for 8N1 */ outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR); - ENABLE_TRACE; } static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < ARRAY_SIZE(bases)) return bases[idx]; return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) { unsigned int div; @@ -94,17 +91,17 @@ void uart_init(int idx) } } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { uart8250_tx_flush(uart_platform_base(idx)); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 8d73272031..1834095014 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -97,7 +97,7 @@ static void uart8250_mem_init(void *base, unsigned int divisor) uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS); } -void uart_init(int idx) +void uart_init(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -109,7 +109,7 @@ void uart_init(int idx) uart8250_mem_init(base, div); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { void *base = uart_platform_baseptr(idx); if (!base) @@ -117,7 +117,7 @@ void uart_tx_byte(int idx, unsigned char data) uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -125,7 +125,7 @@ unsigned char uart_rx_byte(int idx) return uart8250_mem_rx_byte(base); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd926888d..73c69cc89f 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -44,7 +44,28 @@ struct drivers_usb_acpi_config { bool use_custom_pld; struct acpi_pld custom_pld; + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* + * Define a GPIO that shows the privacy status of the USB device. + * E.g. On a camera: if it is one, it is recording black frames. + * E.g. On a mic: if it is one, it is recording white-noise. + */ + struct acpi_gpio privacy_gpio; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index d33b7deeaf..9d68d0a923 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -10,13 +10,27 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { - /* - * Return false if reset GPIO is not provided. - */ - if (cfg->reset_gpio.pin_count == 0) - return false; + if (cfg->privacy_gpio.pin_count) + return true; - return true; + if (cfg->reset_gpio.pin_count && !cfg->has_power_resource) + return true; + + return false; +} + +static int usb_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index) +{ + int ret = -1; + + if (gpio->pin_count == 0) + return ret; + + acpi_device_write_gpio(gpio); + ret = *curr_index; + (*curr_index)++; + + return ret; } static void usb_acpi_fill_ssdt_generator(const struct device *dev) @@ -24,7 +38,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev) struct drivers_usb_acpi_config *config = dev->chip_info; const char *path = acpi_device_path(dev); - if (!dev->enabled || !path || !config) + if (!path || !config) return; /* Don't generate output for hubs, only ports */ @@ -49,18 +63,47 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev) /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { struct acpi_dp *dsd; + int idx = 0; + int reset_gpio_index = -1; + int privacy_gpio_index; acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); - acpi_device_write_gpio(&config->reset_gpio); + if (!config->has_power_resource) { + reset_gpio_index = usb_acpi_write_gpio( + &config->reset_gpio, &idx); + } + privacy_gpio_index = usb_acpi_write_gpio(&config->privacy_gpio, + &idx); acpigen_write_resourcetemplate_footer(); dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0, - config->reset_gpio.active_low); + if (reset_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "reset-gpio", path, + reset_gpio_index, 0, + config->reset_gpio.active_low); + if (privacy_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "privacy-gpio", path, + privacy_gpio_index, 0, + config->privacy_gpio.active_low); acpi_dp_write(dsd); } + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + NULL, + 0, + 0 + }; + acpi_device_add_power_res(&power_res_params); + } + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index 5ab85963f6..9635460bdb 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -40,7 +40,6 @@ struct ehci_caps { u8 portroute[8]; /* nibbles for routing - offset 0xC */ } __packed; - /* Section 2.3 Host Controller Operational Registers */ struct ehci_regs { diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 07d87ae6c5..2fbdf3aff9 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -421,8 +421,6 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) return -1; //-ENOTCONN; } - - static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; @@ -436,7 +434,7 @@ static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_d int playtimes = 3; /* Keep all endpoints disabled before any printk() call. */ - memset(info, 0, sizeof (*info)); + memset(info, 0, sizeof(*info)); info->ehci_base = ehci_bar; info->ehci_debug = ehci_bar + offset; info->ep_pipe[0].status |= DBGP_EP_NOT_PRESENT; @@ -549,7 +547,6 @@ try_next_port: } dprintk(BIOS_INFO, "EHCI done waiting for port.\n"); - /* Enable the debug port */ ctrl = read32(&ehci_debug->control); ctrl |= DBGP_CLAIM; @@ -600,7 +597,7 @@ next_debug_port: goto try_next_time; } - return -10; + return ret; } static int dbgp_enabled(void) diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index b7aad23450..c6a89bf5c0 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -17,7 +17,6 @@ #define USB_HUB_C_PORT_CONNECTION 16 #define USB_HUB_C_PORT_RESET 20 - static int hub_port_status(const char *buf, int feature) { return !!(buf[feature>>3] & (1<<(feature&0x7))); @@ -73,7 +72,6 @@ static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned char hub_a if (ret < 0) goto err; - /* Set PORT_RESET, poll for C_PORT_RESET. */ ret = dbgp_control_msg(ehci_debug, hub_addr, USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER, diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index b787127c2f..6a56ca2293 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -24,7 +24,6 @@ __weak enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) return CB_SUCCESS; } - static void xhci_count_ports(void *context, const struct xhci_supported_protocol *data) { struct port_counts *counts = context; @@ -187,11 +186,16 @@ static void xhci_add_devices(const struct device *dev) static void xhci_fill_ssdt(const struct device *dev) { int gpe; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) + return; printk(BIOS_DEBUG, "xHCI SSDT generation\n"); - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_ADR_pci_device(dev); acpigen_write_name_string("_DDN", "xHC - Extensible Host Controller"); diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index eda9130dd4..7d45eb6a85 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -5,3 +5,22 @@ config VPD default n help Enable support for flash based vital product data. + +config VPD_FMAP_NAME + string + depends on VPD + default "RO_VPD" + help + Name of the FMAP region created in the default FMAP to store VPD tables. + +config VPD_FMAP_SIZE + hex + depends on VPD + default 0x4000 + help + Size in bytes of the FMAP region created to store VPD tables. + +config SMBIOS_SERIAL_FROM_VPD + bool "Load device serial from VPD" + depends on VPD && GENERATE_SMBIOS_TABLES + default n diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index f54c4d0dd9..615e48a18e 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -5,3 +5,4 @@ verstage-$(CONFIG_VPD) += vpd_decode.c vpd.c romstage-$(CONFIG_VPD) += vpd_decode.c vpd.c postcar-$(CONFIG_VPD) += vpd_decode.c vpd.c ramstage-$(CONFIG_VPD) += vpd_decode.c vpd.c +ramstage-$(CONFIG_SMBIOS_SERIAL_FROM_VPD) += vpd_serial.c diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index c332a6e94c..d3ff37019d 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -3,10 +3,12 @@ #include #include #include +#include #include #include #include #include +#include #include "vpd.h" #include "vpd_decode.h" @@ -274,4 +276,25 @@ bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val) return false; } +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. Leaves `val` untouched if unsuccessful. + */ +bool vpd_get_int(const char *const key, const enum vpd_region region, int *const val) +{ + char value[11]; + + if (!vpd_gets(key, value, sizeof(value), region)) + return false; + + if (!isdigit(*value)) + return false; + + *val = (int)atol(value); + return true; +} + ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 25e0aed4ee..817867aba4 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -50,4 +50,13 @@ const void *vpd_find(const char *key, int *size, enum vpd_region region); bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val); +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. + */ +bool vpd_get_int(const char *key, enum vpd_region region, int *val); + #endif /* __VPD_H__ */ diff --git a/src/drivers/vpd/vpd_serial.c b/src/drivers/vpd/vpd_serial.c new file mode 100644 index 0000000000..528dcbb368 --- /dev/null +++ b/src/drivers/vpd/vpd_serial.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include + +#include "vpd.h" +#include "vpd_tables.h" + +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} diff --git a/src/drivers/wifi/Makefile.inc b/src/drivers/wifi/Makefile.inc deleted file mode 100644 index d37015c7d3..0000000000 --- a/src/drivers/wifi/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_WIFI) += generic.c diff --git a/src/drivers/wifi/Kconfig b/src/drivers/wifi/generic/Kconfig similarity index 77% rename from src/drivers/wifi/Kconfig rename to src/drivers/wifi/generic/Kconfig index 11ac7c1464..43c7d9ee1b 100644 --- a/src/drivers/wifi/Kconfig +++ b/src/drivers/wifi/generic/Kconfig @@ -1,12 +1,20 @@ -config DRIVERS_GENERIC_WIFI +config DRIVERS_WIFI_GENERIC bool default n - depends on HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI tables that are common to WiFi chipsets from multiple vendors. -if DRIVERS_GENERIC_WIFI +config DRIVERS_INTEL_WIFI + bool "Support Intel PCI-e WiFi adapters" + depends on PCI + default y if PCIEXP_PLUGIN_SUPPORT + select DRIVERS_WIFI_GENERIC + help + When enabled, add identifiers in ACPI and SMBIOS tables to + make OS drivers work with certain Intel PCI-e WiFi chipsets. + +if DRIVERS_WIFI_GENERIC config USE_SAR bool @@ -54,4 +62,4 @@ config DSAR_SET_NUM help There can be up to 3 optional SAR table sets. -endif # DRIVERS_GENERIC_WIFI +endif # DRIVERS_WIFI_GENERIC diff --git a/src/drivers/intel/wifi/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc similarity index 51% rename from src/drivers/intel/wifi/Makefile.inc rename to src/drivers/wifi/generic/Makefile.inc index 57f60afb99..c17844993d 100644 --- a/src/drivers/intel/wifi/Makefile.inc +++ b/src/drivers/wifi/generic/Makefile.inc @@ -1,7 +1,12 @@ -# SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c +ifeq ($(CONFIG_DRIVERS_WIFI_GENERIC),y) + +ramstage-y += generic.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH)) wifi_sar_defaults.hex-type := raw + +endif diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic/acpi.c similarity index 81% rename from src/drivers/wifi/generic.c rename to src/drivers/wifi/generic/acpi.c index 8858fab097..4440b81b5b 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic/acpi.c @@ -3,12 +3,12 @@ #include #include #include -#include -#include +#include #include -#include #include -#include "generic_wifi.h" + +#include "chip.h" +#include "wifi_private.h" /* WRDS Spec Revision */ #define WRDS_REVISION 0x0 @@ -33,21 +33,27 @@ */ #define WIFI_ACPI_NAME_MAX_LEN 5 -__weak -int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +__weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { return -1; } -static void emit_sar_acpi_structures(void) +static void emit_sar_acpi_structures(const struct device *dev) { int i, j, package_size; struct wifi_sar_limits sar_limits; struct wifi_sar_delta_table *wgds; + /* + * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR + * ACPI tables are currently used only by Intel WiFi devices. + */ + if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VENDOR_ID_INTEL) + return; + /* Retrieve the sar limits data */ if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + printk(BIOS_DEBUG, "failed from getting SAR limits!\n"); return; } @@ -105,7 +111,6 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); acpigen_pop_len(); - if (!CONFIG(GEO_SAR_ENABLE)) return; @@ -159,36 +164,31 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); } -void generic_wifi_fill_ssdt(const struct device *dev, - const struct generic_wifi_config *config) +static void wifi_ssdt_write_device(const struct device *dev, const char *path) { - const char *path; - u32 address; - - if (!dev->enabled) - return; - - path = acpi_device_path(dev->bus->dev); - if (!path) - return; - /* Device */ - acpigen_write_scope(path); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_device(path); acpi_device_write_uid(dev); if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); /* Address */ - address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; - address <<= 16; - address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; - acpigen_write_name_dword("_ADR", address); + acpigen_write_ADR_pci_device(dev); + + acpigen_pop_len(); /* Device */ +} + +static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) +{ + const struct drivers_wifi_generic_config *config = dev->chip_info; + + /* Scope */ + acpigen_write_scope(scope); /* Wake capabilities */ if (config) - acpigen_write_PRW(config->wake, config->maxsleep); + acpigen_write_PRW(config->wake, ACPI_S3); /* Fill regulatory domain structure */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) { @@ -213,16 +213,27 @@ void generic_wifi_fill_ssdt(const struct device *dev, /* Fill Wifi sar related ACPI structures */ if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(); + emit_sar_acpi_structures(dev); - acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); + printk(BIOS_INFO, "%s: %s %s\n", scope, dev->chip_ops ? dev->chip_ops->name : "", + dev_path(dev)); } -const char *generic_wifi_acpi_name(const struct device *dev) +void wifi_pcie_fill_ssdt(const struct device *dev) +{ + const char *path; + + path = acpi_device_path(dev); + if (!path) + return; + + wifi_ssdt_write_device(dev, path); + wifi_ssdt_write_properties(dev, path); +} + +const char *wifi_pcie_acpi_name(const struct device *dev) { static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; @@ -231,3 +242,14 @@ const char *generic_wifi_acpi_name(const struct device *dev) (dev_path_encode(dev) & 0xff)); return wifi_acpi_name; } + +void wifi_cnvi_fill_ssdt(const struct device *dev) +{ + const char *path; + + path = acpi_device_path(dev->bus->dev); + if (!path) + return; + + wifi_ssdt_write_properties(dev, path); +} diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h new file mode 100644 index 0000000000..e3b0ba5698 --- /dev/null +++ b/src/drivers/wifi/generic/chip.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WIFI_GENERIC_H_ +#define _WIFI_GENERIC_H_ + +/** + * struct drivers_wifi_generic_config - Data structure to contain generic wifi config + * @wake: Wake pin for ACPI _PRW + */ +struct drivers_wifi_generic_config { + unsigned int wake; +}; + +#endif /* _GENERIC_WIFI_H_ */ diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c new file mode 100644 index 0000000000..31c681619b --- /dev/null +++ b/src/drivers/wifi/generic/generic.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "wifi_private.h" + +static void wifi_pci_dev_init(struct device *dev) +{ + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); +} + +struct device_operations wifi_pcie_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = wifi_pci_dev_init, + .ops_pci = &pci_dev_ops_pci, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = wifi_pcie_acpi_name, + .acpi_fill_ssdt = wifi_pcie_fill_ssdt, +#endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_wifi_pcie, +#endif +}; + +struct device_operations wifi_cnvi_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = wifi_cnvi_fill_ssdt, +#endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_wifi_cnvi, +#endif +}; + +static void wifi_generic_enable(struct device *dev) +{ + struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; + + if (!config) + return; + + if (dev->path.type == DEVICE_PATH_PCI) + dev->ops = &wifi_pcie_ops; + else + dev->ops = &wifi_cnvi_ops; +} + +struct chip_operations drivers_wifi_generic_ops = { + CHIP_NAME("WIFI Device") + .enable_dev = wifi_generic_enable +}; + +static const unsigned short intel_pci_device_ids[] = { + PCI_DEVICE_ID_1000_SERIES_WIFI, + PCI_DEVICE_ID_6005_SERIES_WIFI, + PCI_DEVICE_ID_6005_I_SERIES_WIFI, + PCI_DEVICE_ID_1030_SERIES_WIFI, + PCI_DEVICE_ID_6030_I_SERIES_WIFI, + PCI_DEVICE_ID_6030_SERIES_WIFI, + PCI_DEVICE_ID_6150_SERIES_WIFI, + PCI_DEVICE_ID_2030_SERIES_WIFI, + PCI_DEVICE_ID_2000_SERIES_WIFI, + PCI_DEVICE_ID_0135_SERIES_WIFI, + PCI_DEVICE_ID_0105_SERIES_WIFI, + PCI_DEVICE_ID_6035_SERIES_WIFI, + PCI_DEVICE_ID_5300_SERIES_WIFI, + PCI_DEVICE_ID_5100_SERIES_WIFI, + PCI_DEVICE_ID_6000_SERIES_WIFI, + PCI_DEVICE_ID_6000_I_SERIES_WIFI, + PCI_DEVICE_ID_5350_SERIES_WIFI, + PCI_DEVICE_ID_5150_SERIES_WIFI, + /* Wilkins Peak 2 */ + PCI_DEVICE_ID_WP_7260_SERIES_1_WIFI, + PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI, + /* Stone Peak 2 */ + PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI, + PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI, + /* Stone Field Peak */ + PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI, + PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, + /* Windstorm Peak */ + PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, + /* Thunder Peak 2 */ + PCI_DEVICE_ID_TP_9260_SERIES_WIFI, + /* Cyclone Peak */ + PCI_DEVICE_ID_CyP_6SERIES_WIFI, + /* Typhoon Peak */ + PCI_DEVICE_ID_TyP_6SERIES_WIFI, + /* Garfield Peak */ + PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, + PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, + 0 +}; + +/* + * The PCI driver is retained for backward compatibility with boards that never utilized the + * chip driver to support Intel WiFi device. For these devices, the PCI driver helps perform the + * same operations as above (except exposing the wake property) by utilizing the same + * `wifi_generic_ops`. + */ +static const struct pci_driver intel_wifi_pci_driver __pci_driver = { + .ops = &wifi_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = intel_pci_device_ids, +}; diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c new file mode 100644 index 0000000000..a1a8e4f204 --- /dev/null +++ b/src/drivers/wifi/generic/smbios.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "wifi_private.h" + +static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) +{ + struct smbios_type_intel_wifi { + u8 type; + u8 length; + u16 handle; + u8 str; + u8 eos[2]; + } __packed; + + struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + int len = sizeof(struct smbios_type_intel_wifi); + + memset(t, 0, sizeof(struct smbios_type_intel_wifi)); + t->type = 0x85; + t->length = len - 2; + t->handle = *handle; + /* Intel wifi driver expects this string to be in the table 0x85. */ + t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + +int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current) +{ + if (dev->vendor == PCI_VENDOR_ID_INTEL) + return smbios_write_intel_wifi(dev, handle, current); + + return 0; +} + +int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current) +{ + return smbios_write_wifi_pcie(dev->bus->dev, handle, current); +} diff --git a/src/drivers/wifi/generic/wifi_private.h b/src/drivers/wifi/generic/wifi_private.h new file mode 100644 index 0000000000..4a2045db8d --- /dev/null +++ b/src/drivers/wifi/generic/wifi_private.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WIFI_GENERIC_PRIVATE_H_ +#define _WIFI_GENERIC_PRIVATE_H_ + +int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current); +int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current); + +const char *wifi_pcie_acpi_name(const struct device *dev); +void wifi_pcie_fill_ssdt(const struct device *dev); + +void wifi_cnvi_fill_ssdt(const struct device *dev); + +#endif diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h deleted file mode 100644 index 57209e9547..0000000000 --- a/src/drivers/wifi/generic_wifi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _GENERIC_WIFI_H_ -#define _GENERIC_WIFI_H_ - -/** - * struct generic_wifi_config - Data structure to contain common wifi config - * @wake: Wake pin for ACPI _PRW - * @maxsleep: Maximum sleep state to wake from - */ -struct generic_wifi_config { - unsigned int wake; - unsigned int maxsleep; -}; - -/** - * wifi_fill_ssdt() - Fill ACPI SSDT table for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * @config: Common wifi config required to fill ACPI SSDT table. - * - * This function implements common device operation to help fill ACPI SSDT - * table for WiFi controller. - */ -void generic_wifi_fill_ssdt(const struct device *dev, - const struct generic_wifi_config *config); - -/** - * wifi_acpi_name() - Get ACPI name for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * - * This function implements common device operation to get the ACPI name for - * WiFi controller. - * - * Return: string representing the ACPI name for WiFi controller. - */ -const char *generic_wifi_acpi_name(const struct device *dev); - -#endif /* _GENERIC_WIFI_H_ */ diff --git a/src/ec/51nb/npce985la0dx/npce985la0dx.c b/src/ec/51nb/npce985la0dx/npce985la0dx.c index f435d3222e..06db530c3b 100644 --- a/src/ec/51nb/npce985la0dx/npce985la0dx.c +++ b/src/ec/51nb/npce985la0dx/npce985la0dx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 6b0997e37d..c4fa3a38d3 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -16,8 +16,7 @@ Device (EC0) Field (ERAM, ByteAcc, Lock, Preserve) { // EC Name Space Configuration - Offset(0x00), - , 1, // Reserved ; 00h.0 + , 1, // Reserved ; 00h.0 LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 , 6, // Reserved ; 00h.2 ~ 00h.6 HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index cacea96e3b..eb0b5ff5ad 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -25,7 +25,6 @@ static int kbc_input_buffer_empty(void) return !!timeout; } - static int kbc_output_buffer_full(void) { u32 timeout; @@ -58,7 +57,6 @@ int kbc_cleanup_buffers(void) return !!timeout; } - /* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * @@ -88,7 +86,6 @@ void ec_kbc_write_ib(u8 data) outb(data, KBD_DATA); } - /* * These functions are for accessing the ENE932 device space, but are not * currently used. diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index d05bc8f177..a1581b5c8f 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -22,14 +22,12 @@ #define CFG_COMMAND_WRITE_ENABLE (1 << 3) #define CFG_STATUS (1 << 1) - #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 #define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) #define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) - /* Wait 400ms for keyboard controller answers */ #define KBC_TIMEOUT_IN_MS 400 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf828..218d08b091 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -10,7 +10,10 @@ #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif - +/* Enable DPTC interface with AMD ALIB */ +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +External(\_SB.DPTC, MethodObj) +#endif Device (EC0) { @@ -28,7 +31,6 @@ Device (EC0) OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte @@ -79,7 +81,7 @@ Device (EC0) Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power -} + } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, @@ -156,6 +158,17 @@ Device (EC0) // Initialize LID switch state Store (LIDS, \LIDS) + +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT + /* + * Per the device mode (clamshell or tablet) to initialize + * the thermal setting on OS startup. + */ + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } +#endif + } /* Read requested temperature and check against EC error values */ @@ -379,6 +392,11 @@ Device (EC0) #endif #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) +#endif +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } #endif } diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 77a6f71139..2a556edc68 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -4,7 +4,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */ -Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 diff --git a/src/ec/google/chromeec/audio_codec/audio_codec.c b/src/ec/google/chromeec/audio_codec/audio_codec.c index 612b1f6995..53037eb01b 100644 --- a/src/ec/google/chromeec/audio_codec/audio_codec.c +++ b/src/ec/google/chromeec/audio_codec/audio_codec.c @@ -15,7 +15,7 @@ static void crosec_audio_codec_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info; - if (!dev->enabled || !scope || !cfg) + if (!scope || !cfg) return; acpigen_write_scope(scope); diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 7c3f9661fe..3915cf92e7 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -3,8 +3,14 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H +#include +#include + +#define MAX_TYPEC_PORTS 4 struct ec_google_chromeec_config { + /* Pointer to PMC Mux connector for each Type-C port */ + DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a97dfb355e..0915833b91 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -393,7 +392,14 @@ void google_chromeec_log_events(uint64_t mask) return; events = google_chromeec_get_events_b() & mask; - for (i = 0; i < sizeof(events) * 8; i++) { + + /* + * This loop starts at 1 because the EC_HOST_EVENT_MASK macro subtracts + * 1 from its argument before applying the left-shift operator. This + * prevents a left-shift of -1 happening, and covers the entire 64-bit + * range of the event mask. + */ + for (i = 1; i <= sizeof(events) * 8; i++) { if (EC_HOST_EVENT_MASK(i) & events) elog_add_event_byte(ELOG_TYPE_EC_EVENT, i); } @@ -835,9 +841,16 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id) return cbi_get_uint32(id, CBI_TAG_SKU_ID); } -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config) +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config) { - return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG); + uint32_t config; + + if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG)) + return -1; + + /* FIXME: Yet to determine source of other 32 bits... */ + *fw_config = (uint64_t)config; + return 0; } int google_chromeec_cbi_get_oem_id(uint32_t *id) @@ -850,6 +863,11 @@ int google_chromeec_cbi_get_board_version(uint32_t *version) return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); } +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) +{ + return cbi_get_uint32(ssfc, CBI_TAG_SSFC); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { @@ -980,9 +998,24 @@ static uint16_t google_chromeec_get_uptime_info( bool google_chromeec_get_ap_watchdog_flag(void) { + int i; struct ec_response_uptime_info resp; - return (!google_chromeec_get_uptime_info(&resp) && - (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); + + if (google_chromeec_get_uptime_info(&resp)) + return false; + + if (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG) + return true; + + /* Find the last valid entry */ + for (i = ARRAY_SIZE(resp.recent_ap_reset) - 1; i >= 0; i--) { + if (resp.recent_ap_reset[i].reset_time_ms == 0) + continue; + return (resp.recent_ap_reset[i].reset_cause == + CHIPSET_RESET_AP_WATCHDOG); + } + + return false; } int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, @@ -1374,11 +1407,11 @@ enum ec_image google_chromeec_get_current_image(void) return ec_image_type; } -int google_chromeec_get_num_pd_ports(int *num_ports) +int google_chromeec_get_num_pd_ports(unsigned int *num_ports) { struct ec_response_charge_port_count resp = {}; struct chromeec_command cmd = { - .cmd_code = EC_CMD_CHARGE_PORT_COUNT, + .cmd_code = EC_CMD_USB_PD_PORTS, .cmd_version = 0, .cmd_data_out = &resp, .cmd_size_in = 0, @@ -1435,6 +1468,65 @@ int google_ec_running_ro(void) return (google_chromeec_get_current_image() == EC_IMAGE_RO); } +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +{ + struct ec_params_usb_pd_control pd_control = { + .port = port, + .role = USB_PD_CTRL_ROLE_NO_CHANGE, + .mux = USB_PD_CTRL_ROLE_NO_CHANGE, + .swap = USB_PD_CTRL_SWAP_NONE, + }; + struct ec_response_usb_pd_control_v2 resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_CONTROL, + .cmd_version = 2, + .cmd_data_in = &pd_control, + .cmd_size_in = sizeof(pd_control), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); + *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *dp_mode = resp.dp_mode; + + return 0; +} + +/** + * Check for the current mux state in EC. Flags representing the mux state found + * in ec_commands.h + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) +{ + struct ec_params_usb_pd_mux_info req_mux = { + .port = port, + }; + struct ec_response_usb_pd_mux_info resp_mux = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_MUX_INFO, + .cmd_version = 0, + .cmd_data_in = &req_mux, + .cmd_size_in = sizeof(req_mux), + .cmd_data_out = &resp_mux, + .cmd_size_out = sizeof(resp_mux), + .cmd_dev_index = 0, + }; + + if (port < 0) + return -1; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *flags = resp_mux.flags; + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * @@ -1533,3 +1625,115 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) return 0; } + +int google_chromeec_ap_reset(void) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_AP_RESET, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable) +{ + struct ec_params_regulator_enable params = { + .index = index, + .enable = enable, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_ENABLE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) +{ + + struct ec_params_regulator_is_enabled params = { + .index = index, + }; + struct ec_response_regulator_is_enabled resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_IS_ENABLED, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *enabled = resp.enabled; + + return 0; +} + +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv) +{ + struct ec_params_regulator_set_voltage params = { + .index = index, + .min_mv = min_mv, + .max_mv = max_mv, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_SET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) +{ + struct ec_params_regulator_get_voltage params = { + .index = index, + }; + struct ec_response_regulator_get_voltage resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_GET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *voltage_mv = resp.voltage_mv; + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aead5f7fa8..7c41f0496f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -27,6 +27,15 @@ int google_ec_running_ro(void); enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); +/* Check for the current mux state in EC + * in: int port physical port number of the type-c port + * out: uint8_t flags flags representing the status of the mux such as + * usb capability, dp capability, cable type, etc + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); +/* Returns data role and type of device connected */ +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, + uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ @@ -74,12 +83,13 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags); */ int google_chromeec_cbi_get_oem_id(uint32_t *id); int google_chromeec_cbi_get_sku_id(uint32_t *id); -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); /* version may be stored in CBI as a smaller integer width, but the EC code handles it correctly. */ int google_chromeec_cbi_get_board_version(uint32_t *version); +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF @@ -306,7 +316,7 @@ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); * of PD-capable USB ports according to the EC. * @return 0 on success, -1 on error */ -int google_chromeec_get_num_pd_ports(int *num_ports); +int google_chromeec_get_num_pd_ports(unsigned int *num_ports); /* Structure representing the capabilities of a USB-PD port */ struct usb_pd_port_caps { @@ -337,6 +347,51 @@ int google_chromeec_get_pd_port_caps(int port, */ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); +/** + * Send EC command to perform AP reset + * + * @return 0 on success, -1 on error + */ +int google_chromeec_ap_reset(void); + +/** + * Configure the regulator as enabled / disabled. + * + * @param index Regulator ID + * @param enable Set to enable / disable the regulator + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable); + +/** + * Query if the regulator is enabled. + * + * @param index Regulator ID + * @param *enabled If successful, enabled indicates enable/disable status. + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled); + +/** + * Set voltage for the voltage regulator within the range specified. + * + * @param index Regulator ID + * @param min_mv Minimum voltage + * @param max_mv Maximum voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv); + +/** + * Get the currently configured voltage for the voltage regulator. + * + * @param index Regulator ID + * @param *voltage_mv If successful, voltage_mv is filled with current voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 8a76805407..fff395411c 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -16,14 +16,6 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" -/* Avoid adding a false dependency on an SoC or intel/common */ -extern const struct device *soc_get_pmc_mux_device(int port_number); - -__weak const struct device *soc_get_pmc_mux_device(int port_number) -{ - return NULL; -} - const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -121,35 +113,18 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location) static struct usb_pd_port_caps port_caps; static void add_port_location(struct acpi_dp *dsd, int port_number) { - acpi_dp_add_string(dsd, "port-location", - port_location_to_str(port_caps.port_location)); -} - -static int conn_id_to_match; - -/* A callback to match a port's connector for dev_find_matching_device_on_bus */ -static bool match_connector(DEVTREE_CONST struct device *dev) -{ - if (CONFIG(DRIVERS_INTEL_PMC)) { - extern struct chip_operations drivers_intel_pmc_mux_conn_ops; - - return (dev->chip_ops == &drivers_intel_pmc_mux_conn_ops && - dev->path.type == DEVICE_PATH_GENERIC && - dev->path.generic.id == conn_id_to_match); - } - - return false; + acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } static void fill_ssdt_typec_device(const struct device *dev) { + struct ec_google_chromeec_config *config = dev->chip_info; int rv; - int i, num_ports; + int i; + unsigned int num_ports; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; - const struct device *mux; - const struct device *conn; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -165,32 +140,24 @@ static void fill_ssdt_typec_device(const struct device *dev) if (rv) continue; - /* Get the MUX device, and find the matching connector on its bus */ - conn = NULL; - mux = soc_get_pmc_mux_device(i); - if (mux) { - conn_id_to_match = i; - conn = dev_find_matching_device_on_bus(mux->link_list, match_connector); - } - usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); - struct typec_connector_class_config config = { + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, .data_role = port_caps.data_role_cap, .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, - .orientation_switch = conn, - .usb_role_switch = conn, - .mode_switch = conn, + .orientation_switch = config->mux_conn[i], + .usb_role_switch = config->mux_conn[i], + .mode_switch = config->mux_conn[i], }; - acpigen_write_typec_connector(&config, i, add_port_location); + acpigen_write_typec_connector(&typec_config, i, add_port_location); } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ @@ -256,9 +223,6 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev) struct device_path path; struct device *ec; - if (!dev->enabled) - return; - /* Set up a minimal EC0 device to pass to the DPTF helpers */ path.type = DEVICE_PATH_GENERIC; path.generic.id = 0; diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a29ad..39e1cec65d 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -29,7 +29,10 @@ extern "C" { #include "compile_time_macros.h" #else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ #endif /* CHROMIUM_EC */ #ifdef __KERNEL__ @@ -50,6 +53,21 @@ extern "C" { #define BIT_ULL(nr) (1ULL << (nr)) #endif +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + #endif /* __KERNEL__ */ /* @@ -1397,6 +1415,18 @@ enum ec_feature_code { EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ EC_FEATURE_ISH = 40, + /* New TCPMv2 TYPEC_ prefaced commands supported */ + EC_FEATURE_TYPEC_CMD = 41, + /* + * The EC will wait for direction from the AP to enter Type-C alternate + * modes or USB4. + */ + EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42, + /* + * The EC will wait for an acknowledge from the AP after setting the + * mux. + */ + EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2527,6 +2557,12 @@ enum motionsense_command { */ MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2579,6 +2615,8 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, MOTIONSENSE_CHIP_MAX, }; @@ -2591,6 +2629,11 @@ enum motionsensor_orientation { MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; + struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; @@ -2598,15 +2641,16 @@ struct ec_response_motion_sensor_data { uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2644,6 +2688,7 @@ enum motionsensor_activity { MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; struct ec_motion_sense_activity { @@ -2828,6 +2873,7 @@ struct ec_params_motion_sense { uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ @@ -2852,8 +2898,19 @@ struct ec_params_motion_sense { /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + }; } spoof; /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ @@ -2882,6 +2939,13 @@ struct ec_params_motion_sense { uint8_t sensor_num; } online_calib_read; + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; }; } __ec_todo_packed; @@ -3033,6 +3097,10 @@ struct ec_response_motion_sense { uint16_t hys_degree; } tablet_mode_threshold; + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; } __ec_todo_packed; @@ -3745,6 +3813,7 @@ struct ec_response_get_next_event_v1 { #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 #define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 @@ -3894,6 +3963,10 @@ struct ec_response_host_event_mask { /* * Unified host event programming interface - Should be used by newer versions * of BIOS/OS to program host events and masks + * + * EC returns: + * - EC_RES_INVALID_PARAM: Action or mask type is unknown. + * - EC_RES_ACCESS_DENIED: Action is prohibited for specified mask type. */ struct ec_params_host_event { @@ -4441,6 +4514,7 @@ struct ec_params_charge_state { uint32_t value; /* value to set */ } set_param; }; + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4609,6 +4683,7 @@ enum ec_device_event { EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -4996,6 +5071,7 @@ enum ec_codec_i2s_rx_subcmd { EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, EC_CODEC_I2S_RX_SUBCMD_COUNT, }; @@ -5108,6 +5184,33 @@ struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm { uint32_t len; }; +/*****************************************************************************/ +/* Commands for PoE PSE controller */ + +#define EC_CMD_PSE 0x00C0 + +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, +}; + +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ +}; + +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, +}; + +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ +}; + /*****************************************************************************/ /* System commands */ @@ -5126,7 +5229,8 @@ enum ec_reboot_cmd { EC_REBOOT_COLD = 4, /* Cold-reboot */ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5235,15 +5339,23 @@ struct ec_response_pd_status { #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE BIT(0) -#define PD_EVENT_POWER_CHANGE BIT(1) -#define PD_EVENT_IDENTITY_RECEIVED BIT(2) -#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) + struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ } __ec_align4; -/* Set USB type-C port role and muxes */ +/* + * Set USB type-C port role and muxes + * + * Deprecated in favor of TYPEC_STATUS and TYPEC_CONTROL commands. + * + * TODO(b/169771803): TCPMv2: Remove EC_CMD_USB_PD_CONTROL + */ #define EC_CMD_USB_PD_CONTROL 0x0101 enum usb_pd_control_role { @@ -5331,10 +5443,6 @@ enum pd_cc_states { /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5727,6 +5835,8 @@ enum cbi_data_tag { CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_COUNT, }; @@ -5766,7 +5876,7 @@ struct ec_params_set_cbi { */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -/* Reset causes */ +/* EC reset causes */ #define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ #define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ #define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ @@ -5791,6 +5901,75 @@ struct ec_params_set_cbi { #define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This * enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ + +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_reset_reason { + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, +}; + +/* + * AP hard shutdowns are logged on the same path as resets. + */ +enum chipset_shutdown_reason { + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + + CHIPSET_SHUTDOWN_COUNT, +}; + struct ec_response_uptime_info { /* @@ -5819,10 +5998,7 @@ struct ec_response_uptime_info { /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* - * See include/chipset.h: enum chipset_{reset,shutdown}_reason - * for details. - */ + /* See enum chipset_{reset,shutdown}_reason for details. */ uint16_t reset_cause; /* Reserved for protocol growth. */ @@ -5942,13 +6118,21 @@ struct ec_response_locate_chip { * * This command is used for validation purpose, where the AP needs to be * returned back to S0 state from G3 state without using the servo to trigger - * wake events.For this,there is no request or response struct. - * - * Order of command usage: - * ectool reboot_ap_on_g3 && shutdown -h now + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [] && shutdown -h now */ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + /*****************************************************************************/ /* Get PD port capabilities * @@ -6053,6 +6237,7 @@ enum keyboard_button_type { KEYBOARD_BUTTON_COUNT }; + /*****************************************************************************/ /* * "Get the Keyboard Config". An EC implementing this command is expected to be @@ -6131,6 +6316,456 @@ struct ec_response_keybd_config { } __ec_align1; +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; + +/* + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. + */ +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + +/* + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. + */ +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 + +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ + struct svid_mode_info svids[0]; +} __ec_align1; + +/* USB Type-C commands for AP-controlled device policy. */ +#define EC_CMD_TYPEC_CONTROL 0x0132 + +enum typec_control_command { + TYPEC_CONTROL_COMMAND_EXIT_MODES, + TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, +}; + +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, +}; + +struct ec_params_typec_control { + uint8_t port; + uint8_t command; /* enum typec_control_command */ + uint16_t reserved; + + /* + * This section will be interpreted based on |command|. Define a + * placeholder structure to avoid having to increase the size and bump + * the command version when adding new sub-commands. + */ + union { + uint32_t clear_events_mask; + uint8_t mode_to_enter; /* enum typec_mode */ + uint8_t placeholder[128]; + }; +} __ec_align1; + +/* + * Gather all status information for a port. + * + * Note: this covers many of the return fields from the deprecated + * EC_CMD_USB_PD_CONTROL command, except those that are redundant with the + * discovery data. The "enum pd_cc_states" is defined with the deprecated + * EC_CMD_USB_PD_CONTROL command. + * + * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. + */ +#define EC_CMD_TYPEC_STATUS 0x0133 + +/* + * Power role. + * + * Note this is also used for PD header creation, and values align to those in + * the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.4 Port Power Role). + */ +enum pd_power_role { + PD_ROLE_SINK = 0, + PD_ROLE_SOURCE = 1 +}; + +/* + * Data role. + * + * Note this is also used for PD header creation, and the first two values + * align to those in the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.6 Port Data Role). + */ +enum pd_data_role { + PD_ROLE_UFP = 0, + PD_ROLE_DFP = 1, + PD_ROLE_DISCONNECTED = 2, +}; + +enum pd_vconn_role { + PD_ROLE_VCONN_OFF = 0, + PD_ROLE_VCONN_SRC = 1, +}; + +/* + * Note: BIT(0) may be used to determine whether the polarity is CC1 or CC2, + * regardless of whether a debug accessory is connected. + */ +enum tcpc_cc_polarity { + /* + * _CCx: is used to indicate the polarity while not connected to + * a Debug Accessory. Only one CC line will assert a resistor and + * the other will be open. + */ + POLARITY_CC1 = 0, + POLARITY_CC2 = 1, + + /* + * _CCx_DTS is used to indicate the polarity while connected to a + * SRC Debug Accessory. Assert resistors on both lines. + */ + POLARITY_CC1_DTS = 2, + POLARITY_CC2_DTS = 3, + + /* + * The current TCPC code relies on these specific POLARITY values. + * Adding in a check to verify if the list grows for any reason + * that this will give a hint that other places need to be + * adjusted. + */ + POLARITY_COUNT +}; + +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) + +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) + +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + +struct ec_params_typec_status { + uint8_t port; +} __ec_align1; + +struct ec_response_typec_status { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* + * BCD PD revisions for partners + * + * The format has the PD major reversion in the upper nibble, and PD + * minor version in the next nibble. Following two nibbles are + * currently 0. + * ex. PD 3.2 would map to 0x3200 + * + * PD major/minor will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ +} __ec_align1; + +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; +} __ec_align2; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is detected in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, +}; + +#define EC_PCHG_STATE_TEXT { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + } + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6174,6 +6809,8 @@ struct ec_params_fp_passthru { #define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ #define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE BIT(31) @@ -6185,6 +6822,7 @@ struct ec_params_fp_passthru { FP_MODE_ENROLL_IMAGE | \ FP_MODE_MATCH | \ FP_MODE_RESET_SENSOR | \ + FP_MODE_SENSOR_MAINTENANCE | \ FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ @@ -6473,6 +7111,28 @@ struct ec_response_battery_static_info { uint32_t cycle_count; } __ec_align4; +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + /* * Get battery dynamic information, i.e. information that is likely to change * every time it is read. @@ -6528,6 +7188,13 @@ struct ec_params_charger_control { uint8_t allow_charging; } __ec_align_size1; +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 0f8d4a313b..631f16ebce 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -135,7 +135,7 @@ static void write_is_policy_enabled(bool enabled) * Local1 = 0 * Local2 = 0 * - * While (Local1 < Local) { + * While (Local1 < Local0) { * If (IDSP[Local1] == Arg0 && Arg1 == enabled) { * Local2 = 1 * } @@ -167,8 +167,7 @@ static void write_is_policy_enabled(bool enabled) */ acpigen_emit_byte(WHILE_OP); acpigen_write_len_f(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LLESS_OP); acpigen_emit_byte(LOCAL1_OP); acpigen_emit_byte(LOCAL0_OP); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 5306dcca5b..b9c972834b 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -307,7 +307,6 @@ static int google_chromeec_command_v1(struct chromeec_command *cec_command) args.checksum = csum; write_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL); - /* Issue the command */ write_byte(cmd_code, EC_LPC_ADDR_HOST_CMD); diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index 0bfc9d4dc6..39a1c0be82 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index ec8bdfc2bf..e61ecfd8c1 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -17,7 +17,7 @@ static void crosec_i2c_tunnel_fill_ssdt(const struct device *dev) struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; struct acpi_dp *dsd; - if (!dev->enabled || !scope || !cfg) + if (!scope || !cfg) return; acpigen_write_scope(scope); diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h index 2db8cfe4ab..8a5b69c34c 100644 --- a/src/ec/google/wilco/bootblock.h +++ b/src/ec/google/wilco/bootblock.h @@ -9,7 +9,7 @@ * This function performs early initialization of the EC: * * - Enable EC UART passthru for COM1 if serial console support - * is enabled with CONFIG_DRIVERS_UART_8250IO. + * is enabled with CONFIG(DRIVERS_UART_8250IO). */ void wilco_ec_early_init(void); diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index dccaa23d01..911eb25074 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -184,9 +184,6 @@ static void wilco_ec_fill_ssdt_generator(const struct device *dev) void *region_ptr; size_t ucsi_alloc_region_len; - if (!dev->enabled) - return; - ucsi_alloc_region_len = ucsi_region_len < UCSI_MIN_ALLOC_REGION_LEN ? UCSI_MIN_ALLOC_REGION_LEN : ucsi_region_len; region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_alloc_region_len); diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index 924501fbeb..cb4ddec7e4 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -5,7 +5,17 @@ config EC_HP_KBC1126 help Interface to SMSC KBC1126 embedded controller in HP laptops. -if EC_HP_KBC1126 +config EC_HP_KBC1126_GPE + hex + depends on EC_HP_KBC1126 + default 0x16 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + depends on EC_HP_KBC1126 + default y + +if EC_HP_KBC1126_ECFW_IN_CBFS comment "Please select the following otherwise your laptop cannot be powered on." diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 54e8b2afc3..92a0a72c02 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,8 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_EC_HP_KBC1126),y) +ifeq ($(CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS),y) KBC1126_EC_INSERT:=$(top)/util/kbc1126/kbc1126_ec_insert -INTERMEDIATE+=kbc1126_ec_insert ifeq ($(CONFIG_KBC1126_FIRMWARE),y) cbfs-files-y += ecfw1.bin @@ -17,17 +16,15 @@ ecfw2.bin-position := $(CONFIG_KBC1126_FW2_OFFSET) ecfw2.bin-type := raw endif -kbc1126_ec_insert: $(obj)/coreboot.pre +$(call add_intermediate, kbc1126_ec_insert, $(obj)/coreboot.pre) ifeq ($(CONFIG_KBC1126_FIRMWARE),y) printf " Building kbc1126_ec_insert.\n" $(MAKE) -C util/kbc1126 printf " KBC1126 Inserting KBC1126 firmware blobs.\n" - $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ + flock $< $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ $(CONFIG_KBC1126_FW1_OFFSET) $(CONFIG_KBC1126_FW2_OFFSET) endif -PHONY+=kbc1126_ec_insert - build_complete:: ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "\n** WARNING **\n" @@ -39,8 +36,8 @@ ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "You can read util/kbc1126/README.md for details.\n\n" endif -ramstage-y += ec.c -bootblock-y += early_init.c -romstage-y += early_init.c - endif + +ramstage-$(CONFIG_EC_HP_KBC1126) += ec.c +bootblock-$(CONFIG_EC_HP_KBC1126) += early_init.c +romstage-$(CONFIG_EC_HP_KBC1126) += early_init.c diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index e5752a802d..81bdff969a 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -4,7 +4,7 @@ Device (EC0) { Name (_HID, EISAID("PNP0C09")) Name (_UID, 0) - Name (_GPE, 0x16) + Name (_GPE, CONFIG_EC_HP_KBC1126_GPE) Name (_CRS, ResourceTemplate () { diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 8ca8d246e9..30f40fe097 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -12,6 +12,13 @@ enum kempld_uart_io { KEMPLD_UART_2E8 = 3, }; +enum kempld_i2c_frequency { + KEMPLD_I2C_FREQ_STANDARD_MODE_100KHZ = 100, + KEMPLD_I2C_FREQ_FAST_MODE_400KHZ = 400, + KEMPLD_I2C_FREQ_FAST_PLUS_MODE_1MHZ = 1000, + KEMPLD_I2C_FREQ_MAX = 2700, +}; + struct kempld_uart { enum kempld_uart_io io; unsigned int irq; @@ -19,6 +26,7 @@ struct kempld_uart { struct ec_kontron_kempld_config { struct kempld_uart uart[KEMPLD_NUM_UARTS]; + unsigned short i2c_frequency; }; #endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c index cb33a8baaf..3cafb1e762 100644 --- a/src/ec/kontron/kempld/early_kempld.c +++ b/src/ec/kontron/kempld/early_kempld.c @@ -43,13 +43,11 @@ void kempld_enable_uart_for_console(void) switch (CONFIG_UART_FOR_CONSOLE) { case 0: kempld_write8(KEMPLD_UART_0, - KEMPLD_UART_ENABLE | - KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); + KEMPLD_UART_ENABLE | KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); break; case 1: kempld_write8(KEMPLD_UART_1, - KEMPLD_UART_ENABLE | - KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); + KEMPLD_UART_ENABLE | KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); break; default: break; diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 19376c7961..f8371a8d82 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -16,21 +16,20 @@ static void kempld_uart_read_resources(struct device *dev) struct resource *const res_io = new_resource(dev, 0); struct resource *const res_irq = new_resource(dev, 1); const unsigned int uart = dev->path.generic.subid; + if (!config || !res_io || !res_irq || uart >= KEMPLD_NUM_UARTS) return; const enum kempld_uart_io io = config->uart[uart].io; if (io >= ARRAY_SIZE(io_addr)) { - printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", - io, uart); + printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", io, uart); dev->enabled = false; return; } const int irq = config->uart[uart].irq; if (irq >= 16) { - printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", - irq, uart); + printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", irq, uart); dev->enabled = false; return; } @@ -49,9 +48,10 @@ static void kempld_uart_read_resources(struct device *dev) const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; const uint8_t val = kempld_read8(reg); - kempld_write8(reg, (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) - | io << KEMPLD_UART_IO_SHIFT - | irq << KEMPLD_UART_IRQ_SHIFT); + kempld_write8(reg, + (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) | + io << KEMPLD_UART_IO_SHIFT | + irq << KEMPLD_UART_IRQ_SHIFT); kempld_release_mutex(); } @@ -90,9 +90,7 @@ static void kempld_enable_dev(struct device *const dev) } /* Fall through. */ default: - printk(BIOS_WARNING, - "KEMPLD: Spurious device %s.\n", - dev_path(dev)); + printk(BIOS_WARNING, "KEMPLD: Spurious device %s.\n", dev_path(dev)); break; } } diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 296cf76ddd..b99c0e48b0 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -13,6 +13,7 @@ #include #include +#include "chip.h" #include "kempld.h" #include "kempld_internal.h" @@ -40,9 +41,6 @@ #define I2C_CMD_READ_NACK 0x29 #define I2C_CMD_IACK 0x01 -#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ -#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ - #define EIO 5 #define ENXIO 6 #define EAGAIN 11 @@ -153,8 +151,7 @@ static int kempld_i2c_process(struct kempld_i2c_data *const i2c) i2c->state = STATE_ADDR; return 0; } - i2c->state = (msg->flags & I2C_M_RD) - ? STATE_READ : STATE_WRITE; + i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; } else { i2c->state = STATE_DONE; kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); @@ -230,7 +227,8 @@ static struct device_operations kempld_i2c_dev_ops = { void kempld_i2c_device_init(struct device *const dev) { - u16 prescale_corr; + const struct ec_kontron_kempld_config *const config = dev->chip_info; + u16 prescale_corr, frequency; long prescale; u8 ctrl; u8 stat; @@ -244,11 +242,23 @@ void kempld_i2c_device_init(struct device *const dev) ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_write8(KEMPLD_I2C_CTRL, ctrl); + frequency = KEMPLD_I2C_FREQ_STANDARD_MODE_100KHZ; + if (config && config->i2c_frequency) { + if (config->i2c_frequency <= KEMPLD_I2C_FREQ_MAX) { + frequency = config->i2c_frequency; + } else { + printk(BIOS_NOTICE, + "kempld_i2c: %d kHz is too high!\n", + config->i2c_frequency); + } + } + printk(BIOS_INFO, "kempld_i2c: Use frequency %d\n", frequency); + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); if (spec_major == 1) - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + prescale = KEMPLD_CLK / (frequency * 5) - 1000; else - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + prescale = KEMPLD_CLK / (frequency * 4) - 3000; if (prescale < 0) prescale = 0; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index aa1877eac6..093a639ed5 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -172,14 +172,14 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) for (i = 0; i < 8; i++) { c = ec_read(0xf0 + i); if (c < 0x20 || c > 0x7f) { - i = snprintf(str, sizeof (str), "*INVALID"); + i = snprintf(str, sizeof(str), "*INVALID"); break; } str[i] = c; } /* EC firmware function specification version */ - i += snprintf(str + i, sizeof (str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); + i += snprintf(str + i, sizeof(str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); i = MIN(buf_len, i); memcpy(buf, str, i); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index c5092c3a29..40816117b1 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -40,7 +40,6 @@ void h8_ssdt_generator(const struct device *dev); */ void h8_mb_init(void); - /* EC registers */ #define H8_CONFIG0 0x00 #define H8_CONFIG0_EVENTS_ENABLE 0x02 @@ -69,16 +68,16 @@ void h8_mb_init(void); #define H8_TRACKPOINT_OFF 0x02 #define H8_TRACKPOINT_ON 0x03 -#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL 0x0c #define H8_LED_CONTROL_OFF 0x00 #define H8_LED_CONTROL_ON 0x80 #define H8_LED_CONTROL_PULSE 0xa0 /* Some models, power LED only*/ #define H8_LED_CONTROL_BLINK 0xc0 #define H8_LED_CONTROL_POWER_LED 0x00 -#define H8_LED_CONTROL_BAT0_LED 0x01 -#define H8_LED_CONTROL_BAT1_LED 0x02 -#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 #define H8_LED_CONTROL_SUSPEND_LED 0x07 #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 @@ -95,51 +94,51 @@ void h8_mb_init(void); #define H8_VOLUME_CONTROL 0x30 #define H8_VOLUME_CONTROL_MUTE 0x40 /* Embedded controller events */ -#define H8_EVENT_FN_F1 0x10 -#define H8_EVENT_FN_F2 0x11 -#define H8_EVENT_FN_F3 0x12 -#define H8_EVENT_FN_F4 0x13 -#define H8_EVENT_FN_HOME 0x14 -#define H8_EVENT_FN_END 0x15 -#define H8_EVENT_FN_F7 0x16 -#define H8_EVENT_FN_F8 0x17 -#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 #define H8_EVENT_FN_THINKVANTAGE 0x19 -#define H8_EVENT_FN_F11 0x1a -#define H8_EVENT_FN_F12 0x1b -#define H8_EVENT_FN_1 0x1c -#define H8_EVENT_FN_2 0x1d -#define H8_EVENT_FN_PGUP 0x1f +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f -#define H8_EVENT_AC_ON 0x26 -#define H8_EVENT_AC_OFF 0x27 +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 -#define H8_EVENT_PWRSW_PRESS 0x28 -#define H8_EVENT_PWRSW_RELEASE 0x29 +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 -#define H8_EVENT_LIDSW_CLOSE 0x2a -#define H8_EVENT_LIDSW_PUSH 0x2b +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b -#define H8_EVENT_UBAY_UNLOCK 0x2c -#define H8_EVENT_UBAY_LOCK 0x2d +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d -#define H8_EVENT_KEYPRESS 0x33 +#define H8_EVENT_KEYPRESS 0x33 -#define H8_EVENT_FN_PRESS 0x39 +#define H8_EVENT_FN_PRESS 0x39 -#define H8_STATUS0 0x46 -#define H8_STATUS0_FN_KEY_DOWN 0x01 -#define H8_STATUS1 0x47 -#define H8_STATUS2 0x48 -#define H8_STATUS3 0x49 +#define H8_STATUS0 0x46 +#define H8_STATUS0_FN_KEY_DOWN 0x01 +#define H8_STATUS1 0x47 +#define H8_STATUS2 0x48 +#define H8_STATUS3 0x49 -#define H8_EVENT_BAT0 0x4a -#define H8_EVENT_BAT0_STATE 0x4b +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b -#define H8_EVENT_BAT1 0x4c -#define H8_EVENT_BAT1_STATE 0x4d +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d -#define H8_EVENT_FN_F5 0x64 -#define H8_EVENT_FN_F6 0x65 +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 #endif /* EC_LENOVO_H8_H */ diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 97abb9de24..b564153331 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -33,7 +33,7 @@ int get_recovery_mode_switch(void) } /** - * Only used if CONFIG_CHROMEOS is set. + * Only used if CONFIG(CHROMEOS) is set. * Always zero as the #WP pin of the flash is tied high. */ int get_write_protect_state(void) diff --git a/src/ec/purism/librem/acpi/battery.asl b/src/ec/purism/librem/acpi/battery.asl index ca682a8f03..742dd250e6 100644 --- a/src/ec/purism/librem/acpi/battery.asl +++ b/src/ec/purism/librem/acpi/battery.asl @@ -65,13 +65,13 @@ Device (BAT) /* Method to enable full battery workaround */ Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } /* Method to disable full battery workaround */ Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } Method (_STA, 0, Serialized) @@ -86,22 +86,22 @@ Device (BAT) Method (_BIF, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIF, 2)) + PBIF [2] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIF, 4)) + PBIF [4] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIF, 1)) + Local0 = BTDA + PBIF [1] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIF, 5)) + Local2 = (Local0 * DWRN) / 100 + PBIF [5] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIF, 6)) + Local2 = (Local0 * DLOW) / 100 + PBIF [6] = Local2 Return (PBIF) } @@ -109,22 +109,22 @@ Device (BAT) Method (_BIX, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIX, 3)) + PBIX [3] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIX, 5)) + PBIX [5] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIX, 2)) + Local0 = BTDA + PBIX [2] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIX, 6)) + Local2 = (Local0 * DWRN) / 100 + PBIX [6] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIX, 7)) + Local2 = (Local0 * DLOW) / 100 + PBIX [7] = Local2 Return (PBIX) } @@ -142,61 +142,60 @@ Device (BAT) /* Check if AC is present */ If (ACEX) { /* Read battery status from EC */ - Store (BSTS, Local0) + Local0 = BSTS } Else { /* Always discharging when on battery power */ - Store (0x01, Local0) + Local0 = 0x01 } /* Check for critical battery level */ If (BFCR) { - Or (Local0, 0x04, Local0) + Local0 |= 0x04 } - Store (Local0, Index (PBST, 0)) + PBST [0] = Local0 /* Notify if battery state has changed since last time */ - If (LNotEqual (Local0, BSTP)) { - Store (Local0, BSTP) + If (Local0 != BSTP) { + BSTP = Local0 Notify (BAT, 0x80) } /* * 1: BATTERY PRESENT RATE */ - Store (BTPR, Local1) - If (And (Local1, 0x8000)) { - And (Not (Local1), 0x7FFF, Local0) - Increment (Local0) + Local1 = BTPR + If (Local1 & 0x8000) { + Local0 = ~Local1 & 0x7FFF + Local0++ } Else { - And (Local1, 0x7FFF, Local0) + Local0 = Local1 & 0x7FFF } - If(LLess(Local0, 0x0352)) + If(Local0 < 0x0352) { - Store(0x0352, Local0) + Local0 = 0x0352 } - Store (Local0, Index (PBST, 1)) + PBST [1] = Local0 /* * 2: BATTERY REMAINING CAPACITY */ - Store (BTRA, Local0) - If (LAnd (BFWK, LAnd (ACEX, LNot (BSTS)))) { - Store (BTDF, Local1) + Local0 = BTRA + If (BFWK && ACEX && !BSTS) { + Local1 = BTDF /* See if within ~6% of full */ - ShiftRight (Local1, 4, Local2) - If (LAnd (LGreater (Local0, Subtract (Local1, Local2)), - LLess (Local0, Add (Local1, Local2)))) + Local2 = Local1 >> 4 + If ((Local0 > (Local1 - Local2)) && (Local0 < (Local1 + Local2))) { - Store (Local1, Local0) + Local0 = Local1 } } - Store (Local0, Index (PBST, 2)) + PBST [2] = Local0 /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BTVO, Index (PBST, 3)) + PBST [3] = BTVO Return (PBST) } diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 668b7d11bf..143dd04494 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -15,12 +15,12 @@ Device (TPSD) Method (FNCX, 1, NotSerialized) { - If (LEqual (Arg0, 0x86)) { + If (Arg0 == 0x86) { /* Enable topstar-laptop kernel driver handling */ - Store (One, ^^EC.TPSE) - } ElseIf (LEqual (Arg0, 0x87)) { + ^^EC.TPSE = 1 + } ElseIf (Arg0 == 0x87) { /* Disable topstar-laptop kernel driver handling */ - Store (Zero, ^^EC.TPSE) + ^^EC.TPSE = 0 } } } @@ -80,10 +80,10 @@ Device (EC) Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACEX, \PWRS) + \PWRS = ACEX /* Initialize LID switch state */ - Store (LIDS, \LIDS) + \LIDS = LIDS } /* Notify topstar-laptop kernel driver */ @@ -115,7 +115,7 @@ Device (EC) /* AC Status Changed */ Method (_Q20) { - Store (ACEX, \PWRS) + \PWRS = ACEX Notify (AC, 0x80) Notify (BAT, 0x80) PNOT () @@ -124,7 +124,7 @@ Device (EC) /* Lid Event */ Method (_Q21) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } @@ -176,7 +176,7 @@ Device (EC) Notify (\_SB.SLPB, 0x80) } - /* KEY_F13 (Touchpad Enable/Disable) + /* KEY_F13 (Touchpad Enable/Disable) */ Method (_Q34) { TPSN (0x87) @@ -193,7 +193,7 @@ Device (EC) /* KEY_BLUETOOTH */ Method (_Q37) { - XOr (^BTLE, One, ^BTLE) + ^BTLE ^= 1 } /* Turbo Enable/Disable */ @@ -208,13 +208,13 @@ Device (EC) * when the system is charging. */ If (TURB) { - Store (PPCM_TURBO, PPCM) + PPCM = PPCM_TURBO PPCN () - Store (One, EDTB) + EDTB = 1 } Else { - Store (PPCM_NOTURBO, PPCM) + PPCM = PPCM_NOTURBO PPCN () - Store (Zero, EDTB) + EDTB = 0 } } diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 532060f8a1..c7b934877c 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -26,7 +26,6 @@ static int ec_input_buffer_empty(u8 status_port) return !!timeout; } - static int ec_output_buffer_full(u8 status_port) { u32 timeout; @@ -41,8 +40,6 @@ static int ec_output_buffer_full(u8 status_port) return !!timeout; } - - /* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index dafafa7992..d354048eb0 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -12,8 +12,6 @@ #define EC_IO_LOW EC_IO + 2 #define EC_IO_DATA EC_IO + 3 - - // 60h/64h Command Interface #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 @@ -192,5 +190,4 @@ void ec_mem_write(u8 addr, u8 data); #define EC_CMD_BURST_DISABLE 0x83 #define EC_CMD_QUERY_EVENT 0x84 - #endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */ diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index a3598bef07..093593cfce 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -16,7 +16,7 @@ Device (EC0) OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0] + // [Configuration Space 0] , 1, // Reserved bit[0] ENGA, 1, // Enable Global attention ENHY, 1, // Enable Hotkey function diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 949f93dc75..80aaa5dd12 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -26,7 +26,6 @@ static int input_buffer_empty(u16 status_reg) return !!timeout; } - static int output_buffer_full(u16 status_reg) { u32 timeout; @@ -42,8 +41,6 @@ static int output_buffer_full(u16 status_reg) return !!timeout; } - - /* The IT8518 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * @@ -73,7 +70,6 @@ void ec_kbc_write_ib(u8 data) outb(data, KBD_DATA); } - /* * These functions are for accessing the IT8518 device RAM space via 0x66/0x68 */ @@ -110,7 +106,6 @@ void ec_write(u16 addr, u8 data) ec_write_ib(data); } - u8 ec_it8518_get_event(void) { u8 cmd = 0; diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 4dcf1580c3..5645062bcc 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -58,7 +58,6 @@ void ec_kbc_write_ib(u8 data); #define EC_IF_MAJ_VER 0xEF #define EC_MBAT_STATUS 0x0138 - // EC 0.83b added status bits: // BIT0=EC in RO mode // BIT1=Recovery Key Sequence Detected diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index d500084cf2..de121c6226 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -14,7 +14,6 @@ Device (EC0) OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0x0] Offset(0x02), // [Configuration Space 0x2] B0ST, 16, // Battery 0 State B0FC, 16, // Battery 0 Last Full Charge Capacity diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index a43ad7be5b..b24137ca4f 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -35,7 +35,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_REG, 2, Serialized) // _REG: Region Availability { Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) - If (((Arg0 == 0x03) && (Arg1 == One))) { + If ((Arg0 == 0x03) && (Arg1 == One)) { // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys ECOS = 1 diff --git a/src/ec/system76/ec/acpi/ec_ram.asl b/src/ec/system76/ec/acpi/ec_ram.asl index 65bd2af7da..6ef54540b6 100644 --- a/src/ec/system76/ec/acpi/ec_ram.asl +++ b/src/ec/system76/ec/acpi/ec_ram.asl @@ -4,51 +4,51 @@ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) { Offset (0x03), - LSTE, 1, // Lid is open - , 1, - LWKE, 1, // Lid wake - , 5, + LSTE, 1, // Lid is open + , 1, + LWKE, 1, // Lid wake + , 5, Offset (0x07), - TMP1, 8, // CPU temperature + TMP1, 8, // CPU temperature Offset (0x10), - ADP, 1, // AC adapter connected - , 1, - BAT0, 1, // Battery connected - , 5, - WFNO, 8, // Wake cause (not implemented) + ADP, 1, // AC adapter connected + , 1, + BAT0, 1, // Battery connected + , 5, + WFNO, 8, // Wake cause (not implemented) Offset (0x16), - BDC0, 32, // Battery design capacity - BFC0, 32, // Battery full capacity + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity Offset (0x22), - BDV0, 32, // Battery design voltage - BST0, 32, // Battery status - BPR0, 32, // Battery current - BRC0, 32, // Battery remaining capacity - BPV0, 32, // Battery voltage + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage Offset (0x3A), - BCW0, 32, - BCL0, 32, + BCW0, 32, + BCL0, 32, Offset (0x68), - ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver Offset (0xC8), - OEM1, 8, - OEM2, 8, - OEM3, 16, - OEM4, 8, // Extra SCI data + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data Offset (0xCD), - TMP2, 8, // GPU temperature - DUT1, 8, // Fan 1 duty - DUT2, 8, // Fan 2 duty - RPM1, 16, // Fan 1 RPM - RPM2, 16, // Fan 2 RPM + TMP2, 8, // GPU temperature + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM Offset (0xD9), - AIRP, 8, // Airplane mode LED - WINF, 8, // Enable ACPI brightness controls + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, - FBF3, 8 + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, } diff --git a/src/ec/system76/ec/acpi/hid.asl b/src/ec/system76/ec/acpi/hid.asl index ce8fd3f28b..6610c2e1bc 100644 --- a/src/ec/system76/ec/acpi/hid.asl +++ b/src/ec/system76/ec/acpi/hid.asl @@ -30,13 +30,13 @@ Device (HIDD) Notify (HIDD, 0xC0) Local0 = Zero - While (((Local0 < 0xFA) && HBSY)) + While ((Local0 < 0xFA) && HBSY) { Sleep (0x04) Local0++ } - If ((HBSY == One)) + If (HBSY == One) { HBSY = Zero HIDX = Zero diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 6e7db17324..3b9e9776e9 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -41,6 +41,8 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ +#define ACPI_DSDT_REV_1 0x01 /* DSDT revision: ACPI v1 */ +#define ACPI_DSDT_REV_2 0x02 /* DSDT revision: ACPI v2.0 and greater */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include @@ -69,9 +71,9 @@ enum coreboot_acpi_ids { enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, + RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ - VFCT, NHLT, SPMI + VFCT, NHLT, SPMI, CRAT }; /* RSDP (Root System Description Pointer) */ @@ -97,19 +99,24 @@ typedef struct acpi_gen_regaddr { u32 addrh; /* Register address, high 32 bits */ } __packed acpi_addr_t; -#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ -#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ -#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ -#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ -#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ +#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_CMOS 5 /* SystemCMOS */ +#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET 6 /* PciBarTarget */ +#define ACPI_ADDRESS_SPACE_IPMI 7 /* IPMI */ +#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO 8 /* GeneralPurposeIO */ +#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS 9 /* GenericSerialBus */ +#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ +#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ @@ -250,6 +257,48 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __packed acpi_madt_t; +/* + * LPIT (Low Power Idle Table) + * Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017. + */ +typedef struct acpi_lpit { + acpi_header_t header; +} __packed acpi_lpit_t; + +/* LPIT: LPI descriptor flags */ +typedef struct acpi_lpi_flags { + uint32_t disabled : 1; + uint32_t counter_not_available : 1; + uint32_t reserved : 30; +} __packed acpi_lpi_desc_flags_t; + +/* LPIT: LPI descriptor types */ +enum acpi_lpi_desc_type { + ACPI_LPI_DESC_TYPE_NATIVE_CSTATE = 0x00, + /* type >= 1 reserved */ +}; + +/* LPIT: LPI descriptor header */ +typedef struct acpi_lpi_desc_hdr { + uint32_t type; + uint32_t length; + uint16_t uid; + uint16_t reserved; +} __packed acpi_lpi_desc_hdr_t; + +#define ACPI_LPIT_CTR_FREQ_TSC 0 + +/* LPIT: Native C-state instruction based LPI structure */ +typedef struct acpi_lpi_desc_ncst { + acpi_lpi_desc_hdr_t header; + acpi_lpi_desc_flags_t flags; + acpi_addr_t entry_trigger; /* Entry trigger C-state */ + uint32_t min_residency; /* Minimum residency or "break-even" in microseconds */ + uint32_t max_latency; /* Worst case exit latency in microseconds */ + acpi_addr_t residency_counter; + uint64_t counter_frequency; /* Frequency in cycles per second - 0 means TSC freq */ +} __packed acpi_lpi_desc_ncst_t; + /* VFCT image header */ typedef struct acpi_vfct_image_hdr { u32 PCIBus; @@ -300,6 +349,14 @@ typedef struct acpi_ivrs { struct acpi_ivrs_ivhd ivhd; } __packed acpi_ivrs_t; +/* CRAT (Component Resource Affinity Table Structure) */ +struct acpi_crat_header { + acpi_header_t header; + uint32_t total_entries; + uint16_t num_nodes; + uint8_t reserved[6]; +} __packed; + /* IVHD Type 11h IOMMU Attributes */ typedef struct ivhd11_iommu_attr { uint32_t reserved1 : 13; @@ -800,6 +857,26 @@ typedef struct acpi_cstate { acpi_addr_t resource; } __packed acpi_cstate_t; +struct acpi_sw_pstate { + u32 core_freq; + u32 power; + u32 transition_latency; + u32 bus_master_latency; + u32 control_value; + u32 status_value; +} __packed; + +struct acpi_xpss_sw_pstate { + u64 core_freq; + u64 power; + u64 transition_latency; + u64 bus_master_latency; + u64 control_value; + u64 status_value; + u64 control_mask; + u64 status_mask; +} __packed; + typedef struct acpi_tstate { u32 percent; u32 power; @@ -884,9 +961,13 @@ void arch_fill_fadt(acpi_fadt_t *fadt); void soc_fill_fadt(acpi_fadt_t *fadt); void mainboard_fill_fadt(acpi_fadt_t *fadt); +void acpi_fill_gnvs(void); + void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); +unsigned long acpi_fill_lpit(unsigned long current); + /* These can be used by the target port. */ u8 acpi_checksum(u8 *table, u32 length); @@ -937,6 +1018,10 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); +void acpi_create_crat(struct acpi_crat_header *crat, + unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, + unsigned long current)); + void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); @@ -986,10 +1071,14 @@ void acpi_write_hest(acpi_hest_t *hest, unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +void acpi_create_lpit(acpi_lpit_t *lpit); +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); + /* For ACPI S3 support. */ -void acpi_resume(void *wake_vec); +void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); +int acpi_handoff_wakeup_s3(void); /* ACPI_Sn assignments are defined to always equal the sleep state numbers */ enum { @@ -1017,6 +1106,8 @@ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) } #endif +uint8_t acpi_get_preferred_pm_profile(void); + /* Returns ACPI_Sx values. */ int acpi_get_sleep_type(void); @@ -1035,24 +1126,16 @@ static inline int acpi_s3_resume_allowed(void) return CONFIG(HAVE_ACPI_RESUME); } -#if CONFIG(HAVE_ACPI_RESUME) - -#if ENV_ROMSTAGE_OR_BEFORE static inline int acpi_is_wakeup_s3(void) { - return (acpi_get_sleep_type() == ACPI_S3); -} -#else -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_s4(void); -#endif + if (!acpi_s3_resume_allowed()) + return 0; -#else -static inline int acpi_is_wakeup(void) { return 0; } -static inline int acpi_is_wakeup_s3(void) { return 0; } -static inline int acpi_is_wakeup_s4(void) { return 0; } -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + return (acpi_get_sleep_type() == ACPI_S3); + + return acpi_handoff_wakeup_s3(); +} static inline uintptr_t acpi_align_current(uintptr_t current) { diff --git a/src/include/acpi/acpi_crat.h b/src/include/acpi/acpi_crat.h new file mode 100644 index 0000000000..b6ae1d64b6 --- /dev/null +++ b/src/include/acpi/acpi_crat.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ACPI_CRAT_H__ +#define __ACPI_CRAT_H__ + +enum crat_entry_type { + CRAT_HSA_PROC_UNIT_TYPE, + CRAT_MEMORY_TYPE, + CRAT_CACHE_TYPE, + CRAT_TLB_TYPE, + CRAT_FPU_TYPE, + CRAT_IO_TYPE, + CRAT_MAX_TYPE, +}; + +#define CRAT_HSA_PR_FLAG_EN_SHFT 0 +#define CRAT_HSA_PR_FLAG_EN (0x1 << CRAT_HSA_PR_FLAG_EN_SHFT) +#define CRAT_HSA_PR_FLAG_HOT_PLUG_SHFT 1 +#define CRAT_HSA_PR_FLAG_HOT_PLUG (0x1 << CRAT_HSA_PR_FLAG_HOT_PLUG_SHFT) +#define CRAT_HSA_PR_FLAG_CPU_PRES_SHFT 2 +#define CRAT_HSA_PR_FLAG_CPU_PRES (0x1 << CRAT_HSA_PR_FLAG_CPU_PRES_SHFT) +#define CRAT_HSA_PR_FLAG_GPU_PRES_SHFT 3 +#define CRAT_HSA_PR_FLAG_GPU_PRES (0x1 << CRAT_HSA_PR_FLAG_GPU_PRES_SHFT) +#define CRAT_HSA_PR_FLAG_CRAT_HSAMMU_SHFT 4 +#define CRAT_HSA_PR_FLAG_CRAT_HSAMMU (0x1 << CRAT_HSA_PR_FLAG_CRAT_HSAMMU_SHFT) +#define CRAT_HSA_PR_FLAG_VAL_LIM_SHFT 5 +#define CRAT_HSA_PR_FLAG_VAL_LIM (0x7 << CRAT_HSA_PR_FLAG_VAL_LIM_SHFT) +#define CRAT_HSA_PR_FLAG_ATOM_OPS_SHFT 8 +#define CRAT_HSA_PR_FLAG_ATOM_OPS (0x3 << CRAT_HSA_PR_FLAG_ATOM_OPS_SHFT) +#define CRAT_HSA_PR_FLAG_SMT_CAPS_SHFT 10 +#define CRAT_HSA_PR_FLAG_SMT_CAPS (0x3 << CRAT_HSA_PR_FLAG_SMT_CAPS_SHFT) + +/* CRAT HSA Processing Unit Affinity Structure */ +struct crat_hsa_processing_unit { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_node; + uint32_t processor_id_low; + uint16_t num_cpu_cores; + uint16_t num_simd_cores; + uint16_t max_waves_simd; + uint16_t io_count; + uint16_t hsa_capability; + uint16_t lds_size_in_kb; + uint8_t wave_front_size; + uint8_t num_shader_banks; + uint16_t uengine_identifier; + uint8_t num_arrays; + uint8_t num_cu_per_array; + uint8_t num_simd_per_cu; + uint8_t max_slots_scratch_cu; + uint8_t reserved1[4]; +} __packed; + +#define CRAT_L1_CACHE 1 +#define CRAT_L2_CACHE 2 +#define CRAT_L3_CACHE 3 + +#define CRAT_MEM_FLAG_EN_SHFT 0 +#define CRAT_MEM_FLAG_EN (0x1 << CRAT_MEM_FLAG_EN_SHFT) +#define CRAT_MEM_FLAG_HOT_PLUG_SHFT 1 +#define CRAT_MEM_FLAG_HOT_PLUG (0x1 << CRAT_MEM_FLAG_HOT_PLUG_SHFT) +#define CRAT_MEM_FLAG_NV_SHFT 2 +#define CRAT_MEM_FLAG_NV (0x1 << CRAT_MEM_FLAG_NV_SHFT) +#define CRAT_MEM_FLAG_ATOM_OPS_SHFT 3 +#define CRAT_MEM_FLAG_ATOM_OPS (0x3 << CRAT_MEM_FLAG_ATOM_OPS_SHFT) + +/* CRAT Memory Affinity Structure */ +struct crat_memory { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_domain; + uint32_t base_address_low; + uint32_t base_address_high; + uint32_t length_low; + uint32_t length_high; + uint32_t width; + uint8_t reserved1[8]; +} __packed; + +#define CRAT_CACHE_FLAG_EN_SHFT 0 +#define CRAT_CACHE_FLAG_EN (0x1 << CRAT_CACHE_FLAG_EN_SHFT) +#define CRAT_CACHE_FLAG_DATA_CACHE_SHFT 1 +#define CRAT_CACHE_FLAG_DATA_CACHE (0x1 << CRAT_CACHE_FLAG_DATA_CACHE_SHFT) +#define CRAT_CACHE_FLAG_INSTR_CACHE_SHFT 2 +#define CRAT_CACHE_FLAG_INSTR_CACHE (0x1 << CRAT_CACHE_FLAG_INSTR_CACHE_SHFT) +#define CRAT_CACHE_FLAG_CPU_CACHE_SHFT 3 +#define CRAT_CACHE_FLAG_CPU_CACHE (0x1 << CRAT_CACHE_FLAG_CPU_CACHE_SHFT) +#define CRAT_CACHE_FLAG_SIMD_CACHE_SHFT 4 +#define CRAT_CACHE_FLAG_SIMD_CACHE (0x1 << CRAT_CACHE_FLAG_SIMD_CACHE_SHFT) +#define CRAT_CACHE_FLAG_GDS_SHFT 5 +#define CRAT_CACHE_FLAG_GDS (0x1 << CRAT_CACHE_FLAG_GDS_SHFT) +#define CRAT_CACHE_FLAG_ATOMIC_OPS_SHFT 6 +#define CRAT_CACHE_FLAG_ATOMIC_OPS (0x1 << CRAT_CACHE_FLAG_ATOMIC_OPS_SHFT) + +/* CRAT Cache Affinity Structure */ +struct crat_cache { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t cache_size; + uint8_t cache_level; + uint8_t lines_per_tag; + uint16_t cache_line_size; + uint8_t associativity; + uint8_t cache_properties; + uint16_t cache_latency; + uint8_t reserved1[8]; +} __packed; + +enum tlb_type { + tlb_2m, + tlb_4k, + tlb_1g, + tlb_type_max, +}; + +#define CRAT_TLB_FLAG_EN_SHFT 0 +#define CRAT_TLB_FLAG_EN (0x1 << CRAT_TLB_FLAG_EN_SHFT) +#define CRAT_TLB_FLAG_DATA_TLB_SHFT 1 +#define CRAT_TLB_FLAG_DATA_TLB (0x1 << CRAT_TLB_FLAG_DATA_TLB_SHFT) +#define CRAT_TLB_FLAG_INSTR_TLB_SHFT 2 +#define CRAT_TLB_FLAG_INSTR_TLB (0x1 << CRAT_TLB_FLAG_INSTR_TLB_SHFT) +#define CRAT_TLB_FLAG_CPU_TLB_SHFT 3 +#define CRAT_TLB_FLAG_CPU_TLB (0x1 << CRAT_TLB_FLAG_CPU_TLB_SHFT) +#define CRAT_TLB_FLAG_SIMD_TLB_SHFT 4 +#define CRAT_TLB_FLAG_SIMD_TLB (0x1 << CRAT_TLB_FLAG_SIMD_TLB_SHFT) +#define CRAT_TLB_FLAG_4K_BASE_256_SHFT 5 +#define CRAT_TLB_FLAG_4K_BASE_256 (0x1 << CRAT_TLB_FLAG_4K_BASE_256_SHFT) +#define CRAT_TLB_FLAG_2MB_BASE_256_SHFT 7 +#define CRAT_TLB_FLAG_2MB_BASE_256 (0x1 << CRAT_TLB_FLAG_2MB_BASE_256_SHFT) +#define CRAT_TLB_FLAG_1GB_BASE_256_SHFT 9 +#define CRAT_TLB_FLAG_1GB_BASE_256 (0x1 << CRAT_TLB_FLAG_1GB_BASE_256_SHFT) + +/* CRAT TLB Affinity Structure */ +struct crat_tlb { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t tlb_level; + uint8_t data_tlb_2mb_assoc; + uint8_t data_tlb_2mb_size; + uint8_t instr_tlb_2mb_assoc; + uint8_t instr_tlb_2mb_size; + uint8_t data_tlb_4k_assoc; + uint8_t data_tlb_4k_size; + uint8_t instr_tlb_4k_assoc; + uint8_t instr_tlb_4k_size; + uint8_t data_tlb_1g_assoc; + uint8_t data_tlb_1g_size; + uint8_t instr_tlb_1g_assoc; + uint8_t instr_tlb_1g_size; + uint8_t reserved1[4]; +} __packed; + +#define CRAT_FPU_FLAG_EN_SHFT 0 +#define CRAT_FPU_FLAG_EN (0x1 << CRAT_TLB_FLAG_EN_SHFT) + +/* CRAT FPU Affinity Structure */ +struct crat_fpu { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t fpu_size; + uint8_t reserved1[16]; +} __packed; + +#define CRAT_IO_FLAG_EN_SHFT 0 +#define CRAT_IO_FLAG_EN (0x1 << CRAT_IO_FLAG_EN_SHFT) +#define CRAT_IO_FLAG_COHER_SHFT 1 +#define CRAT_IO_FLAG_COHER (0x1 << CRAT_IO_FLAG_COHER_SHFT) + +/* CRAT IO Affinity Structure */ +struct crat_io { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_domain_from; + uint32_t proximity_domain_to; + uint8_t io_type; + uint8_t version_major; + uint16_t version_minor; + uint32_t minimum_latency; + uint32_t maximum_latency; + uint32_t minimum_bandwidth; + uint32_t maximum_bandwidth; + uint32_t recommended_transfer_size; + uint8_t reserved1[24]; +} __packed; + +#endif /* __ACPI_CRAT_H__ */ diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 6287ba1672..301f9b0156 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -4,8 +4,8 @@ #define __ACPI_ACPI_DEVICE_H__ #include -#include #include +#include enum acpi_dp_type { ACPI_DP_TYPE_UNKNOWN, @@ -545,6 +545,22 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low); +struct acpi_gpio_res_params { + /* Reference to the parent device. */ + const char *ref; + /* Index to the GpioIo resource within the _CRS. */ + int index; + /* Index to the pin within the GpioIo resource, usually 0. */ + int pin; + /* Flag to indicate if pin is active low. */ + int active_low; +}; + +/* Add a GPIO binding device property for array of GPIOs */ +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const struct acpi_gpio_res_params *params, + size_t param_count); + /* Add a child table of Device Properties */ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, struct acpi_dp *child); diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index 6173fa168b..b35874d4e9 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -7,30 +7,22 @@ void *acpi_get_gnvs(void); void *gnvs_get_or_create(void); -void acpi_inject_nvsa(void); void gnvs_assign_chromeos(void); +void gnvs_set_ecfw_rw(void); /* Platform code must implement these. */ +struct global_nvs; size_t gnvs_size_of_array(void); -uint32_t *gnvs_cbmc_ptr(void); -void *gnvs_chromeos_ptr(void); +uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs); +void *gnvs_chromeos_ptr(struct global_nvs *gnvs); /* - * Creates acpi gnvs and adds it to the DSDT table. - * GNVS creation is chipset specific and is done in soc specific acpi.c file. - */ -struct device; -void southbridge_inject_dsdt(const struct device *device); - -/* - * This function populates the gnvs structure in acpi table. + * These functions populate the gnvs structure in acpi table. * Defined as weak in common acpi as gnvs structure definition is * chipset specific. */ -struct global_nvs; - -void acpi_create_gnvs(struct global_nvs *gnvs); -void acpi_init_gnvs(struct global_nvs *gnvs); +void soc_fill_gnvs(struct global_nvs *gnvs); +void mainboard_fill_gnvs(struct global_nvs *gnvs); #endif diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index 82748d0f5f..fe0aa408fd 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -11,6 +11,8 @@ #ifndef __ACPI_ACPI_IVRS_H__ #define __ACPI_ACPI_IVRS_H__ +#include + /* I/O Virtualization Reporting Structure (IVRS) */ #define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 #define IVHD_BLOCK_TYPE_FULL__FIXED 0x11 @@ -40,6 +42,7 @@ /* Extended Feature Support */ #define IVINFO_EFR_SUPPORTED 0x01 +#define EFR_FEATURE_SUP (1 << 27) /* IVHD Flags Field */ #define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ @@ -61,6 +64,7 @@ #define IOMMU_FEATURE_PN_BANKS_SHIFT 17 #define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 #define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ +#define IOMMU_FEATURE_GLX_SHIFT 3 #define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ #define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ @@ -68,8 +72,9 @@ #define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ -#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */ +#define IOMMU_FEATURE_GT_SUP (1 << 2) /* Type 10h only */ +#define IOMMU_FEATURE_NX_SUP (1 << 1) /* Type 10h only */ +#define IOMMU_FEATURE_XT_SUP (1 << 0) /* IVHD Device Entry Type Codes */ #define IVHD_DEV_4_BYTE_ALL 0x01 @@ -106,6 +111,64 @@ #define IVHD_UID_INT 0x01 #define IVHD_UID_STRING 0x02 +#define IOMMU_CAP_ID 0x0f + +/* MMIO Offset 0x30: IOMMU Extended Feature Register */ +#define MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT 0 +#define MMIO_EXT_FEATURE_PRE_F_SUP (0x1 << MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PPR_SUP_SHIFT 1 +#define MMIO_EXT_FEATURE_PPR_SUP (0x1 << MMIO_EXT_FEATURE_PPR_SUP_SHIFT) +#define MMIO_EXT_FEATURE_XT_SUP_SHIFT 2 +#define MMIO_EXT_FEATURE_XT_SUP (0x1 << MMIO_EXT_FEATURE_XT_SUP_SHIFT) +#define MMIO_EXT_FEATURE_NX_SUP_SHIFT 3 +#define MMIO_EXT_FEATURE_NX_SUP (0x1 << MMIO_EXT_FEATURE_NX_SUP_SHIFT) +#define MMIO_EXT_FEATURE_GT_SUP_SHIFT 4 +#define MMIO_EXT_FEATURE_GT_SUP (0x1 << MMIO_EXT_FEATURE_GT_SUP_SHIFT) +#define MMIO_EXT_FEATURE_IA_SUP_SHIFT 6 +#define MMIO_EXT_FEATURE_IA_SUP (0x1 << MMIO_EXT_FEATURE_IA_SUP_SHIFT) +#define MMIO_EXT_FEATURE_GA_SUP_SHIFT 7 +#define MMIO_EXT_FEATURE_GA_SUP (0x1 << MMIO_EXT_FEATURE_GA_SUP_SHIFT) +#define MMIO_EXT_FEATURE_HE_SUP_SHIFT 8 +#define MMIO_EXT_FEATURE_HE_SUP (0x1 << MMIO_EXT_FEATURE_HE_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PC_SUP_SHIFT 9 +#define MMIO_EXT_FEATURE_PC_SUP (0x1 << MMIO_EXT_FEATURE_PC_SUP_SHIFT) +#define MMIO_EXT_FEATURE_HATS_SHIFT 10 +#define MMIO_EXT_FEATURE_HATS_MASK (0x3 << MMIO_EXT_FEATURE_HATS_SHIFT) +#define MMIO_EXT_FEATURE_GATS_SHIFT 12 +#define MMIO_EXT_FEATURE_GATS_MASK (0x3 << MMIO_EXT_FEATURE_GATS_SHIFT) +#define MMIO_EXT_FEATURE_GLX_SHIFT 14 +#define MMIO_EXT_FEATURE_GLX_SUP_MASK (0x3 << MMIO_EXT_FEATURE_GLX_SHIFT) +#define MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT 16 +#define MMIO_EXT_FEATURE_SMI_F_SUP_MASK (0x3 << MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT) +#define MMIO_EXT_FEATURE_SMI_FRC_SHIFT 18 +#define MMIO_EXT_FEATURE_SMI_FRC_MASK (0x7 << MMIO_EXT_FEATURE_SMI_FRC_SHIFT) +#define MMIO_EXT_FEATURE_GAM_SUP_SHIFT 21 +#define MMIO_EXT_FEATURE_GAM_SUP_MASK (0x7 << MMIO_EXT_FEATURE_GAM_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PAS_MAX_SHIFT 32 +#define MMIO_EXT_FEATURE_PAS_MAX_MASK (0x1fULL << MMIO_EXT_FEATURE_PAS_MAX_SHIFT) + +/* MMIO Offset 0x18: IOMMU Control Register */ +#define MMIO_CTRL_IOMMU_EN (1 << 0) +#define MMIO_CTRL_HT_TUN_EN (1 << 1) +#define MMIO_CTRL_PASS_PW (1 << 8) +#define MMIO_CTRL_RES_PASS_PW (1 << 9) +#define MMIO_CTRL_COHERENT (1 << 10) +#define MMIO_CTRL_ISOC (1 << 11) + +/* MMIO Offset 0x4000: Counter Configuration Register */ +#define MMIO_CNT_CFG_N_CNT_BANKS_SHIFT 12 +#define MMIO_CNT_CFG_N_COUNTER_BANKS (0x3f << MMIO_CNT_CFG_N_CNT_BANKS_SHIFT) +#define MMIO_CNT_CFG_N_COUNTER_SHIFT 7 +#define MMIO_CNT_CFG_N_COUNTER (0xf << MMIO_CNT_CFG_N_COUNTER_SHIFT) + +/* Capability offset 0 */ +#define CAP_OFFSET_0_IOTLB_SP_SHIFT 24 +#define CAP_OFFSET_0_IOTLB_SP (1 << CAP_OFFSET_0_IOTLB_SP_SHIFT) + +/// Capability offset 10h +#define CAP_OFFSET_10_MSI_NUM_PPR_SHIFT 27 +#define CAP_OFFSET_10_MSI_NUM_PPR (0x1f << CAP_OFFSET_10_MSI_NUM_PPR_SHIFT) + /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ typedef struct ivrs_ivhd_generic { uint8_t type; @@ -123,6 +186,24 @@ typedef struct ivrs_ivhd_alias { uint8_t reserved2; } __packed ivrs_ivhd_alias_t; +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */ +typedef struct acpi_ivrs_ivhd_40 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + uint32_t iommu_attributes; + uint32_t efr_reg_image_low; + uint32_t efr_reg_image_high; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd40_t; + typedef struct ivrs_ivhd_extended { uint8_t type; uint16_t dev_id; @@ -139,4 +220,14 @@ typedef struct ivrs_ivhd_special { uint8_t variety; } __packed ivrs_ivhd_special_t; +typedef struct ivrs_ivhd_f0_entry { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint8_t hardware_id[8]; + uint8_t compatible_id[8]; + uint8_t uuid_format; + uint8_t uuid_length; +} __packed ivrs_ivhd_f0_entry_t; + #endif /* __ACPI_ACPI_IVRS_H__ */ diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 98a9fe474c..15af0192a3 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -3,6 +3,7 @@ #ifndef __ACPI_ACPIGEN_H__ #define __ACPI_ACPIGEN_H__ +#include #include #include #include @@ -157,6 +158,10 @@ enum { .name = X, \ .bits = Y, \ } +#define FIELDLIST_RESERVED(X) { .type = RESERVED, \ + .name = "", \ + .bits = X, \ + } #define FIELD_ANYACC 0 #define FIELD_BYTEACC 1 @@ -173,6 +178,7 @@ enum { enum field_type { OFFSET, NAME_STRING, + RESERVED, FIELD_TYPE_MAX, }; @@ -225,6 +231,10 @@ struct dsm_uuid { void *arg; }; +#define CPPC_VERSION_1 1 +#define CPPC_VERSION_2 2 +#define CPPC_VERSION_3 3 + /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ enum cppc_fields { CPPC_HIGHEST_PERF, /* can be DWORD */ @@ -276,6 +286,7 @@ struct cppc_config { }; void acpigen_write_return_integer(uint64_t arg); +void acpigen_write_return_namestr(const char *arg); void acpigen_write_return_string(const char *arg); void acpigen_write_len_f(void); void acpigen_pop_len(void); @@ -323,6 +334,7 @@ void acpigen_write_STA_ext(const char *namestring); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); +void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries); typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); @@ -330,6 +342,10 @@ void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); +void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts); +void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value); +void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, + size_t nentries); void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); void acpigen_write_processor_package(const char *name, unsigned int first_core, @@ -350,6 +366,8 @@ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, const char * const dev_states[], size_t dev_states_count); void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst); +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); @@ -357,6 +375,7 @@ void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_not(uint8_t arg, uint8_t res); void acpigen_write_debug_string(const char *str); +void acpigen_write_debug_namestr(const char *str); void acpigen_write_debug_integer(uint64_t val); void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); @@ -365,8 +384,10 @@ void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val); void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); void acpigen_write_to_integer(uint8_t src, uint8_t dst); +void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op); void acpigen_write_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); @@ -379,6 +400,10 @@ void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); struct soundwire_address; void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); +void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name); /* * Generate ACPI AML code for _DSM method. * This function takes as input uuid for the device, set of callbacks and @@ -410,7 +435,7 @@ void acpigen_write_rom(void *bios, const size_t length); * This function takes input region name, region space, region offset & region * length. */ -void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_opregion(const struct opregion *opreg); /* * Generate ACPI AML code for Mutex * This function takes mutex name and initial value. @@ -443,7 +468,7 @@ int get_cst_entries(acpi_cstate_t **); /* * Get element from package into specified destination op: - * = DeRefOf ([ = DeRefOf ([]) * * Example: * acpigen_get_package_op_element(ARG0_OP, 0, LOCAL0_OP) @@ -451,6 +476,25 @@ int get_cst_entries(acpi_cstate_t **); */ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op); +/* Set element of package op to specified op: DeRefOf ([]) = */ +void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src); + +/* Get element from package to specified op: = [] */ +void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op); + +/* Set element of package to specified op: [] = */ +void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src); + +/* Set element of package to specified namestr: [] = */ +void acpigen_set_package_element_namestr(const char *package, unsigned int element, + const char *src); + +/* + * Delay up to wait_ms milliseconds until the provided name matches the expected value. + * If wait_ms is >= 32ms then it will wait in 16ms chunks. This function uses LOCAL7_OP. + */ +void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value); + /* * Soc-implemented functions for generating ACPI AML code for GPIO handling. All * these functions are expected to use only Local5, Local6 and Local7 @@ -480,8 +524,8 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio); +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a RX GPIO value based on the GPIO polarity. @@ -489,7 +533,7 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_rx_gpio(struct acpi_gpio *gpio); +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a TX GPIO value based on the GPIO polarity. @@ -497,7 +541,7 @@ void acpigen_get_rx_gpio(struct acpi_gpio *gpio); * This function ends up calling acpigen_soc_get_tx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_tx_gpio(struct acpi_gpio *gpio); +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio); /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 1790df77e8..b173bb8214 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -5,6 +5,7 @@ #include #include +#include /* A common idiom is to use a default value if none is provided (i.e., == 0) */ #define DEFAULT_IF_0(thing, default_) ((thing) ? (thing) : (default_)) diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h index 90524c2e5a..858c2ce1c3 100644 --- a/src/include/acpi/acpigen_ps2_keybd.h +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __ACPI_ACPIGEN_PS2_KEYBD_H__ #define __ACPI_ACPIGEN_PS2_KEYBD_H__ diff --git a/src/include/asan.h b/src/include/asan.h new file mode 100644 index 0000000000..103fcc92d2 --- /dev/null +++ b/src/include/asan.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASAN_H +#define __ASAN_H + +#include + +#define ASAN_SHADOW_SCALE_SHIFT 3 + +#define ASAN_SHADOW_SCALE_SIZE (1UL << ASAN_SHADOW_SCALE_SHIFT) +#define ASAN_SHADOW_MASK (ASAN_SHADOW_SCALE_SIZE - 1) + +#define ASAN_GLOBAL_REDZONE 0xFA +#define ASAN_STACK_LEFT 0xF1 +#define ASAN_STACK_MID 0xF2 +#define ASAN_STACK_RIGHT 0xF3 +#define ASAN_STACK_PARTIAL 0xF4 +#define ASAN_USE_AFTER_SCOPE 0xF8 + +#define _RET_IP_ ((unsigned long)__builtin_return_address(0)) +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define WARN_ON(condition) ({ \ + int __ret_warn_on = !!(condition); \ + unlikely(__ret_warn_on); \ +}) + +#ifndef ASAN_ABI_VERSION +#define ASAN_ABI_VERSION 5 +#endif + +/* The layout of struct dictated by compiler */ +struct asan_source_location { + const char *filename; + int line_no; + int column_no; +}; + +/* The layout of struct dictated by compiler */ +struct asan_global { + const void *beg; /* Address of the beginning of the global variable. */ + size_t size; /* Size of the global variable. */ + size_t size_with_redzone; /* Size of the variable + size of the red zone + 32 bytes aligned. */ + const void *name; + const void *module_name; /* Name of the module where the global variable + is declared. */ + unsigned long has_dynamic_init; /* This needed for C++. */ +#if ASAN_ABI_VERSION >= 4 + struct asan_source_location *location; +#endif +#if ASAN_ABI_VERSION >= 5 + char *odr_indicator; +#endif +}; + +void asan_unpoison_shadow(const void *address, size_t size); +void asan_report(unsigned long addr, size_t size, bool is_write, + unsigned long ip); +void asan_init(void); +void check_memory_region(unsigned long addr, size_t size, bool write, + unsigned long ret_ip); + +uintptr_t __asan_shadow_offset(uintptr_t addr); +void __asan_register_globals(struct asan_global *globals, size_t size); +void __asan_unregister_globals(struct asan_global *globals, size_t size); +void __asan_poison_stack_memory(const void *addr, size_t size); +void __asan_unpoison_stack_memory(const void *addr, size_t size); + +void __asan_load1(unsigned long addr); +void __asan_store1(unsigned long addr); +void __asan_load2(unsigned long addr); +void __asan_store2(unsigned long addr); +void __asan_load4(unsigned long addr); +void __asan_store4(unsigned long addr); +void __asan_load8(unsigned long addr); +void __asan_store8(unsigned long addr); +void __asan_load16(unsigned long addr); +void __asan_store16(unsigned long addr); +void __asan_loadN(unsigned long addr, size_t size); +void __asan_storeN(unsigned long addr, size_t size); + +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_load16_noabort(unsigned long addr); +void __asan_store16_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t size); +void __asan_storeN_noabort(unsigned long addr, size_t size); +void __asan_handle_no_return(void); + +void __asan_set_shadow_00(const void *addr, size_t size); +void __asan_set_shadow_f1(const void *addr, size_t size); +void __asan_set_shadow_f2(const void *addr, size_t size); +void __asan_set_shadow_f3(const void *addr, size_t size); +void __asan_set_shadow_f5(const void *addr, size_t size); +void __asan_set_shadow_f8(const void *addr, size_t size); + +void __asan_report_load1_noabort(unsigned long addr); +void __asan_report_store1_noabort(unsigned long addr); +void __asan_report_load2_noabort(unsigned long addr); +void __asan_report_store2_noabort(unsigned long addr); +void __asan_report_load4_noabort(unsigned long addr); +void __asan_report_store4_noabort(unsigned long addr); +void __asan_report_load8_noabort(unsigned long addr); +void __asan_report_store8_noabort(unsigned long addr); +void __asan_report_load16_noabort(unsigned long addr); +void __asan_report_store16_noabort(unsigned long addr); +void __asan_report_load_n_noabort(unsigned long addr, size_t size); +void __asan_report_store_n_noabort(unsigned long addr, size_t size); +#endif diff --git a/src/include/assert.h b/src/include/assert.h index f656d81683..944c67768a 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -5,6 +5,7 @@ #include #include +#include /* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more properly isolated. */ @@ -12,31 +13,48 @@ #undef ASSERT #endif +/* Do not use filenames nor line numbers on timeless builds, to preserve reproducibility */ +#if ENV_TIMELESS +#define __ASSERT_FILE__ "(filenames not available on timeless builds)" +#define __ASSERT_LINE__ 404 +#else +#define __ASSERT_FILE__ __FILE__ +#define __ASSERT_LINE__ __LINE__ +#endif + +#ifndef _PORTING_H_ /* TODO: Isolate AGESA properly. */ +#define __build_time_assert(x) \ + (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) +#else +#define __build_time_assert(x) 0 +#endif + /* GCC and CAR versions */ -#define ASSERT(x) { \ - if (!(x)) { \ - printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ - ", line %d\n", __FILE__, __LINE__); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ - } \ +#define ASSERT(x) { \ + if (!__build_time_assert(x) && !(x)) { \ + printk(BIOS_EMERG, \ + "ASSERTION ERROR: file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ } - -#define ASSERT_MSG(x, msg) { \ - if (!(x)) { \ - printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ - ", line %d\n", __FILE__, __LINE__); \ - printk(BIOS_EMERG, "%s", msg); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ - } \ +#define ASSERT_MSG(x, msg) { \ + if (!__build_time_assert(x) && !(x)) { \ + printk(BIOS_EMERG, \ + "ASSERTION ERROR: file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + printk(BIOS_EMERG, "%s", msg); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ } - -#define BUG() { \ - printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ - ", line %d\n", __FILE__, __LINE__); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ +#define BUG() { \ + printk(BIOS_EMERG, \ + "ERROR: BUG ENCOUNTERED at file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ } #define assert(statement) ASSERT(statement) @@ -62,4 +80,15 @@ extern void _dead_code_assertion_failed(void) __attribute__((noreturn)); *(type *)(uintptr_t)0; \ }) +#ifdef __x86_64__ +#define pointer_to_uint32_safe(x) ({ \ + if ((uintptr_t)(x) > 0xffffffffUL) \ + die("Cast from pointer to uint32_t overflows"); \ + (uint32_t)(uintptr_t)(x); \ +}) +#else +#define pointer_to_uint32_safe(x) ({ \ + (uint32_t)(uintptr_t)(x); \ +}) +#endif #endif // __ASSERT_H__ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 5bebd4a623..7fd9ac169b 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -3,6 +3,8 @@ #include #include +#include + /* function prototypes for building the coreboot table */ /* diff --git a/src/include/boot_device.h b/src/include/boot_device.h index a03e5aa8f3..84bd16ef65 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -27,7 +27,8 @@ enum bootdev_prot_type { * most likely not to work so don't rely on such semantics. */ -/* Return the region_device for the read-only boot device. */ +/* Return the region_device for the read-only boot device. This is the root + device for all CBFS boot devices. */ const struct region_device *boot_device_ro(void); /* Return the region_device for the read-write boot device. */ diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96629..da627d23d4 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -29,6 +29,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist); asmlinkage void ap_bootblock_c_entry(void); void bootblock_main_with_basetime(uint64_t base_timestamp); +void bootblock_main_with_timestamp(uint64_t base_timestamp, + struct timestamp_entry *timestamps, size_t num_timestamps); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 3262b3a5c0..9fac70113e 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -4,7 +4,6 @@ #include #include -#include /* Only declare main() when in ramstage. */ #if ENV_RAMSTAGE #include diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 29621c6680..cad01c623d 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -3,8 +3,11 @@ #ifndef _CBFS_H_ #define _CBFS_H_ +#include #include #include +#include +#include /*********************************************** * Perform CBFS operations on the boot device. * @@ -16,19 +19,28 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev); /* Locate file by name and optional type. Return 0 on success. < 0 on error. */ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Map file into memory leaking the mapping. Only should be used when - * leaking mappings are a no-op. Returns NULL on error, else returns - * the mapping and sets the size of the file. */ -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); +/* Map file into memory, returning a pointer to the mapping or NULL on error. + If |size_out| is not NULL, it will pass out the size of the mapped file. + NOTE: Since this may return a direct pointer to memory-mapped hardware, + compressed files are NOT transparently decompressed (unlike cbfs_load()). */ +void *cbfs_map(const char *name, size_t *size_out); +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size_out); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ +int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type); -/* Load an arbitrary type file from CBFS into a buffer. Returns amount of - * loaded bytes on success or 0 on error. File will get decompressed as - * necessary. Same decompression requirements as - * cbfs_load_and_decompress(). */ -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type); +/* Load a file from CBFS into a buffer. Returns amount of loaded bytes on + success or 0 on error. File will get decompressed as necessary. Same + decompression requirements as cbfs_load_and_decompress(). */ +size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. @@ -40,8 +52,36 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); -/* Returns the region device of the currently active CBFS. - Return < 0 on error, 0 on success. */ -int cbfs_boot_region_device(struct region_device *rdev); +/* + * Data structure that represents "a" CBFS boot device, with optional metadata + * cache. Generally we only have one of these, or two (RO and RW) when + * CONFIG(VBOOT) is set. The region device stored here must always be a + * subregion of boot_device_ro(). + */ +struct cbfs_boot_device { + struct region_device rdev; + void *mcache; + size_t mcache_size; +}; + +/* Helper to fill out |mcache| and |mcache_size| in a cbfs_boot_device. */ +void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id); + +/* + * Retrieves the currently active CBFS boot device. If |force_ro| is set, will + * always return the read-only CBFS instead (this only makes a difference when + * CONFIG(VBOOT) is enabled). May perform certain CBFS initialization tasks. + * Returns NULL on error (e.g. boot device IO error). + */ +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro); + +/* + * Builds the mcache (if |cbd->mcache| is set) and verifies |metadata_hash| (if + * it is not NULL). If CB_CBFS_CACHE_FULL is returned, the mcache is incomplete + * but still valid and the metadata hash was still verified. Should be called + * once per *boot* (not once per stage) before the first CBFS access. + */ +cb_err_t cbfs_init_boot_device(const struct cbfs_boot_device *cbd, + struct vb2_hash *metadata_hash); #endif diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h new file mode 100644 index 0000000000..ffca83ef06 --- /dev/null +++ b/src/include/cbfs_glue.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include +#include +#include + +/* + * This flag prevents linking hashing functions into stages where they're not required. We don't + * need them at all if verification is disabled. If verification is enabled without TOCTOU + * safety, we only need to verify the metadata hash in the initial stage and can assume it stays + * valid in later stages. If TOCTOU safety is required, we may need them in every stage to + * reverify metadata that had to be reloaded from flash (e.g. because it didn't fit the mcache). + * Note that this only concerns metadata hashing -- file access functions may still link hashing + * routines independently for file data hashing. + */ +#define CBFS_ENABLE_HASHING (CONFIG(CBFS_VERIFICATION) && \ + (CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE)) + +#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#define DEBUG(...) do { \ + if (CONFIG(DEBUG_CBFS)) \ + printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \ +} while (0) + +typedef const struct region_device *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + return rdev_readat(dev, buffer, offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return region_device_sz(dev); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/src/include/cbfs_private.h b/src/include/cbfs_private.h new file mode 100644 index 0000000000..8e9803616f --- /dev/null +++ b/src/include/cbfs_private.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_PRIVATE_H_ +#define _CBFS_PRIVATE_H_ + +#include +#include +#include + +/* + * This header contains low-level CBFS APIs that should only be used by code + * that really needs this level of access. Most code (particularly platform + * code) should use the higher-level CBFS APIs in . Code using these + * APIs needs to take special care to ensure CBFS file data is verified (in a + * TOCTOU-safe manner) before access (TODO: add details on how to do this once + * file verification code is in). + */ + +/* Find by name, load metadata into |mdata| and chain file data to |rdev|. */ +cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev); + +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b548cd9559..9e12afe4a3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -155,4 +155,15 @@ static inline int cbmem_possibly_online(void) return 1; } +/* Returns 1 after running cbmem init hooks, 0 otherwise. */ +static inline int cbmem_online(void) +{ + extern int cbmem_initialized; + + if (!cbmem_possibly_online()) + return 0; + + return cbmem_initialized; +} + #endif /* _CBMEM_H_ */ diff --git a/src/include/console/debug.h b/src/include/console/debug.h new file mode 100644 index 0000000000..174c287c6a --- /dev/null +++ b/src/include/console/debug.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CONSOLE_DEBUG_H_ +#define _CONSOLE_DEBUG_H_ + +#if CONFIG(DEBUG_FUNC) +#include + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +#else /* FUNC_DEBUG */ + +#define FUNC_ENTER() +#define FUNC_EXIT() + +#endif /* FUNC_DEBUG */ + +#endif diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 8104e5c485..9a0dc63915 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -27,5 +27,4 @@ static inline void __flashconsole_tx_byte(u8 data) {} static inline void __flashconsole_tx_flush(void) {} #endif /* __CONSOLE_FLASH_ENABLE__ */ - #endif /* CONSOLE_FLASH_H */ diff --git a/src/include/console/spi.h b/src/include/console/spi.h index cb32d7e64c..2eff0a8903 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -8,7 +8,7 @@ void spiconsole_init(void); void spiconsole_tx_byte(unsigned char c); -#define __CONSOLE_SPI_ENABLE__ (CONFIG(SPI_CONSOLE) && \ +#define __CONSOLE_SPI_ENABLE__ (CONFIG(EM100PRO_SPI_CONSOLE) && \ (ENV_RAMSTAGE || (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CONSOLE_SPI_ENABLE__ @@ -52,6 +52,4 @@ struct em100_msg { char data[MAX_MSG_LENGTH]; } __packed; - - #endif /* CONSOLE_SPI_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 9d37886ccd..2e23d43a4e 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -20,6 +20,18 @@ static inline unsigned int get_uart_baudrate(void) } #endif +#if CONFIG(OVERRIDE_UART_FOR_CONSOLE) +/* Return the index of uart port, define this in your platform + * when need to use variables to override the index. + */ +unsigned int get_uart_for_console(void); +#else +static inline unsigned int get_uart_for_console(void) +{ + return CONFIG_UART_FOR_CONSOLE; +} +#endif + /* Returns the divisor value for a given baudrate. * The formula to satisfy is: * refclk / divisor = baudrate * oversample @@ -35,14 +47,14 @@ unsigned int uart_input_clock_divider(void); /* Bitbang out one byte on an 8n1 UART through the output function set_tx(). */ void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state)); -void uart_init(int idx); -void uart_tx_byte(int idx, unsigned char data); -void uart_tx_flush(int idx); -unsigned char uart_rx_byte(int idx); +void uart_init(unsigned int idx); +void uart_tx_byte(unsigned int idx, unsigned char data); +void uart_tx_flush(unsigned int idx); +unsigned char uart_rx_byte(unsigned int idx); -uintptr_t uart_platform_base(int idx); +uintptr_t uart_platform_base(unsigned int idx); -static inline void *uart_platform_baseptr(int idx) +static inline void *uart_platform_baseptr(unsigned int idx) { return (void *)uart_platform_base(idx); } @@ -56,15 +68,15 @@ void oxford_remap(unsigned int new_base); #if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_init(void) { - uart_init(CONFIG_UART_FOR_CONSOLE); + uart_init(get_uart_for_console()); } static inline void __uart_tx_byte(u8 data) { - uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); + uart_tx_byte(get_uart_for_console(), data); } static inline void __uart_tx_flush(void) { - uart_tx_flush(CONFIG_UART_FOR_CONSOLE); + uart_tx_flush(get_uart_for_console()); } #else static inline void __uart_init(void) {} diff --git a/src/include/cpu/amd/cpuid.h b/src/include/cpu/amd/cpuid.h new file mode 100644 index 0000000000..b593562a09 --- /dev/null +++ b/src/include/cpu/amd/cpuid.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file applies to AMD64 products. + * The definitions come from the AMD64 Programmers Manual vol2 + * Revision 3.30 and/or the device's BKDG. + */ + +#ifndef CPU_AMD_CPUID_H +#define CPU_AMD_CPUID_H + +#define CPUID_L1_TLB_CACHE_IDS 0x80000005 +/* Fn0x80000005_EAX */ +#define L1_DAT_TLB_2M4M_ASSOC_SHFT 24 +#define L1_DAT_TLB_2M4M_ASSOC_MASK (0xff << L1_DAT_TLB_2M4M_ASSOC_SHFT) +#define L1_DAT_TLB_2M4M_SIZE_SHFT 16 +#define L1_DAT_TLB_2M4M_SIZE_MASK (0xff << L1_DAT_TLB_2M4M_SIZE_SHFT) +#define L1_INST_TLB_2M4M_ASSOC_SHFT 8 +#define L1_INST_TLB_2M4M_ASSOC_MASK (0xff << L1_INST_TLB_2M4M_ASSOC_SHFT) +#define L1_INST_TLB_2M4M_SIZE_SHFT 0 +#define L1_INST_TLB_2M4M_SIZE_MASK (0xff << L1_INST_TLB_2M4M_SIZE_SHFT) +/* Fn0x80000005_EBX */ +#define L1_DAT_TLB_4K_ASSOC_SHFT 24 +#define L1_DAT_TLB_4K_ASSOC_MASK (0xff << L1_DAT_TLB_4K_ASSOC_SHFT) +#define L1_DAT_TLB_4K_SIZE_SHFT 16 +#define L1_DAT_TLB_4K_SIZE_MASK (0xff << L1_DAT_TLB_4K_SIZE_SHFT) +#define L1_INST_TLB_4K_ASSOC_SHFT 8 +#define L1_INST_TLB_4K_ASSOC_MASK (0xff << L1_INST_TLB_4K_ASSOC_SHFT) +#define L1_INST_TLB_4K_SIZE_SHFT 0 +#define L1_INST_TLB_4K_SIZE_MASK (0xff << L1_INST_TLB_4K_SIZE_SHFT) +/* Fn0x80000005_ECX */ +#define L1_DC_SIZE_SHFT 24 +#define L1_DC_SIZE_MASK (0xff << L1_DC_SIZE_SHFT) +#define L1_DC_ASSOC_SHFT 16 +#define L1_DC_ASSOC_MASK (0xff << L1_DC_ASSOC_SHFT) +#define L1_DC_LINE_TAG_SHFT 8 +#define L1_DC_LINE_TAG_MASK (0xff << L1_DC_LINE_TAG_SHFT) +#define L1_DC_LINE_SIZE_SHFT 0 +#define L1_DC_LINE_SIZE_MASK (0xff << L1_DC_LINE_SIZE_SHFT) +/* Fn0x80000005_EDX */ +#define L1_IC_SIZE_SHFT 24 +#define L1_IC_SIZE_MASK (0xff << L1_IC_SIZE_SHFT) +#define L1_IC_ASSOC_SHFT 16 +#define L1_IC_ASSOC_MASK (0xff << L1_IC_ASSOC_SHFT) +#define L1_IC_LINE_TAG_SHFT 8 +#define L1_IC_LINE_TAG_MASK (0xff << L1_IC_LINE_TAG_SHFT) +#define L1_IC_LINE_SIZE_SHFT 0 +#define L1_IC_LINE_SIZE_MASK (0xff << L1_IC_LINE_SIZE_SHFT) + +#define CPUID_L2_L3_CACHE_L2_TLB_IDS 0x80000006 +/* Fn0x80000006_EAX */ +#define L2_DAT_TLB_2M4M_ASSOC_SHFT 28 +#define L2_DAT_TLB_2M4M_ASSOC_MASK (0xf << L2_DAT_TLB_2M4M_ASSOC_SHFT) +#define L2_DAT_TLB_2M4M_SIZE_SHFT 16 +#define L2_DAT_TLB_2M4M_SIZE_MASK (0xfff << L2_DAT_TLB_2M4M_SIZE_SHFT) +#define L2_INST_TLB_2M4M_ASSOC_SHFT 12 +#define L2_INST_TLB_2M4M_ASSOC_MASK (0xf << L2_INST_TLB_2M4M_ASSOC_SHFT) +#define L2_INST_TLB_2M4M_SIZE_SHFT 0 +#define L2_INST_TLB_2M4M_SIZE_MASK (0xfff << L2_INST_TLB_2M4M_SIZE_SHFT) +/*Fn0x80000006_EBX */ +#define L2_DAT_TLB_4K_ASSOC_SHFT 28 +#define L2_DAT_TLB_4K_ASSOC_MASK (0xf << L2_DAT_TLB_4K_ASSOC_SHFT) +#define L2_DAT_TLB_4K_SIZE_SHFT 16 +#define L2_DAT_TLB_4K_SIZE_MASK (0xfff << L2_DAT_TLB_4K_SIZE_SHFT) +#define L2_INST_TLB_4K_ASSOC_SHFT 12 +#define L2_INST_TLB_4K_ASSOC_MASK (0xf << L2_INST_TLB_4K_ASSOC_SHFT) +#define L2_INST_TLB_4K_SIZE_SHFT 0 +#define L2_INST_TLB_4K_SIZE_MASK (0xfff << L2_INST_TLB_4K_SIZE_SHFT) +/* Fn0x80000006_ECX */ +#define L2_DC_SIZE_SHFT 16 +#define L2_DC_SIZE_MASK (0xffff << L2_DC_SIZE_SHFT) +#define L2_DC_ASSOC_SHFT 12 +#define L2_DC_ASSOC_MASK (0xf << L2_DC_ASSOC_SHFT) +#define L2_DC_LINE_TAG_SHFT 8 +#define L2_DC_LINE_TAG_MASK (0xf << L2_DC_LINE_TAG_SHFT) +#define L2_DC_LINE_SIZE_SHFT 0 +#define L2_DC_LINE_SIZE_MASK (0xff << L2_DC_LINE_SIZE_SHFT) +/* Fn0x80000006_EDX */ +#define L3_DC_SIZE_SHFT 18 +#define L3_DC_SIZE_MASK (0x3fff << L3_DC_SIZE_SHFT) +#define L3_DC_ASSOC_SHFT 12 +#define L3_DC_ASSOC_MASK (0xf << L3_DC_ASSOC_SHFT) +#define L3_DC_LINE_TAG_SHFT 8 +#define L3_DC_LINE_TAG_MASK (0xf << L3_DC_LINE_TAG_SHFT) +#define L3_DC_LINE_SIZE_SHFT 0 +#define L3_DC_LINE_SIZE_MASK (0xff << L3_DC_LINE_SIZE_SHFT) + +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 + +#define CPUID_TLB_L1L2_1G_IDS 0x80000019 +/* Fn0x80000019_EAX */ +#define L1_DAT_TLB_1G_ASSOC_SHFT 28 +#define L1_DAT_TLB_1G_ASSOC_MASK (0xf << L1_DAT_TLB_1G_ASSOC_SHFT) +#define L1_DAT_TLB_1G_SIZE_SHFT 16 +#define L1_DAT_TLB_1G_SIZE_MASK (0xfff << L1_DAT_TLB_1G_SIZE_SHFT) +#define L1_INST_TLB_1G_ASSOC_SHFT 12 +#define L1_INST_TLB_1G_ASSOC_MASK (0xf << L1_INST_TLB_1G_ASSOC_SHFT) +#define L1_INST_TLB_1G_SIZE_SHFT 0 +#define L1_INST_TLB_1G_SIZE_MASK (0xfff << L1_INST_TLB_1G_SIZE_SHFT) +/* Fn0x80000019_EBX */ +#define L2_DAT_TLB_1G_ASSOC_SHFT 28 +#define L2_DAT_TLB_1G_ASSOC_MASK (0xf << L2_DAT_TLB_1G_ASSOC_SHFT) +#define L2_DAT_TLB_1G_SIZE_SHFT 16 +#define L2_DAT_TLB_1G_SIZE_MASK (0xfff << L2_DAT_TLB_1G_SIZE_SHFT) +#define L2_INST_TLB_1G_ASSOC_SHFT 12 +#define L2_INST_TLB_1G_ASSOC_MASK (0xf << L2_INST_TLB_1G_ASSOC_SHFT) +#define L2_INST_TLB_1G_SIZE_SHFT 0 +#define L2_INST_TLB_1G_SIZE_MASK (0xfff << L2_INST_TLB_1G_SIZE_SHFT) + +#define CPUID_CACHE_PROPS 0x8000001D +#define CACHE_PROPS_0 0 +#define CACHE_PROPS_1 1 +#define CACHE_PROPS_2 2 +#define CACHE_PROPS_3 3 +#define NUM_SHARE_CACHE_SHFT 14 +#define NUM_SHARE_CACHE_MASK (0xfff << NUM_SHARE_CACHE_SHFT) +#define CACHE_INCLUSIVE_SHFT 1 +#define CACHE_INCLUSIVE_MASK (0x1 << CACHE_INCLUSIVE_SHFT) + +#define CPUID_EBX_CORE_ID 0x8000001E +#define CPUID_EBX_THREADS_SHIFT 8 +#define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) + +#endif /* CPU_AMD_CPUID_H */ diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 8bc00d1624..78676de266 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -10,15 +10,13 @@ #include -#define CPUID_EXT_PM 0x80000007 -#define CPUID_MODEL 1 #define MC4_MISC0 0x00000413 #define MC4_MISC1 0xC0000408 #define MC4_MISC2 0xC0000409 #define FS_Base 0xC0000100 -#define HWCR_MSR 0xC0010015 +#define HWCR_MSR 0xC0010015 #define SMM_LOCK (1 << 0) -#define NB_CFG_MSR 0xC001001f +#define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC1_CTL_MASK 0xC0010045 #define MC4_CTL_MASK 0xC0010048 @@ -30,6 +28,9 @@ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */ #define PS_MAX_VAL_SHFT 4 +#define PS_LIM_MAX_VAL_MASK (0x7 << PS_MAX_VAL_SHFT) +#define MAX_PSTATES 8 + /* P-state Control Register */ #define PS_CTL_REG 0xC0010062 /* P-state Control Register CMD Mask OFF */ @@ -43,11 +44,15 @@ #define PSTATE_2_MSR 0xC0010066 #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 - +/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_MAX_MICROVOLTS 1550000L #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 #define MSR_CSTATE_ADDRESS 0xC0010073 +#define MSR_CSTATE_ADDRESS_MASK 0xFFFF + #define OSVW_ID_Length 0xC0010140 #define OSVW_Status 0xC0010141 diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 906a7c00f0..608a9df1ec 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -41,6 +41,7 @@ #if !defined(__ASSEMBLER__) #include +#include void amd_setup_mtrrs(void); struct device; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index db324b6da9..99249ba629 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -2,6 +2,7 @@ #define CPU_CPU_H #include +#include void cpu_initialize(unsigned int cpu_index); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index 8596ce519d..b656a284b3 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -66,7 +66,6 @@ typedef struct { u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 2e4e0d5748..6884b285b5 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -6,7 +6,6 @@ #include #include - /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: * - Westmere @@ -83,7 +82,6 @@ typedef struct { u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 1c33c24895..ceddf1d150 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -13,6 +13,8 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H +#include + #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h new file mode 100644 index 0000000000..935ac30096 --- /dev/null +++ b/src/include/cpu/intel/msr.h @@ -0,0 +1,19 @@ +#ifndef CPU_INTEL_MSR_H +#define CPU_INTEL_MSR_H + +/* + * Common MSRs for Intel CPUs + */ + +#define MSR_FEATURE_CONFIG 0x13c +#define AESNI_DISABLE (1 << 1) +#define AESNI_LOCK (1 << 0) + +#define MSR_PIC_MSG_CONTROL 0x2e +#define TPR_UPDATES_DISABLE (1 << 10) + +#define MSR_PLATFORM_INFO 0xce + +#define MSR_PKG_C10_RESIDENCY 0x632 + +#endif /* CPU_INTEL_MSR_H */ diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 07fe0381a1..126aa2a4e2 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_ bool cpu_has_alternative_smrr(void); - #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index d66b8e2a7e..e085e34230 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -18,7 +18,6 @@ */ #define PMB1_BASE 0x800 - /* Speedstep related MSRs */ #define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h index 9535e69781..eb34c97e34 100644 --- a/src/include/cpu/x86/bist.h +++ b/src/include/cpu/x86/bist.h @@ -2,6 +2,7 @@ #define CPU_X86_BIST_H #include +#include static inline void report_bist_failure(u32 bist) { diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 01b202eb1a..62341104a4 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -8,6 +8,8 @@ #define CR0_CacheDisable (CR0_CD) #define CR0_NoWriteThrough (CR0_NW) +#define CPUID_FEATURE_CLFLUSH_BIT 19 + #if !defined(__ASSEMBLER__) static inline void wbinvd(void) diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 5ab57554f2..f4291ab35b 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -73,7 +73,7 @@ static inline void lapic_write_atomic(unsigned long reg, uint32_t v) # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -void do_lapic_init(void); +void lapic_virtual_wire_mode_init(void); /* See if I need to initialize the local APIC */ static inline int need_lapic_init(void) @@ -84,7 +84,7 @@ static inline int need_lapic_init(void) static inline void setup_lapic(void) { if (need_lapic_init()) - do_lapic_init(); + lapic_virtual_wire_mode_init(); else disable_lapic(); } diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 04f7804d74..b2704eb5b0 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -5,6 +5,8 @@ #include #include +#include +#include #define CACHELINE_SIZE 64 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc04b6..5ae3ddf93a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,11 +48,12 @@ #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 +#define ENERGY_POLICY_MASK 0xf #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define SMRR_PHYSBASE_MSR 0x1F2 #define SMRR_PHYSMASK_MSR 0x1F3 #define IA32_PLATFORM_DCA_CAP 0x1f8 +#define DCA_TYPE0_EN (1 << 0) #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 @@ -90,6 +91,9 @@ #define IA32_L3_MASK_1 0xc91 #define IA32_L3_MASK_2 0xc92 +#define IA32_CR_SF_QOS_MASK_1 0x1891 +#define IA32_CR_SF_QOS_MASK_2 0x1892 + #ifndef __ASSEMBLER__ #include @@ -296,25 +300,46 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } - -/* Helper for setting single MSR bits */ -static inline void msr_set_bit(unsigned int reg, unsigned int bit) +/** + * Helper for (un)setting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] unset Bitmask with ones to the bits to unset from the MSR. + * @param[in] set Bitmask with ones to the bits to set from the MSR. + */ +static inline void msr_unset_and_set(unsigned int reg, uint64_t unset, uint64_t set) { - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } + msr_t msr; + msr = rdmsr(reg); + msr.lo &= (unsigned int)~unset; + msr.hi &= (unsigned int)~(unset >> 32); + msr.lo |= (unsigned int)set; + msr.hi |= (unsigned int)(set >> 32); wrmsr(reg, msr); } +/** + * Helper for setting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] set Bitmask with ones to the bits to set from the MSR. + */ +static inline void msr_set(unsigned int reg, uint64_t set) +{ + msr_unset_and_set(reg, 0, set); +} + +/** + * Helper for unsetting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] unset Bitmask with ones to the bits to unset from the MSR. + */ +static inline void msr_unset(unsigned int reg, uint64_t unset) +{ + msr_unset_and_set(reg, unset, 0); +} #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b02ea..b8d15179e9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -27,13 +27,14 @@ #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) - #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +#define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + These are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index fce39b774d..077f964335 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -3,7 +3,6 @@ #include - #if CONFIG(POST_IO) #define post_code(value) \ movb $value, %al; \ diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h new file mode 100644 index 0000000000..d6fcf63d79 --- /dev/null +++ b/src/include/cpu/x86/save_state.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_X86_SAVE_STATE_H__ +#define __CPU_X86_SAVE_STATE_H__ + +#include + +enum cpu_reg { + RAX, + RBX, + RCX, + RDX +}; + +#define SMM_REV_INVALID 0xffffffff + +struct smm_save_state_ops { + const uint32_t *revision_table; + /* Accessors for CPU registers in the SMM save state + Returns -1 on failure, 0 on success */ + int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + /* Returns -1 on failure, the node on which the 'cmd' was send on success */ + int (*apmc_node)(u8 cmd); +}; + +/* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */ +int get_apmc_node(u8 cmd); +/* Return -1 on failure, 0 on succes. + Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */ +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); +int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + +#endif /* __CPU_X86_SAVE_STATE_H__ */ diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h index d7f3c7fd9e..6213915eee 100644 --- a/src/include/cpu/x86/smi_deprecated.h +++ b/src/include/cpu/x86/smi_deprecated.h @@ -3,6 +3,8 @@ #ifndef __X86_SMI_DEPRECATED_H__ #define __X86_SMI_DEPRECATED_H__ +#include + #if CONFIG(PARALLEL_MP) || !CONFIG(HAVE_SMI_HANDLER) /* Empty stubs for platforms without SMI handlers. */ static inline void smm_init(void) { } @@ -13,6 +15,6 @@ void smm_init_completion(void); #endif /* Entry from smmhandler.S. */ -void smi_handler(u32 smm_revision); +void smi_handler(void); #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a3101e5155..9106842840 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,11 +22,10 @@ #define APM_CNT_PST_CONTROL 0x80 #define APM_CNT_ACPI_DISABLE 0x1e #define APM_CNT_ACPI_ENABLE 0xe1 -#define APM_CNT_MBI_UPDATE 0xeb -#define APM_CNT_GNVS_UPDATE 0xea #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed #define APM_CNT_ELOG_GSMI 0xef @@ -75,7 +74,7 @@ struct smm_runtime { struct smm_module_params { void *arg; - int cpu; + size_t cpu; const struct smm_runtime *runtime; /* A canary value that has been placed at the end of the stack. * If (uintptr_t)canary != *canary then a stack overflow has occurred. @@ -128,6 +127,12 @@ static inline bool smm_points_to_smram(const void *ptr, const size_t len) * into this field so the code doing the loading can manipulate the * runtime's assumptions. e.g. updating the APIC id to CPU map to * handle sparse APIC id space. + * The following parameters are only used when X86_SMM_LOADER_VERSION2 is enabled. + * - smm_entry - entry address of first CPU thread, all others will be tiled + * below this address. + * - smm_main_entry_offset - default entry offset (e.g 0x8000) + * - smram_start - smaram starting address + * - smram_end - smram ending address */ struct smm_loader_params { void *stack_top; @@ -141,12 +146,24 @@ struct smm_loader_params { void *handler_arg; struct smm_runtime *runtime; + + /* The following are only used by X86_SMM_LOADER_VERSION2 */ +#if CONFIG(X86_SMM_LOADER_VERSION2) + uintptr_t smm_entry; + uintptr_t smm_main_entry_offset; + uintptr_t smram_start; + uintptr_t smram_end; +#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); +#if CONFIG(X86_SMM_LOADER_VERSION2) +u32 smm_get_cpu_smbase(unsigned int cpu_num); +#endif + /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); @@ -175,4 +192,12 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size); /* Print the SMM memory layout on console. */ void smm_list_regions(void); +#define SMM_REVISION_OFFSET_FROM_TOP (0x8000 - 0x7efc) +/* Return the SMM save state revision. The revision can be fetched from the smm savestate + which is always at the same offset downward from the top of the save state. */ +uint32_t smm_revision(void); +/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2). + On AMD systems it is sometimes configurable. */ +uint16_t pm_acpi_smi_cmd_port(void); + #endif /* CPU_X86_SMM_H */ diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6943b93018..ddce96bb39 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -41,22 +41,16 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); } -static inline unsigned long long rdtscll(void) -{ - unsigned long long val; - asm volatile ( - TSC_SYNC - "rdtsc" - : "=A" (val) - ); - return val; -} - static inline uint64_t tsc_to_uint64(tsc_t tstamp) { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } +static inline unsigned long long rdtscll(void) +{ + return tsc_to_uint64(rdtsc()); +} + /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 2e93fe937a..85b7221053 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -3,6 +3,7 @@ #ifndef CRC_BYTE_H #define CRC_BYTE_H +#include #include /* This function is used to calculate crc7 byte by byte, with polynomial diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 90260913ae..1b4e769c3f 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -3,11 +3,25 @@ #ifndef DEVICE_AZALIA_H #define DEVICE_AZALIA_H -#include #include #include #include +#include +#define HDA_GCAP_REG 0x00 +#define HDA_GCTL_REG 0x08 +#define HDA_GCTL_CRST (1 << 0) +#define HDA_STATESTS_REG 0x0e +#define HDA_IC_REG 0x60 +#define HDA_IR_REG 0x64 +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +int azalia_set_bits(void *port, u32 mask, u32 val); +int azalia_enter_reset(u8 *base); +int azalia_exit_reset(u8 *base); +u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; @@ -44,7 +58,7 @@ enum azalia_pin_type { STEREO_MONO_1_4, ATAPI, RCA, - OPTIONAL, + OPTICAL, OTHER_DIGITAL, OTHER_ANALOG, MULTICHANNEL_ANALOG, @@ -101,7 +115,7 @@ enum azalia_pin_location_2 { ((type) << 16) | \ ((color) << 12) | \ ((no_presence_detect) << 8) | \ - ((sequence) << 4) | \ + ((association) << 4) | \ ((sequence) << 0)) #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ @@ -118,6 +132,8 @@ enum azalia_pin_location_2 { (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \ | (((val) >> 24) & 0xff)) +#define AZALIA_PIN_CFG_NC(n) (0x411111f0 | (n & 0xf)) + #define AZALIA_RESET(pin) \ (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00), \ (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00) diff --git a/src/include/device/device.h b/src/include/device/device.h index 082dcbb4d3..1fc5e62bdc 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -6,6 +6,7 @@ #include #include #include +#include #include struct fw_config; @@ -16,6 +17,7 @@ struct smbus_bus_operations; struct pnp_mode_ops; struct spi_bus_operations; struct usb_bus_operations; +struct gpio_operations; /* Chip operations */ struct chip_operations { @@ -62,6 +64,7 @@ struct device_operations { const struct spi_bus_operations *ops_spi_bus; const struct smbus_bus_operations *ops_smbus_bus; const struct pnp_mode_ops *ops_pnp_mode; + const struct gpio_operations *ops_gpio; }; /** @@ -195,6 +198,11 @@ void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); void add_more_links(struct device *dev, unsigned int total_links); +static inline bool is_dev_enabled(const struct device *const dev) +{ + return dev && dev->enabled; +} + /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); @@ -202,6 +210,10 @@ void run_bios(struct device *dev, unsigned long addr); DEVTREE_CONST struct device *find_dev_path( const struct bus *parent, const struct device_path *path); +DEVTREE_CONST struct device *find_dev_nested_path( + const struct bus *parent, + const struct device_path nested_path[], + size_t nested_path_length); struct device *alloc_find_dev(struct bus *parent, struct device_path *path); struct device *dev_find_device(u16 vendor, u16 device, struct device *from); struct device *dev_find_class(unsigned int class, struct device *from); @@ -252,6 +264,38 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +/* Debug macros */ +#if CONFIG(DEBUG_RESOURCES) +#include +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) +#else /* DEBUG_RESOURCES*/ +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) +#define LOG_IO_RESOURCE(type, dev, index, base, size) +#endif /* DEBUG_RESOURCES*/ + +#if CONFIG(DEBUG_FUNC) +#include +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) +#else /* DEBUG_FUNC */ +#define DEV_FUNC_ENTER(dev) +#define DEV_FUNC_EXIT(dev) +#endif /* DEBUG_FUNC */ + /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ @@ -330,6 +374,12 @@ DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const void devtree_bug(const char *func, pci_devfn_t devfn); void __noreturn devtree_die(void); +/* + * Dies if `dev` or `dev->chip_info` are NULL. Returns `dev->chip_info` otherwise. + * + * Only use if missing `chip_info` is fatal and we can't boot. If it's + * not fatal, please handle the NULL case gracefully. + */ static inline DEVTREE_CONST void *config_of(const struct device *dev) { if (dev && dev->chip_info) @@ -338,11 +388,13 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev) devtree_die(); } -static inline DEVTREE_CONST void *config_of_soc(void) -{ - return config_of(pcidev_on_root(0, 0)); -} +/* + * Returns pointer to config structure of root device (B:D:F = 0:00:0) defined by + * sconfig in static.{h/c}. + */ +#define config_of_soc() __pci_0_00_0_config +void enable_static_device(struct device *dev); void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index c1b4f7621b..9475853924 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -33,10 +33,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 9acf794dec..6200fdedd6 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -47,35 +47,35 @@ union dimm_flags_ddr2_st { * We do not care how these bits are ordered */ struct { /* Module can work at 5.00V */ - unsigned operable_5_00V:1; + unsigned int operable_5_00V:1; /* Module can work at 3.33V */ - unsigned operable_3_33V:1; + unsigned int operable_3_33V:1; /* Module can work at 2.50V */ - unsigned operable_2_50V:1; + unsigned int operable_2_50V:1; /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ - unsigned operable_1_80V:1; + unsigned int operable_1_80V:1; /* Module can work at 1.50V */ - unsigned operable_1_50V:1; + unsigned int operable_1_50V:1; /* Module can work at 1.35V */ - unsigned operable_1_35V:1; + unsigned int operable_1_35V:1; /* Module can work at 1.20V */ - unsigned operable_1_25V:1; + unsigned int operable_1_25V:1; /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ - unsigned is_ecc:1; + unsigned int is_ecc:1; /* Supports weak driver */ - unsigned weak_driver:1; + unsigned int weak_driver:1; /* Supports terminating at 50 Ohm */ - unsigned terminate_50ohms:1; + unsigned int terminate_50ohms:1; /* Partial Array Self Refresh */ - unsigned pasr:1; + unsigned int pasr:1; /* Supports burst length 8 */ - unsigned bl8:1; + unsigned int bl8:1; /* Supports burst length 4 */ - unsigned bl4:1; + unsigned int bl4:1; /* DIMM Package is stack */ - unsigned stacked:1; + unsigned int stacked:1; /* the assembly supports self refresh */ - unsigned self_refresh:1; + unsigned int self_refresh:1; }; unsigned int raw; }; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index a209e48b8b..0814990eb9 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -19,7 +19,6 @@ #include #include - /** * Convenience definitions for SPD offsets * @@ -34,10 +33,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index f258fa9f09..eac8bf8920 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -21,7 +21,6 @@ #define SPD_DDR4_PART_OFF 329 #define SPD_DDR4_PART_LEN 20 - /* * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. @@ -70,4 +69,9 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, const dimm_attr *info); +/** + * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz); + #endif /* DEVICE_DRAM_DDR4L_H */ diff --git a/src/include/device/drm_dp_helper.h b/src/include/device/drm_dp_helper.h deleted file mode 100644 index f2e06c33f3..0000000000 --- a/src/include/device/drm_dp_helper.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -/* From the VESA DisplayPort spec */ - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) - -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) - -/* AUX CH addresses */ -/* DPCD */ -#define DP_DPCD_REV 0x000 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 - -/* link configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_PSR_EN_CFG 0x170 -# define DP_PSR_ENABLE (1 << 0) -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) -# define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_EDP_CONFIGURATION_SET 0x10a - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/src/include/device/gpio.h b/src/include/device/gpio.h new file mode 100644 index 0000000000..67975b3c45 --- /dev/null +++ b/src/include/device/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DEVICE_GPIO_H__ +#define __DEVICE_GPIO_H__ + +#include + +struct gpio_operations { + int (*get)(uint32_t gpio); + void (*set)(uint32_t gpio, int value); + void (*input_pulldown)(uint32_t gpio); + void (*input_pullup)(uint32_t gpio); + void (*input)(uint32_t gpio); + void (*output)(uint32_t gpio, int value); +}; + +/* Helper for getting gpio operations from a device */ +const struct gpio_operations *dev_get_gpio_ops(struct device *dev); + +#endif /* __DEVICE_GPIO_H__ */ diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h deleted file mode 100644 index 382731fe86..0000000000 --- a/src/include/device/hypertransport.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_H -#define DEVICE_HYPERTRANSPORT_H - -#include - -extern struct device_operations default_ht_ops_bus; - -#define HT_IO_HOST_ALIGN 4096 -#define HT_MEM_HOST_ALIGN (1024*1024) - -#endif /* DEVICE_HYPERTRANSPORT_H */ diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h deleted file mode 100644 index a0b1a36a21..0000000000 --- a/src/include/device/hypertransport_def.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_DEF_H -#define DEVICE_HYPERTRANSPORT_DEF_H - -#define HT_FREQ_200Mhz 0 -#define HT_FREQ_300Mhz 1 -#define HT_FREQ_400Mhz 2 -#define HT_FREQ_500Mhz 3 -#define HT_FREQ_600Mhz 4 -#define HT_FREQ_800Mhz 5 -#define HT_FREQ_1000Mhz 6 -#define HT_FREQ_1200Mhz 7 -#define HT_FREQ_1400Mhz 8 -#define HT_FREQ_1600Mhz 9 -#define HT_FREQ_1800Mhz 10 -#define HT_FREQ_2000Mhz 11 -#define HT_FREQ_2200Mhz 12 -#define HT_FREQ_2400Mhz 13 -#define HT_FREQ_2600Mhz 14 -#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ - - -static inline bool offset_unit_id(bool is_sb_ht_chain) -{ - bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) - || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && is_sb_ht_chain; -} - -#endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 0e35a61176..b5e77105b5 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -3,6 +3,7 @@ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ +#include #include #include #include diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index 03d68281ef..de1c0eb4b8 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -5,6 +5,7 @@ #include #include +#include int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count); diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 86b5116005..951caaacaa 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -20,6 +20,7 @@ /* Contributing Members */ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 +#define MIPI_DEV_ID_REALTEK_ALC711 0x0711 #define MIPI_MFG_ID_MAXIM 0x019f #define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b4461e05e7..9b79d79bb5 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -150,21 +150,44 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, _BF_APPLY6(op, __VA_ARGS__)) #define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLY9(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY8(op, __VA_ARGS__)) +#define _BF_APPLY10(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY9(op, __VA_ARGS__)) +#define _BF_APPLY11(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY10(op, __VA_ARGS__)) +#define _BF_APPLY12(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY11(op, __VA_ARGS__)) +#define _BF_APPLY13(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY12(op, __VA_ARGS__)) +#define _BF_APPLY14(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY13(op, __VA_ARGS__)) +#define _BF_APPLY15(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY14(op, __VA_ARGS__)) +#define _BF_APPLY16(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY15(op, __VA_ARGS__)) #define _BF_APPLYINVALID(...) \ _Static_assert(0, "Invalid arguments for {WRITE,SET}*_BITFIELDS") #define _BF_IMPL2(op, addr, \ n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, n13, v13, n14, v14, n15, v15, n16, v16, \ NARGS, ...) \ \ op(addr, \ _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8), \ + n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16), \ _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8)) + n5, v5, n6, v6, n7, v7, n8, v8,\ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16)) #define _BF_IMPL(op, addr, ...) \ _BF_IMPL2(op, addr, __VA_ARGS__, \ + 16, INVALID, 15, INVALID, 14, INVALID, 13, INVALID, \ + 12, INVALID, 11, INVALID, 10, INVALID, 9, INVALID, \ 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) diff --git a/src/include/device/path.h b/src/include/device/path.h index 4db83b7b3f..0cdb997726 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -21,6 +21,7 @@ enum device_path_type { DEVICE_PATH_MMIO, DEVICE_PATH_ESPI, DEVICE_PATH_LPC, + DEVICE_PATH_GPIO, /* * When adding path types to this table, please also update the @@ -46,6 +47,7 @@ enum device_path_type { "DEVICE_PATH_MMIO", \ "DEVICE_PATH_ESPI", \ "DEVICE_PATH_LPC", \ + "DEVICE_PATH_GPIO", \ } struct domain_path { @@ -116,6 +118,10 @@ struct lpc_path { uintptr_t addr; }; +struct gpio_path { + unsigned int id; +}; + struct device_path { enum device_path_type type; union { @@ -134,10 +140,10 @@ struct device_path { struct mmio_path mmio; struct espi_path espi; struct lpc_path lpc; + struct gpio_path gpio; }; }; - #define DEVICE_PATH_MAX 40 #define BUS_PATH_MAX (DEVICE_PATH_MAX+10) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4529074e9b..045eec1aa6 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -79,7 +79,6 @@ void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned int devfn); - void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus)(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn)); @@ -128,6 +127,18 @@ static inline int pci_base_address_is_memory_space(unsigned int attr) } void pci_dev_disable_bus_master(const struct device *dev); + +static __always_inline +#if ENV_PCI_SIMPLE_DEVICE +void pci_dev_request_bus_master(pci_devfn_t dev) +#else +void pci_dev_request_bus_master(struct device *dev) +#endif /* ENV_PCI_SIMPLE_DEVICE */ +{ + if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); +} + #endif /* CONFIG_PCI */ void pci_early_bridge_init(void); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 07ba4a2b30..e0d891eeb9 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -136,7 +136,7 @@ /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_PARITY 0x01 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ -#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ @@ -305,7 +305,6 @@ #define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ - /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ @@ -521,7 +520,6 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ - /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index c3bcdc90f8..e7a445d377 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -5,6 +5,7 @@ #include #include +#include #define EHCI_BAR_INDEX 0x10 #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62220d87e9..0b78c9f9e9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -301,11 +301,13 @@ #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 @@ -453,24 +455,41 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_GNB 0x15D0 -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 -#define PCI_DEVICE_ID_AMD_FAM17H_GPU 0x15D8 -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC -#define PCI_DEVICE_ID_AMD_FAM17H_HDA0 0x15DE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 -#define PCI_DEVICE_ID_AMD_FAM17H_DF0 0x15E8 -#define PCI_DEVICE_ID_AMD_FAM17H_DF1 0x15E9 -#define PCI_DEVICE_ID_AMD_FAM17H_DF2 0x15EA -#define PCI_DEVICE_ID_AMD_FAM17H_DF3 0x15EB -#define PCI_DEVICE_ID_AMD_FAM17H_DF4 0x15EC -#define PCI_DEVICE_ID_AMD_FAM17H_DF5 0x15ED -#define PCI_DEVICE_ID_AMD_FAM17H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3 0x15EB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670 +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1671 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 @@ -478,7 +497,16 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E -#define PCI_DEVICE_ID_AMD_FAM17H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 +#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 + +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C +#define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU 0x1638 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_HDA0 0x1637 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 @@ -517,7 +545,6 @@ #define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 - #define PCI_VENDOR_ID_TSENG 0x100c #define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 #define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 @@ -1249,6 +1276,7 @@ #define PCI_DEVICE_ID_INTERG_5050 0x5050 #define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_5261 0x5261 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 @@ -1663,7 +1691,6 @@ #define PCI_DEVICE_ID_ATT_L56XMF 0x0440 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 @@ -2032,6 +2059,10 @@ #define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_VENDOR_ID_GLI 0x17a0 +#define PCI_DEVICE_ID_GLI_9763E 0xe763 +#define PCI_DEVICE_ID_GLI_9755 0x9755 + #define PCI_VENDOR_ID_XGI 0x18ca #define PCI_DEVICE_ID_XGI_20 0x0020 #define PCI_DEVICE_ID_XGI_40 0x0040 @@ -2746,6 +2777,9 @@ #define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 #define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 +/* Intel SDMA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SDMA 0x9c60 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 @@ -2803,6 +2837,7 @@ #define PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER 0xa24a #define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b #define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c +#define PCI_DEVICE_ID_INTEL_EMB_SUPER 0x1b81 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 @@ -2890,9 +2925,90 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 -#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87 +#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0x4d87 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0 0x7a00 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1 0x7a01 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2 0x7a02 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3 0x7a03 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4 0x7a04 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5 0x7a05 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6 0x7a06 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7 0x7a07 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8 0x7a08 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9 0x7a09 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10 0x7a0a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11 0x7a0b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12 0x7a0c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13 0x7a0d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14 0x7a0e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15 0x7a0f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16 0x7a10 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17 0x7a11 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18 0x7a12 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19 0x7a13 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20 0x7a14 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21 0x7a15 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22 0x7a16 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23 0x7a17 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24 0x7a18 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25 0x7a19 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26 0x7a1a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27 0x7a1b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28 0x7a1c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29 0x7a1d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33 0x5182 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3 0x7a83 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4 0x7a84 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5 0x7a85 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6 0x7a86 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7 0x7a87 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8 0x7a88 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9 0x7a89 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10 0x7a8a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11 0x7a8b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12 0x7a8c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13 0x7a8d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14 0x7a8e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15 0x7a8f +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16 0x7a90 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17 0x7a91 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18 0x7a92 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19 0x7a93 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20 0x7a94 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21 0x7a95 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22 0x7a96 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23 0x7a97 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24 0x7a98 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25 0x7a99 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26 0x7a9a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27 0x7a9b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28 0x7a9c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29 0x7a9d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30 0x7a9e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f /* Intel PCIE device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2 0x8c12 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3 0x8c14 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4 0x8c16 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5 0x8c18 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6 0x8c1a +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7 0x8c1c +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8 0x8c1e +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1 0x9c10 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2 0x9c12 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3 0x9c14 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4 0x9c16 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5 0x9c18 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6 0x9c1a + #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 @@ -3129,7 +3245,66 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP4 0x51bb +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP5 0x51bc +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP6 0x51bd +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP7 0x51be +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP8 0x51bf +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP9 0x51b0 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP10 0x51b1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP11 0x51b2 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP12 0x51b3 + +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP1 0x7ab8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP2 0x7ab9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP3 0x7aba +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP4 0x7abb +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP5 0x7abc +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP6 0x7abd +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP7 0x7abe +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP8 0x7abf +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP9 0x7ab0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP10 0x7ab1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP11 0x7ab2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP12 0x7ab3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP13 0x7ab4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP14 0x7ab5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP15 0x7ab6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP16 0x7ab7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP17 0x7ac0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP18 0x7ac1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP19 0x7ac2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP20 0x7ac3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP21 0x7ac4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP22 0x7ac5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP23 0x7ac6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP24 0x7ac7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP25 0x7ac8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26 0x7ac9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27 0x7aca +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb + /* Intel SATA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1 0x8c04 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM 0x8c06 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45 0x8c08 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2 0x8c0e +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE 0x8c01 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI 0x8c03 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1 0x8c05 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1 0x9c05 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2 0x9c0f + #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a @@ -3166,6 +3341,18 @@ #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 #define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2 #define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_1 0x7a52 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_2 0x7a53 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_3 0x7a54 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_4 0x7a55 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_5 0x7a56 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_6 0x7a57 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_1 0x7ae2 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_2 0x7ae3 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_3 0x7ae4 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_4 0x7ae5 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_5 0x7ae6 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_6 0x7ae7 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3183,8 +3370,12 @@ #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 #define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 +#define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 /* Intel I2C device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C1 0x9c62 #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 #define PCI_DEVICE_ID_INTEL_SPT_I2C1 0x9d61 #define PCI_DEVICE_ID_INTEL_SPT_I2C2 0x9d62 @@ -3261,7 +3452,23 @@ #define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 #define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C0 0x51e8 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C1 0x51e9 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C2 0x51ea +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C3 0x51eb +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C4 0x51c5 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C5 0x51c6 + +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C0 0x7acc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C1 0x7acd +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C2 0x7ace +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C3 0x7acf +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C4 0x7afc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd + /* Intel UART device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64 #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 #define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66 @@ -3304,7 +3511,25 @@ #define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 #define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART0 0x51a8 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART1 0x51a9 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART2 0x51c7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART3 0x51da +#define PCI_DEVICE_ID_INTEL_ADP_P_UART4 0x51db +#define PCI_DEVICE_ID_INTEL_ADP_P_UART5 0x51dc +#define PCI_DEVICE_ID_INTEL_ADP_P_UART6 0x51dd + +#define PCI_DEVICE_ID_INTEL_ADP_S_UART0 0x7aa8 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART1 0x7aa9 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART2 0x7afe +#define PCI_DEVICE_ID_INTEL_ADP_S_UART3 0x7adc +#define PCI_DEVICE_ID_INTEL_ADP_S_UART4 0x7add +#define PCI_DEVICE_ID_INTEL_ADP_S_UART5 0x7ade +#define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf + /* Intel SPI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66 #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 #define PCI_DEVICE_ID_INTEL_SPT_SPI3 0x9d2a @@ -3340,7 +3565,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab -#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0xa0fb #define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de @@ -3354,6 +3579,24 @@ #define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb #define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4 +#define PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI 0x51a4 +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI0 0x51aa +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI1 0x51ab +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI2 0x51fb +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI3 0x51fd +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI4 0x51fe +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI5 0x51de +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI6 0x51df + +#define PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI 0x7aa4 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI0 0x7aaa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI1 0x7aab +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI2 0x7afb +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI3 0x7af9 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI4 0x7afa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI5 0x7aee +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI6 0x7aef + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3466,6 +3709,22 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 #define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 #define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 +#define PCI_DEVICE_ID_INTEL_JSL_GT3 0x4E61 +#define PCI_DEVICE_ID_INTEL_JSL_GT4 0x4E55 + +#define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff +#define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_1 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_2 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_3 0x4603 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_4 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_5 0x4611 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_6 0x4612 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_7 0x4613 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3521,18 +3780,58 @@ #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 -#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 -#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 -#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12 #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_EHL_ID_2 0x4522 +#define PCI_DEVICE_ID_INTEL_EHL_ID_3 0x4524 +#define PCI_DEVICE_ID_INTEL_EHL_ID_4 0x4512 +#define PCI_DEVICE_ID_INTEL_EHL_ID_5 0x4526 +#define PCI_DEVICE_ID_INTEL_EHL_ID_6 0x4514 +#define PCI_DEVICE_ID_INTEL_EHL_ID_7 0x4528 +#define PCI_DEVICE_ID_INTEL_EHL_ID_8 0x452A +#define PCI_DEVICE_ID_INTEL_EHL_ID_9 0x4516 +#define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452C +#define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x452E +#define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 +#define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 #define PCI_DEVICE_ID_INTEL_JSL_ID_4 0x4e14 +#define PCI_DEVICE_ID_INTEL_JSL_ID_5 0x4e24 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_1 0x4660 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_2 0x4664 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_3 0x4668 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_4 0x466c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_5 0x4670 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_6 0x4640 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_7 0x4644 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_8 0x4648 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_9 0x464c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_10 0x4650 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_11 0x4630 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_12 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_13 0x4673 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_14 0x4623 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_15 0x0060 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_3 0x4641 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_4 0x4649 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_5 0x4621 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_6 0x4609 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f /* Intel SMBUS device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 +#define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 #define PCI_DEVICE_ID_INTEL_LWB_SMBUS 0xa1a3 @@ -3545,8 +3844,17 @@ #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 #define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 +#define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 + +/* Intel EHCI device IDs */ +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2 0x8c2d +#define PCI_DEVICE_ID_INTEL_LPT_LP_EHCI 0x9c26 /* Intel XHCI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_XHCI 0x8c31 +#define PCI_DEVICE_ID_INTEL_LPT_LP_XHCI 0x9c31 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f @@ -3563,6 +3871,9 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded +#define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed +#define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3580,6 +3891,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 #define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 +#define PCI_DEVICE_ID_INTEL_ADP_P_P2SB 0x7a20 +#define PCI_DEVICE_ID_INTEL_ADP_S_P2SB 0x7aa0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3592,8 +3905,12 @@ #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def +#define PCI_DEVICE_ID_INTEL_ADP_P_SRAM 0x7a6f +#define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 /* Intel AUDIO device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 +#define PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO 0x9c20 #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 @@ -3610,8 +3927,19 @@ #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 #define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1 0x7ad0 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2 0x7ad1 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3 0x7ad2 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4 0x7ad3 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5 0x7ad4 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6 0x7ad5 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7 0x7ad6 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8 0x7ad7 +#define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 /* Intel HECI/ME device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a +#define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 @@ -3635,6 +3963,14 @@ #define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 #define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 #define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE0 0x51e0 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE1 0x51e1 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE2 0x51e4 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE3 0x51e5 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE0 0x7ae8 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE1 0x7ae9 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE2 0x7aec +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE3 0x7aed /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3649,8 +3985,12 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee +#define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee +#define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e /* Intel SD device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d @@ -3672,8 +4012,14 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP0 0x466e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP1 0x463f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP2 0x462f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP3 0x461f #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0 0x463e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1 0x466d /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 @@ -3698,29 +4044,44 @@ #define PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI 0x08b2 #define PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI 0x095a #define PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI 0x095b -#define PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI 0x9df0 -#define PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI 0x31dc -#define PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI 0xa370 #define PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI 0x24f3 #define PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI 0x24f4 #define PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI 0x24fd #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI 0x2526 -#define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI 0x34f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI 0x06f0 #define PCI_DEVICE_ID_CyP_6SERIES_WIFI 0x2723 -#define PCI_DEVICE_ID_HrP_6SERIES_WIFI 0x2720 #define PCI_DEVICE_ID_TyP_6SERIES_WIFI 0x2725 #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 #define PCI_DEVICE_ID_INTEL_TGL_IPU 0x9a19 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 +#define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d /* Intel Dynamic Tuning Technology Device */ +#define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 #define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 +#define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d + +/* Intel CNVi WiFi/BT device IDs */ +#define PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI 0x02f0 +#define PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI 0x06f0 +#define PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI 0x9df0 +#define PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI 0xa370 +#define PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI 0x31dc +#define PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI 0x34f0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0 0x4df0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1 0x4df1 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2 0x4df2 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3 0x4df3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0 0xa0f0 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1 0xa0f1 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2 0xa0f2 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3 0xa0f3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0 0xa0f5 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1 0xa0f6 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2 0xa0f7 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3 0xa0f8 #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index d3666c241d..234ebb4c2c 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -7,7 +7,6 @@ #include #include - /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ extern u8 *const pci_mmconf; diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index cdf02d6a56..7fe7d429e2 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -209,4 +209,12 @@ u16 pci_find_capability(const struct device *dev, u16 cap) return pci_s_find_capability(PCI_BDF(dev), cap); } +/* + * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and + * PME_ENABLE bits in PM control and status register. + * + * Returns true if PCI device is wake source, false otherwise. + */ +bool pci_dev_is_wake_source(const struct device *dev); + #endif /* PCI_OPS_H */ diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index c49389f396..8b04d09987 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,8 +1,9 @@ #ifndef PCI_ROM_H #define PCI_ROM_H + #include -#include #include +#include #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index ca482d26ac..def7f6cca2 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,6 +2,9 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +#include +#include + void pcix_scan_bridge(struct device *dev); const char *pcix_speed(u16 sstatus); diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 800bcc0557..955eac29ac 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -3,6 +3,7 @@ #include #include +/* When is needed, it supposed to provide */ #include #include #include @@ -37,37 +38,37 @@ struct pnp_info { #define PNP_SKIP_FUNCTION 0xffff u16 function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; -#define PNP_IO0 0x000001 -#define PNP_IO1 0x000002 -#define PNP_IO2 0x000004 -#define PNP_IO3 0x000008 -#define PNP_IRQ0 0x000010 -#define PNP_IRQ1 0x000020 -#define PNP_DRQ0 0x000040 -#define PNP_DRQ1 0x000080 -#define PNP_EN 0x000100 -#define PNP_MSC0 0x000200 -#define PNP_MSC1 0x000400 -#define PNP_MSC2 0x000800 -#define PNP_MSC3 0x001000 -#define PNP_MSC4 0x002000 -#define PNP_MSC5 0x004000 -#define PNP_MSC6 0x008000 -#define PNP_MSC7 0x010000 -#define PNP_MSC8 0x020000 -#define PNP_MSC9 0x040000 -#define PNP_MSCA 0x080000 -#define PNP_MSCB 0x100000 -#define PNP_MSCC 0x200000 -#define PNP_MSCD 0x400000 -#define PNP_MSCE 0x800000 - u16 io0, io1, io2, io3; +#define PNP_IO0 0x0000001 +#define PNP_IO1 0x0000002 +#define PNP_IO2 0x0000004 +#define PNP_IO3 0x0000008 +#define PNP_IO4 0x0000010 +#define PNP_IRQ0 0x0000020 +#define PNP_IRQ1 0x0000040 +#define PNP_DRQ0 0x0000080 +#define PNP_DRQ1 0x0000100 +#define PNP_EN 0x0000200 +#define PNP_MSC0 0x0000400 +#define PNP_MSC1 0x0000800 +#define PNP_MSC2 0x0001000 +#define PNP_MSC3 0x0002000 +#define PNP_MSC4 0x0004000 +#define PNP_MSC5 0x0008000 +#define PNP_MSC6 0x0010000 +#define PNP_MSC7 0x0020000 +#define PNP_MSC8 0x0040000 +#define PNP_MSC9 0x0080000 +#define PNP_MSCA 0x0100000 +#define PNP_MSCB 0x0200000 +#define PNP_MSCC 0x0400000 +#define PNP_MSCD 0x0800000 +#define PNP_MSCE 0x1000000 + u16 io0, io1, io2, io3, io4; }; struct resource *pnp_get_resource(struct device *dev, unsigned int index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); - struct pnp_mode_ops { void (*enter_conf_mode)(struct device *dev); void (*exit_conf_mode)(struct device *dev); @@ -133,4 +134,37 @@ static inline void pnp_write_index(u16 port, u8 reg, u8 value) outb(value, port + 1); } +/* + * void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set) + * Description: + * This routine unsets and sets bits from indexed I/O registers. The + * reg byte is written to the index register at I/O address = port. + * The value byte to update is data register at I/O address = port + 1. + * + * Unlike and-then-or style operations, no bitwise negation is necessary + * to specify the bits to unset. Because the bitwise negation implicitly + * promotes operands to int before operating, one may have to explicitly + * downcast the result if the data width is smaller than that of an int. + * Since warnings are errors in coreboot, explicit casting is necessary. + * + * Performing said negation inside this routine alleviates this problem, + * while allowing the compiler to warn if the input parameters overflow. + * Casting outside this function would silence valid compiler warnings. + * + * Parameters: + * @param[in] u16 port = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register. + * @param[in] u8 set = Bitmask with ones to the bits to set from the data register. + */ +static inline void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set) +{ + outb(reg, port); + + u8 value = inb(port + 1); + value &= (u8)~unset; + value |= set; + outb(value, port + 1); +} + #endif /* DEVICE_PNP_H */ diff --git a/src/include/device/pnp_def.h b/src/include/device/pnp_def.h index 7701d842f2..712357bb7c 100644 --- a/src/include/device/pnp_def.h +++ b/src/include/device/pnp_def.h @@ -6,6 +6,7 @@ #define PNP_IDX_IO1 0x62 #define PNP_IDX_IO2 0x64 #define PNP_IDX_IO3 0x66 +#define PNP_IDX_IO4 0x68 #define PNP_IDX_IRQ0 0x70 #define PNP_IDX_IRQ1 0x72 #define PNP_IDX_DRQ0 0x74 diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 0cfdd61c27..b57be454a4 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -4,9 +4,7 @@ #define __DEVICE_PNP_OPS_H__ #include -#include #include -#include #if ENV_PNP_SIMPLE_DEVICE @@ -22,6 +20,12 @@ static __always_inline uint8_t pnp_read_config( return pnp_read_index(dev >> 8, reg); } +static __always_inline void pnp_unset_and_set_config( + pnp_devfn_t dev, uint8_t reg, uint8_t unset, uint8_t set) +{ + pnp_unset_and_set_index(dev >> 8, reg, unset, set); +} + static __always_inline void pnp_set_logical_device(pnp_devfn_t dev) { @@ -32,13 +36,13 @@ void pnp_set_logical_device(pnp_devfn_t dev) static __always_inline void pnp_set_enable(pnp_devfn_t dev, int enable) { - pnp_write_config(dev, 0x30, enable?0x1:0x0); + pnp_write_config(dev, PNP_IDX_EN, enable?0x1:0x0); } static __always_inline int pnp_read_enable(pnp_devfn_t dev) { - return !!pnp_read_config(dev, 0x30); + return !!pnp_read_config(dev, PNP_IDX_EN); } static __always_inline diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 42c7e6ae45..3a7ccf09e6 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -109,7 +109,6 @@ static inline void *res2mmio(struct resource *res, unsigned long offset, const struct device *largest_resource(struct bus *bus, struct resource **result_res, unsigned long type_mask, unsigned long type); - /* Compute and allocate resources. This is the main resource allocator entry point. */ void allocate_resources(const struct device *root); diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 4bc80092b5..e113aec94a 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -3,6 +3,7 @@ #ifndef __DEVICE_SMBUS_HOST_H__ #define __DEVICE_SMBUS_HOST_H__ +#include #include #include diff --git a/src/include/device/soundwire.h b/src/include/device/soundwire.h index 85e3186219..6f966ae2f4 100644 --- a/src/include/device/soundwire.h +++ b/src/include/device/soundwire.h @@ -16,8 +16,7 @@ #ifndef __DEVICE_SOUNDWIRE_H__ #define __DEVICE_SOUNDWIRE_H__ -#include -#include +#include /** * enum soundwire_limits - Limits on number of SoundWire devices in topology. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index bd0d151508..ae30c59710 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -4,6 +4,7 @@ #ifndef __DEVICE_TREE_H__ #define __DEVICE_TREE_H__ +#include #include #include @@ -42,8 +43,6 @@ struct fdt_property uint32_t size; }; - - /* * Unflattened device tree structures. */ @@ -87,8 +86,6 @@ struct device_tree struct device_tree_node *root; }; - - /* * Flattened device tree functions. These generally return the number of bytes * which were consumed reading the requested value. @@ -108,8 +105,6 @@ int fdt_skip_node(const void *blob, uint32_t offset); invalidates the unflattened one. */ struct device_tree *fdt_unflatten(const void *blob); - - /* * Unflattened device tree functions. */ diff --git a/src/include/edid.h b/src/include/edid.h index 7536a66119..691cf76b97 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -4,6 +4,7 @@ #define EDID_H #include +#include #include "commonlib/coreboot_tables.h" enum edid_modes { @@ -95,8 +96,6 @@ enum edid_status { int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/include/elog.h b/src/include/elog.h index ab855448af..3071271b3e 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -3,6 +3,8 @@ #ifndef ELOG_H_ #define ELOG_H_ +#include + #define MAX_EVENT_SIZE 0x7F /* End of log */ @@ -77,7 +79,7 @@ #define ELOG_WAKE_SOURCE_PME 0x01 #define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 #define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_GPE 0x04 #define ELOG_WAKE_SOURCE_SMBUS 0x05 #define ELOG_WAKE_SOURCE_PWRBTN 0x06 #define ELOG_WAKE_SOURCE_PME_HDA 0x07 @@ -117,6 +119,11 @@ #define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b +#define ELOG_WAKE_SOURCE_GPIO 0x2c +#define ELOG_WAKE_SOURCE_PME_TBT 0x2d +#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e +#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA 0x30 struct elog_event_data_wake { u8 source; @@ -199,7 +206,6 @@ struct elog_event_mem_cache_update { #define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HR 0xb5 - struct elog_event_extended_event { u8 event_type; u32 event_complement; diff --git a/src/include/fit_payload.h b/src/include/fit_payload.h index 8632b05b82..4ebe3ce78e 100644 --- a/src/include/fit_payload.h +++ b/src/include/fit_payload.h @@ -4,7 +4,6 @@ #define __FIT_PAYLOAD_H_ #include -#include void fit_payload(struct prog *payload); diff --git a/src/include/fmap.h b/src/include/fmap.h index a07bae22f5..761e742f56 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -5,6 +5,8 @@ #include #include +#include +#include /* Locate the named area in the fmap and fill in a region device representing * that area. The region is a sub-region of the readonly boot media. Return diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h new file mode 100644 index 0000000000..07ddd31ce8 --- /dev/null +++ b/src/include/framebuffer_info.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __FRAMEBUFFER_INFO_H_ +#define __FRAMEBUFFER_INFO_H_ + +#include +#include +#include + +struct fb_info; + +struct fb_info * +fb_add_framebuffer_info_ex(const struct lb_framebuffer *fb); + +struct fb_info *fb_add_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel); + +void fb_set_orientation(struct fb_info *info, + enum lb_fb_orientation orientation); + +struct edid; +struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr); + +#endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/include/fw_config.h b/src/include/fw_config.h index d41afd6c5d..b702871358 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -8,6 +8,8 @@ #include #include +#define UNDEFINED_FW_CONFIG ~((uint64_t)0) + /** * struct fw_config - Firmware configuration field and option. * @field_name: Name of the field that this option belongs to. @@ -18,8 +20,8 @@ struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; /* Generate a pointer to a compound literal of the fw_config structure. */ @@ -30,6 +32,13 @@ struct fw_config { .value = FW_CONFIG_FIELD_##__field##_OPTION_##__option##_VALUE \ }) +/** + * fw_config_get() - Provide firmware configuration value. + * + * Return 64bit firmware configuration value determined for the system. + */ +uint64_t fw_config_get(void); + #if CONFIG(FW_CONFIG) /** @@ -40,6 +49,27 @@ struct fw_config { */ bool fw_config_probe(const struct fw_config *match); +/** + * fw_config_for_each_found() - Call a callback for each fw_config field found + * @cb: The callback function + * @arg: A context argument that is passed to the callback + */ +void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg); + +/** + * fw_config_is_provisioned() - Determine if FW_CONFIG has been provisioned. + * Return %true if FW_CONFIG has been provisioned, %false otherwise. + */ +bool fw_config_is_provisioned(void); + +/** + * fw_config_get_found() - Return a pointer to the fw_config struct for a given field. + * @field_mask: A field mask from static.h, e.g., FW_CONFIG_FIELD_FEATURE_MASK + * + * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL. +*/ +const struct fw_config *fw_config_get_found(uint64_t field_mask); + #else static inline bool fw_config_probe(const struct fw_config *match) diff --git a/src/include/imd.h b/src/include/imd.h index 314d223341..df669fd366 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -40,11 +40,13 @@ struct imd_entry; struct imd; +static const size_t LIMIT_ALIGN = 4096; + /* * Initialize handle to use for working with an imd. Upper limit is the - * exclusive address to start allocating down from. This function needs - * to be called at least once before any other imd related functions - * can be used. + * exclusive address (aligned down to LIMIT_ALIGN) to start allocating down + * from. This function needs to be called at least once before any other imd + * related functions can be used. */ void imd_handle_init(struct imd *imd, void *upper_limit); @@ -60,7 +62,9 @@ void imd_handle_init_partial_recovery(struct imd *imd); * Create an empty imd with a specified root_size and each entry is aligned to * the provided entry_align. As noted above the root size encompasses the * root pointer and root block leading to the number of imd entries being a - * function of the root_size parameter. + * function of the root_size parameter. Please note, that one entry is allocated + * for covering root region, thus caller should consider this calculating + * root_size. */ int imd_create_empty(struct imd *imd, size_t root_size, size_t entry_align); @@ -101,14 +105,14 @@ const struct imd_entry *imd_entry_find(const struct imd *imd, uint32_t id); const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, uint32_t id, size_t size); -/* Returns size of entry or 0 on failure. */ -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); +/* Returns size of entry. */ +size_t imd_entry_size(const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); /* Returns id for the imd entry. */ -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); +uint32_t imd_entry_id(const struct imd_entry *entry); /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); diff --git a/src/include/imd_private.h b/src/include/imd_private.h new file mode 100644 index 0000000000..43c3b7d50b --- /dev/null +++ b/src/include/imd_private.h @@ -0,0 +1,38 @@ +#ifndef _IMD_PRIVATE_H_ +#define _IMD_PRIVATE_H_ + +#include + +/* In-memory data structures. */ +struct imd_root_pointer { + uint32_t magic; + /* Relative to upper limit/offset. */ + int32_t root_offset; +} __packed; + +struct imd_entry { + uint32_t magic; + /* start is located relative to imd_root */ + int32_t start_offset; + uint32_t size; + uint32_t id; +} __packed; + +struct imd_root { + uint32_t max_entries; + uint32_t num_entries; + uint32_t flags; + uint32_t entry_align; + /* Used for fixing the size of an imd. Relative to the root. */ + int32_t max_offset; + struct imd_entry entries[0]; +} __packed; + +#define IMD_ROOT_PTR_MAGIC 0xc0389481 +#define IMD_ENTRY_MAGIC (~0xc0389481) +#define SMALL_REGION_ID CBMEM_ID_IMD_SMALL +#define LIMIT_ALIGN 4096 + +#define IMD_FLAG_LOCKED 1 + +#endif /* _IMD_PRIVATE_H */ diff --git a/src/include/input-event-codes.h b/src/include/input-event-codes.h index 006c2627ad..abb1e08a5b 100644 --- a/src/include/input-event-codes.h +++ b/src/include/input-event-codes.h @@ -870,7 +870,6 @@ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) diff --git a/src/include/lib.h b/src/include/lib.h index 46d8b02112..5c6eef2a70 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -46,6 +46,8 @@ void hexdump32(char LEVEL, const void *d, size_t len); */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); +/* Population Count: number of bits that are one */ +static inline int popcnt(u32 x) { return __builtin_popcount(x); } /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ @@ -56,4 +58,9 @@ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } +static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } +static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } +static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } + #endif /* __LIB_H__ */ diff --git a/src/include/list.h b/src/include/list.h index a8990354d7..6f0b54d818 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -4,9 +4,6 @@ #ifndef __LIST_H__ #define __LIST_H__ -#include -#include - struct list_node { struct list_node *next; struct list_node *prev; @@ -19,10 +16,10 @@ void list_insert_after(struct list_node *node, struct list_node *after); // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); -#define list_for_each(ptr, head, member) \ - for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ - &((ptr)->member); \ - (ptr) = container_of((ptr)->member.next, \ +#define list_for_each(ptr, head, member) \ + for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ + (uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \ + (ptr) = container_of((ptr)->member.next, \ typeof(*(ptr)), member)) #endif /* __LIST_H__ */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index bd1d6846f0..bf830b7d24 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -71,6 +71,9 @@ _ = ASSERT(sz >= FMAP_SIZE, \ STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); +#define CBFS_MCACHE(addr, sz) \ + REGION(cbfs_mcache, addr, sz, 4) + #if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ diff --git a/src/include/memory_info.h b/src/include/memory_info.h index a9891189d2..1ba73291a8 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -5,6 +5,7 @@ #define _MEMORY_INFO_H_ #include +#include #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 33 @@ -27,6 +28,10 @@ struct dimm_info { * See the smbios.h smbios_memory_type enum. */ uint16_t ddr_type; + /* + * ddr_frequency is deprecated. + * Use max_speed_mts and configured_speed_mts instead. + */ uint16_t ddr_frequency; uint8_t rank_per_dimm; uint8_t channel_num; @@ -78,11 +83,35 @@ struct dimm_info { * Voltage Level */ uint16_t vdd_voltage; + /* + * Max speed in MT/s + * If the value is 0, ddr_frequency should be used instead. + */ + uint16_t max_speed_mts; + /* + * Configured speed in MT/s + * If the value is 0, ddr_frequency should be used instead. + */ + uint16_t configured_speed_mts; } __packed; struct memory_info { + /* controller specific */ + bool ecc_capable; + /* Maximum capacity the DRAM controller/mainboard supports */ + uint32_t max_capacity_mib; + /* Maximum number of DIMMs the DRAM controller/mainboard supports */ + uint16_t number_of_devices; + + /* active DIMM configuration */ uint8_t dimm_cnt; struct dimm_info dimm[DIMM_INFO_TOTAL]; } __packed; +/* + * mainboard_get_dram_part_num returns a DRAM part number override string + * return NULL = no part number override provided by mainboard + * return non-NULL = pointer to a string terminating in '\0' + */ +const char *mainboard_get_dram_part_num(void); #endif diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00ecf8..80db5985ed 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -4,6 +4,7 @@ #include #include +#include /* A memranges structure consists of a list of range_entry(s). The structure * is exposed so that a memranges can be used on the stack if needed. */ @@ -81,7 +82,6 @@ static inline bool memranges_is_empty(const struct memranges *ranges) #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) - /* Initialize memranges structure providing an optional array of range_entry * to use as the free list. Additionally, it accepts an align parameter that * represents the required alignment(log 2) of addresses. */ diff --git a/src/include/metadata_hash.h b/src/include/metadata_hash.h new file mode 100644 index 0000000000..2d3b8a86bc --- /dev/null +++ b/src/include/metadata_hash.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _METADATA_HASH_H_ +#define _METADATA_HASH_H_ + +#include + +/* Verify the an FMAP data structure with the FMAP hash that is stored together with the CBFS + metadata hash in the bootblock's metadata hash anchor (when CBFS verification is enabled). */ +vb2_error_t metadata_hash_verify_fmap(const void *fmap_base, size_t fmap_size); + +#if CONFIG(CBFS_VERIFICATION) +/* Get the (RO) CBFS metadata hash for this CBFS image, which forms the root of trust for CBFS + verification. This function is only available in the bootblock. */ +struct vb2_hash *metadata_hash_get(void); +#else +static inline struct vb2_hash *metadata_hash_get(void) { return NULL; } +#endif + +#endif diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 5131cbccd2..f1e6b52010 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -14,18 +14,37 @@ enum { /* * It's up to the caller to decide when to retrieve and stash data. There is - * differentiation on recovery mode CONFIG_HAS_RECOVERY_MRC_CACHE, but that's + * differentiation on recovery mode CONFIG(HAS_RECOVERY_MRC_CACHE), but that's * only for locating where to retrieve and save the data. If a platform doesn't * want to update the data then it shouldn't stash the data for saving. * Similarly, if the platform doesn't need the data for booting because of a * policy don't request the data. */ -/* Get and stash data for saving provided the type passed in. The functions - * return < 0 on error, 0 on success. */ -int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev); +/* Get and stash data for saving provided the type passed in. */ + +/** + * mrc_cache_load_current + * + * Fill in the buffer with the latest slot data. This will be a + * common entry point for ARM platforms. Returns < 0 on error, size + * of the returned data on success. + */ +ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer, + size_t buffer_size); +/** + * mrc_cache_mmap_leak + * + * Return a pointer to a buffer with the latest slot data. An mmap + * will be executed (without a matching unmap). This will be a common + * entry point for platforms where mmap is considered a noop, like x86 + */ +void *mrc_cache_current_mmap_leak(int type, uint32_t version, + size_t *data_size); +/** + * Returns < 0 on error, 0 on success. + */ int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size); + size_t size); #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 30cb274874..167be520dc 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -187,6 +187,7 @@ enum { enum { NHLT_PDM_DEV, + NHLT_PDM_DEV_CAVS15, // NHLT_PDM_DEV on cAVS1.5 (KBL) based platforms }; /* Endpoint direction. */ @@ -219,7 +220,6 @@ enum { SPEAKER_TOP_BACK_RIGHT = 1 << 17, }; - /* Supporting structures. Only SoC/chipset and the library code directly should * be manipulating these structures. */ struct sub_format { diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index c3d0a93b5e..9268cd11fa 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -3,6 +3,8 @@ #ifndef PC80_I8259_H #define PC80_I8259_H +#include + /* * IRQ numbers and common usage * If an IRQ does not say it is 'Reserved' diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index a2c65cb4c0..2f94cc0213 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -17,7 +17,6 @@ #define RTC_REG_C 12 #define RTC_REG_D 13 - /********************************************************************** * register details **********************************************************************/ diff --git a/src/include/ramdetect.h b/src/include/ramdetect.h index 93c5db1382..55c81d08c5 100644 --- a/src/include/ramdetect.h +++ b/src/include/ramdetect.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include /* * Used in probe_ramsize(). This is a weak function and it's overridden for diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 59da0cb2ed..aa6bf80fa5 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -355,7 +355,6 @@ struct reg_script_bus_entry { #define REG_RES_XOR32(bar_, reg_, value_) \ REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) - #if CONFIG(SOC_INTEL_BAYTRAIL) /* * IO Sideband Function diff --git a/src/include/region_file.h b/src/include/region_file.h index 0df64e5593..a3cb79d044 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -4,6 +4,7 @@ #define REGION_FILE_H #include +#include #include /* @@ -30,9 +31,22 @@ int region_file_init(struct region_file *f, const struct region_device *p); */ int region_file_data(const struct region_file *f, struct region_device *rdev); +/* + * Create region file entry struct to insert multiple data buffers + * into the same region_file. + */ +struct update_region_file_entry { + /* size of this entry */ + size_t size; + /* data pointer */ + const void *data; +}; + /* Update region file with latest data. Returns < 0 on error, 0 on success. */ -int region_file_update_data(struct region_file *f, const void *buf, - size_t size); +int region_file_update_data_arr(struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries); +int region_file_update_data(struct region_file *f, const void *buf, size_t size); /* Declared here for easy object allocation. */ struct region_file { diff --git a/src/include/rules.h b/src/include/rules.h index 160829efa4..6ebb37e804 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -3,6 +3,12 @@ #ifndef _RULES_H #define _RULES_H +#if defined(__TIMELESS__) +#define ENV_TIMELESS 1 +#else +#define ENV_TIMELESS 0 +#endif + /* Useful helpers to tell whether the code is executing in bootblock, * romstage, ramstage or SMM. */ @@ -57,10 +63,11 @@ /* * NOTE: "verstage" code may either run as a separate stage or linked into the - * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The - * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when - * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or - * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options). + * bootblock/romstage, depending on the setting of the VBOOT_SEPARATE_VERSTAGE + * kconfig option. The ENV_SEPARATE_VERSTAGE macro will only return true for + * "verstage" code when CONFIG(VBOOT_SEPARATE_VERSTAGE) is true, otherwise that + * code will have ENV_BOOTBLOCK or ENV_ROMSTAGE set (depending on the + * "VBOOT_STARTS_IN_"... kconfig options). */ #elif defined(__VERSTAGE__) #define ENV_DECOMPRESSOR 0 @@ -72,7 +79,11 @@ #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#define ENV_STRING "verstage-before-bootblock" +#else #define ENV_STRING "verstage" +#endif #elif defined(__RAMSTAGE__) #define ENV_DECOMPRESSOR 0 @@ -261,6 +272,20 @@ /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) +/* Set USER_SPACE in the makefile for the rare code that runs in userspace */ +#if defined(__USER_SPACE__) +#define ENV_USER_SPACE 1 +#else +#define ENV_USER_SPACE 0 +#endif + +/* Define the first stage to run */ +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#define ENV_INITIAL_STAGE ENV_SEPARATE_VERSTAGE +#else +#define ENV_INITIAL_STAGE ENV_BOOTBLOCK +#endif + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/include/smbios.h b/src/include/smbios.h index ed09d642b9..e451d17ef8 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -40,6 +40,7 @@ const char *smbios_system_sku(void); unsigned int smbios_cpu_get_max_speed_mhz(void); unsigned int smbios_cpu_get_current_speed_mhz(void); +unsigned int smbios_cpu_get_voltage(void); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); @@ -54,6 +55,18 @@ const char *smbios_chassis_version(void); const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); + +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); +unsigned int smbios_processor_external_clock(void); +unsigned int smbios_processor_characteristics(void); +struct cpuid_result; +unsigned int smbios_processor_family(struct cpuid_result res); + +unsigned int smbios_cache_error_correction_type(u8 level); +unsigned int smbios_cache_sram_type(void); +unsigned int smbios_cache_conf_operation_mode(u8 level); + /* Used by mainboard to add port information of type 8 */ struct port_information; int smbios_write_type8(unsigned long *current, int *handle, @@ -247,6 +260,19 @@ struct smbios_entry { u8 smbios_bcd_revision; } __packed; +struct smbios_entry30 { + u8 anchor[5]; + u8 checksum; + u8 length; + u8 major_version; + u8 minor_version; + u8 smbios_doc_rev; + u8 entry_point_rev; + u8 reserved; + u32 struct_table_length; + u64 struct_table_address; +} __packed; + struct smbios_type0 { u8 type; u8 length; @@ -402,9 +428,17 @@ struct smbios_type4 { u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; +/* defines for smbios_type4 */ + +#define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) +#define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) + /* defines for supported_sram_type/current_sram_type */ #define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) @@ -473,6 +507,13 @@ enum smbios_cache_associativity { #define SMBIOS_CACHE_SIZE2_UNIT_64KB (1UL << 31) #define SMBIOS_CACHE_SIZE2_MASK 0x7fffffff +/* define for cache operation mode */ + +#define SMBIOS_CACHE_OP_MODE_WRITE_THROUGH 0 +#define SMBIOS_CACHE_OP_MODE_WRITE_BACK 1 +#define SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS 2 +#define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 + struct smbios_type7 { u8 type; u8 length; @@ -828,6 +869,19 @@ struct smbios_type17 { u8 eos[2]; } __packed; +struct smbios_type19 { + u8 type; + u8 length; + u16 handle; + u32 starting_address; + u32 ending_address; + u16 memory_array_handle; + u8 partition_width; + u64 extended_starting_address; + u64 extended_ending_address; + u8 eos[2]; +} __packed; + struct smbios_type32 { u8 type; u8 length; diff --git a/src/include/smmstore.h b/src/include/smmstore.h index ff0b72001a..2c37ca39b9 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -10,10 +10,18 @@ #define SMMSTORE_RET_FAILURE 1 #define SMMSTORE_RET_UNSUPPORTED 2 +/* Version 1 */ #define SMMSTORE_CMD_CLEAR 1 #define SMMSTORE_CMD_READ 2 #define SMMSTORE_CMD_APPEND 3 +/* Version 2 */ +#define SMMSTORE_CMD_INIT 4 +#define SMMSTORE_CMD_RAW_READ 5 +#define SMMSTORE_CMD_RAW_WRITE 6 +#define SMMSTORE_CMD_RAW_CLEAR 7 + +/* Version 1 */ struct smmstore_params_read { void *buf; ssize_t bufsize; @@ -26,12 +34,90 @@ struct smmstore_params_append { size_t valsize; }; -/* SMM responder */ +/* Version 2 */ +/* + * The Version 2 protocol separates the SMMSTORE into 64KiB blocks, each + * of which can be read/written/cleared in an independent manner. The + * data format isn't specified. See documentation page for more details. + */ + +#define SMM_BLOCK_SIZE (64 * KiB) + +/* + * Sets the communication buffer to use for read and write operations. + */ +struct smmstore_params_init { + uint32_t com_buffer; + uint32_t com_buffer_size; +} __packed; + +/* + * Returns the number of blocks the SMMSTORE supports and their size. + * For EDK2 this should be at least two blocks with 64 KiB each. + * The mmap_addr is set the memory mapped physical address of the SMMSTORE. + */ +struct smmstore_params_info { + uint32_t num_blocks; + uint32_t block_size; + uint32_t mmap_addr; +} __packed; + +/* + * Reads a chunk of raw data with size @bufsize from the block specified by + * @block_id starting at @bufoffset. + * The read data is placed in memory pointed to by @buf. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_write { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Writes a chunk of raw data with size @bufsize to the block specified by + * @block_id starting at @bufoffset. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_read { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Erases the specified block. + * + * @block_id must be less than num_blocks + */ +struct smmstore_params_raw_clear { + uint32_t block_id; +} __packed; + + +/* SMM handler */ uint32_t smmstore_exec(uint8_t command, void *param); -/* implementation */ +/* Implementation of Version 1 */ int smmstore_read_region(void *buf, ssize_t *bufsize); -int smmstore_append_data(void *key, uint32_t key_sz, - void *value, uint32_t value_sz); +int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); + +/* Implementation of Version 2 */ +int smmstore_init(void *buf, size_t len); +int smmstore_rawread_region(uint32_t block_id, uint32_t offset, uint32_t bufsize); +int smmstore_rawwrite_region(uint32_t block_id, uint32_t offset, uint32_t bufsize); +int smmstore_rawclear_region(uint32_t block_id); +#if ENV_RAMSTAGE +int smmstore_get_info(struct smmstore_params_info *info); +#endif + +/* Advertise SMMSTORE v2 support */ +struct lb_header; +void lb_smmstorev2(struct lb_header *header); + #endif diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index ed70cb7baa..5e78ae4462 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -31,7 +31,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_set(v, i) (((v)->counter) = (i)) - /** * atomic_inc - increment atomic variable * @param v: pointer of type atomic_t @@ -41,7 +40,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_inc(v) (((v)->counter)++) - /** * atomic_dec - decrement atomic variable * @param v: pointer of type atomic_t @@ -51,7 +49,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_dec(v) (((v)->counter)--) - #endif /* CONFIG_SMP */ #endif /* SMP_ATOMIC_H */ diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index 98ab3a778a..8554aa0589 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -6,12 +6,10 @@ #else /* !CONFIG_SMP */ #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #endif #endif /* SMP_SPINLOCK_H */ diff --git a/src/include/spd.h b/src/include/spd.h index f46bde6522..9afb706c97 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -136,7 +136,6 @@ /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ #define SPD_tRFC 42 - /* SPD_MEMORY_TYPE values. */ enum spd_memory_type { SPD_MEMORY_TYPE_UNDEFINED = 0x00, diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index f8d7d68622..a53b8eb948 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -4,8 +4,10 @@ #define __SPD_CACHE_H #include +#include +#include -#define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE" +#define SPD_CACHE_FMAP_NAME (CONFIG_SPD_CACHE_FMAP_NAME) #define SC_SPD_NUMS (CONFIG_DIMM_MAX) #define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n) #define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE) diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 35b02dbb3d..a7f707eb1c 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -202,7 +202,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash); int chipset_volatile_group_end(const struct spi_flash *flash); /* Return spi_flash object reference for the boot device. This is only valid - * if CONFIG_BOOT_DEVICE_SPI_FLASH is enabled. */ + * if CONFIG(BOOT_DEVICE_SPI_FLASH) is enabled. */ const struct spi_flash *boot_device_spi_flash(void); /* Protect a region of spi flash using its controller, if available. Returns @@ -225,4 +225,12 @@ int spi_flash_vector_helper(const struct spi_slave *slave, int (*func)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin)); +/* + * Fill in the memory mapped windows used by the SPI flash device. This is useful for payloads + * to identify SPI flash to host space mapping. + * + * Returns number of windows added to the table. + */ +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table); + #endif /* _SPI_FLASH_H_ */ diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h index 028f6a351e..8f64e5eea9 100644 --- a/src/include/spi_sdcard.h +++ b/src/include/spi_sdcard.h @@ -3,6 +3,8 @@ #ifndef _SPI_SDCARD_H_ #define _SPI_SDCARD_H_ +#include + struct spi_sdcard { int type; struct spi_slave slave; diff --git a/src/include/stdbool.h b/src/include/stdbool.h index d7f9e643ea..3733527bd2 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -3,9 +3,6 @@ #ifndef __STDBOOL_H__ #define __STDBOOL_H__ -#include - - typedef _Bool bool; #define true 1 #define false 0 diff --git a/src/include/string.h b/src/include/string.h index 8eef0680cb..3cfa18d33c 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -29,6 +29,7 @@ int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, int maxlen); int strspn(const char *str, const char *spn); int strcspn(const char *str, const char *spn); +char *strstr(const char *haystack, const char *needle); char *strtok_r(char *str, const char *delim, char **ptr); char *strtok(char *str, const char *delim); long atol(const char *str); diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h index 661f3ee430..f26a0171f5 100644 --- a/src/include/superio/hwm5_conf.h +++ b/src/include/superio/hwm5_conf.h @@ -4,6 +4,7 @@ #define DEVICE_PNP_HWM5_CONF_H #include +#include /* The address/data register pair for the indirect/indexed IO space of the * hardware monitor (HWM) that does temperature and voltage sensing and fan @@ -11,14 +12,14 @@ * of the corresponding IO address region, but at offset 5 and 6. */ /* - * u8 pnp_read_hwm5_index(u16 port, u8 reg) + * u8 pnp_read_hwm5_index(u16 base, u8 reg) * Description: * This routine reads indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The result is then - * read from the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The result is then + * read from the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The I/O address of the port index register. + * @param[in] u16 base = The I/O address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[out] u8 result = The value read back from the data register. */ @@ -28,14 +29,14 @@ static inline u8 pnp_read_hwm5_index(u16 base, u8 reg) } /* - * void pnp_write_hwm5_index(u16 port, u8 reg, u8 value) + * void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) * Description: * This routine writes indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The value byte is then - * written to the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The value byte is then + * written to the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The address of the port index register. + * @param[in] u16 base = The address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[in] u8 value = The value to be written to the data register. */ @@ -44,4 +45,32 @@ static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) pnp_write_index(base + 5, reg, value); } +/* + * void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set) + * Description: + * This routine unsets and sets bits from indexed I/O registers. The + * reg byte is written to the index register at I/O address = base + 5. + * The value byte to update is data register at I/O address = base + 6. + * + * Unlike and-then-or style operations, no bitwise negation is necessary + * to specify the bits to unset. Because the bitwise negation implicitly + * promotes operands to int before operating, one may have to explicitly + * downcast the result if the data width is smaller than that of an int. + * Since warnings are errors in coreboot, explicit casting is necessary. + * + * Performing said negation inside this routine alleviates this problem, + * while allowing the compiler to warn if the input parameters overflow. + * Casting outside this function would silence valid compiler warnings. + * + * Parameters: + * @param[in] u16 base = The address of the base index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register. + * @param[in] u8 set = Bitmask with ones to the bits to set from the data register. + */ +static inline void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set) +{ + pnp_unset_and_set_index(base + 5, reg, unset, set); +} + #endif /* DEVICE_PNP_HWM5_CONF_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index f84672ed22..6fe24f5e44 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -13,17 +13,41 @@ extern u8 _dram[]; extern u8 _##name[]; \ extern u8 _e##name[]; +/* + * Regions can be declared optional if not all configurations provide them in + * memlayout and you want code to be able to check for their existence at + * runtime. Not every region that is architecture or platform-specific should + * use this -- only declare regions optional if the code *accessing* them runs + * both on configurations that have the region and those that don't. That code + * should then check (REGION_SIZE(name) != 0) before accessing it. + */ +#define DECLARE_OPTIONAL_REGION(name) \ + __weak extern u8 _##name[]; \ + __weak extern u8 _e##name[]; + DECLARE_REGION(sram) -DECLARE_REGION(timestamp) +DECLARE_OPTIONAL_REGION(timestamp) DECLARE_REGION(preram_cbmem_console) DECLARE_REGION(cbmem_init_hooks) DECLARE_REGION(stack) DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) +DECLARE_REGION(cbfs_mcache) DECLARE_REGION(fmap_cache) DECLARE_REGION(tpm_tcpa_log) +#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) +DECLARE_REGION(bss) +DECLARE_REGION(asan_shadow) +#endif + +#if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE) +DECLARE_REGION(data) +DECLARE_REGION(heap) +DECLARE_REGION(asan_shadow) +#endif + /* Regions for execution units. */ DECLARE_REGION(payload) @@ -42,22 +66,14 @@ DECLARE_REGION(ramstage) DECLARE_REGION(pagetables) DECLARE_REGION(ttb) -DECLARE_REGION(ttb_subtables) +DECLARE_OPTIONAL_REGION(ttb_subtables) DECLARE_REGION(dma_coherent) DECLARE_REGION(soc_registers) DECLARE_REGION(framebuffer) DECLARE_REGION(pdpt) -DECLARE_REGION(opensbi) -DECLARE_REGION(bl31) - -/* - * Put this into a .c file accessing a linker script region to mark that region - * as "optional". If it is defined in memlayout.ld (or anywhere else), the - * values from that definition will be used. If not, start, end and size will - * all evaluate to 0. (We can't explicitly assign the symbols to 0 in the - * assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) - */ -#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name) +DECLARE_OPTIONAL_REGION(opensbi) +DECLARE_OPTIONAL_REGION(bl31) +DECLARE_REGION(transfer_buffer) /* Returns true when pre-RAM symbols are known to the linker. * (Does not necessarily mean that the memory is accessible.) */ diff --git a/src/include/thread.h b/src/include/thread.h index df307fa6f8..a2c7ed2085 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -2,7 +2,6 @@ #ifndef THREAD_H_ #define THREAD_H_ -#include #include #include #include diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 06c99acb3c..647cd13897 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -4,6 +4,7 @@ #define __TIMESTAMP_H__ #include +#include #if CONFIG(COLLECT_TIMESTAMPS) /* diff --git a/src/include/trace.h b/src/include/trace.h deleted file mode 100644 index ece1b2110c..0000000000 --- a/src/include/trace.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __TRACE_H -#define __TRACE_H - -#if !ENV_ROMSTAGE_OR_BEFORE && CONFIG(TRACE) - -void __cyg_profile_func_enter(void *, void *) - __attribute__((no_instrument_function)); - -void __cyg_profile_func_exit(void *, void *) - __attribute__((no_instrument_function)); - -extern volatile int trace_dis; - -#define DISABLE_TRACE do { trace_dis = 1; } while (0); -#define ENABLE_TRACE do { trace_dis = 0; } while (0); -#define DISABLE_TRACE_ON_FUNCTION __attribute__((no_instrument_function)); - -#else /* !CONFIG_TRACE */ - -#define DISABLE_TRACE -#define ENABLE_TRACE -#define DISABLE_TRACE_ON_FUNCTION - -#endif - -#endif diff --git a/src/lib/Kconfig b/src/lib/Kconfig index a6fb1f149e..e1d56fe26b 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -5,14 +5,6 @@ config MISSING_BOARD_RESET implementation. This activates a stub that logs the missing board reset and halts execution. -config NO_EDID_FILL_FB - bool - default y if !MAINBOARD_DO_NATIVE_VGA_INIT - help - Don't include default fill_lb_framebuffer() implementation. Select - this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides - its own fill_lb_framebuffer() implementation. - config RAMSTAGE_ADA bool help @@ -30,12 +22,11 @@ config FLATTENED_DEVICE_TREE Selected by features that require to parse and manipulate a flattened devicetree in ramstage. -config GENERIC_SPD_BIN +config HAVE_SPD_IN_CBFS bool help If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. + and locating it runtime to load SPD. config DIMM_MAX int @@ -55,6 +46,23 @@ config DIMM_SPD_SIZE config SPD_READ_BY_WORD bool +config SPD_CACHE_IN_FMAP + bool + default n + help + Enables capability to cache DIMM SPDs in a dedicated FMAP region + to speed loading of SPD data. Currently requires board-level + romstage implementation to read/write/utilize cached SPD data. + When the default FMAP is used, will create a region named RW_SPD_CACHE + to store the cached SPD data. + +config SPD_CACHE_FMAP_NAME + string + depends on SPD_CACHE_IN_FMAP + default "RW_SPD_CACHE" + help + Name of the FMAP region created in the default FMAP to cache SPD data. + if RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO @@ -81,3 +89,23 @@ config ESPI_DEBUG help This option enables eSPI library helper functions for displaying debug information. + +config NO_CBFS_MCACHE + bool + help + Disables the CBFS metadata cache. This means that your platform does + not need to provide a CBFS_MCACHE section in memlayout and can save + the associated CAR/SRAM size. In that case every single CBFS file + lookup must re-read the same CBFS directory entries from flash to find + the respective file. + +config CBFS_MCACHE_RW_PERCENTAGE + int + depends on VBOOT && !NO_CBFS_MCACHE + default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification new file mode 100644 index 0000000000..4e2ed8cf01 --- /dev/null +++ b/src/lib/Kconfig.cbfs_verification @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later +# +# This file is part of the coreboot project. +# +# This file is sourced from src/security/Kconfig for menuconfig convenience. + +#menu "CBFS verification" # TODO: enable once it works + +config CBFS_VERIFICATION + bool # TODO: make user selectable once it works + depends on !COMPRESS_BOOTBLOCK # TODO: figure out decompressor anchor + depends on !VBOOT_STARTS_BEFORE_BOOTBLOCK # this is gonna get tricky... + select VBOOT_LIB + help + Work in progress. Do not use (yet). + +config TOCTOU_SAFETY + bool + depends on CBFS_VERIFICATION + depends on !NO_FMAP_CACHE + depends on !NO_CBFS_MCACHE + depends on !USE_OPTION_TABLE && !FSP_CAR # Known to access CBFS before CBMEM init + help + Work in progress. Not actually TOCTOU safe yet. Do not use. + + Design idea here is that mcache overflows in this mode are only legal + for the RW CBFS, because it's relatively easy to retrieve the RW + metadata hash from persistent vboot context at any time, but the RO + metadata hash is lost after the bootblock is unloaded. This avoids the + need to carry yet another piece forward through the stages. Mcache + overflows are mostly a concern for RW updates (if an update adds more + files than originally planned for), for the RO section it should + always be possible to dimension the mcache correctly beforehand, so + this should be an acceptable limitation. + +config CBFS_HASH_ALGO + int + default 1 if CBFS_HASH_SHA1 + default 2 if CBFS_HASH_SHA256 + default 3 if CBFS_HASH_SHA512 + +choice + prompt "--> hash type" + depends on CBFS_VERIFICATION + default CBFS_HASH_SHA256 + +config CBFS_HASH_SHA1 + bool "SHA-1" + +config CBFS_HASH_SHA256 + bool "SHA-256" + +config CBFS_HASH_SHA512 + bool "SHA-512" + +endchoice + +#endmenu diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 72d4f2414c..8424cbfac3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -7,6 +7,27 @@ ramstage-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined endif +# Ensure that asan_shadow_offset_callback patch is applied to GCC before ASan is used. +CFLAGS_asan += -fsanitize=kernel-address --param asan-use-shadow-offset-callback=1 \ + --param asan-stack=1 -fsanitize-address-use-after-scope \ + --param asan-instrumentation-with-call-threshold=0 \ + --param use-after-scope-direct-emission-threshold=0 + +ifeq ($(CONFIG_ASAN_IN_ROMSTAGE),y) +romstage-y += asan.c +CFLAGS_asan += --param asan-globals=0 +CFLAGS_romstage += $(CFLAGS_asan) +# Allow memory access without __asan_load and __asan_store checks. +$(obj)/romstage/lib/asan.o: CFLAGS_asan = +endif + +ifeq ($(CONFIG_ASAN_IN_RAMSTAGE),y) +ramstage-y += asan.c +CFLAGS_asan += --param asan-globals=1 +CFLAGS_ramstage += $(CFLAGS_asan) +$(obj)/ramstage/lib/asan.o: CFLAGS_asan = +endif + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -26,6 +47,7 @@ bootblock-y += prog_ops.c bootblock-y += cbfs.c bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c bootblock-y += libgcc.c +bootblock-$(CONFIG_CBFS_VERIFICATION) += metadata_hash.c bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -47,10 +69,7 @@ verstage-y += libgcc.c verstage-y += memcmp.c verstage-y += string.c -# TODO: Remove this when PSP bootblock timestamps are implemented. -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -82,6 +101,7 @@ ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -121,14 +141,10 @@ ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c -ramstage-$(CONFIG_TRACE) += trace.c -postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ifneq ($(CONFIG_NO_EDID_FILL_FB),y) ramstage-y += edid_fill_fb.c -endif ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c @@ -332,24 +348,28 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c -ifeq ($(CONFIG_GENERIC_SPD_BIN),y) +ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y) LIB_SPD_BIN = $(obj)/spd.bin LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) # Include spd ROM data $(LIB_SPD_BIN): $(LIB_SPD_DEPS) + test -n "$(SPD_SOURCES)" || \ + (echo "HAVE_SPD_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) + test -n "$(LIB_SPD_DEPS)" || \ + (echo "SPD_SOURCES is set but no SPD file was found" && exit 1) for f in $(LIB_SPD_DEPS); \ do for c in $$(cat $$f | grep --binary-files=text -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ -cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +cbfs-files-y += spd.bin spd.bin-file := $(LIB_SPD_BIN) spd.bin-type := spd endif ramstage-y += uuid.c -romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c +romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c diff --git a/src/lib/asan.c b/src/lib/asan.c new file mode 100644 index 0000000000..cf91111ab2 --- /dev/null +++ b/src/lib/asan.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * Address sanitizer support. + * + * Parts of this file are based on mm/kasan + * from the Linux kernel 4.19.137. + * + */ + +#include +#include +#include +#include +#include + +static inline void *asan_mem_to_shadow(const void *addr) +{ +#if ENV_ROMSTAGE + return (void *)((uintptr_t)&_asan_shadow + (((uintptr_t)addr - + (uintptr_t)&_car_region_start) >> ASAN_SHADOW_SCALE_SHIFT)); +#elif ENV_RAMSTAGE + return (void *)((uintptr_t)&_asan_shadow + (((uintptr_t)addr - + (uintptr_t)&_data) >> ASAN_SHADOW_SCALE_SHIFT)); +#endif +} + +static inline const void *asan_shadow_to_mem(const void *shadow_addr) +{ +#if ENV_ROMSTAGE + return (void *)((uintptr_t)&_car_region_start + (((uintptr_t)shadow_addr - + (uintptr_t)&_asan_shadow) << ASAN_SHADOW_SCALE_SHIFT)); +#elif ENV_RAMSTAGE + return (void *)((uintptr_t)&_data + (((uintptr_t)shadow_addr - + (uintptr_t)&_asan_shadow) << ASAN_SHADOW_SCALE_SHIFT)); +#endif +} + +static void asan_poison_shadow(const void *address, size_t size, u8 value) +{ + void *shadow_start, *shadow_end; + + shadow_start = asan_mem_to_shadow(address); + shadow_end = asan_mem_to_shadow(address + size); + + __builtin_memset(shadow_start, value, shadow_end - shadow_start); +} + +void asan_unpoison_shadow(const void *address, size_t size) +{ + asan_poison_shadow(address, size, 0); + + if (size & ASAN_SHADOW_MASK) { + u8 *shadow = (u8 *)asan_mem_to_shadow(address + size); + *shadow = size & ASAN_SHADOW_MASK; + } +} + +static __always_inline bool memory_is_poisoned_1(unsigned long addr) +{ + s8 shadow_value = *(s8 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(shadow_value)) { + s8 last_accessible_byte = addr & ASAN_SHADOW_MASK; + return unlikely(last_accessible_byte >= shadow_value); + } + + return false; +} + +static __always_inline bool memory_is_poisoned_2_4_8(unsigned long addr, + unsigned long size) +{ + u8 *shadow_addr = (u8 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(((addr + size - 1) & ASAN_SHADOW_MASK) < size - 1)) + return *shadow_addr || memory_is_poisoned_1(addr + size - 1); + + return memory_is_poisoned_1(addr + size - 1); +} + +static __always_inline bool memory_is_poisoned_16(unsigned long addr) +{ + u16 *shadow_addr = (u16 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(!IS_ALIGNED(addr, ASAN_SHADOW_SCALE_SIZE))) + return *shadow_addr || memory_is_poisoned_1(addr + 15); + + return *shadow_addr; +} + +static __always_inline unsigned long bytes_is_nonzero(const u8 *start, + size_t size) +{ + while (size) { + if (unlikely(*start)) + return (unsigned long)start; + start++; + size--; + } + + return 0; +} + +static __always_inline unsigned long memory_is_nonzero(const void *start, + const void *end) +{ + unsigned int words; + unsigned long ret; + unsigned int prefix = (unsigned long)start % 8; + + if (end - start <= 16) + return bytes_is_nonzero(start, end - start); + + if (prefix) { + prefix = 8 - prefix; + ret = bytes_is_nonzero(start, prefix); + if (unlikely(ret)) + return ret; + start += prefix; + } + + words = (end - start) / 8; + while (words) { + if (unlikely(*(u64 *)start)) + return bytes_is_nonzero(start, 8); + start += 8; + words--; + } + + return bytes_is_nonzero(start, (end - start) % 8); +} + +static __always_inline bool memory_is_poisoned_n(unsigned long addr, + size_t size) +{ + unsigned long ret; + + ret = memory_is_nonzero(asan_mem_to_shadow((void *)addr), + asan_mem_to_shadow((void *)addr + size - 1) + 1); + + if (unlikely(ret)) { + unsigned long last_byte = addr + size - 1; + s8 *last_shadow = (s8 *)asan_mem_to_shadow((void *)last_byte); + + if (unlikely(ret != (unsigned long)last_shadow || + ((long)(last_byte & ASAN_SHADOW_MASK) >= *last_shadow))) + return true; + } + return false; +} + +static __always_inline bool memory_is_poisoned(unsigned long addr, size_t size) +{ + if (__builtin_constant_p(size)) { + switch (size) { + case 1: + return memory_is_poisoned_1(addr); + case 2: + case 4: + case 8: + return memory_is_poisoned_2_4_8(addr, size); + case 16: + return memory_is_poisoned_16(addr); + default: + assert(0); + } + } + + return memory_is_poisoned_n(addr, size); +} + +static const void *find_first_bad_addr(const void *addr, size_t size) +{ + u8 shadow_val = *(u8 *)asan_mem_to_shadow(addr); + const void *first_bad_addr = addr; + + while (!shadow_val && first_bad_addr < addr + size) { + first_bad_addr += ASAN_SHADOW_SCALE_SIZE; + shadow_val = *(u8 *)asan_mem_to_shadow(first_bad_addr); + } + return first_bad_addr; +} + +static const char *get_shadow_bug_type(const void *addr, size_t size) +{ + const char *bug_type = "unknown-crash"; + u8 *shadow_addr; + const void *first_bad_addr; + + if (addr < asan_shadow_to_mem((void *) &_asan_shadow)) + return bug_type; + + first_bad_addr = find_first_bad_addr(addr, size); + + shadow_addr = (u8 *)asan_mem_to_shadow(first_bad_addr); + + if (*shadow_addr > 0 && *shadow_addr <= ASAN_SHADOW_SCALE_SIZE - 1) + shadow_addr++; + + switch (*shadow_addr) { + case 0 ... ASAN_SHADOW_SCALE_SIZE - 1: + bug_type = "out-of-bounds"; + break; + case ASAN_GLOBAL_REDZONE: + bug_type = "global-out-of-bounds"; + break; + case ASAN_STACK_LEFT: + case ASAN_STACK_MID: + case ASAN_STACK_RIGHT: + case ASAN_STACK_PARTIAL: + bug_type = "stack-out-of-bounds"; + break; + case ASAN_USE_AFTER_SCOPE: + bug_type = "use-after-scope"; + break; + default: + bug_type = "unknown-crash"; + } + + return bug_type; +} + +void asan_report(unsigned long addr, size_t size, bool is_write, + unsigned long ip) +{ + const char *bug_type = get_shadow_bug_type((void *) addr, size); + printk(BIOS_ERR, "\n"); + printk(BIOS_ERR, "ASan: %s in %p\n", bug_type, (void *) ip); + printk(BIOS_ERR, "%s of %zu byte%s at addr %p\n", + is_write ? "Write" : "Read", size, (size > 1 ? "s" : ""), + (void *) addr); + printk(BIOS_ERR, "\n"); +} + +static __always_inline void check_memory_region_inline(unsigned long addr, + size_t size, bool write, + unsigned long ret_ip) +{ +#if ENV_ROMSTAGE + if (((uintptr_t)addr < (uintptr_t)&_car_region_start) || + ((uintptr_t)addr > (uintptr_t)&_ebss)) + return; +#elif ENV_RAMSTAGE + if (((uintptr_t)addr < (uintptr_t)&_data) || + ((uintptr_t)addr > (uintptr_t)&_eheap)) + return; +#endif + if (unlikely(size == 0)) + return; + + if (unlikely((void *)addr < + asan_shadow_to_mem((void *) &_asan_shadow))) { + asan_report(addr, size, write, ret_ip); + return; + } + + if (likely(!memory_is_poisoned(addr, size))) + return; + + asan_report(addr, size, write, ret_ip); +} + +void check_memory_region(unsigned long addr, size_t size, bool write, + unsigned long ret_ip) +{ + check_memory_region_inline(addr, size, write, ret_ip); +} + +uintptr_t __asan_shadow_offset(uintptr_t addr) +{ +#if ENV_ROMSTAGE + return (uintptr_t)&_asan_shadow - (((uintptr_t)&_car_region_start) >> + ASAN_SHADOW_SCALE_SHIFT); +#elif ENV_RAMSTAGE + return (uintptr_t)&_asan_shadow - (((uintptr_t)&_data) >> + ASAN_SHADOW_SCALE_SHIFT); +#endif +} + +static void register_global(struct asan_global *global) +{ + size_t aligned_size = ALIGN_UP(global->size, ASAN_SHADOW_SCALE_SIZE); + + asan_unpoison_shadow(global->beg, global->size); + + asan_poison_shadow(global->beg + aligned_size, + global->size_with_redzone - aligned_size, + ASAN_GLOBAL_REDZONE); +} + +void __asan_register_globals(struct asan_global *globals, size_t size) +{ + int i; + + for (i = 0; i < size; i++) + register_global(&globals[i]); +} + +void __asan_unregister_globals(struct asan_global *globals, size_t size) +{ +} + +/* + * GCC adds constructors invoking __asan_register_globals() and passes + * information about global variable (address, size, size with redzone ...) + * to it so we could poison variable's redzone. + * This function calls those constructors. + */ +#if ENV_RAMSTAGE +static void asan_ctors(void) +{ + extern long __CTOR_LIST__; + typedef void (*func_ptr)(void); + func_ptr *ctor = (func_ptr *) &__CTOR_LIST__; + if (ctor == NULL) + return; + + for (; *ctor != (func_ptr) 0; ctor++) + (*ctor)(); +} +#endif + +void asan_init(void) +{ +#if ENV_ROMSTAGE + size_t size = (size_t)&_ebss - (size_t)&_car_region_start; + asan_unpoison_shadow((void *)&_car_region_start, size); +#elif ENV_RAMSTAGE + size_t size = (size_t)&_eheap - (size_t)&_data; + asan_unpoison_shadow((void *)&_data, size); + asan_ctors(); +#endif +} + +void __asan_poison_stack_memory(const void *addr, size_t size) +{ + asan_poison_shadow(addr, ALIGN_UP(size, ASAN_SHADOW_SCALE_SIZE), + ASAN_USE_AFTER_SCOPE); +} + +void __asan_unpoison_stack_memory(const void *addr, size_t size) +{ + asan_unpoison_shadow(addr, size); +} + +#define DEFINE_ASAN_LOAD_STORE(size) \ + void __asan_load##size(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, false, _RET_IP_);\ + } \ + void __asan_load##size##_noabort(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, false, _RET_IP_);\ + } \ + void __asan_store##size(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, true, _RET_IP_); \ + } \ + void __asan_store##size##_noabort(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, true, _RET_IP_); \ + } + +DEFINE_ASAN_LOAD_STORE(1); +DEFINE_ASAN_LOAD_STORE(2); +DEFINE_ASAN_LOAD_STORE(4); +DEFINE_ASAN_LOAD_STORE(8); +DEFINE_ASAN_LOAD_STORE(16); + +void __asan_loadN(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, false, _RET_IP_); +} + +void __asan_storeN(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, true, _RET_IP_); +} + +void __asan_loadN_noabort(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, false, _RET_IP_); +} + +void __asan_storeN_noabort(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, true, _RET_IP_); +} + +void __asan_handle_no_return(void) +{ +} + +#define DEFINE_ASAN_SET_SHADOW(byte) \ + void __asan_set_shadow_##byte(const void *addr, size_t size) \ + { \ + __builtin_memset((void *)addr, 0x##byte, size); \ + } + +DEFINE_ASAN_SET_SHADOW(00); +DEFINE_ASAN_SET_SHADOW(f1); +DEFINE_ASAN_SET_SHADOW(f2); +DEFINE_ASAN_SET_SHADOW(f3); +DEFINE_ASAN_SET_SHADOW(f5); +DEFINE_ASAN_SET_SHADOW(f8); + +#define DEFINE_ASAN_REPORT_LOAD(size) \ +void __asan_report_load##size##_noabort(unsigned long addr) \ +{ \ + asan_report(addr, size, false, _RET_IP_); \ +} + +#define DEFINE_ASAN_REPORT_STORE(size) \ +void __asan_report_store##size##_noabort(unsigned long addr) \ +{ \ + asan_report(addr, size, true, _RET_IP_); \ +} + +DEFINE_ASAN_REPORT_LOAD(1); +DEFINE_ASAN_REPORT_LOAD(2); +DEFINE_ASAN_REPORT_LOAD(4); +DEFINE_ASAN_REPORT_LOAD(8); +DEFINE_ASAN_REPORT_LOAD(16); +DEFINE_ASAN_REPORT_STORE(1); +DEFINE_ASAN_REPORT_STORE(2); +DEFINE_ASAN_REPORT_STORE(4); +DEFINE_ASAN_REPORT_STORE(8); +DEFINE_ASAN_REPORT_STORE(16); + +void __asan_report_load_n_noabort(unsigned long addr, size_t size) +{ + asan_report(addr, size, false, _RET_IP_); +} + +void __asan_report_store_n_noabort(unsigned long addr, size_t size) +{ + asan_report(addr, size, true, _RET_IP_); +} diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 1c433d008e..1509c8cb59 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -10,8 +10,6 @@ #include #include -DECLARE_OPTIONAL_REGION(timestamp); - __weak void bootblock_mainboard_early_init(void) { /* no-op */ } __weak void bootblock_soc_early_init(void) { /* do nothing */ } __weak void bootblock_soc_init(void) { /* do nothing */ } @@ -25,7 +23,7 @@ __weak void bootblock_mainboard_init(void) { /* do nothing */ } * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ -static void bootblock_main_with_timestamp(uint64_t base_timestamp, +void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index fa1f8bc6fd..1fe23c2828 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -231,15 +231,15 @@ void *bootmem_allocate_buffer(size_t size) size = ALIGN(size, 4096); region = NULL; memranges_each_entry(r, &bootmem) { + if (range_entry_base(r) >= max_addr) + break; + if (range_entry_size(r) < size) continue; if (range_entry_tag(r) != BM_MEM_RAM) continue; - if (range_entry_base(r) >= max_addr) - continue; - end = range_entry_end(r); if (end > max_addr) end = max_addr; diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 050d713154..0eb94dc812 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -16,8 +16,7 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution, fb_resolution); struct jpeg_decdata *decdata; - unsigned char *jpeg = - cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); + unsigned char *jpeg = cbfs_map("bootsplash.jpg", NULL); if (!jpeg) { printk(BIOS_ERR, "Could not find bootsplash.jpg\n"); return; @@ -31,6 +30,7 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, decdata = malloc(sizeof(*decdata)); int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, decdata); + cbfs_unmap(jpeg); if (ret != 0) { printk(BIOS_ERR, "Bootsplash could not be decoded. jpeg_decode returned %d.\n", ret); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index cb66f81d99..60dc15a7cb 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,11 +3,14 @@ #include #include #include +#include +#include #include +#include #include -#include #include #include +#include #include #include #include @@ -15,62 +18,112 @@ #include #include -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif +cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev) +{ + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd) + return CB_ERR; + + size_t data_offset; + cb_err_t err = CB_CBFS_CACHE_FULL; + if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM && cbd->mcache_size) + err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, + name, mdata, &data_offset); + if (err == CB_CBFS_CACHE_FULL) { + struct vb2_hash *metadata_hash = NULL; + if (CONFIG(TOCTOU_SAFETY)) { + if (ENV_SMM) /* Cannot provide TOCTOU safety for SMM */ + dead_code(); + if (!cbd->mcache_size) + die("Cannot access CBFS TOCTOU-safely in " ENV_STRING " before CBMEM init!\n"); + /* We can only reach this for the RW CBFS -- an mcache + overflow in the RO CBFS would have been caught when + building the mcache in cbfs_get_boot_device(). + (Note that TOCTOU_SAFETY implies !NO_CBFS_MCACHE.) */ + assert(cbd == vboot_get_cbfs_boot_device()); + /* TODO: set metadata_hash to RW metadata hash here. */ + } + err = cbfs_lookup(&cbd->rdev, name, mdata, &data_offset, + metadata_hash); + } + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && + err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + return cbfs_boot_lookup(name, true, mdata, rdev); + } + if (err) { + if (err == CB_CBFS_NOT_FOUND) + printk(BIOS_WARNING, "CBFS: '%s' not found.\n", name); + else if (err == CB_CBFS_HASH_MISMATCH) + printk(BIOS_ERR, "CBFS ERROR: metadata hash mismatch!\n"); + else + printk(BIOS_ERR, + "CBFS ERROR: error %d when looking up '%s'\n", + err, name); + return err; + } + + if (rdev_chain(rdev, &cbd->rdev, data_offset, be32toh(mdata->h.len))) + return CB_ERR; + + if (tspi_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) + return CB_ERR; + + return CB_SUCCESS; +} int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - struct region_device rdev; - - if (cbfs_boot_region_device(&rdev)) + if (cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) return -1; - int ret = cbfs_locate(fh, &rdev, name, type); + size_t msize = be32toh(fh->mdata.h.offset); + if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev, + (uintptr_t)&fh->mdata, msize)) + return -1; - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { - - /* - * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the - * active RW region, the RO (COREBOOT) region will be used to locate the file. - * - * This functionality makes it possible to avoid duplicate files in the RO - * and RW partitions while maintaining updateability. - * - * Files can be added to the RO_REGION_ONLY config option to use this feature. - */ - printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) - ERROR("RO region not found\n"); - else - ret = cbfs_locate(fh, &rdev, name, type); + if (type) { + if (!*type) + *type = be32toh(fh->mdata.h.type); + else if (*type != be32toh(fh->mdata.h.type)) + return -1; } - if (!ret) - if (tspi_measure_cbfs_hook(fh, name)) - return -1; - - return ret; + return 0; } -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) +static void *_cbfs_map(const char *name, size_t *size_out, bool force_ro) { - struct cbfsf fh; - size_t fsize; + struct region_device rdev; + union cbfs_mdata mdata; - if (cbfs_boot_locate(&fh, name, &type)) + if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return NULL; - fsize = region_device_sz(&fh.data); + if (size_out != NULL) + *size_out = region_device_sz(&rdev); - if (size != NULL) - *size = fsize; + return rdev_mmap_full(&rdev); +} - return rdev_mmap(&fh.data, 0, fsize); +void *cbfs_map(const char *name, size_t *size_out) +{ + return _cbfs_map(name, size_out, false); +} + +void *cbfs_ro_map(const char *name, size_t *size_out) +{ + return _cbfs_map(name, size_out, true); +} + +int cbfs_unmap(void *mapping) +{ + /* This works because munmap() only works on the root rdev and never + cares about which chained subregion something was mapped from. */ + return rdev_munmap(boot_device_ro(), mapping); } int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -84,9 +137,13 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, return -1; } + uint32_t dummy_type = 0; + if (!type) + type = &dummy_type; + ret = cbfs_locate(fh, &rdev, name, type); if (!ret) - if (tspi_measure_cbfs_hook(fh, name)) + if (tspi_measure_cbfs_hook(&rdev, name, *type)) return -1; return ret; } @@ -245,7 +302,7 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) tohex16(vendor, name + 3); tohex16(device, name + 8); - return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); + return cbfs_map(name, NULL); } void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev) @@ -256,27 +313,39 @@ void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t tohex16(device, name + 8); tohex8(rev, name + 13); - return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); + return cbfs_map(name, NULL); } -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + struct region_device rdev; + union cbfs_mdata mdata; - if (cbfs_boot_locate(&fh, name, &type) < 0) + if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + const struct cbfs_file_attr_compression *attr = cbfs_find_attr(&mdata, + CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*attr)); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&rdev, 0, region_device_sz(&rdev), + buf, buf_size, compression); +} + +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); } int cbfs_prog_stage_load(struct prog *pstage) @@ -296,10 +365,16 @@ int cbfs_prog_stage_load(struct prog *pstage) foffset = 0; foffset += sizeof(stage); + /* cbfs_stage fields are written in little endian despite the other + cbfs data types being encoded in big endian. */ + stage.compression = read_le32(&stage.compression); + stage.entry = read_le64(&stage.entry); + stage.load = read_le64(&stage.load); + stage.len = read_le32(&stage.len); + stage.memlen = read_le32(&stage.memlen); + assert(fsize == stage.len); - /* Note: cbfs_stage fields are currently in the endianness of the - * running processor. */ load = (void *)(uintptr_t)stage.load; entry = (void *)(uintptr_t)stage.entry; @@ -330,9 +405,115 @@ out: return 0; } -int cbfs_boot_region_device(struct region_device *rdev) +void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id) { - boot_device_init(); - return vboot_locate_cbfs(rdev) && - fmap_locate_area_as_rdev("COREBOOT", rdev); + if (CONFIG(NO_CBFS_MCACHE) || ENV_SMM) + return; + + if (cbd->mcache_size) + return; + + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(id))) { + cbd->mcache = cbmem_entry_start(entry); + cbd->mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + u8 *boundary = _ecbfs_mcache - REGION_SIZE(cbfs_mcache) * + CONFIG_CBFS_MCACHE_RW_PERCENTAGE / 100; + boundary = (u8 *)ALIGN_DOWN((uintptr_t)boundary, + CBFS_MCACHE_ALIGNMENT); + if (id == CBMEM_ID_CBFS_RO_MCACHE) { + cbd->mcache = _cbfs_mcache; + cbd->mcache_size = boundary - _cbfs_mcache; + } else if (id == CBMEM_ID_CBFS_RW_MCACHE) { + cbd->mcache = boundary; + cbd->mcache_size = _ecbfs_mcache - boundary; + } + } } + +cb_err_t cbfs_init_boot_device(const struct cbfs_boot_device *cbd, + struct vb2_hash *metadata_hash) +{ + /* If we have an mcache, mcache_build() will also check mdata hash. */ + if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM && cbd->mcache_size > 0) + return cbfs_mcache_build(&cbd->rdev, cbd->mcache, + cbd->mcache_size, metadata_hash); + + /* No mcache and no verification means we have nothing special to do. */ + if (!CONFIG(CBFS_VERIFICATION) || !metadata_hash) + return CB_SUCCESS; + + /* Verification only: use cbfs_walk() without a walker() function to + just run through the CBFS once, will return NOT_FOUND by default. */ + cb_err_t err = cbfs_walk(&cbd->rdev, NULL, NULL, metadata_hash, 0); + if (err == CB_CBFS_NOT_FOUND) + err = CB_SUCCESS; + return err; +} + +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) +{ + static struct cbfs_boot_device ro; + + /* Ensure we always init RO mcache, even if first file is from RW. + Otherwise it may not be available when needed in later stages. */ + if (ENV_INITIAL_STAGE && !force_ro && !region_device_sz(&ro.rdev)) + cbfs_get_boot_device(true); + + if (!force_ro) { + const struct cbfs_boot_device *rw = vboot_get_cbfs_boot_device(); + /* This will return NULL if vboot isn't enabled, didn't run yet + or decided to boot into recovery mode. */ + if (rw) + return rw; + } + + /* In rare cases post-RAM stages may run this before cbmem_initialize(), + so we can't lock in the result of find_mcache() on the first try and + should keep trying every time until an mcache is found. */ + cbfs_boot_device_find_mcache(&ro, CBMEM_ID_CBFS_RO_MCACHE); + + if (region_device_sz(&ro.rdev)) + return &ro; + + if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) + die("Cannot locate primary CBFS"); + + if (ENV_INITIAL_STAGE) { + cb_err_t err = cbfs_init_boot_device(&ro, metadata_hash_get()); + if (err == CB_CBFS_HASH_MISMATCH) + die("RO CBFS metadata hash verification failure"); + else if (CONFIG(TOCTOU_SAFETY) && err == CB_CBFS_CACHE_FULL) + die("RO mcache overflow breaks TOCTOU safety!\n"); + else if (err && err != CB_CBFS_CACHE_FULL) + die("RO CBFS initialization error: %d", err); + } + + return &ro; +} + +#if !CONFIG(NO_CBFS_MCACHE) +static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) +{ + if (!cbd) + return; + + size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); + void *cbmem_mcache = cbmem_add(cbmem_id, real_size); + if (!cbmem_mcache) { + printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", + cbmem_id, real_size); + return; + } + memcpy(cbmem_mcache, cbd->mcache, real_size); +} + +static void cbfs_mcache_migrate(int unused) +{ + mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE); + mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE); +} +ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate) +#endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9148405879..e00c2a4a52 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -20,16 +22,11 @@ #include #include #include +#include + #if CONFIG(USE_OPTION_TABLE) #include #endif -#if CONFIG(CHROMEOS) -#if CONFIG(HAVE_ACPI_TABLES) -#include -#endif -#include -#include -#endif #if CONFIG(PLATFORM_USES_FSP2_0) #include #else @@ -155,7 +152,6 @@ void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, gpios->size += table_size; } -#if CONFIG(CHROMEOS) static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; @@ -194,6 +190,7 @@ static void lb_gpios(struct lb_header *header) } } +#if CONFIG(CHROMEOS) static void lb_vbnv(struct lb_header *header) { #if CONFIG(PC80_SYSTEM) @@ -211,33 +208,14 @@ static void lb_vbnv(struct lb_header *header) __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } - -static void lb_board_id(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t bid = board_id(); - - if (bid == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_BOARD_ID; - rec->size = sizeof(*rec); - rec->id_code = bid; - - printk(BIOS_INFO, "Board ID: %d\n", bid); -} +__weak uint64_t fw_config_get(void) { return UNDEFINED_FW_CONFIG; } static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; const struct region_device *boot_dev; - struct region_device cbfs_dev; - - boot_device_init(); - - if (cbfs_boot_region_device(&cbfs_dev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return; boot_dev = boot_device_ro(); @@ -248,47 +226,13 @@ static void lb_boot_media_params(struct lb_header *header) bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS; bmp->size = sizeof(*bmp); - bmp->cbfs_offset = region_device_offset(&cbfs_dev); - bmp->cbfs_size = region_device_sz(&cbfs_dev); + bmp->cbfs_offset = region_device_offset(&cbd->rdev); + bmp->cbfs_size = region_device_sz(&cbd->rdev); bmp->boot_media_size = region_device_sz(boot_dev); bmp->fmap_offset = get_fmap_flash_offset(); } -static void lb_ram_code(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t code = ram_code(); - - if (code == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_RAM_CODE; - rec->size = sizeof(*rec); - rec->id_code = code; - - printk(BIOS_INFO, "RAM code: %d\n", code); -} - -static void lb_sku_id(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t sid = sku_id(); - - if (sid == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_SKU_ID; - rec->size = sizeof(*rec); - rec->id_code = sid; - - printk(BIOS_INFO, "SKU ID: %d\n", sid); -} - static void lb_mmc_info(struct lb_header *header) { struct lb_mmc_info *rec; @@ -368,6 +312,24 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) return mainboard; } +static struct lb_board_config *lb_board_config(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_board_config *config; + rec = lb_new_record(header); + config = (struct lb_board_config *)rec; + + config->tag = LB_TAG_BOARD_CONFIG; + config->size = sizeof(*config); + + config->board_id = board_id(); + config->ram_code = ram_code(); + config->sku_id = sku_id(); + config->fw_config = pack_lb64(fw_config_get()); + + return config; +} + #if CONFIG(USE_OPTION_TABLE) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { @@ -487,8 +449,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) #if CONFIG(USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + cbfs_map("cmos_layout.bin", NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a @@ -526,19 +487,15 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Record our framebuffer */ lb_framebuffer(head); -#if CONFIG(CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ - lb_gpios(head); + if (CONFIG(CHROMEOS)) + lb_gpios(head); +#if CONFIG(CHROMEOS) /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif - /* Add strapping IDs if available */ - lb_board_id(head); - lb_ram_code(head); - lb_sku_id(head); - /* Pass mmc early init status */ lb_mmc_info(head); @@ -548,15 +505,24 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) add_cbmem_pointers(head); + /* SMMSTORE v2 */ + if (CONFIG(SMMSTORE_V2)) + lb_smmstorev2(head); + /* Add board-specific table entries, if any. */ lb_board(head); -#if CONFIG(CHROMEOS_RAMOOPS) - lb_ramoops(head); -#endif + if (CONFIG(CHROMEOS_RAMOOPS)) + lb_ramoops(head); lb_boot_media_params(head); + /* Board configuration information (including straps) */ + lb_board_config(head); + + if (CONFIG(TPM_PPI)) + lb_tpm_ppi(head); + /* Add architecture records. */ lb_arch_add_records(head); diff --git a/src/lib/edid.c b/src/lib/edid.c index f20d23959e..cd7a47ac78 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -261,6 +261,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, extract_string(x + 5, &c->has_valid_string_termination, EDID_ASCII_STRING_LENGTH)); + c->has_name_descriptor = 1; return 1; case 0xFD: { diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 422feaf9e7..712cd0f525 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -3,75 +3,171 @@ #include #include #include +#include +#include +#include +#include +#include -static int fb_valid; -static struct lb_framebuffer edid_fb; +struct fb_info { + struct list_node node; + struct lb_framebuffer fb; +}; +static struct list_node list; /* - * Take an edid, and create a framebuffer. Set fb_valid to 1. + * Allocate a new framebuffer info struct on heap. + * Returns NULL on error. */ -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +static struct fb_info *fb_new_framebuffer_info(void) { - edid_fb.physical_address = fb_addr; - edid_fb.x_resolution = edid->x_resolution; - edid_fb.y_resolution = edid->y_resolution; - edid_fb.bytes_per_line = edid->bytes_per_line; - /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention - * nowadays seems to be to round it up to the nearest reasonable - * boundary, because otherwise the byte-packing is hideous. - * So, for example, in RGB with no alpha, the bytes are still - * packed into 32-bit words, the so-called 32bpp-no-alpha mode. - * Or, in 5:6:5 mode, the bytes are also packed into 32-bit words, - * and in 4:4:4 mode, they are packed into 16-bit words. - * Good call on the hardware guys part. - * It's not clear we're covering all cases here, but - * I'm not sure with grahpics you ever can. - */ - edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel; - edid_fb.reserved_mask_pos = 0; - edid_fb.reserved_mask_size = 0; - switch (edid->framebuffer_bits_per_pixel) { - case 32: - case 24: - /* packed into 4-byte words */ - edid_fb.reserved_mask_pos = 24; - edid_fb.reserved_mask_size = 8; - edid_fb.red_mask_pos = 16; - edid_fb.red_mask_size = 8; - edid_fb.green_mask_pos = 8; - edid_fb.green_mask_size = 8; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - edid_fb.red_mask_pos = 11; - edid_fb.red_mask_size = 5; - edid_fb.green_mask_pos = 5; - edid_fb.green_mask_size = 6; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - edid->framebuffer_bits_per_pixel); - return; - } + struct fb_info *ret; + ret = malloc(sizeof(struct fb_info)); + if (ret) + memset(ret, 0, sizeof(struct fb_info)); - fb_valid = 1; + return ret; } -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation) +/* + * Fills a provided framebuffer info struct and adds it to the internal list if it's + * valid. Returns NULL on error. + */ +struct fb_info * +fb_add_framebuffer_info_ex(const struct lb_framebuffer *fb) { - edid_fb.orientation = orientation; + struct fb_info *info; + uint8_t bpp_mask; + + /* Validate input */ + if (!fb || !fb->x_resolution || !fb->y_resolution || !fb->bytes_per_line || + !fb->bits_per_pixel) { + printk(BIOS_ERR, "%s: Invalid framebuffer data provided\n", __func__); + return NULL; + } + + bpp_mask = fb->blue_mask_size + fb->green_mask_size + fb->red_mask_size + + fb->reserved_mask_size; + if (fb->bits_per_pixel != bpp_mask) { + printk(BIOS_ERR, "%s: BPP=%d and channel bit mask=%d doesn't match." + " This is a driver bug.\n", __func__, fb->bits_per_pixel, bpp_mask); + return NULL; + } + + info = fb_new_framebuffer_info(); + if (!info) + return NULL; + + printk(BIOS_INFO, "framebuffer_info: bytes_per_line: %d, bits_per_pixel: %d\n " + " x_res x y_res: %d x %d, size: %d at 0x%llx\n", + fb->bytes_per_line, fb->bits_per_pixel, fb->x_resolution, + fb->y_resolution, (fb->bytes_per_line * fb->y_resolution), + fb->physical_address); + + /* Update */ + info->fb = *fb; + + list_insert_after(&info->node, &list); + + return info; +} + +/* + * Allocates a new framebuffer info struct and fills it for 32/24/16bpp framebuffers. + * Intended for drivers that only support reporting the current information or have a single + * modeset invocation. + * + * Complex drivers should use fb_add_framebuffer_info_ex() instead. + */ +struct fb_info * +fb_add_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel) +{ + struct fb_info *info = NULL; + + switch (bits_per_pixel) { + case 32: + case 24: { + /* FIXME: 24 BPP might be RGB8 or XRGB8 */ + /* packed into 4-byte words */ + + const struct lb_framebuffer fb = { + .physical_address = fb_addr, + .x_resolution = x_resolution, + .y_resolution = y_resolution, + .bytes_per_line = bytes_per_line, + .bits_per_pixel = bits_per_pixel, + .red_mask_pos = 16, + .red_mask_size = 8, + .green_mask_pos = 8, + .green_mask_size = 8, + .blue_mask_pos = 0, + .blue_mask_size = 8, + .reserved_mask_pos = 24, + .reserved_mask_size = 8, + .orientation = LB_FB_ORIENTATION_NORMAL, + }; + + info = fb_add_framebuffer_info_ex(&fb); + break; + } + case 16: { + /* packed into 2-byte words */ + const struct lb_framebuffer fb = { + .physical_address = fb_addr, + .x_resolution = x_resolution, + .y_resolution = y_resolution, + .bytes_per_line = bytes_per_line, + .bits_per_pixel = 16, + .red_mask_pos = 11, + .red_mask_size = 5, + .green_mask_pos = 5, + .green_mask_size = 6, + .blue_mask_pos = 0, + .blue_mask_size = 5, + .reserved_mask_pos = 0, + .reserved_mask_size = 0, + .orientation = LB_FB_ORIENTATION_NORMAL, + }; + info = fb_add_framebuffer_info_ex(&fb); + break; + } + default: + printk(BIOS_ERR, "%s: unsupported BPP %d\n", __func__, bits_per_pixel); + } + if (!info) + printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__); + + return info; +} + +void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation) +{ + if (!info) + return; + + info->fb.orientation = orientation; +} + +/* + * Take an edid, and create a framebuffer. + */ +struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr) +{ + return fb_add_framebuffer_info(fb_addr, edid->x_resolution, edid->y_resolution, + edid->bytes_per_line, edid->framebuffer_bits_per_pixel); } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { - if (!fb_valid) - return -1; + struct fb_info *i; - *framebuffer = edid_fb; - - return 0; + list_for_each(i, list, node) { + //TODO: Add support for advertising all framebuffers in this list + *framebuffer = i->fb; + return 0; + } + return -1; } diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2fb1e9ee90..d498597d13 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -111,7 +111,7 @@ void stage_cache_get_raw(int stage_id, void **base, size_t *size) } *base = imd_entry_at(imd, e); - *size = imd_entry_size(imd, e); + *size = imd_entry_size(e); } void stage_cache_load_stage(int stage_id, struct prog *stage) @@ -141,7 +141,7 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) } c = imd_entry_at(imd, e); - size = imd_entry_size(imd, e); + size = imd_entry_size(e); memcpy((void *)(uintptr_t)meta->load_addr, c, size); diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 671a962c25..418e715b3e 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -27,9 +28,20 @@ uint64_t get_fmap_flash_offset(void) return FMAP_OFFSET; } -static int check_signature(const struct fmap *fmap) +static int verify_fmap(const struct fmap *fmap) { - return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)); + if (memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature))) + return -1; + + static bool done = false; + if (!CONFIG(CBFS_VERIFICATION) || !ENV_INITIAL_STAGE || done) + return 0; /* Only need to check hash in first stage. */ + + if (metadata_hash_verify_fmap(fmap, FMAP_SIZE) != VB2_SUCCESS) + return -1; + + done = true; + return 0; } static void report(const struct fmap *fmap) @@ -46,6 +58,10 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) if (CONFIG(NO_FMAP_CACHE)) return; + /* No need to use FMAP cache in SMM */ + if (ENV_SMM) + return; + if (!ENV_ROMSTAGE_OR_BEFORE) { /* We get here if ramstage makes an FMAP access before calling cbmem_initialize(). We should avoid letting it come to that, @@ -56,14 +72,15 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) } struct fmap *fmap = (struct fmap *)_fmap_cache; - if (!ENV_BOOTBLOCK) { - /* NOTE: This assumes that for all platforms running this code, - the bootblock is the first stage and the bootblock will make + if (!(ENV_INITIAL_STAGE)) { + /* NOTE: This assumes that the first stage will make at least one FMAP access (usually from finding CBFS). */ - if (!check_signature(fmap)) + if (!verify_fmap(fmap)) goto register_cache; printk(BIOS_ERR, "ERROR: FMAP cache corrupted?!\n"); + if (CONFIG(TOCTOU_SAFETY)) + die("TOCTOU safety relies on FMAP cache"); } /* In case we fail below, make sure the cache is invalid. */ @@ -77,7 +94,7 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) /* memlayout statically guarantees that the FMAP_CACHE is big enough. */ if (rdev_readat(boot_rdev, fmap, FMAP_OFFSET, FMAP_SIZE) != FMAP_SIZE) return; - if (check_signature(fmap)) + if (verify_fmap(fmap)) return; report(fmap); @@ -108,8 +125,9 @@ static int find_fmap_directory(struct region_device *fmrd) if (fmap == NULL) return -1; - if (check_signature(fmap)) { - printk(BIOS_DEBUG, "No FMAP found at %zx offset.\n", offset); + if (verify_fmap(fmap)) { + printk(BIOS_ERR, "FMAP missing or corrupted at offset 0x%zx!\n", + offset); rdev_munmap(boot, fmap); return -1; } @@ -146,6 +164,9 @@ int fmap_locate_area(const char *name, struct region *ar) struct region_device fmrd; size_t offset; + if (name == NULL || ar == NULL) + return -1; + if (find_fmap_directory(&fmrd)) return -1; @@ -188,6 +209,9 @@ int fmap_find_region_name(const struct region * const ar, struct region_device fmrd; size_t offset; + if (name == NULL || ar == NULL) + return -1; + if (find_fmap_directory(&fmrd)) return -1; diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index e97cfdc72a..2c4c6b290c 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -1,22 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include #include +#include +#include #include #include -/** - * fw_config_get() - Provide firmware configuration value. - * - * Return 32bit firmware configuration value determined for the system. - */ -static uint32_t fw_config_get(void) +uint64_t fw_config_get(void) { - static uint32_t fw_config_value; + static uint64_t fw_config_value; static bool fw_config_value_initialized; /* Nothing to prepare if setup is already done. */ @@ -26,14 +24,13 @@ static uint32_t fw_config_get(void) /* Look in CBFS to allow override of value. */ if (CONFIG(FW_CONFIG_SOURCE_CBFS)) { - if (cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/fw_config", - &fw_config_value, sizeof(fw_config_value), - CBFS_TYPE_RAW) != sizeof(fw_config_value)) { + if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value, + sizeof(fw_config_value)) != sizeof(fw_config_value)) { printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", __func__); - fw_config_value = 0; + fw_config_value = UNDEFINED_FW_CONFIG; } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n", + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -41,11 +38,13 @@ static uint32_t fw_config_get(void) /* Read the value from EC CBI. */ if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) { - if (google_chromeec_cbi_get_fw_config(&fw_config_value)) + if (google_chromeec_cbi_get_fw_config(&fw_config_value)) { printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); + fw_config_value = UNDEFINED_FW_CONFIG; + } } - printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value); + printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -57,7 +56,8 @@ bool fw_config_probe(const struct fw_config *match) printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name, match->option_name); else - printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n", + printk(BIOS_INFO, "fw_config match found: mask=0x%" PRIx64 " value=0x%" + PRIx64 "\n", match->mask, match->value); return true; } @@ -65,7 +65,46 @@ bool fw_config_probe(const struct fw_config *match) return false; } +bool fw_config_is_provisioned(void) +{ + return fw_config_get() != UNDEFINED_FW_CONFIG; +} + #if ENV_RAMSTAGE + +/* + * The maximum number of fw_config fields is limited by the 64-bit mask that is used to + * represent them. + */ +#define MAX_CACHE_ELEMENTS (8 * sizeof(uint64_t)) + +static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS]; + +static size_t probe_index(uint64_t mask) +{ + assert(mask); + return __ffs64(mask); +} + +const struct fw_config *fw_config_get_found(uint64_t field_mask) +{ + const struct fw_config *config; + config = cached_configs[probe_index(field_mask)]; + if (config && config->mask == field_mask) + return config; + + return NULL; +} + +void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg) +{ + size_t i; + + for (i = 0; i < MAX_CACHE_ELEMENTS; ++i) + if (cached_configs[i]) + cb(cached_configs[i], arg); +} + static void fw_config_init(void *unused) { struct device *dev; @@ -80,6 +119,7 @@ static void fw_config_init(void *unused) for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { if (fw_config_probe(probe)) { match = true; + cached_configs[probe_index(probe->mask)] = probe; break; } } @@ -90,5 +130,5 @@ static void fw_config_init(void *unused) } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 101aec9b7f..14f3e3ec3b 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -82,7 +82,7 @@ static int fseek(FILE *stream, long offset, int whence) static long ftell(FILE *stream) { /* ftell should currently not be called */ - gcc_assert(0); + BUG(); #if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "ftell %s\n", stream->filename); #endif diff --git a/src/lib/gnat/i-c.ads b/src/lib/gnat/i-c.ads index 1403fcec80..7e90a60e65 100644 --- a/src/lib/gnat/i-c.ads +++ b/src/lib/gnat/i-c.ads @@ -59,6 +59,9 @@ package Interfaces.C is type size_t is mod 2 ** System.Parameters.ptr_bits; + -- For convenience, also provide an uintptr_t type + type uintptr_t is mod 2 ** System.Parameters.ptr_bits; + ---------------------------- -- Characters and Strings -- ---------------------------- diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 3f3ae60d91..801a3b3b9c 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -114,6 +114,12 @@ uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first) printk(BIOS_DEBUG, "%c ", tristate_char[temp]); result = (result * 3) + temp; + /* Disable pull to avoid wasting power. For HiZ we leave the + pull-down enabled, since letting them float freely back and + forth may waste power in the SoC's GPIO input logic. */ + if (temp != Z) + gpio_input(gpio[index]); + /* * For binary_first we keep track of the normal ternary result * and whether we found any pin that was a Z. We also determine @@ -159,10 +165,6 @@ uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first) printk(BIOS_DEBUG, "= %d (%s base3 number system)\n", result, binary_first ? "binary_first" : "standard"); - /* Disable pull up / pull down to conserve power */ - for (index = 0; index < num_gpio; ++index) - gpio_input(gpio[index]); - return result; } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 4276027a9f..d040a0ef93 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -169,9 +170,9 @@ static boot_state_t bs_os_resume(void *wake_vector) if (CONFIG(HAVE_ACPI_RESUME)) { arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); + /* We will not come back. */ } - - return BS_WRITE_TABLES; + die("Failed OS resume\n"); } static boot_state_t bs_write_tables(void *arg) @@ -444,9 +445,13 @@ void main(void) post_code(POST_ENTRY_RAMSTAGE); /* Handoff sleep type from romstage. */ - acpi_is_wakeup(); + acpi_is_wakeup_s3(); threads_initialize(); + /* Initialise GNVS early. */ + if (CONFIG(HAVE_ACPI_TABLES)) + gnvs_get_or_create(); + /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); diff --git a/src/lib/imd.c b/src/lib/imd.c index e19c03d0b7..ac19d76f52 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -7,41 +7,11 @@ #include #include #include +#include + /* For more details on implementation and usage please see the imd.h header. */ -static const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; -static const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; -static const uint32_t SMALL_REGION_ID = CBMEM_ID_IMD_SMALL; -static const size_t LIMIT_ALIGN = 4096; - -/* In-memory data structures. */ -struct imd_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __packed; - -struct imd_entry { - uint32_t magic; - /* start is located relative to imd_root */ - int32_t start_offset; - uint32_t size; - uint32_t id; -} __packed; - -struct imd_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - /* Used for fixing the size of an imd. Relative to the root. */ - int32_t max_offset; - struct imd_entry entries[0]; -} __packed; - -#define IMD_FLAG_LOCKED 1 - static void *relative_pointer(void *base, ssize_t offset) { intptr_t b = (intptr_t)base; @@ -145,10 +115,11 @@ static int imdr_create_empty(struct imdr *imdr, size_t root_size, /* * root_size needs to be large enough to accommodate root pointer and - * root book keeping structure. The caller needs to ensure there's - * enough room for tracking individual allocations. + * root book keeping structure. Furthermore, there needs to be a space + * for at least one entry covering root region. The caller needs to + * ensure there's enough room for tracking individual allocations. */ - if (root_size < (sizeof(*rp) + sizeof(*r))) + if (root_size < (sizeof(*rp) + sizeof(*r) + sizeof(*e))) return -1; /* For simplicity don't allow sizes or alignments to exceed LIMIT_ALIGN. @@ -201,9 +172,8 @@ static int imdr_recover(struct imdr *imdr) r = relative_pointer(rp, rp->root_offset); - /* Confirm the root and root pointer are just under the limit. */ - if (ALIGN_UP((uintptr_t)&r->entries[r->max_entries], LIMIT_ALIGN) != - imdr->limit) + /* Ensure that root is just under the root pointer */ + if ((intptr_t)rp - (intptr_t)&r->entries[r->max_entries] > sizeof(struct imd_entry)) return -1; if (r->num_entries > r->max_entries) @@ -288,8 +258,7 @@ static int imdr_limit_size(struct imdr *imdr, size_t max_size) return 0; } -static size_t imdr_entry_size(const struct imdr *imdr, - const struct imd_entry *e) +static size_t imdr_entry_size(const struct imd_entry *e) { return e->size; } @@ -324,7 +293,7 @@ static struct imd_entry *imd_entry_add_to_root(struct imd_root *r, uint32_t id, last_entry = root_last_entry(r); e_offset = last_entry->start_offset; e_offset -= (ssize_t)used_size; - if (e_offset > last_entry->start_offset) + if (e_offset >= last_entry->start_offset) return NULL; entry = root_last_entry(r) + 1; @@ -409,7 +378,7 @@ void imd_handle_init_partial_recovery(struct imd *imd) return; imd->sm.limit = (uintptr_t)imdr_entry_at(imdr, e); - imd->sm.limit += imdr_entry_size(imdr, e); + imd->sm.limit += imdr_entry_size(e); imdr = &imd->sm; rp = imdr_get_root_pointer(imdr); imdr->r = relative_pointer(rp, rp->root_offset); @@ -467,14 +436,14 @@ int imd_recover(struct imd *imd) if (imdr_recover(imdr) != 0) return -1; - /* Determine if small region is region is present. */ + /* Determine if small region is present. */ e = imdr_entry_find(imdr, SMALL_REGION_ID); if (e == NULL) return 0; small_upper_limit = (uintptr_t)imdr_entry_at(imdr, e); - small_upper_limit += imdr_entry_size(imdr, e); + small_upper_limit += imdr_entry_size(e); imd->sm.limit = small_upper_limit; @@ -592,9 +561,9 @@ const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, return imd_entry_add(imd, id, size); } -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry) +size_t imd_entry_size(const struct imd_entry *entry) { - return imdr_entry_size(NULL, entry); + return imdr_entry_size(entry); } void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) @@ -609,7 +578,7 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) return imdr_entry_at(imdr, entry); } -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +uint32_t imd_entry_id(const struct imd_entry *entry) { return entry->id; } @@ -626,15 +595,16 @@ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) r = imdr_root(imdr); - if (r == NULL) - return -1; - if (root_is_locked(r)) return -1; if (entry != root_last_entry(r)) return -1; + /* Don't remove entry covering root region */ + if (r->num_entries == 1) + return -1; + r->num_entries--; return 0; @@ -671,7 +641,7 @@ static void imdr_print_entries(const struct imdr *imdr, const char *indent, printk(BIOS_DEBUG, "%s", name); printk(BIOS_DEBUG, "%2zu. ", i); printk(BIOS_DEBUG, "%p ", imdr_entry_at(imdr, e)); - printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(imdr, e)); + printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(e)); } } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index cb66c3b219..4b7c4120b0 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -30,6 +30,8 @@ void *cbmem_top(void) dead_code(); } +int cbmem_initialized; + static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; @@ -79,6 +81,8 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) /* Complete migration to CBMEM. */ cbmem_run_init_hooks(no_recovery); + + cbmem_initialized = 1; } int cbmem_initialize(void) @@ -112,6 +116,8 @@ int cbmem_initialize_id_size(u32 id, u64 size) /* Complete migration to CBMEM. */ cbmem_run_init_hooks(recovery); + cbmem_initialized = 1; + /* Recovery successful. */ return 0; } @@ -178,7 +184,7 @@ int cbmem_entry_remove(const struct cbmem_entry *entry) u64 cbmem_entry_size(const struct cbmem_entry *entry) { - return imd_entry_size(&imd, cbmem_to_imd(entry)); + return imd_entry_size(cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) @@ -232,7 +238,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) if (e == NULL) break; - id = imd_entry_id(&imd, e); + id = imd_entry_id(e); /* Don't add these metadata entries. */ if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) continue; @@ -241,7 +247,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) lbe->tag = LB_TAG_CBMEM_ENTRY; lbe->size = sizeof(*lbe); lbe->address = (uintptr_t)imd_entry_at(&imd, e); - lbe->entry_size = imd_entry_size(&imd, e); + lbe->entry_size = imd_entry_size(e); lbe->id = id; } } diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index 887351aa57..571aa7bb8e 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -25,12 +25,12 @@ permissions described in the GCC Runtime Library Exception, version #ifdef __COREBOOT__ #include #include +#include #include #include typedef s32 pid_t; #define gcc_assert(x) ASSERT(x) #define fprintf(file, x...) printk(BIOS_ERR, x) -#define alloca(size) __builtin_alloca(size) #include "gcov-glue.c" /* Define MACROs to be used by coreboot compilation. */ diff --git a/src/lib/metadata_hash.c b/src/lib/metadata_hash.c new file mode 100644 index 0000000000..f296cf58a5 --- /dev/null +++ b/src/lib/metadata_hash.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include + +__attribute__((used, section(".metadata_hash_anchor"))) +static struct metadata_hash_anchor metadata_hash_anchor = { + /* This is the only place in all of coreboot where we actually need to use this. */ + .magic = DO_NOT_USE_METADATA_HASH_ANCHOR_MAGIC_DO_NOT_USE, + .cbfs_hash = { .algo = CONFIG_CBFS_HASH_ALGO } +}; + +struct vb2_hash *metadata_hash_get(void) +{ + return &metadata_hash_anchor.cbfs_hash; +} + +vb2_error_t metadata_hash_verify_fmap(const void *fmap_buffer, size_t fmap_size) +{ + struct vb2_hash hash = { .algo = metadata_hash_anchor.cbfs_hash.algo }; + memcpy(hash.raw, metadata_hash_anchor_fmap_hash(&metadata_hash_anchor), + vb2_digest_size(hash.algo)); + return vb2_hash_verify(fmap_buffer, fmap_size, &hash); +} diff --git a/src/lib/program.ld b/src/lib/program.ld index 88a3126038..3eebd6cc22 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -13,11 +13,12 @@ .text . : { _program = .; _text = .; + *(.init._start); + *(.init); + *(.init.*); *(.text._start); *(.text.stage_entry); -#if !ENV_X86 && (ENV_DECOMPRESSOR || ENV_BOOTBLOCK && !CONFIG(COMPRESS_BOOTBLOCK)) - KEEP(*(.id)); -#endif + KEEP(*(.metadata_hash_anchor)); *(.text); *(.text.*); @@ -51,7 +52,7 @@ _etext = .; } : to_load -#if ENV_RAMSTAGE && CONFIG(COVERAGE) +#if ENV_RAMSTAGE && (CONFIG(COVERAGE) || CONFIG(ASAN_IN_RAMSTAGE)) .ctors . : { . = ALIGN(0x100); __CTOR_LIST__ = .; @@ -126,6 +127,11 @@ } #endif +#if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE) + _shadow_size = (_eheap - _data) >> 3; + REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) +#endif + _eprogram = .; /* Discard the sections we don't need/want */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68cd0e..bad9d9c53e 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } diff --git a/src/lib/region_file.c b/src/lib/region_file.c index ce2ed30f7a..4fe91b62bf 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -365,12 +365,16 @@ static int commit_data_allocation(struct region_file *f, size_t data_blks) return 0; } -static int commit_data(const struct region_file *f, const void *buf, - size_t size) +static int commit_data(const struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries) { size_t offset = block_to_bytes(region_file_data_begin(f)); - if (rdev_writeat(&f->rdev, buf, offset, size) < 0) - return -1; + for (int i = 0; i < num_entries; i++) { + if (rdev_writeat(&f->rdev, entries[i].data, offset, entries[i].size) < 0) + return -1; + offset += entries[i].size; + } return 0; } @@ -399,8 +403,9 @@ static int handle_need_to_empty(struct region_file *f) return 0; } -static int handle_update(struct region_file *f, size_t blocks, const void *buf, - size_t size) +static int handle_update(struct region_file *f, size_t blocks, + const struct update_region_file_entry *entries, + size_t num_entries) { if (!update_can_fit(f, blocks)) { printk(BIOS_INFO, "REGF update can't fit. Will empty.\n"); @@ -413,7 +418,7 @@ static int handle_update(struct region_file *f, size_t blocks, const void *buf, return -1; } - if (commit_data(f, buf, size)) { + if (commit_data(f, entries, num_entries)) { printk(BIOS_ERR, "REGF failed to commit data.\n"); return -1; } @@ -421,11 +426,16 @@ static int handle_update(struct region_file *f, size_t blocks, const void *buf, return 0; } -int region_file_update_data(struct region_file *f, const void *buf, size_t size) +int region_file_update_data_arr(struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries) { int ret; size_t blocks; + size_t size = 0; + for (int i = 0; i < num_entries; i++) + size += entries[i].size; blocks = bytes_to_block(ALIGN_UP(size, REGF_BLOCK_GRANULARITY)); while (1) { @@ -442,7 +452,7 @@ int region_file_update_data(struct region_file *f, const void *buf, size_t size) ret = -1; break; default: - ret = handle_update(f, blocks, buf, size); + ret = handle_update(f, blocks, entries, num_entries); break; } @@ -459,3 +469,12 @@ int region_file_update_data(struct region_file *f, const void *buf, size_t size) return ret; } + +int region_file_update_data(struct region_file *f, const void *buf, size_t size) +{ + struct update_region_file_entry entry = { + .size = size, + .data = buf, + }; + return region_file_update_data_arr(f, &entry, 1); +} diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index b54619d8d8..0a7a822f7b 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -8,7 +8,7 @@ struct romstage_handoff { /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * CONFIG_RELOCATABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage * will be re-loaded from cbfs (which can be slower since it lives * in flash). */ diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 38888961b3..863218c2d3 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -17,6 +18,12 @@ void dump_spd_info(struct spd_block *blk) } } +const char * __weak mainboard_get_dram_part_num(void) +{ + /* Default weak implementation, no need to override part number. */ + return NULL; +} + static bool use_ddr4_params(int dram_type) { switch (dram_type) { @@ -136,33 +143,41 @@ static int spd_get_busw(const uint8_t spd[], int dram_type) return spd_busw[index]; } -static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) +static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, size_t *len) { - switch (dram_type) { + *spd_name = mainboard_get_dram_part_num(); + if (*spd_name != NULL) { + *len = strlen(*spd_name); + return; + } + + switch (type) { case SPD_DRAM_DDR3: - memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); - spd_name[DDR3_SPD_PART_LEN] = 0; + *spd_name = (const char *) &spd[DDR3_SPD_PART_OFF]; + *len = DDR3_SPD_PART_LEN; break; case SPD_DRAM_LPDDR3_INTEL: - memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], - LPDDR3_SPD_PART_LEN); - spd_name[LPDDR3_SPD_PART_LEN] = 0; + *spd_name = (const char *) &spd[LPDDR3_SPD_PART_OFF]; + *len = LPDDR3_SPD_PART_LEN; break; - /* LPDDR3, LPDDR4 and DDR4 have the same part number offset */ + /* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: - memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); - spd_name[DDR4_SPD_PART_LEN] = 0; + case SPD_DRAM_LPDDR4X: + *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; + *len = DDR4_SPD_PART_LEN; break; default: + *len = 0; break; } } void print_spd_info(uint8_t spd[]) { - char spd_name[DDR4_SPD_PART_LEN + 1] = { 0 }; + const char *nameptr = NULL; + size_t len; int type = spd[SPD_DRAM_TYPE]; int banks = spd_get_banks(spd, type); int capmb = spd_get_capmb(spd); @@ -176,9 +191,9 @@ void print_spd_info(uint8_t spd[]) printk(BIOS_INFO, "SPD: module type is %s\n", spd_get_module_type_string(type)); /* Module Part Number */ - spd_get_name(spd, spd_name, type); - - printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name); + spd_get_name(spd, type, &nameptr, &len); + if (nameptr) + printk(BIOS_INFO, "SPD: module part number is %.*s\n", (int) len, nameptr); printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", @@ -212,12 +227,11 @@ int read_ddr3_spd_from_cbfs(u8 *buf, int idx) const int SPD_CRC_HI = 127; const int SPD_CRC_LO = 126; - const char *spd_file; + char *spd_file; size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) @@ -227,6 +241,7 @@ int read_ddr3_spd_from_cbfs(u8 *buf, int idx) memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + cbfs_unmap(spd_file); u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); diff --git a/src/lib/string.c b/src/lib/string.c index e8f72a28e8..9677520137 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -163,6 +163,16 @@ int strcspn(const char *str, const char *spn) return ret; } +char *strstr(const char *haystack, const char *needle) +{ + size_t needle_len = strlen(needle); + for (; *haystack; haystack++) { + if (!strncmp(haystack, needle, needle_len)) + return (char *)haystack; + } + return NULL; +} + char *strtok_r(char *str, const char *delim, char **ptr) { char *start; diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index f368409ef1..badc600d64 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include + #include #define MAX_TIMER_QUEUE_ENTRIES 64 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 24d80ea89a..7347d07b16 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -12,8 +11,6 @@ #define MAX_TIMESTAMPS 192 -DECLARE_OPTIONAL_REGION(timestamp); - /* This points to the active timestamp_table and can change within a stage as CBMEM comes available. */ static struct timestamp_table *glob_ts_table; diff --git a/src/lib/trace.c b/src/lib/trace.c deleted file mode 100644 index a3db40b5f7..0000000000 --- a/src/lib/trace.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -int volatile trace_dis = 0; - -void __cyg_profile_func_enter(void *func, void *callsite) -{ - - if (trace_dis) - return; - - DISABLE_TRACE - printk(BIOS_INFO, "~%p(%p)\n", func, callsite); - ENABLE_TRACE -} - -void __cyg_profile_func_exit(void *func, void *callsite) -{ -} diff --git a/src/lib/ubsan.c b/src/lib/ubsan.c index 8c1f64d427..1037b1b17a 100644 --- a/src/lib/ubsan.c +++ b/src/lib/ubsan.c @@ -68,7 +68,7 @@ struct ubsan_type_mismatch_data { unsigned char type_check_kind; }; -void __ubsan_handle_type_mismatch(void *data_raw, void *pointer_raw) +void __ubsan_handle_type_mismatch_v1(void *data_raw, void *pointer_raw) { const struct ubsan_type_mismatch_data *data = (struct ubsan_type_mismatch_data *)data_raw; @@ -81,7 +81,7 @@ void __ubsan_handle_type_mismatch(void *data_raw, void *pointer_raw) ubsan_abort(&data->location, violation); } -ABORT_VARIANT_VP_VP(type_mismatch); +ABORT_VARIANT_VP_VP(type_mismatch_v1); struct ubsan_overflow_data { struct ubsan_source_location location; @@ -156,6 +156,23 @@ void __ubsan_handle_divrem_overflow(void *data_raw, void *lhs_raw, ABORT_VARIANT_VP_VP_VP(divrem_overflow); +struct ubsan_pointer_overflow_data { + struct ubsan_source_location location; +}; + +void __ubsan_handle_pointer_overflow(void *data_raw, void *base_raw, void *result_raw) +{ + const struct ubsan_pointer_overflow_data *data = + (struct ubsan_pointer_overflow_data *)data_raw; + ubsan_value_handle_t base = (ubsan_value_handle_t)base_raw; + ubsan_value_handle_t result = (ubsan_value_handle_t)result_raw; + (void)base; + (void)result; + ubsan_abort(&data->location, "pointer overflow"); +} + +ABORT_VARIANT_VP_VP_VP(pointer_overflow); + struct ubsan_shift_out_of_bounds_data { struct ubsan_source_location location; struct ubsan_type_descriptor *lhs_type; @@ -228,15 +245,7 @@ void __ubsan_handle_vla_bound_not_positive(void *data_raw, void *bound_raw) ABORT_VARIANT_VP_VP(vla_bound_not_positive); struct ubsan_float_cast_overflow_data { -/* -* TODO: Remove this GCC 5.x compatibility after switching to GCC 6.x. The -* GCC developers accidentally forgot the source location. Their -* libubsan probes to see if it looks like a path, but we don't need -* to maintain compatibility with multiple gcc releases. See below. -*/ -#if !(defined(__GNUC__) && __GNUC__ < 6) struct ubsan_source_location location; -#endif struct ubsan_type_descriptor *from_type; struct ubsan_type_descriptor *to_type; }; @@ -247,11 +256,7 @@ void __ubsan_handle_float_cast_overflow(void *data_raw, void *from_raw) (struct ubsan_float_cast_overflow_data *)data_raw; ubsan_value_handle_t from = (ubsan_value_handle_t)from_raw; (void) from; -#if !(defined(__GNUC__) && __GNUC__ < 6) ubsan_abort(&data->location, "float cast overflow"); -#else - ubsan_abort(((void) data, &unknown_location), "float cast overflow"); -#endif } ABORT_VARIANT_VP_VP(float_cast_overflow); diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index 824e8b3608..efd21da26e 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -28,10 +28,6 @@ config MAINBOARD_DIR string default "51nb/x210" -config MAX_CPUS - int - default 8 - config VGA_BIOS_ID string default "8086,5917" diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index 33e5aeb889..f9022a4c75 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Device (BAT) { diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index c7a91774d3..78e156c6a2 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Device (EC) { diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl index 3c44c47ca2..e57753888c 100644 --- a/src/mainboard/51nb/x210/acpi/graphics.asl +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) Method (_DOS, 1, NotSerialized) { /* We never do anything in firmware, so _DOS is a noop */ diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl index c8c4f255a9..89df7f4d93 100644 --- a/src/mainboard/51nb/x210/acpi/mainboard.asl +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Scope (\_SB) { diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl index fc0333511b..6cf3f32f23 100644 --- a/src/mainboard/51nb/x210/acpi/platform.asl +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Enable ACPI _SWS methods */ #include diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl index 6fe3084c5e..ee2eabeb75 100644 --- a/src/mainboard/51nb/x210/acpi/superio.asl +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b610904a9e..433bc22fbb 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -1,11 +1,13 @@ chip soc/intel/skylake # Enable Panel as eDP and configure power delays - register "gpu_pp_up_delay_ms" = "210" # T3 - register "gpu_pp_down_delay_ms" = "500" # T10 - register "gpu_pp_cycle_delay_ms" = "5000" # T12 - register "gpu_pp_backlight_on_delay_ms" = "1" # T7 - register "gpu_pp_backlight_off_delay_ms" = "200" # T9 + register "panel_cfg" = "{ + .up_delay_ms = 210, // T3 + .down_delay_ms = 500, // T10 + .cycle_delay_ms = 5000, // T12 + .backlight_on_delay_ms = 1, // T7 + .backlight_off_delay_ms = 200, // T9 + }" # Enable deep Sx states register "deep_s3_enable_ac" = "1" @@ -28,16 +30,10 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataMode" = "0" @@ -48,40 +44,20 @@ chip soc/intel/skylake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - register "PmConfigPciClockRun" = "1" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" @@ -138,9 +114,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -159,6 +137,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip ec/51nb/npce985la0dx device pnp 0c09.0 on end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index c648d42568..58f5511510 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -1,11 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( "dsdt.aml", "DSDT", - 0x05, // DSDT revision: ACPI v5.0 + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index c517b44628..53a7547f31 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H @@ -6,174 +6,186 @@ #include #include +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_NC(GPP_A8, UP_20K), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A12, 0, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), + PAD_NC(GPP_B15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, UP_20K, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, UP_20K, PLTRST, OFF, ACPI), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C4, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C17, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C18, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C19, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D7, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D8, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D14, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, UP_20K, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, UP_20K, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c index 6799c38735..730cc443a7 100644 --- a/src/mainboard/51nb/x210/hda_verb.c +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c index 4e6f1d588a..e05331c1ed 100644 --- a/src/mainboard/51nb/x210/mainboard.c +++ b/src/mainboard/51nb/x210/mainboard.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "gpio.h" diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 60f008c20a..38652b5068 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include -#include #include static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 77fcba16e6..af685db17a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -13,10 +13,6 @@ source "src/mainboard/*/Kconfig" config MAINBOARD_VENDOR string "Mainboard vendor name" -config BOARD_ROMSIZE_KB_64 - bool -config BOARD_ROMSIZE_KB_128 - bool config BOARD_ROMSIZE_KB_256 bool config BOARD_ROMSIZE_KB_512 @@ -47,8 +43,6 @@ config BOARD_ROMSIZE_KB_65536 # TODO: No help text possible for choice fields? choice prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 @@ -68,16 +62,6 @@ choice The build system will take care of creating a coreboot.rom file of the matching size. -config COREBOOT_ROMSIZE_KB_64 - bool "64 KB" - help - Choose this option if you have a 64 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_128 - bool "128 KB" - help - Choose this option if you have a 128 KB ROM chip. - config COREBOOT_ROMSIZE_KB_256 bool "256 KB" help @@ -148,8 +132,6 @@ endchoice # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 default 256 if COREBOOT_ROMSIZE_KB_256 default 512 if COREBOOT_ROMSIZE_KB_512 default 1024 if COREBOOT_ROMSIZE_KB_1024 @@ -167,8 +149,6 @@ config COREBOOT_ROMSIZE_KB # Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x00010000 if COREBOOT_ROMSIZE_KB_64 - default 0x00020000 if COREBOOT_ROMSIZE_KB_128 default 0x00040000 if COREBOOT_ROMSIZE_KB_256 default 0x00080000 if COREBOOT_ROMSIZE_KB_512 default 0x00100000 if COREBOOT_ROMSIZE_KB_1024 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000000..1c39839154 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000000..bb177f9e49 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig new file mode 100644 index 0000000000..941070ed2d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ACER_G43T_AM3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_ITE_IT8720F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select DRIVERS_I2C_CK505 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + +config VGA_BIOS_ID + string + default "8086,2e22" + +config MAINBOARD_DIR + string + default "acer/g43t-am3" + +config MAINBOARD_PART_NUMBER + string + default "G43T-AM3" + +endif # BOARD_ACER_G43T_AM3 diff --git a/src/mainboard/acer/g43t-am3/Kconfig.name b/src/mainboard/acer/g43t-am3/Kconfig.name new file mode 100644 index 0000000000..a9b34ff25f --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_G43T_AM3 + bool "G43T-AM3" diff --git a/src/mainboard/acer/g43t-am3/Makefile.inc b/src/mainboard/acer/g43t-am3/Makefile.inc new file mode 100644 index 0000000000..ede8d87e92 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += cstates.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/acer/g43t-am3/acpi/ec.asl b/src/mainboard/acer/g43t-am3/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000000..b7588dcc41 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0001ffff, 0, 0, 0x14}, + Package() { 0x0001ffff, 1, 0, 0x15}, + Package() { 0x0001ffff, 2, 0, 0x16}, + Package() { 0x0001ffff, 3, 0, 0x17}, + + Package() { 0x0002ffff, 0, 0, 0x15}, + Package() { 0x0002ffff, 1, 0, 0x16}, + Package() { 0x0002ffff, 2, 0, 0x17}, + Package() { 0x0002ffff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/acer/g43t-am3/acpi/superio.asl b/src/mainboard/acer/g43t-am3/acpi/superio.asl new file mode 100644 index 0000000000..9f3900b86c --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/superio.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#include diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c new file mode 100644 index 0000000000..2bdb744af3 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ +} diff --git a/src/mainboard/acer/g43t-am3/board_info.txt b/src/mainboard/acer/g43t-am3/board_info.txt new file mode 100644 index 0000000000..aaf657b583 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default new file mode 100644 index 0000000000..706f5dd551 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/acer/g43t-am3/cmos.layout b/src/mainboard/acer/g43t-am3/cmos.layout new file mode 100644 index 0000000000..9f5012adb4 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.layout @@ -0,0 +1,72 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/acer/g43t-am3/cstates.c b/src/mainboard/acer/g43t-am3/cstates.c new file mode 100644 index 0000000000..21b18b9e8d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/acer/g43t-am3/data.vbt b/src/mainboard/acer/g43t-am3/data.vbt new file mode 100644 index 0000000000..646adbae1b Binary files /dev/null and b/src/mainboard/acer/g43t-am3/data.vbt differ diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb new file mode 100644 index 0000000000..4266861bdc --- /dev/null +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + subsystemid 0x8086 0x0028 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + + # Enable PCIe ports 0,1 as slots. + register "pcie_slot_implemented" = "0x3" + + # "Additional LPC IO decode ranges": used for SuperIO's + # Environment Controller on 0xa15/0xa16 + register "gen1_dec" = "0x00fc0a01" + + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8720f # Super I/O + register "ec.smbus_en" = "1" + register "ec.smbus_24mhz" = "1" + register "TMPIN1.mode" = "THERMAL_DIODE" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "100" + register "TMPIN3.min" = "0" + register "TMPIN3.max" = "100" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "0" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "90" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "1" + register "FAN1.smart.smoothing" = "0" + register "FAN1.smart.pwm_start" = "30" + register "FAN1.smart.slope" = "0x0d" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # System fan + register "FAN2.smart.tmpin" = "2" + register "FAN2.smart.tmp_off" = "0" + register "FAN2.smart.tmp_start" = "40" + register "FAN2.smart.tmp_full" = "90" + register "FAN2.smart.tmp_delta" = "2" + register "FAN2.smart.full_lmt" = "0" + register "FAN2.smart.smoothing" = "0" + register "FAN2.smart.pwm_start" = "48" + register "FAN2.smart.slope" = "0x20" + register "FAN3.mode" = "FAN_MODE_OFF" # Not connected + + register "ec.vin_mask" = "VIN_ALL" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM 1 + device pnp 2e.2 off end # COM 2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x60 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 0x1 + io 0x62 = 0x064 + irq 0xf0 = 0x00 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0x0c + irq 0xf0 = 0x00 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa20 + io 0x64 = 0xa30 + irq 0xc0 = 0x01 # Simple IO Set 1 + irq 0xc1 = 0x0c # Simple IO Set 2 + irq 0xc2 = 0x70 # Simple IO Set 3 + irq 0xc3 = 0x00 # Simple IO Set 4 + irq 0xc8 = 0x01 # Simple IO Set 1 Output + irq 0xc9 = 0x0c # Simple IO Set 2 Output + irq 0xca = 0x00 # Simple IO Set 3 Output + irq 0xcb = 0x00 # Simple IO Set 4 Output + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x12 + irq 0xf9 = 0x02 + irq 0xfa = 0x13 + irq 0xfb = 0x02 + #irq 0xfc = 0xef # VID Input + irq 0xfd = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # IDT CV194 + register "mask" = "{ 0xff, 0xff, 0xff, 0x00, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0xff, 0xff, 0xff, + 0x00, 0xff }" + register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x7d, 0x96, + 0x00, 0x9d }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) + device pci 1f.6 off end # Thermal Subsystem + end + end +end diff --git a/src/mainboard/acer/g43t-am3/dsdt.asl b/src/mainboard/acer/g43t-am3/dsdt.asl new file mode 100644 index 0000000000..dacd76cc46 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090811 // OEM revision +) +{ + // global NVS and variables + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include +} diff --git a/src/mainboard/acer/g43t-am3/early_init.c b/src/mainboard/acer/g43t-am3/early_init.c new file mode 100644 index 0000000000..b34ab4651b --- /dev/null +++ b/src/mainboard/acer/g43t-am3/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO set 1 + ite_reg_write(GPIO_DEV, 0x26, 0x0c); // GPIO set 2 + ite_reg_write(GPIO_DEV, 0x27, 0x70); // GPIO set 3 + ite_reg_write(GPIO_DEV, 0x28, 0x40); // GPIO set 4 + ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO set 5 + + /* Enable 3VSB during Suspend-to-RAM */ + ite_enable_3vsbsw(GPIO_DEV); + + /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */ + ite_delay_pwrgd3(GPIO_DEV); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/acer/g43t-am3/gma-mainboard.ads b/src/mainboard/acer/g43t-am3/gma-mainboard.ads new file mode 100644 index 0000000000..c9e4326924 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/acer/g43t-am3/gpio.c b/src/mainboard/acer/g43t-am3/gpio.c new file mode 100644 index 0000000000..38239baf79 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gpio.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, + +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + +}; diff --git a/src/mainboard/acer/g43t-am3/hda_verb.c b/src/mainboard/acer/g43t-am3/hda_verb.c new file mode 100644 index 0000000000..32a9b25874 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/hda_verb.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x1025024c, // Subsystem ID + 14, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x014b7140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19851), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x18567130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* HDMI */ + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(0, 0x03, 0x18560010) +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index d4d1c4a7ab..d362ca9a91 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -70,7 +69,6 @@ Name(APR0, Package(){ Package(){0x0011FFFF, 0, 0, 19 }, }) - /* GPP 0 */ Name(PS4, Package(){ Package(){0x0000FFFF, 0, INTA, 0 }, diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index a2de6351c1..38cd34cd12 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -5,9 +5,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index f9cf2ca3f5..0338115439 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/inagua/acpi/sata.asl +++ b/src/mainboard/amd/inagua/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index a395d248cf..92591d75ff 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 53427558ad..48afb3f9ad 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -31,7 +31,6 @@ static void init_gpios(void) gpio_100_write8(0x32, 0x48); } - /********************************************** * Enable the dedicated functions of the board. **********************************************/ diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index efbadbb50f..85a60e251b 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -37,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -140,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig new file mode 100644 index 0000000000..4b77f0421d --- /dev/null +++ b/src/mainboard/amd/majolica/Kconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AMD_MAJOLICA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_CEZANNE + select AMD_SOC_CONSOLE_UART + +config FMDFILE + string + default "src/mainboard/amd/majolica/board.fmd" + +config MAINBOARD_DIR + default "amd/majolica" + +config MAINBOARD_PART_NUMBER + default "MAJOLICA" + +config MAJOLICA_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config MAJOLICA_MCHP_FW_FILE + string + depends on MAJOLICA_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/majolica/EC_majolica.bin" + help + The EC firmware blob is usually the first 128kByte of the stock + firmware image. + +endif # BOARD_AMD_MAJOLICA diff --git a/src/mainboard/amd/majolica/Kconfig.name b/src/mainboard/amd/majolica/Kconfig.name new file mode 100644 index 0000000000..8c305cf7b7 --- /dev/null +++ b/src/mainboard/amd/majolica/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MAJOLICA + bool "Majolica" diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc new file mode 100644 index 0000000000..7472599772 --- /dev/null +++ b/src/mainboard/amd/majolica/Makefile.inc @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_MAJOLICA_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw, $(obj)/coreboot.pre) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAJOLICA_MCHP_FW_FILE) --fill-upward +else +files_added:: warn_no_mchp +endif # CONFIG_MAJOLICA_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC FW.\n" + printf "Do not flash this image. Your Majolica's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/majolica/board.fmd b/src/mainboard/amd/majolica/board.fmd new file mode 100644 index 0000000000..442d80f341 --- /dev/null +++ b/src/mainboard/amd/majolica/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/majolica/board_info.txt b/src/mainboard/amd/majolica/board_info.txt new file mode 100644 index 0000000000..b351b8e696 --- /dev/null +++ b/src/mainboard/amd/majolica/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb new file mode 100644 index 0000000000..a1415525c7 --- /dev/null +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/cezanne + + device domain 0 on + end + +end diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 599e64ab83..c1d68fa58b 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,8 +8,11 @@ config BOARD_SPECIFIC_OPTIONS select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME + select DRIVERS_UART_ACPI + select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD config FMDFILE string @@ -18,17 +21,36 @@ config FMDFILE config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" default n - select PICASSO_LPC_IOMUX + select MANDOLIN_LPC select SUPERIO_SMSC_SIO1036 help - AMD's debug card contains an SMSC SIO1036 device which provides - an I/O-based UART in the system. This feature is not compatible with - CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. - Note that Kconfig does not currently enforce this restriction. + AMD's debug card contains an SMSC SIO1036 device which provides an + I/O-mapped UART in the system. This is mutually exclusive with + AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped + UART for coreboot console output. + +choice + prompt "SMSC/Microchip 1036 SuperIO config address" + depends on SUPERIO_SMSC_SIO1036 + default SMSC_SIO1036_BASE_164E + +config SMSC_SIO1036_BASE_4E + bool "0x4e/0x4d base address" + +config SMSC_SIO1036_BASE_164E + bool "0x164e/0x164d base address" + +endchoice + +config SUPERIO_ADDR_BASE + hex + default 0x4e if SMSC_SIO1036_BASE_4E + default 0x164e if SMSC_SIO1036_BASE_164E config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP config MAINBOARD_DIR string @@ -37,19 +59,17 @@ config MAINBOARD_DIR config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME config DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config MAX_CPUS - int - default 8 - config ONBOARD_VGA_IS_PRIMARY bool default y @@ -57,6 +77,7 @@ config ONBOARD_VGA_IS_PRIMARY config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs @@ -68,9 +89,13 @@ config MANDOLIN_MCHP_FW_FILE string depends on MANDOLIN_HAVE_MCHP_FW default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME + help + The EC firmware blob is usually the first 128kByte of the stock + firmware image. if !AMD_LPC_DEBUG_CARD -choice MANDOLIN_LPC_IOMUX +choice prompt "State of IOMux for LPC/eMMC signals" default MANDOLIN_IOMUX_USE_EMMC help @@ -86,7 +111,7 @@ config MANDOLIN_IOMUX_USE_EMMC endchoice endif # !AMD_LPC_DEBUG_CARD -config PICASSO_LPC_IOMUX +config MANDOLIN_LPC bool default y if MANDOLIN_IOMUX_USE_LPC help @@ -104,5 +129,22 @@ config VGA_BIOS_DGPU_ID config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME -endif # BOARD_AMD_MANDOLIN +config EFS_SPI_READ_MODE + int + default 0 if EM100 + default 0 if BOARD_AMD_CEREME + default 3 + +config EFS_SPI_SPEED + int + default 3 if EM100 + default 1 if BOARD_AMD_CEREME + default 0 + +config EFS_SPI_MICRON_FLAG + int + default 0 + +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3fd71..6f512337a3 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1865e74dd9..6644bb36db 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -6,20 +6,19 @@ bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c -ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) +ifneq ($(CONFIG_MANDOLIN_LPC),y) ramstage-y += emmc_gpio.c endif -# APCB_mandolin.bin -APCB_SOURCES = mandolin - -PHONY+=add_mchp_fw -INTERMEDIATE+=add_mchp_fw +ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin +else # CONFIG_BOARD_AMD_CEREME +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin +endif ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) -MANDOLIN_MICROCHIP_FW_OFFSET=0 -add_mchp_fw: $(obj)/coreboot.pre +$(call add_intermediate, add_mchp_fw, $(obj)/coreboot.pre) $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward else diff --git a/src/mainboard/amd/mandolin/bootblock.c b/src/mainboard/amd/mandolin/bootblock.c index 06da379d93..94a132938f 100644 --- a/src/mainboard/amd/mandolin/bootblock.c +++ b/src/mainboard/amd/mandolin/bootblock.c @@ -5,14 +5,19 @@ #include #include "gpio.h" -#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1) void bootblock_mainboard_early_init(void) { mainboard_program_early_gpios(); if (CONFIG(SUPERIO_SMSC_SIO1036)) { - lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + if (CONFIG_SUPERIO_ADDR_BASE == 0x4e) { + lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + } else { + // set up 16 byte wide I/O range window for the super IO + lpc_set_wideio_range(CONFIG_SUPERIO_ADDR_BASE & ~0xF, 16); + } lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 06612a8904..d2fa4add7b 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -5,9 +5,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/mandolin/emmc_gpio.c b/src/mainboard/amd/mandolin/emmc_gpio.c index 2ae72a6ec7..a88a5c59b2 100644 --- a/src/mainboard/amd/mandolin/emmc_gpio.c +++ b/src/mainboard/amd/mandolin/emmc_gpio.c @@ -6,7 +6,7 @@ /* eMMC controller driving either an SD card or eMMC device. */ static const struct soc_amd_gpio emmc_gpios[] = { PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), - PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP), + PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_UP), PAD_NF(GPIO_68, EMMC_CD, PULL_UP), PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP), diff --git a/src/mainboard/amd/mandolin/hda_verb.c b/src/mainboard/amd/mandolin/hda_verb.c index 37bb710c7c..0f61f31525 100644 --- a/src/mainboard/amd/mandolin/hda_verb.c +++ b/src/mainboard/amd/mandolin/hda_verb.c @@ -3,7 +3,7 @@ #include const u32 cim_verb_data[] = { - /* Realtek ALC701 */ + /* Realtek ALC701 on mainboard */ 0x10ec0701, 0x00000000, 0x00000016, @@ -35,7 +35,7 @@ const u32 cim_verb_data[] = { 0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1 0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2 - /* Realtek ALC285 */ + /* Realtek ALC285 on extension card */ 0x10ec0285, 0x00000000, 0x00000028, diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index c22ed34849..0d208da348 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -29,30 +29,6 @@ static uint8_t fch_apic_routing[0x80]; _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); -/* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; @@ -100,9 +76,6 @@ static void init_tables(void) static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } @@ -111,13 +84,13 @@ static void mainboard_init(void *chip_info) { struct soc_amd_picasso_config *cfg = config_of_soc(); - if (!CONFIG(PICASSO_LPC_IOMUX)) - cfg->sd_emmc_config = SD_EMMC_EMMC_HS400; + if (!CONFIG(MANDOLIN_LPC)) + cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ - if (CONFIG(PICASSO_LPC_IOMUX)) + if (CONFIG(MANDOLIN_LPC)) printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); else mainboard_program_emmc_gpios(); diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000000..442d80f341 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000000..1a8164f0a2 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec + + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port4 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port5 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping; all ports share one OC pin + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocessor + device pci 0.3 on end # USB 3.1 + device pci 0.4 off end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 off end # AHCI + device pci 0.1 off end # integrated Ethernet MAC + device pci 0.2 off end # integrated Ethernet MAC + end + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c new file mode 100644 index 0000000000..800bd71590 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), + /* PCIe Reset 0 */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIe Reset 1 */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/gpio.c b/src/mainboard/amd/mandolin/variants/cereme/gpio.c new file mode 100644 index 0000000000..0ba2580ce1 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/gpio.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* EC SCI# */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* not Blink */ + PAD_GPI(GPIO_11, PULL_UP), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* SD card detect */ + PAD_GPI(GPIO_31, PULL_UP), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* NFC wake output# */ + PAD_GPO(GPIO_89, HIGH), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000000..8fc94f8c3b --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const fsp_dxio_descriptor pollock_dxio_descriptors[] = { + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = pollock_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd index 382c03066d..33b281d37f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd +++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd @@ -1,8 +1,8 @@ -FLASH@0xFF800000 0x800000 { - BIOS@0x0 { - EC@0x0 0x20000 - RW_MRC_CACHE@0x20000 0x10000 - FMAP 0x1000 +FLASH@0xFF800000 8M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + FMAP 4K COREBOOT(CBFS) } } diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index f83a634195..db73ac73aa 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -5,18 +5,108 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON" + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "sd_emmc_config" = "SD_EMMC_DISABLE" + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port0 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port1 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping; all ports share one OC pin + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" # eSPI Configuration register "common_config.espi_config" = "{ @@ -36,6 +126,15 @@ chip soc/amd/picasso .flash_ch_en = 0, }" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" + device cpu_cluster 0 on device lapic 0 on end end @@ -49,7 +148,7 @@ chip soc/amd/picasso device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor + device pci 0.2 on end # Crypto Coprocessor device pci 0.3 on end # USB 3.1 device pci 0.4 on end # USB 3.1 device pci 0.5 on end # Audio @@ -61,8 +160,8 @@ chip soc/amd/picasso device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SM - device pci 14.3 on # - D14F3 bridge + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end @@ -76,4 +175,10 @@ chip soc/amd/picasso device pci 18.6 on end device pci 18.7 on end end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c b/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c index 678de59b2c..63e01ef5d9 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c +++ b/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c @@ -17,7 +17,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* not USB_OC2_L */ PAD_GPI(GPIO_18, PULL_UP), /* SDIO eMMC power control */ - PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), /* PCIe SSD power enable */ PAD_GPO(GPIO_23, HIGH), /* PCIe Reset to DP0, DP1, J2105, TP, FP */ diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c index 326bcaa0e7..5213176a1d 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c +++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c @@ -4,12 +4,12 @@ #include #include -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 15, + .start_logical_lane = 8, + .end_logical_lane = 15, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, @@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* SSD */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WLAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* LAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, @@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WWAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 6, - .end_lane = 6, + .start_logical_lane = 6, + .end_logical_lane = 6, .device_number = 1, .function_number = 4, .link_aspm = ASPM_L1, @@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WIFI */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 7, - .end_lane = 7, + .start_logical_lane = 7, + .end_logical_lane = 7, .gpio_group_id = 1, .device_number = 1, .function_number = 5, @@ -87,19 +87,19 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* SATA EXPRESS */ .port_present = true, .engine_type = SATA_ENGINE, - .start_lane = 2, - .end_lane = 3, + .start_logical_lane = 2, + .end_logical_lane = 3, .gpio_group_id = 1, .channel_type = SATA_CHANNEL_LONG, } }; -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 11, + .start_logical_lane = 8, + .end_logical_lane = 11, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, @@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* SSD */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* WLAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* LAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, @@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* SATA */ .port_present = true, .engine_type = SATA_ENGINE, - .start_lane = 2, - .end_lane = 3, + .start_logical_lane = 2, + .end_logical_lane = 3, .gpio_group_id = 1, .channel_type = SATA_CHANNEL_LONG, } @@ -193,23 +193,23 @@ static const fsp_ddi_descriptor dali_ddi_descriptors[] = { }, { /* DDI2 - DP */ .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, + .aux_index = AUX4, + .hdp_index = HDP4, } }; -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { if (soc_is_reduced_io_sku()) { /* Dali */ - *pcie_descs = dali_pcie_descriptors; - *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *dxio_descs = dali_dxio_descriptors; + *dxio_num = ARRAY_SIZE(dali_dxio_descriptors); *ddi_descs = dali_ddi_descriptors; *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); } else { /* Picasso and default */ - *pcie_descs = pco_pcie_descriptors; - *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *dxio_descs = pco_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pco_dxio_descriptors); *ddi_descs = pco_ddi_descriptors; *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); } diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ b/src/mainboard/amd/olivehill/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c index d1bdd09e26..efdf57d1c2 100644 --- a/src/mainboard/amd/olivehill/bootblock.c +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 0e09739f03..7a1f3590de 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 428ea84cfe..894df574ea 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select STONEYRIDGE_LEGACY_FREE select ONBOARD_VGA_IS_PRIMARY - select BOOTBLOCK_CONSOLE select SUPERIO_FINTEK_F81803A select SUPERIO_FINTEK_COMMON_PRE_RAM select SUPERIO_FINTEK_FAN_CONTROL @@ -28,7 +27,7 @@ config MAINBOARD_PART_NUMBER string default "Padmelon" -choice PADMELON_SOC +choice prompt "SOC used in padmelon board" default PADMELON_MERLIN_FALCON diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl index 40a1b5b520..de6ff3d92f 100644 --- a/src/mainboard/amd/padmelon/acpi/routing.asl +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c index dbdfa47041..6937429934 100644 --- a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -95,7 +95,6 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { }; - static const PCIe_DDI_DESCRIPTOR DdiList[] = { /* DP0 */ { diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 716c7919e5..f4cb15fc16 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index e10da6f1b7..352ab25b4d 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -5,7 +5,6 @@ #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 726e111ff6..91bcabc52d 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 5ab39a13b2..030634605d 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index b04567a948..940487f20b 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 167a85790f..14fff7da30 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include - static const PCIe_PORT_DESCRIPTOR PortList[] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index 656a0be1ee..b7fd53af8c 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -41,7 +41,6 @@ Scope(\_SB) { /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - /* SB devices */ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/persimmon/acpi/sata.asl +++ b/src/mainboard/amd/persimmon/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index a395d248cf..92591d75ff 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 87a5cc48a0..32c22bcfa1 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -37,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -140,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 14574f0e1c..339469bb87 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/south_station/acpi/sata.asl +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 1f898d55e4..c873e4e904 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit chip northbridge/amd/agesa/family14 device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -85,5 +85,5 @@ chip northbridge/amd/agesa/family14/root_complex end # agesa northbridge - end #domain + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index a395d248cf..92591d75ff 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index efbadbb50f..85a60e251b 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -37,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -140,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 1cba1a3cd9..4dddaef54d 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -154,7 +154,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) } } - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index ec1f0ae4dc..23cda27728 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -5,7 +5,6 @@ #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 726e111ff6..91bcabc52d 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 433a9f428e..72390c0ae2 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index b04567a948..940487f20b 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/union_station/acpi/sata.asl +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 185369a3d5..6c88931d17 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit chip northbridge/amd/agesa/family14 device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -61,5 +61,5 @@ chip northbridge/amd/agesa/family14/root_complex end # agesa northbridge - end #domain + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index a395d248cf..92591d75ff 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index efbadbb50f..85a60e251b 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -37,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -140,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 613de6ff66..4227ff2b06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20111103 // OEM revision diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index eb367fa98b..e8c7da8cff 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -32,27 +32,27 @@ Device(EC) Method(SBPC, 0, NotSerialized) { - Store(1000, Local0) + Local0 = 1000 While(Local0) { - If(LEqual(SPTR, 0x00)) + If(SPTR == 0) { Return() } Sleep(1) - Decrement(Local0) + Local0-- } } Method(SBRW, 2, NotSerialized) { Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x09, SPTR) + SADR = (Arg0 << 1) + SCMD = Arg1 + SPTR = 0x09 SBPC() - Store(SBDW, Local0) + Local0 = SBDW Release(ECLK) Return(Local0) } @@ -60,11 +60,11 @@ Device(EC) Method(SBRB, 2, NotSerialized) { Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x0B, SPTR) + SADR = (Arg0 << 1) + SCMD = Arg1 + SPTR = 0x0B SBPC() - Store(SBFR, Local0) + Local0 = SBFR Release(ECLK) Return(Local0) } @@ -112,9 +112,9 @@ Device(EC) Method(_PSW, 1, NotSerialized) { if (Arg0) { - Store(1, WKLD) + WKLD = 1 } else { - Store(0, WKLD) + WKLD = 0 } } } @@ -172,19 +172,19 @@ Device(EC) Method(_BIF, 0, NotSerialized) { - Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) - Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) - Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) - Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) - Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) - Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + BATS [0x01] = (SBRW (0x0B, 0x18) * 10) + BATS [0x02] = (SBRW (0x0B, 0x10) * 10) + BATS [0x04] = SBRW (0x0B, 0x19) + BATS [0x09] = SBRB (0x0B, 0x21) + BATS [0x0B] = SBRB (0x0B, 0x22) + BATS [0x0C] = SBRB (0x0B, 0x20) Return(BATS) } Method(_STA, 0, NotSerialized) { - If(And(^^SBRW(0x0A, 0x01), 0x01)) { + If (SBRW(0x0A, 1) & 1) { Return(0x1f) } else { Return(0x0f) @@ -194,7 +194,7 @@ Device(EC) Method(_BST, 0, NotSerialized) { /* Check for battery presence. */ - If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + If (!(SBRW (0x0A, 1) & 1)) { Return(Package(4) { 0, 0xFFFFFFFF, @@ -202,30 +202,30 @@ Device(EC) 0xFFFFFFFF }) } - Store(^^SBRW(0x0B, 0x09), Local1) - Store(Local1, Index(BATI, 0x03)) - Store(^^SBRW(0x0B, 0x0A), Local0) + Local1 = SBRW(0x0B, 0x09) + BATI [3] = Local1 + Local0 = SBRW (0x0B, 0x0A) /* Sign-extend Local0. */ - If(And(Local0, 0x8000)) + If(Local0 & 0x8000) { - Not(Local0, Local0) - And(Increment(Local0), 0xFFFF, Local0) + Local0 = ~Local0 + Local0 = (Local0++ & 0xFFFF) } - Multiply(Local0, Local1, Local0) - Divide(Local0, 1000, , Index(BATI, 1)) - Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + Local0 *= Local1 + BATI [1] = (Local0 / 1000) + BATI [2] = (SBRW (0x0B, 0x0F) * 10) If(HPAC) { - If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { - Store(2, Index(BATI, 0)) + If (!(SBRW (0x0B, 0x16) & 0x40)) { + BATI [0] = 2 } Else { - Store(0, Index(BATI, 0)) + BATI [0] = 0 } } Else { - Store(0x01, Index(BATI, 0)) + BATI [0] = 1 } Return(BATI) diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index 862292403d..abba5abf25 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -10,12 +10,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -46,7 +46,7 @@ Scope(\_SB) * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index 52c2fbbec1..6970dfc45e 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 2df318f036..5d3d0746ab 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -4,102 +4,76 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 9b5ba55018..4ea20e5be5 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index f4ecb1ecdf..7f153a0ad7 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -3,73 +3,48 @@ # ----------------------------------------------------------------- entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused -#400 8 r 0 reserved for century byte +395 4 e 6 debug_level +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -#432 5 e 11 gfx_uma_size -#437 3 r 0 unused -#440 8 h 0 volume +#432 5 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums checksum 392 447 984 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 6e99b63077..50507586ee 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "1" + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "10" register "gpu_panel_power_cycle_delay" = "6" @@ -15,12 +15,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x13121312" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index e68c018226..a25c8b64cb 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 9da67022c8..a32298d536 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -26,8 +26,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { void *spd_file; size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (spd_file && spd_file_len >= 1024) { int i; for (i = 0; i < 4; i++) diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 846f0797bc..06763d3abb 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 678c48b268..af69d5872e 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "4" @@ -15,12 +15,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 20cca3e259..2f919170ad 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc651208f0..f55cf09423 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -5,19 +5,23 @@ if BOARD_ASROCK_B85M_PRO4 config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 +config CBFS_SIZE + hex + default 0x200000 + config MAINBOARD_DIR string default "asrock/b85m_pro4" diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c index eed290d500..59c4186665 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi_tables.c +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index 0cedcd6e47..7314552767 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -54,6 +54,7 @@ void mainboard_config_superio(void) pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout index ed022330dd..efdc333fc2 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -14,7 +14,6 @@ 984 16 h 0 check_sum # ----------------------------------------------------------------- - # ----------------------------------------------------------------- enumerations # ----------------------------------------------------------------- @@ -41,7 +40,6 @@ 5 2 Keep # ----------------------------------------------------------------- - # ----------------------------------------------------------------- checksums # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index a044d0a8a3..43a65f8197 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end @@ -27,15 +20,6 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x83" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x83" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x8a" - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" device pci 14.0 on end # xHCI controller @@ -111,6 +95,9 @@ chip northbridge/intel/haswell device pnp 2e.16 off end # Deep sleep device pnp 2e.17 off end # GPIOA end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end end device pci 1f.2 on end # SATA (AHCI) device pci 1f.3 on end # SMBus diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index bbc9630a28..bba5c2e593 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ @@ -20,7 +20,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 6bd2f981a8..391b308941 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include - static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 75526c6227..28b4b42be1 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -5,55 +5,52 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 2 e 3 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 2 e 3 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -3 0 Off -3 1 On -3 2 Last -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +3 0 Off +3 1 On +3 2 Last +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index d1896adf22..27f9de0f6a 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index fe0d50e71c..81e2bac79d 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include @@ -9,7 +8,6 @@ #include - u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 21ecebe51b..6994575985 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -37,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -140,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index 9eef15936a..7206526637 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index f90467cdb9..a9abba3f81 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -4,85 +4,59 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 42555bf7b5..2c9f6347c4 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -32,7 +32,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(1, 0x03, 0x18560010), - /* coreboot specific header */ /* Realtek ALC662 rev1 */ 0x10ec0662, /* Vendor ID */ diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 75020712fc..9d22761a7c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -69,8 +69,8 @@ chip northbridge/intel/x4x # Northbridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + irq 0x70 = 6 + drq 0x74 = 2 end device pnp 2e.1 on # Parallel port # global diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c index 722e4cc7b3..87ace2c933 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c @@ -88,7 +88,6 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, }; - const struct pch_gpio_map mainboard_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 425aff4868..cec5db8413 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -11,9 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H - select GENERIC_SPD_BIN + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM @@ -30,14 +29,6 @@ config MAINBOARD_PART_NUMBER string default "H110M" -config MAX_CPUS - int - default 8 - -config DEVICETREE - string - default "devicetree.cb" - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 @@ -46,9 +37,4 @@ config DIMM_SPD_SIZE int default 512 #DDR4 -# This is overridden if CMOS is used for configuration values. -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - endif diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 1327a3615f..4cb873585f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -2,10 +2,6 @@ chip soc/intel/skylake - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_WAKE_PIN" register "eist_enable" = "1" @@ -18,41 +14,12 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Set @0x280-0x2ff I/O Range for SuperIO HWM - register "gen1_dec" = "0x007c0281" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" - register "SkipExtGfxScan" = "0" register "PrimaryDisplay" = "Display_PEG" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "0" - register "PchHdaVcType" = "Vc1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Set LPC Serial IRQ mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -67,184 +34,6 @@ chip soc/intel/skylake # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration - #+----------------+-------+-------+-------------+-------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax* | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------+ - # * - is set automatically in the vr_config.c - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(4), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0 ,\ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - register "EnableLan" = "0" - - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - # SATA4 and SATA5 are located in the lower right corner of the board, - # but they are not populated. This is because the same PCB is used to - # make boards with better PCHs, which can have up to six SATA ports. - # However, the H110 PCH only has four SATA ports, which explains why - # two connectors are missing. - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Disable CLKREQ#, since onboard LAN is always present - register "PcieRpClkReqSupport[5]" = "0" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -262,6 +51,12 @@ chip soc/intel/skylake end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + register "Peg0MaxLinkWidth" = "Peg0_x16" + + # Configure PCIe clockgen in PCH + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 @@ -270,6 +65,32 @@ chip soc/intel/skylake device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" end device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on # Thermal Subsystem @@ -279,8 +100,11 @@ chip soc/intel/skylake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -288,6 +112,18 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA subsystemid 0x1849 0xa102 + register "SataSalpSupport" = "1" + # SATA4 and SATA5 are located in the lower right corner of the board, + # but they are not populated. This is because the same PCB is used to + # make boards with better PCHs, which can have up to six SATA ports. + # However, the H110 PCH only has four SATA ports, which explains why + # two connectors are missing. + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + }" end device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 @@ -296,9 +132,33 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 on # PCI Express Port 5 - PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpHotPlug[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 - Onboard LAN + register "PcieRpEnable[5]" = "1" + + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device pci 1c.6 on # PCI Express Port 7 - PCIE slot + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "3" + register "PcieRpHotPlug[6]" = "1" + end device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -311,9 +171,15 @@ chip soc/intel/skylake device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/common device pnp 2e.0 on # passes SIO base addr to SSDT gen @@ -421,7 +287,9 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaVcType" = "Vc1" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 405959601e..3820b945b1 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 2a3b424b3c..9b2193b587 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -10,37 +10,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A7 - GPIO */ PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), /* GPP_A12 - GPIO */ PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* GPP_A16 - GPIO */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), /* GPP_A17 - GPIO */ @@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B3 - GPIO */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* GPP_B4 - CPU_GP3 */ - PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), /* GPP_B5 - GPIO */ PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), /* GPP_B6 - GPIO */ @@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B7 - NC */ PAD_NC(GPP_B7, NONE), /* GPP_B8 - GPIO */ - PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B8, UP_5K, PLTRST, OFF), /* GPP_B9 - GPIO */ PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), /* GPP_B10 - GPIO */ @@ -88,11 +88,11 @@ static const struct pad_config gpio_table[] = { PAD_BUF(NO_DISABLE), PAD_PULL(NONE)), /* GPP_B12 - SLP_S0# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), /* GPP_B16 - GPIO */ @@ -110,35 +110,31 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, - PAD_FUNC(NF2) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | - PAD_BUF(RX_DISABLE) | 1, - PAD_PULL(20K_PD)), + PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* GPP_C1 - SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* GPP_C2 - GPIO */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPP_C3 - SML0CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 - SML0DATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* GPP_C5 - GPIO */ PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - UART0_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), /* GPP_C9 - UART0_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), /* GPP_C10 - UART0_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), /* GPP_C11 - UART0_CTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), /* GPP_C12 - GPIO */ PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), /* GPP_C13 - GPIO */ @@ -156,13 +152,13 @@ static const struct pad_config gpio_table[] = { /* GPP_C19 - GPIO */ PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), /* GPP_C20 - UART2_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), /* GPP_C21 - UART2_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), /* GPP_C22 - UART2_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* GPP_C23 - GPIO */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + PAD_CFG_GPI_SCI_LOW(GPP_C23, NONE, DEEP, LEVEL), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -176,13 +172,13 @@ static const struct pad_config gpio_table[] = { /* GPP_D4 - GPIO */ PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), /* GPP_D5 - I2S_SFRM */ - PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), /* GPP_D6 - I2S_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), /* GPP_D7 - I2S_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* GPP_D8 - I2S_SCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* GPP_D9 - GPIO */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), /* GPP_D10 - GPIO */ @@ -204,9 +200,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D18 - GPIO */ PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D19, UP_20K, PLTRST, NF1), /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D20, UP_20K, PLTRST, NF1), /* GPP_D21 - GPIO */ PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), /* GPP_D22 - GPIO */ @@ -216,37 +212,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* GPP_E4 - SATA_DEVSLP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* GPP_E5 - SATA_DEVSLP1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* GPP_E6 - SATA_DEVSLP2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* GPP_E7 - GPIO */ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - USB_OC1# */ - PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* GPP_E11 - USB_OC2# */ - PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* GPP_E12 - USB_OC3# */ - PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), /* GPP_F2 - GPIO */ PAD_NC(GPP_F2, NONE), /* GPP_F3 - GPIO */ @@ -264,21 +260,21 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPP_F10 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* GPP_F11 - GPIO */ PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), /* GPP_F12 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), /* GPP_F13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), /* GPP_F14 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), /* GPP_F15 - USB_OC4# */ - PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* GPP_F16 - USB_OC5# */ - PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* GPP_F17 - USB_OC6# */ - PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* GPP_F18 - GPIO */ PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPP_F19 - GPIO */ @@ -308,7 +304,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G6 - GPIO */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G7 - GPIO */ @@ -324,7 +320,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G12 - GPIO */ _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G13 - GPIO */ @@ -332,19 +328,19 @@ static const struct pad_config gpio_table[] = { /* GPP_G14 - GPIO */ _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G15 - GPIO */ PAD_CFG_GPO(GPP_G15, 0, PLTRST), /* GPP_G16 - GPIO */ - PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), /* GPP_G17 - GPIO */ PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), /* GPP_G18 - GPIO */ - PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* GPP_G20 - GPIO */ PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), /* GPP_G21 - GPIO */ @@ -382,11 +378,11 @@ static const struct pad_config gpio_table[] = { /* GPP_H12 - GPIO */ PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), /* GPP_H13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), /* GPP_H14 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), /* GPP_H15 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), /* GPP_H16 - GPIO */ PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* GPP_H17 - GPIO */ @@ -410,13 +406,13 @@ static const struct pad_config gpio_table[] = { /* GPD1 - GPIO */ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPD2 - LAN_WAKE# */ - PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), /* GPD7 - GPIO */ @@ -426,70 +422,70 @@ static const struct pad_config gpio_table[] = { PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPD8 - SUSCLK */ - PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* GPD9 - SLP_WLAN# */ - PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* GPD10 - SLP_S5# */ - PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* GPD11 - GPIO */ PAD_CFG_GPO(GPD11, 0, PWROK), /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - DDPB_HPD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* GPP_I1 - DDPC_HPD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* GPP_I2 - DDPD_HPD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* GPP_I3 - DDPE_HPD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* GPP_I4 - GPIO */ PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), /* GPP_I5 - DDPB_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* GPP_I6 - DDPB_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* GPP_I7 - DDPC_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* GPP_I8 - DDPC_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* GPP_I9 - DDPD_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* GPP_I10 - DDPD_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), }; /* Early pad configuration in romstage */ static const struct pad_config early_gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 7a17915534..ca3058fa9f 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -1,71 +1,36 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 200, 81, 162 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[5] = { - 100, 40, 40, 23, 40 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; + const u16 rcomp_resistors[3] = { 121, 75, 100 }; + + const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { - .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + .addr_map = { 0x50, 0x52 }, }; - mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; - mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; - mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; dump_spd_info(&blk); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + /* use virtual channel 1 for the dmi interface of the PCH */ mupd->FspmTestConfig.DmiVc1 = 1; diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 62036108dd..af723a3e04 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -5,7 +5,6 @@ if BOARD_ASROCK_H81M_HDS config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -18,8 +17,8 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE hex diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c deleted file mode 100644 index 8ec5b118c5..0000000000 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index e03d040796..c9ba76c78f 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -4,75 +4,53 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 4 debug_level -#399 1 r 0 unused +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail +408 1 e 1 nmi +409 2 e 5 power_on_after_fail # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index f08d2d560f..7b08af96d8 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end @@ -35,16 +28,6 @@ chip northbridge/intel/haswell end chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x8a" - - register "sata_ahci" = "1" register "sata_port_map" = "0x33" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 8fec596fe1..d3e7ba17d0 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v3.0 */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181031 /* OEM Revision */ @@ -20,7 +20,7 @@ DefinitionBlock( { Device (PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index b1e3e88d59..b97be80398 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -5,7 +5,6 @@ #include - static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 20c4b8d781..4761728927 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -7,7 +7,6 @@ #include #include - u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c new file mode 100644 index 0000000000..24a7208e3b --- /dev/null +++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; + +static const CODEC_TBL_LIST CodecTableList[] = { + {0x10ec0887, (CODEC_ENTRY *)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig new file mode 100644 index 0000000000..17fbe28cd5 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_A88XM_E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default "asus/a88xm-e" + +config MAINBOARD_PART_NUMBER + string + default "A88XM-E" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config VGA_BIOS_ID + string + default "1002,990e" + +config HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name new file mode 100644 index 0000000000..492d6109ee --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_A88XM_E + bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc new file mode 100644 index 0000000000..549801d78f --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c new file mode 100644 index 0000000000..aa880e7bee --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OemCustomize.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include +#include + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI, HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/* CUSTOMER OVERRIDES MEMORY TABLE */ +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h similarity index 73% rename from src/mainboard/lippert/toucan-af/OptionsIds.h rename to src/mainboard/asus/a88xm-e/OptionsIds.h index ce3a8a0170..adbb4763ee 100644 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -6,14 +6,12 @@ * IDS Option File * * This file is used to switch on/off IDS features. - * */ #ifndef _OPTION_IDS_H_ #define _OPTION_IDS_H_ /** - * - * This file generates the defaults tables for the Integrated Debug Support + * This file generates the defaults tables for the Integrated Debug Support * Module. The documented build options are imported from a user controlled * file for processing. The build options for the Integrated Debug Support * Module are listed below: @@ -26,13 +24,15 @@ * IDSOPT_ASSERT_ENABLED * IDS_DEBUG_PORT * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * **/ -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE - +//#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW //#define IDSOPT_HOST_SIMNOW FALSE diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl new file mode 100644 index 0000000000..35583de49f --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. + */ + +/* + * P-state support: the maximum number of P-states supported + * by the CPUs that we'll use - is 6. Taken from AMI BIOS. + */ +Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } +}) + +Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} +}) + +Method(_PPC, 0){ + Return(0) +} diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl new file mode 100644 index 0000000000..9f01c7a0ca --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + } + + /* Legacy PM event */ + Method(_L08) { + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + } + + /* USB controller PME# */ + Method(_L0B) { + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl new file mode 100644 index 0000000000..699bc6b031 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) + /* Length of PCIe config space, 1MB each bus */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) + /* Base address of HPET table */ + Name(HPBA, 0xFED00000) + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl new file mode 100644 index 0000000000..99511c5a21 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 PCIe Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl new file mode 100644 index 0000000000..87773378c9 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ +Method(\_PTS, 1) { + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ +Method(\_WAK, 1) { + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl new file mode 100644 index 0000000000..d90fffdd40 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c similarity index 73% rename from src/mainboard/lippert/toucan-af/acpi_tables.c rename to src/mainboard/asus/a88xm-e/acpi_tables.c index f75f823f38..ff4a3b97b6 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/asus/a88xm-e/acpi_tables.c @@ -8,22 +8,21 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); + current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - + current, 0, 9, 9, 0xF); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); /* 1: LINT1 connect to NMI */ return current; diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt new file mode 100644 index 0000000000..579dce634d --- /dev/null +++ b/src/mainboard/asus/a88xm-e/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/bootblock.c b/src/mainboard/asus/a88xm-e/bootblock.c new file mode 100644 index 0000000000..0bc8d2e15e --- /dev/null +++ b/src/mainboard/asus/a88xm-e/bootblock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void sbxxx_enable_48mhzout(void) +{ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + u32 reg32; + reg32 = misc_read32(0x28); + reg32 &= ~(7 << 19); + reg32 |= (2 << 19); + misc_write32(0x28, reg32); + + /* Enable Auxiliary OSCOUT2 */ + misc_write32(0x40, misc_read32(0x40) & ~(1 << 7)); +} + +static void superio_init_m(void) +{ + const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +void bootblock_mainboard_early_init(void) +{ + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + superio_init_m(); +} diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c new file mode 100644 index 0000000000..25e7d3aed2 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Include the files that instantiate the configuration definitions. */ +#include +#include +#include +#include +/* AGESA nonsense: the next two headers depend on heapManager.h */ +#include +#include +/* These tables are optional and may be used to adjust memory timing settings */ +#include +#include + +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type */ +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE + +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE + +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto + +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Customized OEM build configurations for FCH component */ +#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE + +GPIO_CONTROL a88xm_e_gpio[] = { + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (a88xm_e_gpio) + +/* Moving this include up will break AGESA. */ +#include diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout new file mode 100644 index 0000000000..4839dd57b8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +#456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/a88xm-e/devicetree.cb b/src/mainboard/asus/a88xm-e/devicetree.cb new file mode 100644 index 0000000000..f427d0d88b --- /dev/null +++ b/src/mainboard/asus/a88xm-e/devicetree.cb @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia (iGPU Audio) + device pci 2.0 on end # PCIEX16 + device pci 3.0 off end # - + device pci 4.0 off end # PCIe x4 (?) + device pci 5.0 off end # PCIe x1 (?) + device pci 6.0 off end # PCIe x1 (?) + device pci 7.0 off end # PCIe x1 (?) + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA AHCI + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on end # SMBUS + device pci 14.1 off end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel Port + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 # SMI + io 0x62 = 0x300 # Simple I/O + io 0x64 = 0 # Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI bridge + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe RP0: PCIEX1_1 + device pci 15.1 off end # PCIe RP1: - + device pci 15.2 on end # PCIe RP2: Onboard Ethernet + device pci 15.3 off end # PCIe RP3: - + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ + { {0xA0, 0x00}, {0xA2, 0x00}, }, + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000000..a72fa36df7 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Describe the supported Sleep States for this Southbridge */ + #include + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c similarity index 82% rename from src/mainboard/lippert/toucan-af/irq_tables.c rename to src/mainboard/asus/a88xm-e/irq_tables.c index 5d2d253bfc..7ca1c4b951 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -1,15 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include -#include static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -27,24 +25,20 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; - u8 *v; u8 sum = 0; int i; /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + addr = ALIGN_UP(addr, 16); /* This table must be between 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); - v = (u8 *) (addr); pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; @@ -61,30 +55,30 @@ unsigned long write_pirq_routing_table(unsigned long addr) memset(pirq->rfu, 0, sizeof(pirq->rfu)); - pirq_info = (void *)(&pirq->checksum + 1); + pirq_info = (void *)(&pirq->slots); slot_num = 0; /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; pirq->size = 32 + 16 * slot_num; - for (i = 0; i < pirq->size; i++) - sum += v[i]; + { + const u8 *const v = (u8 *)(pirq); + for (i = 0; i < pirq->size; i++) + sum += v[i]; + } sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c new file mode 100644 index 0000000000..2e08188d15 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, +}; +static const u8 mainboard_intr_data[84] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* dedicated "enable" function (taken from thatcher) */ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); + + msr = rdmsr(LS_CFG_MSR); + /* Enable streaming store functionality. */ + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + /* Enable speculative TLB preloads. */ + msr.lo &= ~(1 << 4); + /* Enable the DC hardware prefetcher. */ + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + /* Disable the L2 way lock. */ + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c new file mode 100644 index 0000000000..b9e743c5f3 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ + bus_isa, (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan */ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /* Local Ints: Type IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c new file mode 100644 index 0000000000..a25195539a --- /dev/null +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void smbus_setup(void) +{ + post_code(0x30); + + /* turn on secondary smbus at b20 */ + pm_write8(0x28, pm_read8(0x28) | 0x01); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + smbus_setup(); +} diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index 6590883353..246c93fe2e 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -85,7 +85,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; - void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index 4cfa5b1c6a..6e71962cee 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index fe0915b8e5..d143cc3967 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -40,7 +40,7 @@ #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY /* FIXME: Turtle RAM? */ +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_ENABLE_ECC_FEATURE FALSE #define BLDCFG_ECC_SYNC_FLOOD FALSE diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout index 9f9ee80faa..40d77fda92 100644 --- a/src/mainboard/asus/am1i-a/cmos.layout +++ b/src/mainboard/asus/am1i-a/cmos.layout @@ -5,46 +5,45 @@ entries -#start-bit length config config-ID name -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_counter -#392 3 r 0 unused -#400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 r 0 boot_index -432 8 r 0 boot_countdown -440 8 e 10 sata_mode -448 8 e 11 sata_speed -#728 256 h 0 user_data -984 16 h 0 check_sum +#start-bit length config config-ID name +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_counter +#400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 r 0 boot_index +432 8 r 0 boot_countdown +440 8 e 10 sata_mode +448 8 e 11 sata_speed +#728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -#1 0 Disable -#1 1 Enable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -10 0 IDE -10 2 AHCI -11 1 3Gbps -11 0 6Gbps +#ID value text +#1 0 Disable +#1 1 Enable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +10 0 IDE +10 2 AHCI +11 1 3Gbps +11 0 6Gbps checksums diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 13e97dc73c..d5e1e18128 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 8413cd3863..326fedd9b6 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO + select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA @@ -83,7 +84,7 @@ config VGA_BIOS_ID config HUDSON_LEGACY_FREE bool - default y + default n config POST_IO bool diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 6b57711507..a69614fd47 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -51,6 +51,7 @@ #define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 #define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT2_PRESENT CONFIG(BOARD_ASUS_F2A85_M_PRO) GPIO_CONTROL f2a85_m_gpio[] = { {-1} diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 2aa2d89b08..830d3a8bcd 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -37,86 +37,71 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0x70 = 4 end device pnp 2e.3 off end # COM2/IR - device pnp 2e.5 off end # Keyboard + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 + irq 0x72 = 12 + end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - io 0xe0 = 0x7f - io 0xe1 = 0x10 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0xff - io 0xe5 = 0xff - io 0xe6 = 0xff - io 0xe7 = 0xff - io 0xec = 0x00 - io 0xed = 0xff - io 0xf4 = 0xff - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xf8 = 0x00 + irq 0xf4 = 0xff # GPIO6 i/o + + irq 0xe0 = 0x7f # GPIO7 i/o + irq 0xe1 = 0x00 # GPIO7 data end - device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - io 0x30 = 0x00 - io 0x60 = 0x00 - io 0x61 = 0x00 - io 0xe0 = 0xff - io 0xe1 = 0xff - io 0xe2 = 0xff - io 0xe3 = 0xff - io 0xe4 = 0xff - io 0xf0 = 0xff - io 0xf1 = 0x28 - io 0xf2 = 0x00 - io 0xf3 = 0x00 - io 0xf4 = 0x08 - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0xff + device pnp 2e.008 off # WDT1 end - device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - io 0x30 = 0xfe - io 0xe0 = 0xff - io 0xe1 = 0x90 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0x7f - io 0xe5 = 0x76 - io 0xe6 = 0x00 - io 0xe7 = 0x00 - io 0xe8 = 0x00 - io 0xe9 = 0x00 - io 0xea = 0x00 - io 0xeb = 0x00 - io 0xee = 0x00 - io 0xf0 = 0xff - io 0xf1 = 0x7b - io 0xf2 = 0x00 - io 0xf4 = 0xff - io 0xf5 = 0xef - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xfe = 0x00 + device pnp 2e.108 on # GPIO0, GPIO1 + irq 0xe0 = 0xff # GPIO0 i/o + irq 0xe2 = 0xff # GPIO0 inversion + irq 0xe4 = 0xff # GPIO0 multiplex + + irq 0xf0 = 0xff # GPIO1 i/o + irq 0xf4 = 0x08 # GPIO1 multiplex + + irq 0xf5 = 0xff # WDT1 control mode + irq 0xf6 = 0x00 # WDT1 counter + irq 0xf7 = 0xff # WDT1 control / status + end + device pnp 2e.009 off # GPIO8 + end + device pnp 2e.109 on # GPIO1 + end + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # GPIO2 i/o + end + device pnp 2e.309 on # GPIO3 + irq 0xe4 = 0x7f # GPIO3 i/o + irq 0xe5 = 0x00 # GPIO3 data + end + device pnp 2e.409 on # GPIO4 + irq 0xf0 = 0xff # GPIO4 i/o + end + device pnp 2e.509 on # GPIO5 + irq 0xf4 = 0xff # GPIO5 i/o + end + device pnp 2e.609 on # GPIO6 + end + device pnp 2e.709 on # GPIO7 end device pnp 2e.a on # ACPI - io 0xe6 = 0x4c - io 0xe7 = 0x11 - io 0xf2 = 0x5d + irq 0xe6 = 0x4c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x30 = 0x01 - io 0x60 = 0x02 - io 0x61 = 0x90 - io 0xe2 = 0x7f - io 0xe4 = 0xf1 + io 0x60 = 0x0290 + irq 0xe2 = 0x7f + irq 0xe4 = 0xf1 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off # GPIO Push-pull/Open-drain selection - io 0xe6 = 7f + device pnp 2e.f on # GPIO Push-pull/Open-drain selection + irq 0xe6 = 7f end - device pnp 2e.14 off # PORT80 UART - io 0xe0 = 0x00 + device pnp 2e.14 on # PORT80 UART + irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep end @@ -126,7 +111,9 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) device pci 15.0 on end # PCI bridge device pci 15.1 on end # PCI bridge - device pci 15.2 on end # PCI bridge # Only present with the original boot firmware + # FIXME: serial console stops working when enabling resources + # for 15.2, and payloads hang + device pci 15.2 off end # PCI bridge end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index 634a92861e..3f72eb105e 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc040..6b1c75ef50 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c deleted file mode 100644 index 852b0b4ae7..0000000000 --- a/src/mainboard/asus/h61m-cs/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout index 1860a78326..8c6a055ca3 100644 --- a/src/mainboard/asus/h61m-cs/cmos.layout +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -4,88 +4,61 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused +421 1 e 9 sata_mode # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index ea2a5d8c1a..60f8191f38 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index ded71a1548..38604c5583 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c deleted file mode 100644 index 14a79f87fb..0000000000 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout index c8c53e745c..54a379b770 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -4,95 +4,73 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 4 debug_level -#399 1 r 0 unused +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # coreboot config options: northbridge -412 3 e 7 gfx_uma_size +412 3 e 7 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index a0b631261b..7b901494db 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index 60d6dc5a63..ec3b9ea140 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20171231 /* OEM Revision */ diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 00295be947..1d3d3b9e0e 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -7,7 +7,6 @@ config BASE_ASUS_P2B_D select SDRAMPWR_4DIMM select HAVE_MP_TABLE select IOAPIC - select SMP config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index e1bda176a9..384f8de2b4 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -9,7 +9,15 @@ #define SUPERIO_SHOW_LPT #include -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 1 + ) { /* \_SB scope defining the main processor is generated in SSDT. */ diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c new file mode 100644 index 0000000000..87838b44c3 --- /dev/null +++ b/src/mainboard/asus/p2b/mainboard.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/** + * Mainboard specific enables. + * + * @param chip_info Ignored + */ +static void mainboard_init(void *chip_info) +{ + const pci_devfn_t px43 = PCI_DEV(0, 4, 3); + u32 reg; + /* + * Set up an 8-byte generic I/O decode block at device 9. + * This will be for W83781D hardware monitor. + * Port 0x290 mask 0x007 + * + * This should enable access to W83781D over the ISA bus. + */ + reg = pci_s_read_config32(px43, DEVRESB); + reg |= (0x290 | (0xe7 << 16)); + pci_s_write_config32(px43, DEVRESB, reg); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init +}; diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb index 541db02be6..77d3bb0419 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -3,8 +3,8 @@ chip northbridge/intel/i440bx # Northbridge chip southbridge/intel/i82371eb # Southbridge register "gpo" = "0x7fbfb9ff" register "gpo22_enable" = "1" # GPO22 controls LVD port termination (0=enabled) - # GPO23 controls SCSI-50 port termination (1=enabled) - # SCSI-68 port is always terminated + # GPO23 controls SCSI-50 port termination (1=enabled) + # SCSI-68 port is always terminated device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.a off # ACPI diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index ff3bbca46e..a0dc96e7c5 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_512 select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c deleted file mode 100644 index 496d4190c6..0000000000 --- a/src/mainboard/asus/p5gc-mx/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index a7c4b7dba7..08fe2255c1 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -2,72 +2,65 @@ # ----------------------------------------------------------------- entries -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi +408 1 e 1 nmi # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 4c26925838..172f65f653 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -25,14 +25,14 @@ chip northbridge/intel/i945 end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x86" - register "pirqd_routing" = "0x85" - register "pirqe_routing" = "0x83" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" + register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x85" + register "pirqh_routing" = "0x80" register "gpe0_en" = "0" diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 0a9ab0fe41..4e43cc47c3 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 65db55f5cb..0d0b24c55f 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index 79f7347410..2b46a5f790 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -4,78 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -#432 554 r 0 unused # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -10 0 AHCI -10 1 Compatible +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index cd885c8f05..fa8820855e 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00000001 // OEM revision diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index 4f59ed01f8..e678bab773 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -4,7 +4,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout index e98886258b..70f29b7a3b 100644 --- a/src/mainboard/asus/p5ql-em/cmos.layout +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -4,64 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -#408 1 e 0 unused -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#436 548 r 0 unused +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl index 2981dc6326..e0290979af 100644 --- a/src/mainboard/asus/p5ql-em/dsdt.asl +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00000001 // OEM revision diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index 9eef15936a..7206526637 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index 4905f1d133..11a078e35c 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -4,85 +4,59 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 069800ade8..a108c3bc0c 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -17,8 +17,8 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select USE_NATIVE_RAMINIT config MAINBOARD_DIR diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c deleted file mode 100644 index 14a79f87fb..0000000000 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout index 2aef2ac876..782a1b8c10 100644 --- a/src/mainboard/asus/p8h61-m_lx/cmos.layout +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -4,90 +4,68 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 4 debug_level -#399 1 r 0 unused +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # coreboot config options: northbridge -412 3 e 7 gfx_uma_size +412 3 e 7 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index 4a29baa579..eddca8144c 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index 60d6dc5a63..ec3b9ea140 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20171231 /* OEM Revision */ diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb index 757c5ccde8..317f9cc22b 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl index fba6cc78eb..f83653051f 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout index 1860a78326..8c6a055ca3 100644 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ b/src/mainboard/asus/p8h61-m_pro/cmos.layout @@ -4,88 +4,61 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused +421 1 e 9 sata_mode # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index b318573b40..969169c139 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 01d1fe633d..6a248b24dd 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index e401b656fa..c1da5cb843 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* critical temp that will shutdown the pc == 95C degrees */ gnvs->tcrt = 95; diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index 1b82ffde13..3d717b444d 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -4,49 +4,27 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 4 debug_level -#399 1 r 0 unused -#400 8 r 0 reserved for century byte +395 4 e 4 debug_level +#400 8 r 0 reserved for century byte # ----------------------------------------------------------------- # coreboot config options: southbridge # Non Maskable Interrupt(NMI) support, which is an interrupt that may # occur on a RAM or unrecoverable error. -408 1 e 1 nmi +408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # ----------------------------------------------------------------- # coreboot config options: northbridge @@ -54,119 +32,119 @@ entries # gfx_uma_size # Quantity of shared video memory the IGP can use # -416 5 e 7 gfx_uma_size +416 5 e 7 gfx_uma_size # ----------------------------------------------------------------- # coreboot config options: usb3 # usb3_mode # Controls how the motherboard's USB3 ports act at boot time -421 2 e 8 usb3_mode +421 2 e 8 usb3_mode # usb3_drv # Load (or not) pre-OS xHCI USB3 BIOS driver # -423 1 e 1 usb3_drv +423 1 e 1 usb3_drv # usb3_streams # Streams can provide more speed (as they can use 64Kb packets), # but they might cause incompatibilities with some devices. # -424 1 e 1 usb3_streams +424 1 e 1 usb3_streams # ----------------------------------------------------------------- # Sandy/Ivy Bridge MRC Scrambler Seed values # note: MUST NOT be covered by checksum! -464 32 r 0 mrc_scrambler_seed -496 32 r 0 mrc_scrambler_seed_s3 -528 16 r 0 mrc_scrambler_seed_chk +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk # ----------------------------------------------------------------- # coreboot config options: check sums -544 16 h 0 check_sum +544 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text +#ID value text # Generic on/off enum -1 0 Disable -1 1 Enable +1 0 Disable +1 1 Enable # boot_option -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal # debug_level -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew # power_on_after_fail -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep # sata_mode -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible # gfx_uma_size (Intel IGP Video RAM size) -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M -7 7 256M -7 8 288M -7 9 320M -7 10 352M -7 11 384M -7 12 416M -7 13 448M -7 14 480M -7 15 512M -7 16 544M -7 17 576M -7 18 608M -7 19 640M -7 20 672M -7 21 704M -7 22 736M -7 23 768M -7 24 800M -7 25 832M -7 26 864M -7 27 896M -7 28 928M -7 29 960M -7 30 992M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 544M +7 17 576M +7 18 608M +7 19 640M +7 20 672M +7 21 704M +7 22 736M +7 23 768M +7 24 800M +7 25 832M +7 26 864M +7 27 896M +7 28 928M +7 29 960M +7 30 992M # usb3_mode # Disable = Use the port always as USB 2.0 for compatibility # Enable = Use the port always as USB 3.0 for speed # Auto = Initialize the port as USB 2.0, until the OS loads -# xHCI USB 3.0 driver +# xHCI USB 3.0 driver # SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver -# and the computer is reset, keep the USB 3.0 mode. +# and the computer is reset, keep the USB 3.0 mode. # -8 0 Disable -8 1 Enable -8 2 Auto -8 3 SmartAuto +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto # ----------------------------------------------------------------- # -# +# checksums checksum 392 431 544 diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index 90feb7ac6c..1d1a244b9f 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index a5ab91d611..ba58cf2412 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 87da010aa4..81eb6f474c 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,15 +85,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 33ff961522..0fc6dc15b7 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index 6fa3b5576c..c49090e154 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 3503e65cef..bea756a1b3 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select GFXUMA select SUPERIO_FINTEK_F81866D + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 5e83e6586f..4e2884aaaa 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -10,22 +10,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex similarity index 100% rename from src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex rename to src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex similarity index 100% rename from src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex rename to src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 1122c43563..ae502cb9dc 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -11,7 +11,6 @@ endchoice source "src/mainboard/biostar/*/Kconfig" - config MAINBOARD_VENDOR default "Biostar" diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index de8845a977..5803e03783 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -38,7 +38,6 @@ const CODEC_ENTRY Alc662_VerbTbl[] = { 0xff, 0xffffffff } }; - static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0662, (CODEC_ENTRY*)&Alc662_VerbTbl[0]}, diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 9de2813f8e..1d94b5bcb4 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -85,7 +85,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; - void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 5c0f1938fc..56f760de40 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -2,7 +2,6 @@ /* No IDE functionality */ - /* Scope (_SB) { Device(PCI0) { diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/biostar/am1ml/acpi/routing.asl +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index a3e8c518ea..d1a4ee72c7 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - - /* Scope (_SB) { Device(PCI0) { diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c index 688f25d129..405271b064 100644 --- a/src/mainboard/biostar/am1ml/bootblock.c +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -14,13 +15,13 @@ static void ite_evc_conf(pnp_devfn_t dev) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); + pnp_write_config(dev, PNP_IDX_MSC1, 0x40); + pnp_write_config(dev, PNP_IDX_MSC4, 0x80); + pnp_write_config(dev, PNP_IDX_MSC5, 0x00); + pnp_write_config(dev, PNP_IDX_MSC6, 0xf0); + pnp_write_config(dev, PNP_IDX_MSC9, 0x48); + pnp_write_config(dev, PNP_IDX_MSCA, 0x00); + pnp_write_config(dev, PNP_IDX_MSCB, 0x00); pnp_exit_conf_state(dev); } @@ -32,7 +33,7 @@ static void ite_gpio_conf(pnp_devfn_t dev) pnp_write_config(dev, 0x26, 0x07); pnp_write_config(dev, 0x28, 0x81); pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, PNP_IDX_IRQ1, 0x00); pnp_write_config(dev, 0x73, 0x00); pnp_write_config(dev, 0xb3, 0x01); pnp_write_config(dev, 0xb8, 0x00); @@ -41,10 +42,10 @@ static void ite_gpio_conf(pnp_devfn_t dev) pnp_write_config(dev, 0xc8, 0x00); pnp_write_config(dev, 0xc9, 0x07); pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); + pnp_write_config(dev, PNP_IDX_MSC0, 0x10); + pnp_write_config(dev, PNP_IDX_MSC4, 0x27); + pnp_write_config(dev, PNP_IDX_MSC8, 0x20); + pnp_write_config(dev, PNP_IDX_MSC9, 0x01); pnp_exit_conf_state(dev); } diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 461561d2e0..808bacec7c 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -11,7 +11,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE //#define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index 0cf4ede05a..7430eb0389 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -5,85 +5,84 @@ entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -386 1 e 1 ECC_memory -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +386 1 e 1 ECC_memory +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 01502b2839..e8b99f4018 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index a85f71544c..cc5f34f398 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #include const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/biostar/th61-itx/Kconfig b/src/mainboard/biostar/th61-itx/Kconfig new file mode 100644 index 0000000000..2719853449 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Kconfig @@ -0,0 +1,33 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_BIOSTAR_TH61_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NO_UART_ON_SUPERIO + +config MAINBOARD_DIR + string + default "biostar/th61-itx" + +config MAINBOARD_PART_NUMBER + string + default "TH61-ITX" + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_BIOSTAR_TH61_ITX diff --git a/src/mainboard/biostar/th61-itx/Kconfig.name b/src/mainboard/biostar/th61-itx/Kconfig.name new file mode 100644 index 0000000000..fecf255b81 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BIOSTAR_TH61_ITX + bool "TH61-ITX" diff --git a/src/mainboard/biostar/th61-itx/Makefile.inc b/src/mainboard/biostar/th61-itx/Makefile.inc new file mode 100644 index 0000000000..549a84fd12 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/biostar/th61-itx/acpi/ec.asl b/src/mainboard/biostar/th61-itx/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/biostar/th61-itx/acpi/platform.asl b/src/mainboard/biostar/th61-itx/acpi/platform.asl new file mode 100644 index 0000000000..bbee0a2787 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/biostar/th61-itx/acpi/superio.asl b/src/mainboard/biostar/th61-itx/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/biostar/th61-itx/board_info.txt b/src/mainboard/biostar/th61-itx/board_info.txt new file mode 100644 index 0000000000..4832134217 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://biostar-usa.com/app/en-us/mb/introduction.php?S_ID=548 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/biostar/th61-itx/cmos.default b/src/mainboard/biostar/th61-itx/cmos.default new file mode 100644 index 0000000000..6f3cec735e --- /dev/null +++ b/src/mainboard/biostar/th61-itx/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/biostar/th61-itx/cmos.layout b/src/mainboard/biostar/th61-itx/cmos.layout new file mode 100644 index 0000000000..483512ed07 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- + +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +421 1 e 9 sata_mode + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/biostar/th61-itx/data.vbt b/src/mainboard/biostar/th61-itx/data.vbt new file mode 100644 index 0000000000..f2ec2fcfb0 Binary files /dev/null and b/src/mainboard/biostar/th61-itx/data.vbt differ diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb new file mode 100644 index 0000000000..118a58eab4 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -0,0 +1,76 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1565 0x3108 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: Realtek RTL8111F GbE NIC + device pci 1c.1 on end # RP #2: ASMedia ASM1042 USB3 #1 + device pci 1c.2 on end # RP #3: ASMedia ASM1042 USB3 #2 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on end # Keyboard + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x26 = 0xff + irq 0x27 = 0x30 + irq 0x28 = 0x80 + irq 0x29 = 0x80 + irq 0x2c = 0x02 + io 0x60 = 0x0a10 + io 0x62 = 0x0a00 + irq 0xb1 = 0x03 + irq 0xb3 = 0x80 + irq 0xb8 = 0x00 + irq 0xf5 = 0x27 + irq 0xf8 = 0x20 + irq 0xf9 = 0x01 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA #1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA #2 (IDE mode) + device pci 1f.6 on end # Thermal subsystem + end + end +end diff --git a/src/mainboard/biostar/th61-itx/dsdt.asl b/src/mainboard/biostar/th61-itx/dsdt.asl new file mode 100644 index 0000000000..60a74677fb --- /dev/null +++ b/src/mainboard/biostar/th61-itx/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include + #include + + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c new file mode 100644 index 0000000000..b1a99e0ee8 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/biostar/th61-itx/gma-mainboard.ads b/src/mainboard/biostar/th61-itx/gma-mainboard.ads new file mode 100644 index 0000000000..81097a67f7 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + -- TODO: verify this with a CPU that has an IGP + ports : constant Port_List := + (HDMI1, -- DVI + HDMI2, -- HDMI + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/biostar/th61-itx/gpio.c b/src/mainboard/biostar/th61-itx/gpio.c new file mode 100644 index 0000000000..bda5328777 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/gpio.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/biostar/th61-itx/hda_verb.c b/src/mainboard/biostar/th61-itx/hda_verb.c new file mode 100644 index 0000000000..2b6d27604d --- /dev/null +++ b/src/mainboard/biostar/th61-itx/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Realtek ALC892 */ + 0x15658229, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x15658229), + AZALIA_PIN_CFG(2, 0x11, 0x01452130), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x01011412), + AZALIA_PIN_CFG(2, 0x16, 0x01016411), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c40), + AZALIA_PIN_CFG(2, 0x19, 0x02a19850), + AZALIA_PIN_CFG(2, 0x1a, 0x0181344f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/bostentech/Kconfig b/src/mainboard/bostentech/Kconfig new file mode 100644 index 0000000000..15a7657faa --- /dev/null +++ b/src/mainboard/bostentech/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_BOSTENTECH + +choice + prompt "Mainboard model" + +source "src/mainboard/bostentech/*/Kconfig.name" + +endchoice + +source "src/mainboard/bostentech/*/Kconfig" + +config MAINBOARD_VENDOR + default "Shenzhen Bostrontium Teng Technology" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_BOSTENTECH diff --git a/src/mainboard/bostentech/Kconfig.name b/src/mainboard/bostentech/Kconfig.name new file mode 100644 index 0000000000..619b526924 --- /dev/null +++ b/src/mainboard/bostentech/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BOSTENTECH + bool "Shenzhen Bostrontium Teng Technology" diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig new file mode 100644 index 0000000000..a26784062a --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_BOSTENTECH_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "bostentech/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4-4L" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Shenzhen Bostrontium Teng Technology" + +endif # BOARD_BOSTENTECH_GBYT4 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig.name b/src/mainboard/bostentech/gbyt4/Kconfig.name new file mode 100644 index 0000000000..c420d5b201 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BOSTENTECH_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc new file mode 100644 index 0000000000..11a2a4a506 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/bostentech/gbyt4/acpi/ec.asl b/src/mainboard/bostentech/gbyt4/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000000..d679d2e2bb --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NOTE: this has to be here even when the board has no LPE audio, otherwise + * it breaks the SOC specific ACPI code + */ +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () {}) +} diff --git a/src/mainboard/bostentech/gbyt4/acpi/superio.asl b/src/mainboard/bostentech/gbyt4/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c new file mode 100644 index 0000000000..dc0d7a2873 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM not present */ + gnvs->tpmp = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_DESKTOP; +} diff --git a/src/mainboard/bostentech/gbyt4/board_info.txt b/src/mainboard/bostentech/gbyt4/board_info.txt new file mode 100644 index 0000000000..0fe176f778 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Shenzhen Bostrontium Teng Technology +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/bostentech/gbyt4/cmos.layout b/src/mainboard/bostentech/gbyt4/cmos.layout new file mode 100644 index 0000000000..018db314ac --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/cmos.layout @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +# coreboot config options: cpu +400 1 e 2 hyper_threading +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb new file mode 100644 index 0000000000..15a5d861da --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -0,0 +1,90 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x3" + register "sata_ahci" = "0x1" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/bostentech/gbyt4/dsdt.asl b/src/mainboard/bostentech/gbyt4/dsdt.asl new file mode 100644 index 0000000000..5d9a8de8f5 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + + // global NVS and variables + #include + #include + + Device (\_SB.PCI0) + { + #include + } + + #include + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/bostentech/gbyt4/early_init.c b/src/mainboard/bostentech/gbyt4/early_init.c new file mode 100644 index 0000000000..9b12a3d2fd --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/early_init.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bostentech/gbyt4/gpio.c b/src/mainboard/bostentech/gbyt4/gpio.c new file mode 100644 index 0000000000..e1d5df8bbb --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gpio.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_NC[00] */ + GPIO_INPUT, /* GPIO_S0_NC[01] */ + GPIO_INPUT, /* GPIO_S0_NC[02] */ + GPIO_INPUT, /* GPIO_S0_NC[03] */ + GPIO_INPUT, /* GPIO_S0_NC[04] */ + GPIO_INPUT, /* GPIO_S0_NC[05] */ + GPIO_INPUT, /* GPIO_S0_NC[06] */ + GPIO_INPUT, /* GPIO_S0_NC[07] */ + GPIO_INPUT, /* GPIO_S0_NC[08] */ + GPIO_INPUT, /* GPIO_S0_NC[09] */ + GPIO_INPUT, /* GPIO_S0_NC[10] */ + GPIO_INPUT, /* GPIO_S0_NC[11] */ + GPIO_INPUT, /* GPIO_S0_NC[12] */ + GPIO_INPUT, /* GPIO_S0_NC[13] */ + GPIO_INPUT, /* GPIO_S0_NC[14] */ + GPIO_INPUT, /* GPIO_S0_NC[15] */ + GPIO_INPUT, /* GPIO_S0_NC[16] */ + GPIO_INPUT, /* GPIO_S0_NC[17] */ + GPIO_INPUT, /* GPIO_S0_NC[18] */ + GPIO_INPUT, /* GPIO_S0_NC[19] */ + GPIO_INPUT, /* GPIO_S0_NC[20] */ + GPIO_INPUT, /* GPIO_S0_NC[21] */ + GPIO_INPUT, /* GPIO_S0_NC[22] */ + GPIO_INPUT, /* GPIO_S0_NC[23] */ + GPIO_INPUT, /* GPIO_S0_NC[24] */ + GPIO_INPUT, /* GPIO_S0_NC[25] */ + GPIO_INPUT, /* GPIO_S0_NC[26] */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_SC[000] */ + GPIO_INPUT, /* GPIO_S0_SC[001] */ + GPIO_FUNC1, /* SATA_LED# */ + GPIO_FUNC1, /* PCIE_CLKREQ[0]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[1]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[2]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[3]# */ + GPIO_INPUT, /* GPIO_S0_SC[007] */ + GPIO_INPUT, /* GPIO_S0_SC[008] */ + GPIO_INPUT, /* GPIO_S0_SC[009] */ + GPIO_INPUT, /* GPIO_S0_SC[010] */ + GPIO_INPUT, /* GPIO_S0_SC[011] */ + GPIO_INPUT, /* GPIO_S0_SC[012] */ + GPIO_INPUT, /* GPIO_S0_SC[013] */ + GPIO_INPUT, /* GPIO_S0_SC[014] */ + GPIO_INPUT, /* GPIO_S0_SC[015] */ + GPIO_INPUT, /* GPIO_S0_SC[016] */ + GPIO_INPUT, /* GPIO_S0_SC[017] */ + GPIO_INPUT, /* GPIO_S0_SC[018] */ + GPIO_INPUT, /* GPIO_S0_SC[019] */ + GPIO_INPUT, /* GPIO_S0_SC[020] */ + GPIO_INPUT, /* GPIO_S0_SC[021] */ + GPIO_INPUT, /* GPIO_S0_SC[022] */ + GPIO_INPUT, /* GPIO_S0_SC[023] */ + GPIO_INPUT, /* GPIO_S0_SC[024] */ + GPIO_INPUT, /* GPIO_S0_SC[025] */ + GPIO_INPUT, /* GPIO_S0_SC[026] */ + GPIO_INPUT, /* GPIO_S0_SC[027] */ + GPIO_INPUT, /* GPIO_S0_SC[028] */ + GPIO_INPUT, /* GPIO_S0_SC[029] */ + GPIO_INPUT, /* GPIO_S0_SC[030] */ + GPIO_INPUT, /* GPIO_S0_SC[031] */ + GPIO_INPUT, /* GPIO_S0_SC[032] */ + GPIO_INPUT, /* GPIO_S0_SC[033] */ + GPIO_INPUT, /* GPIO_S0_SC[034] */ + GPIO_INPUT, /* GPIO_S0_SC[035] */ + GPIO_INPUT, /* GPIO_S0_SC[036] */ + GPIO_INPUT, /* GPIO_S0_SC[037] */ + GPIO_INPUT, /* GPIO_S0_SC[038] */ + GPIO_INPUT, /* GPIO_S0_SC[039] */ + GPIO_INPUT, /* GPIO_S0_SC[040] */ + GPIO_INPUT, /* GPIO_S0_SC[041] */ + GPIO_FUNC1, /* ILB_LPC_AD[0] */ + GPIO_FUNC1, /* ILB_LPC_AD[1] */ + GPIO_FUNC1, /* ILB_LPC_AD[2] */ + GPIO_FUNC1, /* ILB_LPC_AD[3] */ + GPIO_FUNC1, /* ILB_LPC_FRAME# */ + GPIO_FUNC1, /* ILB_LPC_CLK[0] */ + GPIO_FUNC1, /* ILB_LPC_CLK[1] */ + GPIO_FUNC1, /* ILB_LPC_CLKRUN# */ + GPIO_FUNC1, /* ILB_LPC_SERIRQ */ + GPIO_FUNC1, /* PCU_SMB_DATA */ + GPIO_FUNC1, /* PCU_SMB_CLK */ + GPIO_FUNC1, /* PCU_SMB_ALERT# */ + GPIO_FUNC1, /* ILB_8254_SPKR */ + GPIO_INPUT, /* GPIO_S0_SC[055] */ + GPIO_INPUT, /* GPIO_S0_SC[056] */ + GPIO_INPUT, /* GPIO_S0_SC[057] */ + GPIO_INPUT, /* GPIO_S0_SC[058] */ + GPIO_INPUT, /* GPIO_S0_SC[059] */ + GPIO_INPUT, /* GPIO_S0_SC[060] */ + GPIO_INPUT, /* GPIO_S0_SC[061] */ + GPIO_INPUT, /* GPIO_S0_SC[062] */ + GPIO_INPUT, /* GPIO_S0_SC[063] */ + GPIO_INPUT, /* GPIO_S0_SC[064] */ + GPIO_INPUT, /* GPIO_S0_SC[065] */ + GPIO_INPUT, /* GPIO_S0_SC[066] */ + GPIO_INPUT, /* GPIO_S0_SC[067] */ + GPIO_INPUT, /* GPIO_S0_SC[068] */ + GPIO_INPUT, /* GPIO_S0_SC[069] */ + GPIO_INPUT, /* GPIO_S0_SC[070] */ + GPIO_INPUT, /* GPIO_S0_SC[071] */ + GPIO_INPUT, /* GPIO_S0_SC[072] */ + GPIO_INPUT, /* GPIO_S0_SC[073] */ + GPIO_INPUT, /* GPIO_S0_SC[074] */ + GPIO_INPUT, /* GPIO_S0_SC[075] */ + GPIO_INPUT, /* GPIO_S0_SC[076] */ + GPIO_INPUT, /* GPIO_S0_SC[077] */ + GPIO_INPUT, /* GPIO_S0_SC[078] */ + GPIO_INPUT, /* GPIO_S0_SC[079] */ + GPIO_INPUT, /* GPIO_S0_SC[080] */ + GPIO_INPUT, /* GPIO_S0_SC[081] */ + GPIO_INPUT, /* GPIO_S0_SC[082] */ + GPIO_INPUT, /* GPIO_S0_SC[083] */ + GPIO_INPUT, /* GPIO_S0_SC[084] */ + GPIO_INPUT, /* GPIO_S0_SC[085] */ + GPIO_INPUT, /* GPIO_S0_SC[086] */ + GPIO_INPUT, /* GPIO_S0_SC[087] */ + GPIO_INPUT, /* GPIO_S0_SC[088] */ + GPIO_INPUT, /* GPIO_S0_SC[089] */ + GPIO_INPUT, /* GPIO_S0_SC[090] */ + GPIO_INPUT, /* GPIO_S0_SC[091] */ + GPIO_INPUT, /* GPIO_S0_SC[092] */ + GPIO_INPUT, /* GPIO_S0_SC[093] */ + GPIO_INPUT, /* GPIO_S0_SC[094] */ + GPIO_INPUT, /* GPIO_S0_SC[095] */ + GPIO_INPUT, /* GPIO_S0_SC[096] */ + GPIO_INPUT, /* GPIO_S0_SC[097] */ + GPIO_INPUT, /* GPIO_S0_SC[098] */ + GPIO_INPUT, /* GPIO_S0_SC[099] */ + GPIO_INPUT, /* GPIO_S0_SC[100] */ + GPIO_INPUT, /* GPIO_S0_SC[101] */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_INPUT, /* GPIO_S5[00] */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[1]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[2]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[3]# */ + GPIO_INPUT, /* GPIO_S5[04] */ + GPIO_INPUT, /* GPIO_S5[05] */ + GPIO_INPUT, /* GPIO_S5[06] */ + GPIO_INPUT, /* GPIO_S5[07] */ + GPIO_INPUT, /* GPIO_S5[08] */ + GPIO_INPUT, /* GPIO_S5[09] */ + GPIO_INPUT, /* GPIO_S5[10] */ + GPIO_INPUT, /* GPIO_S5[11] */ + GPIO_INPUT, /* GPIO_S5[12] */ + GPIO_INPUT, /* GPIO_S5[13] */ + GPIO_INPUT, /* GPIO_S5[14] */ + GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# */ + GPIO_FUNC(0, PULL_UP, 20K), /* PMC_PWRBTN# */ + GPIO_INPUT, /* GPIO_S5[17] */ + GPIO_INPUT, /* GPIO_S5[18] */ + GPIO_INPUT, /* GPIO_S5[19] */ + GPIO_INPUT, /* GPIO_S5[20] */ + GPIO_INPUT, /* GPIO_S5[21] */ + GPIO_INPUT, /* GPIO_S5[22] */ + GPIO_INPUT, /* GPIO_S5[23] */ + GPIO_INPUT, /* GPIO_S5[24] */ + GPIO_INPUT, /* GPIO_S5[25] */ + GPIO_INPUT, /* GPIO_S5[26] */ + GPIO_INPUT, /* GPIO_S5[27] */ + GPIO_INPUT, /* GPIO_S5[28] */ + GPIO_INPUT, /* GPIO_S5[29] */ + GPIO_INPUT, /* GPIO_S5[30] */ + GPIO_INPUT, /* GPIO_S5[31] */ + GPIO_INPUT, /* GPIO_S5[32] */ + GPIO_INPUT, /* GPIO_S5[33] */ + GPIO_INPUT, /* GPIO_S5[34] */ + GPIO_INPUT, /* GPIO_S5[35] */ + GPIO_INPUT, /* GPIO_S5[36] */ + GPIO_INPUT, /* GPIO_S5[37] */ + GPIO_INPUT, /* GPIO_S5[38] */ + GPIO_INPUT, /* GPIO_S5[39] */ + GPIO_INPUT, /* GPIO_S5[40] */ + GPIO_INPUT, /* GPIO_S5[41] */ + GPIO_INPUT, /* GPIO_S5[42] */ + GPIO_INPUT, /* GPIO_S5[43] */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl b/src/mainboard/bostentech/gbyt4/irqroute.c similarity index 51% rename from src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl rename to src/mainboard/bostentech/gbyt4/irqroute.c index 318b0dea04..6fa036672e 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl +++ b/src/mainboard/bostentech/gbyt4/irqroute.c @@ -1,3 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/bostentech/gbyt4/irqroute.h b/src/mainboard/bostentech/gbyt4/irqroute.h new file mode 100644 index 0000000000..946062270d --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/irqroute.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/bostentech/gbyt4/mainboard.c b/src/mainboard/bostentech/gbyt4/mainboard.c new file mode 100644 index 0000000000..d0131bc2d1 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/mainboard.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#if CONFIG(VGA_ROM_RUN) +#include +#endif +#include + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bostentech/gbyt4/romstage.c b/src/mainboard/bostentech/gbyt4/romstage.c new file mode 100644 index 0000000000..ec18cfc05b --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_SMBUS; + mp->mainboard.dram_is_slotted = 1; + mp->mainboard.spd_addrs[0] = 0x50; /* Board only has one slot */ +} diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig new file mode 100644 index 0000000000..1c95d2b420 --- /dev/null +++ b/src/mainboard/clevo/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_CLEVO + +choice + prompt "Mainboard model" + +source "src/mainboard/clevo/*/Kconfig.name" + +endchoice + +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + default "Clevo" + +endif # VENDOR_CLEVO diff --git a/src/mainboard/clevo/Kconfig.name b/src/mainboard/clevo/Kconfig.name new file mode 100644 index 0000000000..730b6bc389 --- /dev/null +++ b/src/mainboard/clevo/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CLEVO + bool "Clevo" diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig new file mode 100644 index 0000000000..5653fb4365 --- /dev/null +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -0,0 +1,90 @@ +config BOARD_CLEVO_CMLU_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_CLEVO_L140CU_OPTIONS + bool + select BOARD_CLEVO_CMLU_COMMON + select EC_SYSTEM76_EC + select HAVE_SPD_IN_CBFS + +if BOARD_CLEVO_CMLU_COMMON + +config MAINBOARD_DIR + string + default "clevo/cml-u" + +config MAINBOARD_PART_NUMBER + string + default "L140CU" if BOARD_CLEVO_L140CU + +config MAINBOARD_VERSION + string + default "2.1A" if BOARD_CLEVO_L140CU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + hex + default 0xc00000 if BOARD_CLEVO_L140CU + +config CONSOLE_POST + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 if BOARD_CLEVO_L140CU + +config DIMM_MAX + int + default 2 if BOARD_CLEVO_L140CU + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,9b41" + +config TPM_PIRQ + hex + default 0x10 if BOARD_CLEVO_L140CU # GPP_A7/PIRQA# + +config POST_DEVICE + bool + default n + +config VARIANT_DIR + string + default "l140cu" if BOARD_CLEVO_L140CU + +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 500 + +endif diff --git a/src/mainboard/clevo/cml-u/Kconfig.name b/src/mainboard/clevo/cml-u/Kconfig.name new file mode 100644 index 0000000000..92555ffd95 --- /dev/null +++ b/src/mainboard/clevo/cml-u/Kconfig.name @@ -0,0 +1,5 @@ +comment "Comet Lake U" + +config BOARD_CLEVO_L140CU + bool "L140CU / L141CU" + select BOARD_CLEVO_L140CU_OPTIONS diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc new file mode 100644 index 0000000000..213e62f1ee --- /dev/null +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -0,0 +1,11 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/system76/kbl-u/acpi/gpe.asl b/src/mainboard/clevo/cml-u/acpi/gpe.asl similarity index 59% rename from src/mainboard/system76/kbl-u/acpi/gpe.asl rename to src/mainboard/clevo/cml-u/acpi/gpe.asl index 986a46c5ba..c1bc04dc9a 100644 --- a/src/mainboard/system76/kbl-u/acpi/gpe.asl +++ b/src/mainboard/clevo/cml-u/acpi/gpe.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// GPP_C19 SCI -Method (_L13, 0, Serialized) { - Debug = Concatenate("GPE _L13: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) If (\_SB.PCI0.LPCB.EC0.ECOK) { If (\_SB.PCI0.LPCB.EC0.WFNO == One) { Notify(\_SB.LID0, 0x80) diff --git a/src/mainboard/clevo/cml-u/acpi/mainboard.asl b/src/mainboard/clevo/cml-u/acpi/mainboard.asl new file mode 100644 index 0000000000..dfa81d3914 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/mainboard.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x50 /* GPP_E16 */ +#define EC_GPE_SWI 0x29 /* GPP_D9 */ +#define EC_COLOR_KEYBOARD 0 +#include + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/kbl-u/acpi/sleep.asl b/src/mainboard/clevo/cml-u/acpi/sleep.asl similarity index 100% rename from src/mainboard/system76/kbl-u/acpi/sleep.asl rename to src/mainboard/clevo/cml-u/acpi/sleep.asl diff --git a/src/mainboard/clevo/cml-u/board_info.txt b/src/mainboard/clevo/cml-u/board_info.txt new file mode 100644 index 0000000000..67109938da --- /dev/null +++ b/src/mainboard/clevo/cml-u/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c new file mode 100644 index 0000000000..0b5965a905 --- /dev/null +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default new file mode 100644 index 0000000000..f3330e5070 --- /dev/null +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout new file mode 100644 index 0000000000..45ddff109f --- /dev/null +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +410 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# vboot nv area +800 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 799 984 diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl new file mode 100644 index 0000000000..05e297b206 --- /dev/null +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/clevo/cml-u/include/variant/gpio.h b/src/mainboard/clevo/cml-u/include/variant/gpio.h new file mode 100644 index 0000000000..95d576294f --- /dev/null +++ b/src/mainboard/clevo/cml-u/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/cml-u/ramstage.c b/src/mainboard/clevo/cml-u/ramstage.c new file mode 100644 index 0000000000..8196970d6e --- /dev/null +++ b/src/mainboard/clevo/cml-u/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void init_mainboard(void *chip_info) +{ + variant_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex similarity index 89% rename from src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex rename to src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex index 390e5a5417..f747f7c34e 100644 --- a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex +++ b/src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex @@ -1,12 +1,12 @@ -# Samsung K4AAG165WA-BCWE +# Samsung K4AAG165WA-BCTD 23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A 20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B 0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -20,7 +20,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 -35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc new file mode 100644 index 0000000000..0e47d8680f --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += romstage.c +SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt b/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt new file mode 100644 index 0000000000..86230320af --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt @@ -0,0 +1,2 @@ +Board name: L140CU +Release year: 2020 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt b/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt new file mode 100644 index 0000000000..f14d8073e9 Binary files /dev/null and b/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt differ diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb new file mode 100644 index 0000000000..4a93065e76 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -0,0 +1,211 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + /* Touchpad */ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + #register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x1401 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_pwm_hz = 1000, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + }" + end + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""ELAN040D"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 2 (J_SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 3 (J_SSD1) + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 Card reader + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 + chip drivers/wifi/generic + device pci 00.0 on end + end + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0e01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0f01" + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads new file mode 100644 index 0000000000..8402b39a94 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c new file mode 100644 index 0000000000..e567ef79d1 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Name format: / */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */ + PAD_NC(GPD2, UP_20K), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */ + PAD_NC(GPD6, UP_20K), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */ + PAD_NC(GPD9, UP_20K), + PAD_NC(GPD10, UP_20K), + PAD_NC(GPD11, UP_20K), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* RCIN# / SB_KBCRST# */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LAD0 / LPC_AD0 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LAD1 / LPC_AD1 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LAD2 / LPC_AD2 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LAD3 / LPC_AD3 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LFRAME# / LPC_FRAME# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PIRQA# / TPM_PIRQ# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# / PM_CLKRUN# + Note: R209 is populated despite being + marked no-stuff in schematic + */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* CLKOUT_LPC0 / PCLK_KBC */ + PAD_NC(GPP_A10, UP_20K), + PAD_NC(GPP_A11, UP_20K), /* INTP_OUT + (Type-C VBUS_SENSE; unused in cb) + */ + PAD_NC(GPP_A12, UP_20K), + PAD_NC(GPP_A13, UP_20K), /* SUSWARN# + (unused due to missing DeepSx support) + */ + PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A15, UP_20K), + PAD_NC(GPP_A16, UP_20K), + PAD_NC(GPP_A17, NONE), /* LEDKB_DET# + (unused in cb; all devices of that + model have KB LED) + */ + PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A19, UP_20K), + PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_A20 / TEST_R */ + PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A22, UP_20K), + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, UP_20K), + PAD_NC(GPP_B1, UP_20K), + PAD_NC(GPP_B2, UP_20K), /* CNVI_WAKE# + (UART_WAKE# in M.2 spec; unused) + */ + PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST), /* GPP_B3 (touchpad interrupt) */ + PAD_NC(GPP_B4, UP_20K), + PAD_NC(GPP_B5, UP_20K), + PAD_NC(GPP_B6, UP_20K), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# / WLAN_CLKREQ# */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3# / CARD_CLKREQ# */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# / SSD2_CLKREQ# */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* SRCCLKREQ5# / SSD1_CLKREQ# */ + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */ + PAD_NC(GPP_B15, UP_20K), + PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, UP_20K), + PAD_NC(GPP_B19, UP_20K), + PAD_NC(GPP_B20, UP_20K), + PAD_NC(GPP_B21, UP_20K), + PAD_NC(GPP_B22, UP_20K), + PAD_NC(GPP_B23, UP_20K), + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */ + PAD_NC(GPP_C2, UP_20K), + PAD_NC(GPP_C3, UP_20K), + PAD_NC(GPP_C4, UP_20K), + PAD_NC(GPP_C5, UP_20K), + PAD_NC(GPP_C6, UP_20K), + PAD_NC(GPP_C7, UP_20K), + PAD_NC(GPP_C8, UP_20K), + PAD_NC(GPP_C9, UP_20K), + PAD_NC(GPP_C10, UP_20K), + PAD_NC(GPP_C11, UP_20K), + PAD_NC(GPP_C12, UP_20K), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPP_C13 / SSD1_PWR_DN# */ + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL */ + PAD_NC(GPP_C18, UP_20K), + PAD_NC(GPP_C19, UP_20K), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, UP_20K), + PAD_NC(GPP_D1, UP_20K), + PAD_NC(GPP_D2, UP_20K), + PAD_NC(GPP_D3, UP_20K), + PAD_NC(GPP_D4, UP_20K), + PAD_NC(GPP_D5, UP_20K), + PAD_NC(GPP_D6, UP_20K), + PAD_NC(GPP_D7, UP_20K), + PAD_CFG_GPO(GPP_D8, 1, DEEP), /* SB_BLON */ + PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), /* EC SWI# */ + PAD_NC(GPP_D10, NONE), /* DDR_TYPE_D10 + (unused; there is only one on-board + ram type/model) + */ + PAD_NC(GPP_D11, NONE), /* BOARD_ID + (unused in cb; we already know the + device model) + */ + PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D13, UP_20K), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* SSD2_PWR_DN# */ + PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D19, UP_20K), + PAD_NC(GPP_D20, UP_20K), + PAD_NC(GPP_D21, NONE), /* TPM_DET# + (currently unused in cb; there seem + to be no devices without TPM) + */ + PAD_NC(GPP_D22, NONE), /* DDR_TYPE_D22 + (unused in cb; there is only one + on-board ram type) + */ + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, UP_20K), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 / SATAGP2 */ + PAD_NC(GPP_E3, UP_20K), + PAD_NC(GPP_E4, UP_20K), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* DEVSLP2 */ + PAD_NC(GPP_E7, UP_20K), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPB_HPD0 / MUX_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPC_HPD1 / HDMI_HPD */ + PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */ + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), /* EC SCI# */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ + PAD_NC(GPP_E18, UP_20K), + PAD_NC(GPP_E19, NONE), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DPPC_CTRLCLK / HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DPPC_CTRLDATA / HDMI_CTRLDATA */ + PAD_NC(GPP_E22, UP_20K), + PAD_NC(GPP_E23, UP_20K), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, UP_20K), + PAD_NC(GPP_F1, UP_20K), + PAD_NC(GPP_F2, UP_20K), + PAD_NC(GPP_F3, UP_20K), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */ + PAD_NC(GPP_F8, UP_20K), + PAD_NC(GPP_F9, UP_20K), + PAD_NC(GPP_F10, UP_20K), + PAD_NC(GPP_F11, UP_20K), + PAD_NC(GPP_F12, UP_20K), + PAD_NC(GPP_F13, UP_20K), + PAD_NC(GPP_F14, UP_20K), + PAD_NC(GPP_F15, UP_20K), + PAD_NC(GPP_F16, UP_20K), + PAD_NC(GPP_F17, UP_20K), + PAD_NC(GPP_F18, UP_20K), + PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F22, UP_20K), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, UP_20K), + PAD_NC(GPP_G1, UP_20K), + PAD_NC(GPP_G2, UP_20K), + PAD_NC(GPP_G3, UP_20K), + PAD_NC(GPP_G4, UP_20K), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, UP_20K), + PAD_NC(GPP_G7, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, UP_20K), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# / CNVI_RST# */ + PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), /* MODEM_CLKREQ / CNVI_CLKREQ */ + PAD_NC(GPP_H3, UP_20K), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C2_SDA / SMD_7411 */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C2_SCL / SMC_7411 */ + PAD_NC(GPP_H6, UP_20K), + PAD_NC(GPP_H7, UP_20K), + PAD_NC(GPP_H8, UP_20K), + PAD_NC(GPP_H9, UP_20K), + PAD_NC(GPP_H10, UP_20K), + PAD_NC(GPP_H11, UP_20K), + PAD_NC(GPP_H12, UP_20K), + PAD_NC(GPP_H13, UP_20K), + PAD_NC(GPP_H14, UP_20K), + PAD_NC(GPP_H15, UP_20K), + PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H17, UP_20K), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */ + PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H23, UP_20K), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio_early.c b/src/mainboard/clevo/cml-u/variants/l140cu/gpio_early.c new file mode 100644 index 0000000000..3ea1c81e99 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Name format: / */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c new file mode 100644 index 0000000000..7bb073698d --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581401, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581401), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel GPU HDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c new file mode 100644 index 0000000000..4cad131765 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + + /* Values of the resistors connected to the DDR_RCOMP_[2:0] pins of the CPU */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Interleaved ("back-to-back") pin mapping */ + .dq_pins_interleaved = 1, + + /* + * DDR4 Vref mapping + * VREF_CA goes to CH_A and VREF_DQ_B (DDR1_VREF_DQ) goes to CH_B. + */ + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig new file mode 100644 index 0000000000..a99f9c6b23 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_CLEVO_KBLU_COMMON + def_bool n + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT +# select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_CLEVO_N130WU_OPTIONS + bool + select BOARD_CLEVO_KBLU_COMMON + +if BOARD_CLEVO_KBLU_COMMON + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config MAINBOARD_DIR + string + default "clevo/kbl-u" + +config VARIANT_DIR + string + default "n13xwu" if BOARD_CLEVO_N130WU + +config MAINBOARD_PART_NUMBER + string + default "N130WU" if BOARD_CLEVO_N130WU + +config CBFS_SIZE + hex + default 0x600000 if BOARD_CLEVO_N130WU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd" if VBOOT && !VBOOT_SLOTS_RW_A + # TODO +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,5917" if BOARD_CLEVO_N130WU + +config PXE_ROM_ID + string + default "10ec,8168" + +config UART_FOR_CONSOLE + int + default 2 + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +config LINEAR_FRAMEBUFFER_MAX_WIDTH + int + default 1920 + +config LINEAR_FRAMEBUFFER_MAX_HEIGHT + int + default 1080 + +endif diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name new file mode 100644 index 0000000000..05a49cda7c --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "Kaby Lake U" + +config BOARD_CLEVO_N130WU + bool "N130WU / N131WU" + select BOARD_CLEVO_N130WU_OPTIONS diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc new file mode 100644 index 0000000000..b424d4da19 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/clevo/kbl-u/acpi/ec.asl b/src/mainboard/clevo/kbl-u/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/clevo/kbl-u/acpi/superio.asl b/src/mainboard/clevo/kbl-u/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/clevo/kbl-u/board_info.txt b/src/mainboard/clevo/kbl-u/board_info.txt new file mode 100644 index 0000000000..97514fc003 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Clevo +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/kbl-u/bootblock.c b/src/mainboard/clevo/kbl-u/bootblock.c new file mode 100644 index 0000000000..b351fbd8ef --- /dev/null +++ b/src/mainboard/clevo/kbl-u/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl new file mode 100644 index 0000000000..21acf37dc2 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/clevo/kbl-u/include/variant/gpio.h b/src/mainboard/clevo/kbl-u/include/variant/gpio.h new file mode 100644 index 0000000000..95d576294f --- /dev/null +++ b/src/mainboard/clevo/kbl-u/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c new file mode 100644 index 0000000000..e34d5002bf --- /dev/null +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * TODO: + * - Add kill switches for WLAN, BT, LTE, CCD + * - Add support for WoL (LAN, WLAN) + * - Make M.2 port configurable (SATA <> PCIe) + * - Make SATA DevSlp configurable + * - Make TBT port configurable (TBT <> DisplayPort) + */ + +static void init_mainboard(void *chip_info) +{ + variant_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c new file mode 100644 index 0000000000..1399d33608 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt new file mode 100644 index 0000000000..30f8ce6e3f --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt @@ -0,0 +1 @@ +Board name: N130WU / N131WU diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt new file mode 100644 index 0000000000..f88aef4c04 Binary files /dev/null and b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt differ diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb new file mode 100644 index 0000000000..29f57bd643 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "panel_cfg" = "{ + .up_delay_ms = 200, // T3 + .down_delay_ms = 0, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_on_delay_ms = 50, // T7 + .backlight_off_delay_ms = 0, // T9 + .backlight_pwm_hz = 200, + }" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # FSP Configuration + register "SkipExtGfxScan" = "1" + register "SaGv" = "SaGv_Enabled" + register "eist_enable" = "1" + + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1558 0x1313 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 14.0 on # USB xHCI + register "SsicPortEnable" = "0" + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left + end + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 17.0 on # SATA + register "SataSalpSupport" = "0" + # Ports + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 on end # UART 2 + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on end # x4 TBT + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" + end + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpLtrEnable[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 WLAN + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpLtrEnable[5]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M (J_SSD1) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 on # Power Management Controller + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + end + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + end +end diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd new file mode 100644 index 0000000000..f53cdf4e47 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd @@ -0,0 +1,32 @@ +FLASH 8M { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + WP_RO@0x2d000 0x5d3000 { + FMAP@0x0 0x800 + RO_VPD(PRESERVE)@0x800 0x4000 + RO_SECTION@0x4800 0x5ce800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x58e000 + } + } + } +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads new file mode 100644 index 0000000000..38abb7aae9 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c new file mode 100644 index 0000000000..4b25993843 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c @@ -0,0 +1,503 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + // RCIN# + _PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0), + + // LAD0 + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0), + + // LAD1 + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0), + + // LAD2 + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0), + + // LAD3 + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0), + + // LFRAME# + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + + // SERIRQ + _PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0), + + // PIRQA# + _PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0), + + // CLKRUN# + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + + // CLKOUT_LPC0 + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + + // CLKOUT_LPC1 + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + + // PME# + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + + // BM_BUSY# + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + + // SUSWARN#/SUSPWRDNACK + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + + // SUS_STAT#/ESPI_RESET# + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + + // SUS_ACK# + _PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0), + + // SD_1P8_SEL + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + + // SD_PWR_EN# + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + + // ISH_GP0 + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + + // ISH_GP1 + _PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0), + + // ISH_GP2 + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + + // ISH_GP3 + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + + // ISH_GP4 + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + + // ISH_GP5 + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + + // CORE_VID0 + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + + // CORE_VID1 + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + + // VRALERT# + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + + // CPU_GP2 + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + + // CPU_GP3 + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + + // SRCCLKREQ0# + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + + // SRCCLKREQ1# + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + + // SRCCLKREQ2# + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + + // SRCCLKREQ3# + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + + // SRCCLKREQ4# + _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + + // SRCCLKREQ5# + _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + + // EXT_PWR_GATE# + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + + // SLP_S0# + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + + // PLTRST# + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + + // SPKR + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + + // GSPI0_CS# + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + + // GSPI0_CLK + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + + // GSPI0_MISO + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + + // GSPI0_MOSI + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + + // GSPI1_CS# + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + + // GSPI1_CLK + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + + // GSPI1_MISO + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + + // GSPI1_MOSI + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + + // SML1ALERT#/PCHHOT# + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + + // SMBCLK + _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), + + // SMBDATA + _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), + + // SMBALERT# + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + + // SML0CLK + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + + // SML0DATA + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + + // SML0ALERT# + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + + // SML1CLK +// _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), + + // SML1DATA +// _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), + + // UART0_RXD + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + + // UART0_TXD + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + + // UART0_RTS# + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + + // UART0_CTS# + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + + // UART1_RXD + _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), + + // UART1_TXD + _PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0), + + // UART1_RTS# + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + + // UART1_CTS# + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + + // I2C0_SDA + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + + // I2C0_SCL + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + + // I2C1_SDA + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + + // I2C1_SCL + _PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0), + + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + + // UART2_RTS# + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + + // UART2_CTS# + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + + // SPI1_CS# + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + + // SPI1_CLK + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + + // SPI1_MISO + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + + // SPI1_MOSI + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + + // FLASHTRIG + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + + // ISH_I2C0_SDA + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + + // ISH_I2C0_SCL + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + + // ISH_I2C1_SDA + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + + // ISH_I2C1_SCL + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + + // ISH_UART0_RXD + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + + // ISH_UART0_TXD + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + + // ISH_UART0_RTS# + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + + // ISH_UART0_CTS# + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + + // DMIC_CLK1 + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + + // DMIC_DATA1 + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + + // DMIC_CLK0 + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + + // DMIC_DATA0 + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + + // SPI1_IO2 + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0), + + // SPI1_IO3 + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + + // I2S_MCLK + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + + // SATAXPCIE0/SATAGP0 + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + + // SATAXPCIE1/SATAGP1 + _PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0), + + // SATAXPCIE2/SATAGP2 + _PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0), + + // CPU_GP0 + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + + // DEVSLP0 + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + + // DEVSLP1 + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + + // DEVSLP2 + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + + // CPU_GP1 + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + + // SATALED# + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + + // USB2_OC0# + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + + // USB2_OC1# + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + + // USB2_OC2# + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + + // USB2_OC3# + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + + // DDPB_HPD0 + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + + // DDPC_HPD1 + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + + // DDPD_HPD2 + _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), + + // DDPE_HPD3 + _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), + + // EDP_HPD + _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + + // DDPB_CTRLCLK + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + + // DDPB_CTRLDATA + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + + // DDPC_CTRLCLK + _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), + + // DDPC_CTRLDATA + _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), + + // DDPD_CTRLCLK + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + + // DDPD_CTRLDATA + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + + // BATLOW# + _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + + // LAN_WAKE# + _PAD_CFG_STRUCT(GPD2, 0x880502, 0x0), + + // PWRBTN# + _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + + // SLP_S3# + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + + // SLP_S4# + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + + // SLP_A# + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + + // RSVD + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + + // SUSCLK + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + + // SLP_WLAN# + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + + // SLP_S5# + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + + // I2S2_SCLK + _PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0), + + // I2S2_SFRM + _PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0), + + // I2S2_TXD + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + + // I2S2_RXD + _PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0), + + // I2C2_SDA + _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + + // I2C2_SCL + _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + + // I2C3_SDA + _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), + + // I2C3_SCL + _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), + + // I2C4_SDA + _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), + + // I2C4_SCL + _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), + + // I2C5_SDA/ISH_I2C2_SDA + _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), + + // I2C5_SCL/ISH_I2C2_SCL + _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), + + // EMMC_CMD + _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + + // EMMC_DATA0 + _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + + // EMMC_DATA1 + _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + + // EMMC_DATA2 + _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + + // EMMC_DATA3 + _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + + // EMMC_DATA4 + _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + + // EMMC_DATA5 + _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + + // EMMC_DATA6 + _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + + // EMMC_DATA7 + _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + + // EMMC_RCLK + _PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0), + + // EMMC_CLK + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + + // SD_CMD + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + + // SD_DATA0 + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0), + + // SD_DATA1 + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + + // SD_DATA2 + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + + // SD_DATA3 + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + + // SD_CD# + _PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), + + // SD_CLK + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + + // SD_WP + _PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0) +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c new file mode 100644 index 0000000000..dc55aae6d3 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0) +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c new file mode 100644 index 0000000000..05bb273a74 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek ALC269VC */ + 0x10ec0269, + 0x15581314, + 11, + AZALIA_SUBVENDOR(0, 0x15581314), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel iGPU HDMI */ + 0x8086280b, + 0x80860101, + 4, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x5, 0x18560010), + AZALIA_PIN_CFG(2, 0x6, 0x18560010), + AZALIA_PIN_CFG(2, 0x7, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c index f9051870d6..fba85e1a84 100644 --- a/src/mainboard/compulab/intense_pc/acpi_tables.c +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -4,7 +4,7 @@ #include /* FIXME: check this function. */ -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 414c410b10..b48dae3169 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -8,12 +8,9 @@ chip northbridge/intel/sandybridge # FIXME: check gfx device cpu_cluster 0x0 on chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/dell/optiplex_9010/acpi_tables.c b/src/mainboard/dell/optiplex_9010/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/dell/optiplex_9010/acpi_tables.c +++ b/src/mainboard/dell/optiplex_9010/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/dell/optiplex_9010/cmos.layout b/src/mainboard/dell/optiplex_9010/cmos.layout index dcf9639d3f..cff6004fec 100644 --- a/src/mainboard/dell/optiplex_9010/cmos.layout +++ b/src/mainboard/dell/optiplex_9010/cmos.layout @@ -4,90 +4,70 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 fan_full_speed +412 1 e 1 fan_full_speed # coreboot config options: northbridge -432 3 e 9 gfx_uma_size +432 3 e 9 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -9 0 32M -9 1 64M -9 2 96M -9 3 128M -9 4 160M -9 5 192M -9 6 224M - +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +9 0 32M +9 1 64M +9 2 96M +9 3 128M +9 4 160M +9 5 192M +9 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index 6a21d20b74..c805b1f35c 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -1,12 +1,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" register "tcc_offset" = "5" # TCC of 95C device lapic 0 on end device lapic 0xacac off end diff --git a/src/mainboard/dell/optiplex_9010/dsdt.asl b/src/mainboard/dell/optiplex_9010/dsdt.asl index 6a6dcb4c36..bd2229bd8f 100644 --- a/src/mainboard/dell/optiplex_9010/dsdt.asl +++ b/src/mainboard/dell/optiplex_9010/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index 5469c94f15..e96ee34aa4 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ void bootblock_mainboard_early_init(void) * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0; sch5545_early_init(0x2e); diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 2719460a9e..8110963c52 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -106,7 +105,6 @@ static const struct ec_val_reg ec_hwm_init_seq[] = { { 0x03, 0x0071 }, }; - static const ec_chassis_tdp_t ec_hwm_chassis3[] = { { 0x33, 0x0005, TDP_COMMON }, { 0x2f, 0x0018, TDP_COMMON }, @@ -336,8 +334,6 @@ static const ec_chassis_tdp_t ec_hwm_chassis6[] = { { 0x03, 0x028d, TDP_COMMON }, }; - - static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) { uint8_t int_sts, int_cond; @@ -424,7 +420,7 @@ static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint uint16_t sch5545_get_ec_fw_version(void) { - uint8_t val; + uint8_t val = 0; uint16_t ec_fw_version; /* Read the FW version currently loaded used by EC */ @@ -446,8 +442,7 @@ void sch5545_update_ec_firmware(uint16_t ec_version) uint32_t *ec_fw_file; size_t ec_fw_file_size; - ec_fw_file = cbfs_boot_map_with_leak("sch5545_ecfw.bin", CBFS_TYPE_RAW, - &ec_fw_file_size); + ec_fw_file = cbfs_map("sch5545_ecfw.bin", &ec_fw_file_size); if (!ec_fw_file || ec_fw_file_size != 0x1750) { printk(BIOS_ERR, "EC firmware file not found in CBFS!\n"); @@ -502,7 +497,7 @@ void sch5545_update_ec_firmware(uint16_t ec_version) void sch5545_ec_hwm_early_init(void) { - uint8_t val; + uint8_t val = 0; int i; printk(BIOS_DEBUG, "%s\n", __func__); @@ -608,7 +603,7 @@ static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value) void sch5545_ec_hwm_init(void *unused) { - uint8_t val, val_2fc, chassis_type, fan_speed_full = 0; + uint8_t val = 0, val_2fc, chassis_type, fan_speed_full = 0; printk(BIOS_DEBUG, "%s\n", __func__); sch5545_emi_init(0x2e); diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index bc5b428588..586e22a9bf 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_bits -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index a395d248cf..92591d75ff 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 5947b7a361..398594f828 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include #include #include - static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -29,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -66,19 +63,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) @@ -93,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index b621f60b81..7926249ff0 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index fbb8e9e44f..53e792044b 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +# The code for this board is under elmex/pcm205400 + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215abc..eb14caca73 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,4 @@ +# The code for this board is under elmex/pcm205400 + config BOARD_ELMEX_PCM205401 bool "pcm205401" diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 368f7f3a69..06a7ea82a0 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -13,10 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARCH_TIMER select BOARD_ROMSIZE_KB_4096 - select BOOTBLOCK_CONSOLE select BOOTBLOCK_CUSTOM select BOOT_DEVICE_NOT_SPI_FLASH - select CONSOLE_SERIAL select DRIVERS_UART_PL011 select HAVE_LINEAR_FRAMEBUFFER select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S index eb595b9d59..287ddbe281 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S +++ b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Early initialization code for aarch64 (a.k.a. armv8) - * - * - * SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index fee2a36e78..6b6ac720cf 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 3025e0a66f..50dd35ebdc 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Memory map for QEMU virt machine since diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index e6da3a6cac..7bf9260f8a 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -1,10 +1,5 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c index 5248110c47..755a661601 100644 --- a/src/mainboard/emulation/qemu-aarch64/media.c +++ b/src/mainboard/emulation/qemu-aarch64/media.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 99f8f22a57..ae00e96665 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -23,9 +19,11 @@ SECTIONS REGION(secram, 0xe000000, 0x1000000, 4096) DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) - ROMSTAGE(0x60030000, 128K) + TIMESTAMP(0x60030000, 1K) + ROMSTAGE(0x60031000, 128K) TTB(0x60070000, 128K) RAMSTAGE(0x600b0000, 16M) diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c index 26fc547a80..0fac64d234 100644 --- a/src/mainboard/emulation/qemu-aarch64/mmio.c +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -1,13 +1,9 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VIRT_UART_BASE; } diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 64e5bb7168..a91299873a 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 - select CONSOLE_SERIAL select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 977725d246..c3d974c429 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -4,15 +4,14 @@ #include #include #include -#include #include #include #include +#include static void init_gfx(void) { uint32_t *pl111; - struct edid edid; /* width is at most 4096 */ /* height is at most 1024 */ int width = 800, height = 600; @@ -28,12 +27,7 @@ static void init_gfx(void) write32(pl111 + 10, 0xff); write32(pl111 + 6, (5 << 1) | 0x801); - edid.framebuffer_bits_per_pixel = 32; - edid.bytes_per_line = width * 4; - edid.x_resolution = width; - edid.y_resolution = height; - - set_vbe_mode_info_valid(&edid, framebuffer); + fb_add_framebuffer_info(framebuffer, width, height, 4 * width, 32); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 9d76d9ddd0..5f32d8b7cc 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,14 +28,17 @@ SECTIONS { /* TODO: does this thing emulate SRAM? */ - BOOTBLOCK(0x00000, 64K) - FMAP_CACHE(0x10000, 2K) + REGION(flash, 0, CONFIG_ROM_SIZE, 4K) DRAM_START(0x60000000) STACK(0x60000000, 64K) - ROMSTAGE(0x60010000, 128K) - RAMSTAGE(0x60030000, 16M) - + BOOTBLOCK(0x60010000, 128K) + FMAP_CACHE(0x60030000, 4K) + TIMESTAMP(0x60031000, 1K) + CBFS_MCACHE(0x60031400, 7K) /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x61030000, 16K) + TTB(0x60034000, 16K) + ROMSTAGE(0x60038000, 128K) + RAMSTAGE(0x60060000, 16M) + POSTRAM_CBFS_CACHE(0x61060000, 8M) } diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c index 3f239153db..0f07e7f1ef 100644 --- a/src/mainboard/emulation/qemu-armv7/mmio.c +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -4,7 +4,7 @@ #define VEXPRESS_UART0_IO_ADDRESS (0x10009000) -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VEXPRESS_UART0_IO_ADDRESS; } diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 06ac685d3d..1b618718b3 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_ASAN_IN_ROMSTAGE + select NO_SMM config VBOOT select VBOOT_MUST_REQUEST_DISPLAY @@ -25,6 +27,15 @@ config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index 9019afb7a3..8963e13e16 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -1,35 +1,35 @@ entries -0 384 r 0 reserved_memory +0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter -400 8 r 0 reserved_century -440 8 r 0 reserved_ibm_ps2_century +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century -448 1 e 1 power_on_after_fail -452 4 e 6 debug_level -456 1 e 1 ECC_memory +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level +456 1 e 1 ECC_memory # VBOOT -464 128 r 0 vbnv +464 128 r 0 vbnv -1008 16 h 0 check_sum +1008 16 h 0 check_sum enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 5a341b49f4..6fd44672e7 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -3,9 +3,9 @@ #include DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, 0x1 // OEM Revision diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 929743ac46..bc97554442 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -28,8 +28,19 @@ static void qemu_nb_init(struct device *dev) pci_assign_irqs(pcidev_on_root(i, 0), qemu_i440fx_irqs + (i % 4)); } +static void qemu_nb_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } +} + static struct device_operations nb_operations = { - .read_resources = pci_dev_read_resources, + .read_resources = qemu_nb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = qemu_nb_init, diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2b7d2036e0..f49d47dac9 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -192,10 +193,10 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * t->size = qemu_get_memory_size() / 1024; t->data_width = 64; t->total_width = 64; - t->form_factor = 9; /* DIMM */ + t->form_factor = MEMORY_FORMFACTOR_DIMM; t->device_locator = smbios_add_string(t->eos, "Virtual"); - t->memory_type = 0x12; /* DDR */ - t->type_detail = 0x80; /* Synchronous */ + t->memory_type = MEMORY_TYPE_DDR; + t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; t->speed = 200; t->clock_speed = 200; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); @@ -244,9 +245,22 @@ static struct device_operations pci_domain_ops = { #endif }; +static const struct mp_ops mp_ops_no_smm = { + .get_cpu_count = fw_cfg_max_cpus, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops_no_smm)) + printk(BIOS_ERR, "MP initialization failure.\n"); +} + static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + if (CONFIG(PARALLEL_MP)) + mp_cpu_bus_init(dev); + else + initialize_cpus(dev->link_list); } static void cpu_bus_scan(struct device *bus) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index 90aaec631d..66f2c7577b 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -13,5 +13,6 @@ SECTIONS STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index c6d7e40fef..4b1bf3287e 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -5,26 +5,26 @@ #include static uint8_t *buf = (void *)0; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) buf; } -void uart_init(int idx) +void uart_init(unsigned int idx) { } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c6d6..d88d0da7ff 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -32,6 +32,15 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d5c1..ddcf6da062 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 104e5d0883..b95e34c123 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -13,7 +13,7 @@ #include "../qemu-i440fx/acpi.h" #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index fafa03b45d..efb3a4f7e1 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,12 +16,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 47d26bf7dd..1af2e02adb 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,9 +1,7 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include "../qemu-i440fx/fw_cfg.h" diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index 9019afb7a3..8963e13e16 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -1,35 +1,35 @@ entries -0 384 r 0 reserved_memory +0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter -400 8 r 0 reserved_century -440 8 r 0 reserved_ibm_ps2_century +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century -448 1 e 1 power_on_after_fail -452 4 e 6 debug_level -456 1 e 1 ECC_memory +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level +456 1 e 1 ECC_memory # VBOOT -464 128 r 0 vbnv +464 128 r 0 vbnv -1008 16 h 0 check_sum +1008 16 h 0 check_sum enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a9c96be8bc..d89d67f998 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -7,9 +7,9 @@ #include DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, 0x2 // OEM Revision diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index d329e5affb..c88874f4f2 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -44,6 +44,12 @@ static void qemu_nb_read_resources(struct device *dev) /* reserve mmconfig */ fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10, IORESOURCE_RESERVE); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } } diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000000..5d8d48295c --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +} diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 5b556fc190..ee0f337f6d 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -57,8 +57,6 @@ config OPENSBI_PLATFORM # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 default 0x80040000 if COREBOOT_ROMSIZE_KB_256 default 0x80080000 if COREBOOT_ROMSIZE_KB_512 default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index cfa0513520..96ab74c516 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -25,6 +25,7 @@ SECTIONS #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 4eee12b933..19a2b0016c 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -4,7 +4,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) QEMU_VIRT_UART0; } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index e08fd72b24..7ec489292c 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -12,7 +12,8 @@ SECTIONS BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) FMAP_CACHE(START + 8M + 4K, 2K) - /* hole at (START + 8M + 6K, 58K) */ + CBFS_MCACHE(START + 8M + 6K, 8K) + /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index d6e0510274..efefc52d62 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -3,7 +3,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) 0x02100000; } diff --git a/src/mainboard/example/Kconfig b/src/mainboard/example/Kconfig new file mode 100644 index 0000000000..5afc8ee5a9 --- /dev/null +++ b/src/mainboard/example/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_EXAMPLE + +choice + prompt "Mainboard model" + +source "src/mainboard/example/*/Kconfig.name" + +endchoice + +source "src/mainboard/example/*/Kconfig" + +config MAINBOARD_VENDOR + default "Example" + +endif # VENDOR_EXAMPLE diff --git a/src/mainboard/example/Kconfig.name b/src/mainboard/example/Kconfig.name new file mode 100644 index 0000000000..9ffc1738bc --- /dev/null +++ b/src/mainboard/example/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_EXAMPLE + bool "Example boards" diff --git a/src/mainboard/example/min86/Kconfig b/src/mainboard/example/min86/Kconfig new file mode 100644 index 0000000000..3a962e27f4 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig @@ -0,0 +1,14 @@ +if BOARD_EXAMPLE_MIN86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_EXAMPLE_MIN86 + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "example/min86" + +config MAINBOARD_PART_NUMBER + default "Min86" + +endif diff --git a/src/mainboard/example/min86/Kconfig.name b/src/mainboard/example/min86/Kconfig.name new file mode 100644 index 0000000000..33131930f5 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_EXAMPLE_MIN86 + bool "Minimal x86 fake board" + help + This example mainboard code along with the example/min86 SoC + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. diff --git a/src/mainboard/example/min86/board_info.txt b/src/mainboard/example/min86/board_info.txt new file mode 100644 index 0000000000..c778859fab --- /dev/null +++ b/src/mainboard/example/min86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/example/min86/devicetree.cb b/src/mainboard/example/min86/devicetree.cb new file mode 100644 index 0000000000..9af04c091a --- /dev/null +++ b/src/mainboard/example/min86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/example/min86 + + device domain 0 on + end + +end diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index ca19e0582c..9e7ab69aac 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -19,8 +19,35 @@ config BOARD_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select DISABLE_HPET select INTEL_GMA_HAVE_VBT - select GENERIC_SPD_BIN - select USE_VENDORCODE_ELTAN + select HAVE_SPD_IN_CBFS + +config USE_VENDORCODE_ELTAN + default y + +if VBOOT + +config VBOOT_VBNV_CMOS + default y + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_NO_BOARD_SUPPORT + default y + +config VBOOT_ENABLE_CBFS_FALLBACK + default y + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw.fmd" + +config RW_REGION_ONLY + default "%/payload logo.bmp %/ramstage vbt.bin %/dsdt.aml config %/postcar" + +config RO_REGION_ONLY + default "spd.bin fsp.bin cpu_microcode_blob.bin" + +endif # VBOOT config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" @@ -49,6 +76,7 @@ config FSP_LOC default 0xfff9c000 config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + depends on USE_VENDORCODE_ELTAN hex default 0xFFFE9000 @@ -69,14 +97,17 @@ config C_ENV_BOOTBLOCK_SIZE default 0x4000 config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + depends on USE_VENDORCODE_ELTAN bool default y config VENDORCODE_ELTAN_VBOOT_MANIFEST + depends on USE_VENDORCODE_ELTAN string default "mainboard/facebook/fbg1701/manifest.h" config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + depends on USE_VENDORCODE_ELTAN hex default 0xFFFF9C00 diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 5fe4a4260e..7538af0231 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -6,10 +6,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 578e4987aa..2865824a90 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -6,7 +6,7 @@ const mboot_measure_item_t mb_log_list[] = { { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, { "revision", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, - { "cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, + { "cmos_layout.bin", CBFS_TYPE_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, #if CONFIG(VENDORCODE_ELTAN_VBOOT) { "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION, diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout index f80f2c597f..29bc4f80b5 100644 --- a/src/mainboard/facebook/fbg1701/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -3,103 +3,55 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) # reboot_counter reserved for core, not used by platform. -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#400 1 e 2 unused -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -#416 568 r 0 unused # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index 70e950c65e..a340fdc37c 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -4,14 +4,9 @@ chip soc/intel/braswell # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ chip soc/intel/braswell register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "1" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ chip soc/intel/braswell register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index b8270bcd85..345ce570d6 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 59832a47fd..be995731ec 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd new file mode 100644 index 0000000000..51ee470cc4 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -0,0 +1,21 @@ +FLASH 8M { + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x08000 { + RW_MRC_CACHE@0 0x08000 + } + RW_SECTION_A@0x08000 0x578000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x567FC0 + } + WP_RO@0x580000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x400 + RO_FRID@0xA00 0x40 + RO_FRID_PAD@0xA40 0x5c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 92c02a799e..ddbc27ef91 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -92,4 +92,7 @@ config VBOOT_ALWAYS_ALLOW_UDC def_bool y depends on VBOOT && !CHROMEOS +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index 8aff5417e0..d9a072952e 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -29,15 +29,14 @@ Device (EC0) OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x00), CPUT, 8, } Method (TSRD, 1, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) + Local0 = Arg0 + Arg0 = Local0 Return (\_SB.DPTF.CTOK (CPUT)) } @@ -45,27 +44,27 @@ Device (EC0) Method (PAT0, 2, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) - Store(Arg1, Local0) - Store(Local0, Arg1) + Local0 = Arg0 + Arg0 = Local0 + Local0 = Arg1 + Arg1 = Local0 } /* Set Aux Trip Point 1 */ Method (PAT1, 2, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) - Store(Arg1, Local0) - Store(Local0, Arg1) + Local0 = Arg0 + Arg0 = Local0 + Local0 = Arg1 + Arg1 = Local0 } /* Disable Aux Trip Point */ Method (PATD, 1, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) + Local0 = Arg0 + Arg0 = Local0 } } diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout index 61c34f3a94..705eaba627 100644 --- a/src/mainboard/facebook/monolith/cmos.layout +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -3,103 +3,55 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option +384 1 e 4 boot_option # reboot_counter reserved for core, not used by platform. -388 4 h 0 reboot_counter -#390 2 r 0 unused +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#400 1 e 2 unused -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -#416 568 r 0 unused # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 102450a77a..974d00e41a 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -29,47 +29,26 @@ chip soc/intel/skylake # "Intel SpeedStep Technology" register "eist_enable" = "1" - # "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # DPTF register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" - register "SaImguEnable" = "0" - register "Cio2Enable" = "0" - register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" - register "EnableLan" = "1" - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -168,7 +147,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[2]" = "1" # Disable Aspm - register "PcieRpAspm[2]" = "AspmDisabled" + register "pcie_rp_aspm[2]" = "AspmDisabled" # PCIE Port 4 disabled # PCIE Port 5 x1 -> MODULE i219 @@ -183,7 +162,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Disable Aspm - register "PcieRpAspm[5]" = "AspmDisabled" + register "pcie_rp_aspm[5]" = "AspmDisabled" # PCIE Port 7 Disabled # PCIE Port 8 Disabled @@ -201,7 +180,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[8]" = "1" # Disable Aspm - register "PcieRpAspm[8]" = "AspmDisabled" + register "pcie_rp_aspm[8]" = "AspmDisabled" # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 @@ -209,21 +188,13 @@ chip soc/intel/skylake register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled register "SsicPortEnable" = "0" @@ -254,10 +225,12 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # Thermal Subsystem + device pci 05.0 off end # SA IMGU device pci 08.0 on end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 238e87b071..40a2a7df3e 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index f0f6eef49d..69ffc6bce0 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -10,52 +10,52 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* PCH_RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LAD_0 */ PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1), +/* LAD_1 */ PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1), +/* LAD_2 */ PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1), +/* LAD_3 */ PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PCH_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* PM_CLKRUN_N */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ -/* NC */ PAD_CFG_NC(GPP_A12), +/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* SLEEP */ PAD_NC(GPP_A11, NONE), /* available on the module not used here */ +/* NC */ PAD_NC(GPP_A12, NONE), /* PCH_SYSWARN */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_A18), -/* NC */ PAD_CFG_NC(GPP_A19), -/* NC */ PAD_CFG_NC(GPP_A20), -/* NC */ PAD_CFG_NC(GPP_A21), -/* NC */ PAD_CFG_NC(GPP_A22), -/* NC */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* NC */ PAD_NC(GPP_A18, NONE), +/* NC */ PAD_NC(GPP_A19, NONE), +/* NC */ PAD_NC(GPP_A20, NONE), +/* NC */ PAD_NC(GPP_A21, NONE), +/* NC */ PAD_NC(GPP_A22, NONE), +/* NC */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_B3), -/* NC */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0 */ PAD_CFG_NC(GPP_B5), -/* SRCCLKREQ1 */ PAD_CFG_NC(GPP_B6), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3 */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5 */ PAD_CFG_NC(GPP_B10), +/* NC */ PAD_NC(GPP_B3, NONE), +/* NC */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0 */ PAD_NC(GPP_B5, NONE), +/* SRCCLKREQ1 */ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3 */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5 */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_B15), -/* NC */ PAD_CFG_NC(GPP_B16), -/* NC */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* NC */ PAD_CFG_NC(GPP_B19), -/* NC */ PAD_CFG_NC(GPP_B20), -/* NC */ PAD_CFG_NC(GPP_B21), -/* BIOS_SEL */ PAD_CFG_NC(GPP_B22), +/* NC */ PAD_NC(GPP_B15, NONE), +/* NC */ PAD_NC(GPP_B16, NONE), +/* NC */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* NC */ PAD_NC(GPP_B19, NONE), +/* NC */ PAD_NC(GPP_B20, NONE), +/* NC */ PAD_NC(GPP_B21, NONE), +/* BIOS_SEL */ PAD_NC(GPP_B22, NONE), /* CB_OVT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_SCL */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), @@ -63,56 +63,56 @@ static const struct pad_config gpio_table[] = { /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0_ALERT */ PAD_CFG_NC(GPP_C5), +/* SML0_ALERT */ PAD_NC(GPP_C5, NONE), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* CPU_UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* CPU_UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* CPU_UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* CPU_UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_C12), -/* NC */ PAD_CFG_NC(GPP_C13), -/* NC */ PAD_CFG_NC(GPP_C14), -/* NC */ PAD_CFG_NC(GPP_C15), +/* NC */ PAD_NC(GPP_C12, NONE), +/* NC */ PAD_NC(GPP_C13, NONE), +/* NC */ PAD_NC(GPP_C14, NONE), +/* NC */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_C18), -/* NC */ PAD_CFG_NC(GPP_C19), -/* NC */ PAD_CFG_NC(GPP_C20), -/* NC */ PAD_CFG_NC(GPP_C21), -/* EC_SCI# NOT USED */ PAD_CFG_NC(GPP_C22), -/* EC_SMI# NOT USED */ PAD_CFG_NC(GPP_C23), -/* TOUCH_SPI1_CS */ PAD_CFG_NC(GPP_D0), -/* TPM_PIRQ_N NOT USED */ PAD_CFG_NC(GPP_D1), -/* NC */ PAD_CFG_NC(GPP_D2), -/* NC */ PAD_CFG_NC(GPP_D3), -/* NC */ PAD_CFG_NC(GPP_D4), -/* NC */ PAD_CFG_NC(GPP_D5), -/* NC */ PAD_CFG_NC(GPP_D6), -/* NC */ PAD_CFG_NC(GPP_D7), -/* NC */ PAD_CFG_NC(GPP_D8), -/* NC */ PAD_CFG_NC(GPP_D9), -/* NC */ PAD_CFG_NC(GPP_D11), -/* NC */ PAD_CFG_NC(GPP_D12), -/* NC */ PAD_CFG_NC(GPP_D13), -/* NC */ PAD_CFG_NC(GPP_D14), -/* NC */ PAD_CFG_NC(GPP_D15), -/* NC */ PAD_CFG_NC(GPP_D16), -/* NC */ PAD_CFG_NC(GPP_D17), -/* NC */ PAD_CFG_NC(GPP_D18), -/* NC */ PAD_CFG_NC(GPP_D19), -/* NC */ PAD_CFG_NC(GPP_D20), -/* LID# NOT USED */ PAD_CFG_NC(GPP_D21), -/* NC */ PAD_CFG_NC(GPP_D22), -/* NC */ PAD_CFG_NC(GPP_D23), -/* NC */ PAD_CFG_NC(GPP_E0), -/* NC */ PAD_CFG_NC(GPP_E1), -/* NC */ PAD_CFG_NC(GPP_E2), -/* NC */ PAD_CFG_NC(GPP_E3), -/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E4), -/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E5), -/* DEVSLP1 TP */ PAD_CFG_NC(GPP_E6), -/* NC */ PAD_CFG_NC(GPP_E7), +/* NC */ PAD_NC(GPP_C18, NONE), +/* NC */ PAD_NC(GPP_C19, NONE), +/* NC */ PAD_NC(GPP_C20, NONE), +/* NC */ PAD_NC(GPP_C21, NONE), +/* EC_SCI# NOT USED */ PAD_NC(GPP_C22, NONE), +/* EC_SMI# NOT USED */ PAD_NC(GPP_C23, NONE), +/* TOUCH_SPI1_CS */ PAD_NC(GPP_D0, NONE), +/* TPM_PIRQ_N NOT USED */ PAD_NC(GPP_D1, NONE), +/* NC */ PAD_NC(GPP_D2, NONE), +/* NC */ PAD_NC(GPP_D3, NONE), +/* NC */ PAD_NC(GPP_D4, NONE), +/* NC */ PAD_NC(GPP_D5, NONE), +/* NC */ PAD_NC(GPP_D6, NONE), +/* NC */ PAD_NC(GPP_D7, NONE), +/* NC */ PAD_NC(GPP_D8, NONE), +/* NC */ PAD_NC(GPP_D9, NONE), +/* NC */ PAD_NC(GPP_D11, NONE), +/* NC */ PAD_NC(GPP_D12, NONE), +/* NC */ PAD_NC(GPP_D13, NONE), +/* NC */ PAD_NC(GPP_D14, NONE), +/* NC */ PAD_NC(GPP_D15, NONE), +/* NC */ PAD_NC(GPP_D16, NONE), +/* NC */ PAD_NC(GPP_D17, NONE), +/* NC */ PAD_NC(GPP_D18, NONE), +/* NC */ PAD_NC(GPP_D19, NONE), +/* NC */ PAD_NC(GPP_D20, NONE), +/* LID# NOT USED */ PAD_NC(GPP_D21, NONE), +/* NC */ PAD_NC(GPP_D22, NONE), +/* NC */ PAD_NC(GPP_D23, NONE), +/* NC */ PAD_NC(GPP_E0, NONE), +/* NC */ PAD_NC(GPP_E1, NONE), +/* NC */ PAD_NC(GPP_E2, NONE), +/* NC */ PAD_NC(GPP_E3, NONE), +/* DEVSLP0 TP */ PAD_NC(GPP_E4, NONE), +/* DEVSLP0 TP */ PAD_NC(GPP_E5, NONE), +/* DEVSLP1 TP */ PAD_NC(GPP_E6, NONE), +/* NC */ PAD_NC(GPP_E7, NONE), /* SATA_LED_N */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC0_1 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC2_3 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -120,27 +120,27 @@ static const struct pad_config gpio_table[] = { /* USB2_OC6_7 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* DDPB_HPD0_C */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1_C */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2_C NC */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3_C NC */ PAD_CFG_NC(GPP_E16), +/* DDPD_HPD2_C NC */ PAD_NC(GPP_E15, NONE), +/* DDPE_HPD3_C NC */ PAD_NC(GPP_E16, NONE), /* EDP_HPD_C */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDI2_DDC_SCL_L */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK NC */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDAT NC */ PAD_CFG_NC(GPP_E23), -/* NC */ PAD_CFG_NC(GPP_F0), -/* NC */ PAD_CFG_NC(GPP_F1), -/* NC */ PAD_CFG_NC(GPP_F2), -/* NC */ PAD_CFG_NC(GPP_F3), -/* NC */ PAD_CFG_NC(GPP_F4), -/* NC */ PAD_CFG_NC(GPP_F5), -/* NC */ PAD_CFG_NC(GPP_F6), -/* NC */ PAD_CFG_NC(GPP_F7), -/* NC */ PAD_CFG_NC(GPP_F8), -/* NC */ PAD_CFG_NC(GPP_F9), -/* NC */ PAD_CFG_NC(GPP_F10), -/* NC */ PAD_CFG_NC(GPP_F11), +/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK NC */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDAT NC */ PAD_NC(GPP_E23, NONE), +/* NC */ PAD_NC(GPP_F0, NONE), +/* NC */ PAD_NC(GPP_F1, NONE), +/* NC */ PAD_NC(GPP_F2, NONE), +/* NC */ PAD_NC(GPP_F3, NONE), +/* NC */ PAD_NC(GPP_F4, NONE), +/* NC */ PAD_NC(GPP_F5, NONE), +/* NC */ PAD_NC(GPP_F6, NONE), +/* NC */ PAD_NC(GPP_F7, NONE), +/* NC */ PAD_NC(GPP_F8, NONE), +/* NC */ PAD_NC(GPP_F9, NONE), +/* NC */ PAD_NC(GPP_F10, NONE), +/* NC */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_STROBE */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_D0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_D1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_M_N */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* BIOS_RECOVERY NOT USED */ PAD_CFG_NC(GPD7), +/* BIOS_RECOVERY NOT USED */ PAD_NC(GPD7, NONE), /* CPU_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 93ce389134..e0aed55cf0 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c deleted file mode 100644 index 496d4190c6..0000000000 --- a/src/mainboard/foxconn/d41s/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 0a329956af..a2298978b3 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -3,71 +3,65 @@ # ----------------------------------------------------------------- entries - # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: cpu -#945 7 r 0 unused # coreboot config options: northbridge -952 3 e 11 gfx_uma_size +952 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 8M -11 1 16M -11 2 32M -11 3 48M -11 4 64M -11 5 128M -11 6 256M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 6e4ecfc7ea..5e74be86e9 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index 781abcce7e..38c070483c 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 1; /* COM 1 port */ diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index f90467cdb9..a9abba3f81 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -4,85 +4,59 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 7924edfb45..d7b642aab5 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -79,9 +79,9 @@ Scope(\_SB) { Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, , Local0) Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) + Divide(Local3, 0x64, , Local0) Increment(Local0) Store(Local0, Index(PBST, 2)) @@ -184,9 +184,9 @@ Scope(\_SB) { Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, , Local0) Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) + Divide(Local3, 0x64, , Local0) Increment(Local0) Store(Local0, Index(PBST, 2)) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae64452e..da6046ce4c 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -87,16 +87,16 @@ Device(EC0) Method (_Q01, 0) { Notify (\_SB.CP00, 0x80) - If(ADP) { - Store(1, \_SB.AC.ACST) - TRAP(0xe3) - Store(1, PWRS) - TRAP(0x2b) + If (ADP) { + \_SB.AC.ACST = 1 + TRAP (0xe3) + PWRS = 1 + TRAP (0x2b) } Else { - Store(0, \_SB.AC.ACST) - Notify(\_SB.AC, 0x80) - Notify(\_SB.BAT0, 0x80) - Store(0, PWRS) + \_SB.AC.ACST = 0 + Notify (\_SB.AC, 0x80) + Notify (\_SB.BAT0, 0x80) + PWRS = 0 TRAP(0x2b) } @@ -107,7 +107,7 @@ Device(EC0) Method (_Q02, 0) { - If(BAT) { + If (BAT) { Notify(\_SB.BAT0, 0x00) Notify(\_SB.AC, 0x80) } Else { @@ -132,7 +132,7 @@ Device(EC0) { TRAP(0xe0) - If (LEqual(RTCF, 0x00)) { + If (RTCF == 0x00) { Notify(LID0, 0x80) } else { TRAP(0xc1) @@ -172,25 +172,25 @@ Device(EC0) Method (_Q24, 0) { - Store(0x3f, HOTK) - If(IGDS) { + HOTK = 0x3f + If (IGDS) { Notify (\_SB.PCI0.GFX0, 0x82) } Else { - TRAP(0xE1) + TRAP (0xE1) } Notify (\_SB.ECO, 0x85) } Method (_Q25, 0) { - Store(0x40, HOTK) + HOTK = 0x40 TRAP(0xe1) Notify(\_SB.ECO, 0x86) } Method (_Q26, 0) { - Store(0x41, HOTK) + HOTK = 0x41 TRAP(0xe1) Notify(\_SB.ECO, 0x87) } @@ -212,7 +212,7 @@ Device(EC0) Method (_Q2A, 0) { - Store(0x57, HOTK) + HOTK = 0x57 TRAP(0xe1) Notify(\_SB.ECO, 0x8b) } @@ -225,7 +225,7 @@ Device(EC0) Method (_Q2C, 0) { - Store(0x59, HOTK) + HOTK = 0x59 TRAP(0xe1) } @@ -241,25 +241,25 @@ Device(EC0) Method (_Q3A, 0) { - Store(1, BRTL) + BRTL = 1 Notify(\_SB.ECO, 0x93) } Method (_Q3B, 0) { - Store(0, BRTL) + BRTL = 0 Notify(\_SB.ECO, 0x93) } Method (_Q3C, 0) { - Store(1, SUN) + SUN = 1 Notify(\_SB.ECO, 0x92) } Method (_Q3D, 0) { - Store(0, SUN) + SUN = 0 Notify(\_SB.ECO, 0x92) } @@ -302,14 +302,14 @@ Device(EC0) Method (_Q48, 0) { TRAP(0xd2) // Check AC Status - Store (1, ODDS) + ODDS = 1 Notify(\_SB.ECO, 0x90) } Method (_Q49, 0) { TRAP(0xd2) // Check AC Status - Store (0, ODDS) + ODDS = 0 Notify(\_SB.ECO, 0x90) } @@ -337,7 +337,7 @@ Device(EC0) Method (_Q5C, 0) { - // Store(2, IGPS) + // IGPS = 2 Notify(\_SB.ECO, 0x94) } @@ -364,26 +364,26 @@ Scope(\_SB) Method (GDPD, 0, Serialized) { // Set flag byte to zero - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x01)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x01) { + Local0 |= 0x01 } - If (And(BRTL, 0x02)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x02) { + Local0 |= 0x04 } - If (And(BRTL, 0x04)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x04) { + Local0 |= 0x02 } - If (And(BRTL, 0x30)) { - Or(Local0, 0x10, Local0) + If (BRTL & 0x30) { + Local0 |= 0x10 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x40, Local0) + If (BRTL & 0x40) { + Local0 |= 0x40 } Return (Local0) @@ -391,18 +391,18 @@ Scope(\_SB) Method (GDPC, 0, Serialized) { - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x10)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x10) { + Local0 |= 0x04 } - If (And( BRTL, 0x20)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x20) { + Local0 |= 0x01 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x40) { + Local0 |= 0x02 } Return (Local0) @@ -411,7 +411,7 @@ Scope(\_SB) /* Set Brightness Level */ Method(SBLL, 1, Serialized) { - Store (Arg0, BRTL) + BRTL = Arg0 TRAP(0xd5) // See mainboard's smihandler.c Return (0) } @@ -426,7 +426,7 @@ Scope(\_SB) /* Get Brightness Level Medium? */ Method(GBLM, 0, Serialized) { - Store(0x3f, BRTL) + BRTL = 0x3f // XXX don't we have to set the brightness? Return(BRTL) } @@ -434,7 +434,7 @@ Scope(\_SB) /* ??? */ Method(SUTE, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf5) } Else { TRAP(0xf6) @@ -462,33 +462,30 @@ Scope(\_SB) /* Let coreboot update the flags */ TRAP(0xe5) - Store (0, Local0) - If(And(RFDV, 0x01)) { - Or(Local0, 0x01, Local0) + Local0 = 0 + If (RFDV & 0x01) { + Local0 |= 0x01 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x02) { + Local0 |= 0x02 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x04) { + Local0 |= 0x04 } - If(And(RFDV, 0x04)) { - Or(Local0, 0x04, Local0) + If (RFDV & 0x08) { + Local0 |= 0x08 } - If(And(RFDV, 0x08)) { - Or(Local0, 0x08, Local0) + If (GP15 & 0x01) { // GDIS + Local0 |= 0x10 } - If(And(GP15, 0x01)) { // GDIS - Or(Local0, 0x10, Local0) + If (GP12 & 0x01) { // WIFI Led (WLED) + Local0 |= 0x20 } - If(And(GP12, 0x01)) { // WIFI Led (WLED) - Or(Local0, 0x20, Local0) + If (BTEN & 0x01) { // BlueTooth Enable + Local0 |= 0x40 } - If(And(BTEN, 0x01)) { // BlueTooth Enable - Or(Local0, 0x40, Local0) - } - If(And(GP10, 0x01)) { // GPS Enable - Or(Local0, 0x80, Local0) + If (GP10 & 0x01) { // GPS Enable + Local0 |= 0x80 } Return (Local0) @@ -497,30 +494,30 @@ Scope(\_SB) /* Set RFD */ Method(SRFD, 1, Serialized) { - If (And(Arg0, 0x01)) { - Store (1, GP14) // GLED - Store (1, GP15) // GDIS + If (Arg0 & 0x01) { + GP14 = 1 // GLED + GP15 = 1 // GDIS } Else { - Store (0, GP14) - Store (0, GP15) + GP14 = 0 + GP15 = 0 } /* WIFI */ - If (And(Arg0, 0x02)) { - Store (1, GP12) // WLED - Store (1, GP25) // WLAN + If (Arg0 & 0x02) { + GP12 = 1 // WLED + GP25 = 1 // WLAN } Else { - Store (0, GP12) - Store (0, GP25) + GP12 = 0 + GP25 = 0 } /* Bluetooth */ - If (And(Arg0, 0x04)) { - Store (1, GP13) // BLED - Store (1, BTEN) + If (Arg0 & 0x04) { + GP13 = 1 // BLED + BTEN = 1 } Else { - Store (0, GP13) // BLED - Store (0, BTEN) + GP13 = 0 // BLED + BTEN = 0 } Return (0) } @@ -542,7 +539,7 @@ Scope(\_SB) /* Set IGD (Graphics) */ Method(SIGD, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf7) } Else { TRAP(0xf8) @@ -553,7 +550,7 @@ Scope(\_SB) /* SMI-C? Set Mic? */ Method (SMIC, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xeb) } Else { TRAP(0xec) @@ -570,7 +567,7 @@ Scope(\_SB) /* Not even decent function names anymore? */ Method(S024, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf1) } Else { TRAP(0xf2) @@ -588,13 +585,13 @@ Scope(\_SB) /* ??? Something with PATA */ Method(S025, 1, Serialized) { - If(And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xfc) - Store (1, GP33) // CREN + GP33 = 1 // CREN Sleep(1500) - Store (1, GP34) // CRRS + GP34 = 1 // CRRS Sleep(500) Notify(^^PCI0.PATA, 0) @@ -602,7 +599,7 @@ Scope(\_SB) } Else { TRAP(0xfb) Sleep(1500) - Store(0, GP33) // CREN + GP33 = 0 // CREN Sleep(1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID, 0) @@ -616,16 +613,16 @@ Scope(\_SB) Method(G021, 0, Serialized) { TRAP(0xfe) - If (LEqual(ACIN, 0)) { + If (ACIN == 0) { TRAP(0xfa) TRAP(0xfd) - If (LEqual(ODDS, 1)) { + If (ODDS == 1) { TRAP(0xfb) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) Notify(^^PCI0.PATA.PRID.DSK0, 1) Sleep (1500) - Store (0, GP33) // CREN + GP33 = 0 // CREN Sleep (1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) @@ -648,7 +645,7 @@ Scope(\_SB) /* ??? */ Method(S00B, 1, Serialized) { - If (And(Arg0, 1)) { + If (Arg0 & 1) { TRAP(0xdc) } Else { TRAP(0xdd) diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl index e72b980183..b9e4056ee7 100644 --- a/src/mainboard/getac/p470/acpi/gpe.asl +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -15,7 +15,7 @@ Scope (_GPE) // Software GPE Method (_L02, 0) { - Store (0, GPEC) + GPEC = 0 } // USB1 @@ -42,7 +42,7 @@ Scope (_GPE) // SMBus (Reserved!) Method (_L07, 0) { - // Store (0x20, \_SB.PCI0.SBUS.HSTS) + // \_SB.PCI0.SBUS.HSTS = 0x20 } // COM1/COM2 (RI) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 98cecbc587..b9835d1f87 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -9,23 +9,23 @@ Method(_PTS,1) TRAP(0xed) Sleep(1000) - Store(0, \_SB.ACFG) + \_SB.ACFG = 0 // Are we going to S4? - If (Lequal(Arg0, 4)) { + If (Arg0 == 4) { TRAP(0xe7) TRAP(0xea) } // Are we going to S5? - If (Lequal(Arg0, 5)) { + If (Arg0 == 5) { TRAP(0xde) } // The 2.6.12.5 ACPI engine seems to optimize the - // If(LEqual(Arg0, 5)) path away. This keeps it from doing so: + // If(Arg0 == 5) path away. This keeps it from doing so: TRAP(Arg0) - Store(Arg0, DBG0) + DBG0 = Arg0 // End of ugly OS bug workaround } @@ -34,12 +34,12 @@ Method(_PTS,1) Method(_WAK,1) { // Enable GPS - Store (1, GP11) // GPSE + GP11 = 1 // GPSE // Wake from S3 or S4? - If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) { - If (And(CFGD, 0x01000000)) { - If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + If (CFGD & 0x01000000) { + If ((CFGD & 0xF0) && (OSYS == 2001)) { TRAP(0x3d) } } @@ -48,26 +48,26 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - If (LEqual(RP1D, 0)) { + If (RP1D == 0) { Notify(\_SB.PCI0.RP01, 0) } - If (LEqual(RP3D, 0)) { + If (RP3D == 0) { Notify(\_SB.PCI0.RP03, 0) } - If (LEqual(RP4D, 0)) { + If (RP4D == 0) { Notify(\_SB.PCI0.RP04, 0) } // Are we coming from S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { TRAP(0xeb) TRAP(0x46) } // Are we coming from S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { Notify(SLPB, 0x02) If (DTSE) { TRAP(0x47) @@ -75,16 +75,16 @@ Method(_WAK,1) } // Windows XP SP2 P-State restore - If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_SB.CP00._PPC, 0)) { - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + If ((OSYS == 2002) && (CFGD & 0x01)) { + If (\_SB.CP00._PPC > 0) { + \_SB.CP00._PPC -= 1 PNOT() - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() } Else { - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC -= 1 PNOT() } } @@ -118,7 +118,7 @@ Scope(\_SB) * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { TRAP(0x3d) } diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 705b2b9c61..ab3839c6aa 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -19,13 +19,13 @@ Device (SIO1) Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Device (SIO1) Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -55,13 +55,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -74,12 +74,12 @@ Device (SIO1) { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -104,8 +104,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = (_STA () & 0x02) + If (Local0 == 0) { Return(NONE) } @@ -117,15 +117,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x24, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -138,29 +138,29 @@ Device (SIO1) WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -168,22 +168,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -199,19 +199,19 @@ Device (SIO1) Method (_STA, 0) { /* IRDA? */ - Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + Local0 = READ(0, 0x0c, 0x38) + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -224,12 +224,12 @@ Device (SIO1) { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -254,8 +254,8 @@ Device (SIO1) IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -267,15 +267,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -288,55 +288,55 @@ Device (SIO1) WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -354,13 +354,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1b, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1b, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x02), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x02) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -373,12 +373,12 @@ Device (SIO1) { WRIT(0, 0x1b, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -403,8 +403,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 5 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -416,15 +416,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1b, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0x00, 0x1b, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -437,29 +437,29 @@ Device (SIO1) WRIT(0, 0x1b, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1b, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -467,22 +467,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -501,13 +501,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1c, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1c, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x04), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x04) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -520,12 +520,12 @@ Device (SIO1) { WRIT(0, 0x1c, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -550,8 +550,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 11 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -563,15 +563,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1c, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x1c, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -584,29 +584,29 @@ Device (SIO1) WRIT(0, 0x1c, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -614,22 +614,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 6e3dc22cf9..4e31ef3a93 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -17,11 +17,11 @@ Scope (\_TZ) // Convert from °C to 1/10 Kelvin Method(DEGR, 1, NotSerialized) { - Store(Arg0, Local0) + Local0 = Arg0 // 10ths of degrees - Multiply(Local0, 10, Local0) + Local0 *= 10 // 0°C is 273.15 K, we need to round it. - Add(Local0, 2732, Local0) + Local0 += 2732 Return(Local0) } @@ -35,24 +35,24 @@ Scope (\_TZ) // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CRTT + Local0 = DEGR (Local0) Return(Local0) } // CPU throttling start temperature Method (_PSV, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTRO + Local0 = DEGR (Local0) Return(Local0) } // Get DTS Temperature Method (_TMP, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTMP + Local0 = DEGR (Local0) Return(Local0) } diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index b5b5223a5f..96e3d31738 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -9,7 +9,7 @@ #include "mainboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable COM port(s) */ gnvs->cmap = 0x01; @@ -44,7 +44,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) ecdt->ec_control.addrl = 0x66; ecdt->ec_control.addrh = 0; - ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ + ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; ecdt->ec_data.bit_width = 8; ecdt->ec_data.bit_offset = 0; ecdt->ec_data.addrl = 0x62; diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index 5f60dc98af..825f54b828 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -4,100 +4,74 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index e6865dd7f2..4686db1b95 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #define ENABLE_TPM -#undef ENABLE_FDC // There is no Floppy for this laptop #include DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 8550f69d03..087e279ac4 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index 9a8bf5bc90..f6a99e7fdb 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c deleted file mode 100644 index 496d4190c6..0000000000 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout index e0d6ec5244..41f967d7ab 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -4,95 +4,69 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index d6f1f5329b..c0f198f4e7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -27,14 +27,14 @@ chip northbridge/intel/i945 end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x8c" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x83" - register "pirqd_routing" = "0x8b" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x85" + register "pirqh_routing" = "0x80" # GPI routing # 0 No effect (default) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index 94684d093a..80c5ff44c6 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index 3012052a24..f22470cf9b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -4,7 +4,7 @@ #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout index 1860a78326..8c6a055ca3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -4,88 +4,61 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused +421 1 e 9 sata_mode # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index fbc31b7788..0c24a9db5b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -2,12 +2,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" # Magic APIC ID to locate this chip device lapic 0x0 on end device lapic 0xacac off end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 2fd748f1f9..7a965176e7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index f7296e14f2..78f2ad633a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->lptp = 0; /* LPT port */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 79094e6009..60635e0b2b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -4,91 +4,64 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c deleted file mode 100644 index 852b0b4ae7..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout index 1860a78326..8c6a055ca3 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout +++ b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout @@ -4,88 +4,61 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused +421 1 e 9 sata_mode # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index cb7b918962..d0ec09c8c1 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index f9d158e8a3..40f5faf465 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 7c667b527d..0d07bdba06 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 1ae2f7b31e..2d5aa7552d 100644 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -15,22 +15,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Elpida_EDJ2116DEBG - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index ef0855517f..c5ad8c850f 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 8046be6477..f24c9e9ead 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -40,7 +40,7 @@ static void mainboard_final(void *chip_info) ABAR &= 0xFFFFFC00; memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ *memptr = 0x21; /* force to GEN2 and start re-negotiate */ - mdelay (1); + mdelay(1); *memptr = 0x20; } diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 2ea529ffcc..af7da08234 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -40,13 +40,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -143,13 +143,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/gizmosphere/gizmo/Elpida_EDJ2116DEBG.spd.hex b/src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex similarity index 100% rename from src/mainboard/gizmosphere/gizmo/Elpida_EDJ2116DEBG.spd.hex rename to src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 7a02ec851b..6375bc4982 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select GFXUMA select HUDSON_IMC_ENABLE + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 653dcc3529..0f808f076f 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -10,22 +10,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_MT41J128M16JT - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex b/src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex similarity index 100% rename from src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex rename to src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig new file mode 100644 index 0000000000..5f5ed856be --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig @@ -0,0 +1,55 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_ASURADA_COMMON + def_bool n + +if BOARD_GOOGLE_ASURADA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8192 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 + +config MAINBOARD_DIR + string + default "google/asurada" + +config MAINBOARD_PART_NUMBER + string + default "Asurada" if BOARD_GOOGLE_ASURADA + default "Hayato" if BOARD_GOOGLE_HAYATO + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 9 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 + +endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name new file mode 100644 index 0000000000..6f287e50f9 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig.name @@ -0,0 +1,9 @@ +comment "Asurada" + +config BOARD_GOOGLE_ASURADA + bool "-> Asurada" + select BOARD_GOOGLE_ASURADA_COMMON + +config BOARD_GOOGLE_HAYATO + bool "-> Hayato" + select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc similarity index 55% rename from src/mainboard/google/cheza/Makefile.inc rename to src/mainboard/google/asurada/Makefile.inc index 949d775624..601b485555 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -1,20 +1,23 @@ -## SPDX-License-Identifier: GPL-2.0-only +subdirs-y += sdram_params/ -bootblock-y += boardid.c -bootblock-y += chromeos.c +bootblock-y += memlayout.ld bootblock-y += bootblock.c -bootblock-y += reset.c +bootblock-y += chromeos.c -verstage-y += boardid.c +verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c +romstage-y += memlayout.ld romstage-y += boardid.c romstage-y += chromeos.c +romstage-y += regulator.c romstage-y += romstage.c -romstage-y += reset.c +romstage-y += sdram_configs.c +ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c +ramstage-y += regulator.c diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/asurada/board_info.txt similarity index 63% rename from src/mainboard/google/cheza/board_info.txt rename to src/mainboard/google/asurada/board_info.txt index 5e6e3b235a..b8059ad8f2 100644 --- a/src/mainboard/google/cheza/board_info.txt +++ b/src/mainboard/google/asurada/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Cheza Qualcomm SDM845 reference board +Board name: Asurada MediaTek MT8192 reference board Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c new file mode 100644 index 0000000000..cb91812bbf --- /dev/null +++ b/src/mainboard/google/asurada/boardid.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +#define ADC_LEVELS 15 + +enum { + RAM_ID_CHANNEL = 3, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, + [12] = 1457500, + [13] = 1575600, + [14] = 1683600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + +uint32_t sku_id(void) +{ + return 0; +} + +uint32_t ram_code(void) +{ + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) + cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + + return cached_ram_code; +} diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c new file mode 100644 index 0000000000..647555a339 --- /dev/null +++ b/src/mainboard/google/asurada/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +void bootblock_mainboard_init(void) +{ + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c new file mode 100644 index 0000000000..56a1084e81 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_H1_AP_INT); +} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd new file mode 100644 index 0000000000..2635854866 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb new file mode 100644 index 0000000000..0bdeec2b5f --- /dev/null +++ b/src/mainboard/google/asurada/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8192 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000000..ae34d33313 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) +/* EN_SPK */ +#define GPIO_EN_SPK_AMP GPIO(CAM_PDN1) + +void setup_chromeos_gpios(void); + +#endif diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c new file mode 100644 index 0000000000..812cb006da --- /dev/null +++ b/src/mainboard/google/asurada/mainboard.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gpio.h" + +#include + +#define MSDC0_DRV_MASK 0x3fffffff +#define MSDC1_DRV_MASK 0x3ffff000 +#define MSDC0_DRV_VALUE 0x24924924 +#define MSDC1_DRV_VALUE 0x1b6db000 + +#define MSDC1_GPIO_MODE0_BASE 0x10005360 +#define MSDC1_GPIO_MODE0_MASK 0x77777000 +#define MSDC1_GPIO_MODE0_VALUE 0x11111000 + +#define MSDC1_GPIO_MODE1_BASE 0x10005370 +#define MSDC1_GPIO_MODE1_MASK 0x7 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +/* GPIO names */ +#define GPIO_EDPBRDG_INT_ODL GPIO(EINT6) /* 6 */ +#define GPIO_EDPBRDG_PWREN GPIO(DSI_TE) /* 41 */ +#define GPIO_EDPBRDG_RST_ODL GPIO(LCM_RST) /* 42 */ +#define GPIO_EN_PP3300_EDP_DX GPIO(PERIPHERAL_EN1) /* 127 */ +#define GPIO_EN_PP1800_EDPBRDG_DX GPIO(PERIPHERAL_EN2) /* 128 */ +#define GPIO_EN_PP1000_EDPBRDG GPIO(PERIPHERAL_EN3) /* 129 */ +#define GPIO_EN_PP3300_DISPLAY_DX GPIO(CAM_CLK3) /* 136 */ +#define GPIO_AP_EDP_BKLTEN GPIO(KPROW1) /* 152 */ +#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) /* 40 */ + +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(¶m_reset.h); +} + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_backlight_and_bridge(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); + gpio_output(GPIO_EN_PP3300_DISPLAY_DX, 1); + + /* Turn on bridge */ + gpio_output(GPIO_EDPBRDG_RST_ODL, 0); + gpio_output(GPIO_EN_PP1000_EDPBRDG, 1); + gpio_output(GPIO_EN_PP1800_EDPBRDG_DX, 1); + gpio_output(GPIO_EN_PP3300_EDP_DX, 1); + mdelay(2); + gpio_output(GPIO_EDPBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_EDPBRDG_RST_ODL, 1); +} + +static bool configure_display(void) +{ + struct edid edid; + const u8 i2c_bus = 3; + + printk(BIOS_INFO, "%s: Starting display init\n", __func__); + + configure_backlight_and_bridge(); + mtk_i2c_bus_init(i2c_bus); + + if (anx7625_init(i2c_bus)) { + printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); + return false; + } + + if (anx7625_dp_get_edid(i2c_bus, &edid)) { + printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); + return false; + } + if (anx7625_dp_start(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Can't start display via ANX7625\n", __func__); + return false; + } + + const char *name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET); + + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); + return false; + } + mtk_ddp_mode_set(&edid); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + return true; +} + +static void configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ + clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); +} + +static void configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RM_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + uint8_t enable = 1; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); + + mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); +} + +static void configure_audio(void) +{ + /* Audio PWR */ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(I2S3_MCK), PAD_I2S3_MCK_FUNC_I2S3_MCK); + gpio_set_mode(GPIO(I2S3_BCK), PAD_I2S3_BCK_FUNC_I2S3_BCK); + gpio_set_mode(GPIO(I2S3_LRCK), PAD_I2S3_LRCK_FUNC_I2S3_LRCK); + gpio_set_mode(GPIO(I2S3_DO), PAD_I2S3_DO_FUNC_I2S3_DO); +} + +static void mainboard_init(struct device *dev) +{ + configure_emmc(); + configure_sdcard(); + configure_audio(); + setup_usb_host(); + + register_reset_to_bl31(); + + if (dpm_init()) + printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n"); + + if (spm_init()) + printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); + + if (display_init_required()) + configure_display(); + else + printk(BIOS_INFO, "%s: Skipped display init\n", __func__); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl b/src/mainboard/google/asurada/memlayout.ld similarity index 60% rename from src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl rename to src/mainboard/google/asurada/memlayout.ld index 66940633a4..0f1fcec9a0 100644 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/asurada/memlayout.ld @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c new file mode 100644 index 0000000000..d57df0126d --- /dev/null +++ b/src/mainboard/google/asurada/regulator.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static int get_mt6360_regulator_id(enum mtk_regulator regulator) +{ + switch (regulator) { + case MTK_REGULATOR_VDD2: + return MT6360_BUCK1; + case MTK_REGULATOR_VDDQ: + return MT6360_LDO7; + case MTK_REGULATOR_VMDDR: + return MT6360_LDO6; + case MTK_REGULATOR_VCC: + return MT6360_LDO5; + case MTK_REGULATOR_VCCQ: + return MT6360_LDO3; + default: + break; + } + + return -1; +} + +static int get_mt6359p_regulator_id(enum mtk_regulator regulator) +{ + switch (regulator) { + case MTK_REGULATOR_VCORE: + return MT6359P_GPU11; + default: + break; + } + + return -1; +} + +void mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + /* + * Handle the regulator that does not have a regulator ID + * in its underlying implementation. + */ + if (regulator == MTK_REGULATOR_VDD1) { + mt6359p_set_vm18_voltage(voltage_uv); + return; + } + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + uint32_t voltage_mv = voltage_uv / 1000; + google_chromeec_regulator_set_voltage(id, voltage_mv, voltage_mv); + return; + } + + id = get_mt6359p_regulator_id(regulator); + if (id >= 0) { + mt6359p_buck_set_voltage(id, voltage_uv); + return; + } + + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); +} + +uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + /* + * Handle the regulator that does not have a regulator ID + * in its underlying implementation. + */ + if (regulator == MTK_REGULATOR_VDD1) + return mt6359p_get_vm18_voltage(); + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + uint32_t voltage_mv = 0; + google_chromeec_regulator_get_voltage(id, &voltage_mv); + return voltage_mv * 1000; + } + + id = get_mt6359p_regulator_id(regulator); + if (id >= 0) + return mt6359p_buck_get_voltage(id); + + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); + + return 0; +} + +int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable) +{ + /* Return 0 if the regulator is already enabled or disabled. */ + if (mainboard_regulator_is_enabled(regulator) == enable) + return 0; + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id < 0) { + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); + return -1; + } + + return google_chromeec_regulator_enable(id, enable); +} + +uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator) +{ + int id; + + id = get_mt6360_regulator_id(regulator); + if (id < 0) { + printk(BIOS_WARNING, "Invalid regulator ID: %d\n; assuming disabled", + regulator); + return 0; + } + + uint8_t enabled; + if (google_chromeec_regulator_is_enabled(id, &enabled) < 0) { + printk(BIOS_WARNING, + "Failed to query regulator ID: %d\n; assuming disabled", + regulator); + return 0; + } + + return enabled; +} diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c new file mode 100644 index 0000000000..91ee7c074d --- /dev/null +++ b/src/mainboard/google/asurada/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +void do_board_reset(void) +{ + gpio_output(GPIO_RESET, 1); +} diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c new file mode 100644 index 0000000000..47c1fb2268 --- /dev/null +++ b/src/mainboard/google/asurada/romstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "read data from flash, ret=%#zx, length=%#zx\n", ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "write data from flash, ret=%#zx, length=%#zx\n", ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + +void platform_romstage_main(void) +{ + mt6359p_romstage_init(); + mt_mem_init(&dparam_ops); + mtk_mmu_after_dram(); +} diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c new file mode 100644 index 0000000000..e1eb527720 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const char *const sdram_configs[] = { + [0] = "sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB", + [1] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB", +}; + +static struct sdram_info params; + +const struct sdram_info *get_sdram_config(void) +{ + uint32_t ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) || + cbfs_load(sdram_configs[ramcode], ¶ms, sizeof(params)) != sizeof(params)) + die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode); + + return ¶ms; +} diff --git a/src/mainboard/google/asurada/sdram_params/Makefile.inc b/src/mainboard/google/asurada/sdram_params/Makefile.inc new file mode 100644 index 0000000000..acc8b5822f --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/Makefile.inc @@ -0,0 +1,10 @@ +sdram-params := +sdram-params += sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB + +$(foreach params,$(sdram-params), \ + $(eval cbfs-files-y += $(params)) \ + $(eval $(params)-file := $(params).c:struct) \ + $(eval $(params)-type := struct) \ + $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ +) diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c new file mode 100644 index 0000000000..8ae9b69bb1 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c new file mode 100644 index 0000000000..36fc0a29ce --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_6GB_3_3, +}; diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index c5e00fd148..5301e32571 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON select MAINBOARD_HAS_TPM1 select INTEL_INT15 select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_BUDDY + select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_BUDDY if BOARD_GOOGLE_BASEBOARD_AURON @@ -57,10 +58,6 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME default "samus" if BOARD_GOOGLE_SAMUS default "" -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 10dc637f01..501f54b4cf 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,16 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -24,18 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index da1b185c7e..77ff74375e 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -4,85 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a84aa98eeb..8bf2c129a4 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,39 +12,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - register "s0ix_enable" = "1" device cpu_cluster 0 on @@ -55,40 +22,64 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sio_acpi_mode" = "1" + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index c0f4d9f1ce..9da89ef439 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -16,7 +16,7 @@ DefinitionBlock( #include "acpi/thermal.asl" // global NVS and variables - #include + #include // CPU #include @@ -24,8 +24,8 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include - #include + #include + #include #include } } diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 371d91e8af..050d9cd54d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -5,7 +5,6 @@ #include "ec.h" #include "variant.h" - __weak void lan_init(void) { } diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd552..62e42b1718 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,16 +1,21 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" - device domain 0 on end + device pci 1f.2 on end # SATA Controller + end + end end diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index a446268132..69f8fd8fae 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Micron_4KTF25664HZ # 0b0000 SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index da00ad9dfb..12a9d7cb12 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -88,7 +88,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131c65..174463d0b7 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,16 +1,21 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" - device domain 0 on end + device pci 1f.2 on end # SATA Controller + end + end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index a446268132..69f8fd8fae 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Micron_4KTF25664HZ # 0b0000 SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index da00ad9dfb..12a9d7cb12 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -88,7 +88,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280b15..6762eb42c4 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,39 +1,43 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "sata_devslp_disable" = "0x1" - - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" register "s0ix_enable" = "0" device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus + chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + end end end diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 81bb828047..2ffc38a185 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -129,9 +129,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5529..ca5d616659 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,16 +1,21 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "500" # 50ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 50, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" - device domain 0 on end + device pci 1f.2 on end # SATA Controller + end + end end diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index a6a8232f48..18b1062bb5 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Samsung_M471B5674EB0-YK0 # 0b0000 SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0001 @@ -14,16 +12,4 @@ SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0101 SPD_SOURCES += empty # 0b0110 SPD_SOURCES += empty # 0b0111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index da00ad9dfb..12a9d7cb12 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -88,7 +88,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd552..62e42b1718 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,16 +1,21 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" - device domain 0 on end + device pci 1f.2 on end # SATA Controller + end + end end diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index c136955d4c..e4ffcf8f6a 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13, GPIO8} SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 # 0b0000 2GB SPD_SOURCES += empty # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b1101 4GB SPD_SOURCES += samsung_4GiB_dimm_K4B8G1646Q-MYK0 # 0b1110 8GB SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 0daf308922..905e196f7b 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -92,7 +92,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -104,7 +104,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) if (spd_file_len < SPD_LEN) die("Missing SPD data."); - /* CH0 */ memcpy(pei_data->spd_data[0][0], spd_file + (spd_index * SPD_LEN), SPD_LEN); diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96cac3f..34a785b711 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -3,38 +3,42 @@ chip soc/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "sata_port0_gen3_tx" = "0x72" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" - - # Disable S0ix for now - register "s0ix_enable" = "0" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" register "vr_slow_ramp_rate_set" = "3" register "vr_slow_ramp_rate_enable" = "1" + # Disable S0ix for now + register "s0ix_enable" = "0" + device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 15.3 on end # GSPI0 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - device pci 1d.0 off end # USB2 EHCI + chip soc/intel/broadwell/pch + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index aaf9b36b3a..cc1542fce2 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO65, GPIO67, GPIO68, GPIO69 } SPD_SOURCES = empty # 0b0000 SPD_SOURCES += empty # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += hynix_16 # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += elpida_16 # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 4684d86dce..4cad47432c 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -88,7 +88,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 0c9311f70c..9cd71a852f 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO def_bool n - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP @@ -60,4 +59,11 @@ config MAINBOARD_SMBIOS_MANUFACTURER config ENABLE_DDR_2X_REFRESH default y +config PCIEXP_AER + def_bool n + +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 3049dbee96..f6adb63ca5 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -14,11 +14,11 @@ Scope (\_SB.PCI0.RP01) Method (_DSW, 3, NotSerialized) { - Store (NIC_WAKE_GPIO, Local0) + Local0 = NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } @@ -36,11 +36,11 @@ Scope (\_SB.PCI0.RP02) Method (_DSW, 3, NotSerialized) { - Store (WLAN_WAKE_GPIO, Local0) + Local0 = WLAN_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 1292af4a20..96acaeb975 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -23,10 +23,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,66 +52,66 @@ Scope (\_TZ) // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available" - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -119,7 +119,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -127,7 +127,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -135,7 +135,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -143,7 +143,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { Return (CTOK (FAN4_THRESHOLD_ON)) @@ -159,25 +159,23 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -186,25 +184,23 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -213,25 +209,23 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -240,25 +234,23 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -267,25 +259,23 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 9756695c3d..e96edad58c 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -3,13 +3,11 @@ #include #include #include -#include #include #include -#include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -22,11 +20,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - // SuperIO is always RO - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index da1b185c7e..77ff74375e 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -4,85 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 304f3cf38f..8c54f6a6d0 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -18,14 +18,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end @@ -36,15 +28,6 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" @@ -54,8 +37,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index e262af9772..45442db902 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include } } diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index c14a1e4584..d9df5a1404 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -110,9 +110,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e87f431494..7eba3c2c2f 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -14,8 +14,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_FINALIZE); } - - static void mainboard_init(struct device *dev) { lan_init(); diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig new file mode 100644 index 0000000000..4f1854c4ea --- /dev/null +++ b/src/mainboard/google/brya/Kconfig @@ -0,0 +1,54 @@ +config BOARD_GOOGLE_BASEBOARD_BRYA + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9324 + select DRIVERS_SPI_ACPI + select DRIVERS_WIFI_GENERIC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_ALDERLAKE + +if BOARD_GOOGLE_BASEBOARD_BRYA + +config BASEBOARD_BRYA_LAPTOP + def_bool n + select SYSTEM_TYPE_LAPTOP + +config CHROMEOS + bool + default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_LID_SWITCH + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "google/brya" + +config MAINBOARD_FAMILY + string + default "Google_Brya0" if BOARD_GOOGLE_BRYA0 + +config MAINBOARD_PART_NUMBER + string + default "brya" if BOARD_GOOGLE_BRYA0 + +config VARIANT_DIR + string + default "brya0" if BOARD_GOOGLE_BRYA0 + +config UART_FOR_CONSOLE + int + default 0 + +endif # BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name new file mode 100644 index 0000000000..2c0e513668 --- /dev/null +++ b/src/mainboard/google/brya/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_GOOGLE_BRYA0 + bool "Brya 0" + select BOARD_GOOGLE_BASEBOARD_BRYA + select BASEBOARD_BRYA_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/google/brya/Makefile.inc similarity index 72% rename from src/mainboard/intel/cannonlake_rvp/Makefile.inc rename to src/mainboard/google/brya/Makefile.inc index 695b1ff349..a186bfc324 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -1,21 +1,20 @@ -## SPDX-License-Identifier: GPL-2.0-only - -subdirs-y += spd - bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += romstage_fsp_params.c +romstage-y += romstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += ec.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) -smm-y += smihandler.c subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/brya/board_info.txt b/src/mainboard/google/brya/board_info.txt new file mode 100644 index 0000000000..dad16fa8b3 --- /dev/null +++ b/src/mainboard/google/brya/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Brya +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c new file mode 100644 index 0000000000..817dd0fa42 --- /dev/null +++ b/src/mainboard/google/brya/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c new file mode 100644 index 0000000000..5b098b52ff --- /dev/null +++ b/src/mainboard/google/brya/chromeos.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd new file mode 100644 index 0000000000..64776feee1 --- /dev/null +++ b/src/mainboard/google/brya/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xb00000 + RW_SECTION_A@0xb00000 0x5e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x32ffc0 + RW_FWID_A@0x33ffc0 0x40 + ME_RW_A(CBFS)@0x340000 0x2a0000 + } + RW_SECTION_B@0x10e0000 0x5e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x32ffc0 + RW_FWID_B@0x33ffc0 0x40 + ME_RW_B(CBFS)@0x340000 0x2a0000 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl new file mode 100644 index 0000000000..fcdd1a8844 --- /dev/null +++ b/src/mainboard/google/brya/dsdt.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include + + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + /* Chipset specific sleep states */ + #include + + /* Chrome OS specific */ + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +} diff --git a/src/mainboard/google/brya/ec.c b/src/mainboard/google/brya/ec.c new file mode 100644 index 0000000000..6d0c4264cc --- /dev/null +++ b/src/mainboard/google/brya/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c new file mode 100644 index 0000000000..99a060df7f --- /dev/null +++ b/src/mainboard/google/brya/mainboard.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static void mainboard_dev_init(struct device *dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c new file mode 100644 index 0000000000..341df1570e --- /dev/null +++ b/src/mainboard/google/brya/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* ToDo : Fill FSP-M memory params */ +} diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c new file mode 100644 index 0000000000..9208d51613 --- /dev/null +++ b/src/mainboard/google/brya/smihandler.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/Makefile.inc similarity index 67% rename from src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc rename to src/mainboard/google/brya/variants/baseboard/Makefile.inc index 0ad298b5f4..9fb63f5f43 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += gpio.c ramstage-y += gpio.c -ramstage-y += nhlt.c diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..479a7eeb19 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref cnvi_bt on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end #USB3-1 Type A + device ref pcie_rp4 on end #USB3-4 WWAN + device ref pcie_rp5 on end #PCIE5 WLAN + device ref pcie_rp6 on end #PCIE6 WWAN + device ref pcie_rp8 on end #PCIE8 SD card + device ref pcie_rp9 on end #PCIE9-12 SSD + device ref uart0 on end + device ref gspi0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end + end +end diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c new file mode 100644 index 0000000000..f91dcc8d33 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -0,0 +1,406 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_A6, NONE, DEEP), + /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), + /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6), + /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6), + /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), + + /* B0 : SOC_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : SOC_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> SAR2_INT_L */ + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C7 : SML1DATA ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + + /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ + PAD_CFG_GPI(GPP_D17, NONE, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : PROC_GP0 ==> HPS_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : PROC_GP1 ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_E17, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), + /* F15 : GSXSRESET# ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_F19, NONE, DEEP), + /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F21, NONE, DEEP, LEVEL, INVERT), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : NC */ + PAD_NC(GPP_F23, NONE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H3, NONE, DEEP), + /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16 : NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_NC(GPD7, NONE), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPD11, NONE, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *__weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..fba653bd75 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..6f41718bd1 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h similarity index 59% rename from src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h rename to src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index f77d38bfb3..663306c291 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -1,21 +1,17 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ #include -#include +#include -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ +/* The next set of functions return the gpio table and fill in the number of entries for + * each table. + */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); - const struct cros_gpio *variant_cros_gpios(size_t *num); -/* Seed the NHLT tables with the board specific information. */ -struct nhlt; -void variant_nhlt_init(struct nhlt *nhlt); - #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brya/variants/brya0/include/variant/ec.h b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h b/src/mainboard/google/brya/variants/brya0/include/variant/gpio.h similarity index 71% rename from src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h rename to src/mainboard/google/brya/variants/brya0/include/variant/gpio.h index 33ccb11351..27c87b3fe7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/brya0/include/variant/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_GPIO_H__ #define __MAINBOARD_GPIO_H__ diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb new file mode 100644 index 0000000000..701a13fd7b --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -0,0 +1,295 @@ +chip soc/intel/alderlake + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + register "SaGv" = "SaGv_Disabled" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + device domain 0 on + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR1 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on end + end + chip drivers/i2c/sx9324 + register "desc" = ""SAR2 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 2C on end + end + end + device ref i2c3 on end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F15)" + register "wake" = "GPE0_DW2_15" + device spi 1 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 7ac37b2d46..ba1aa810a3 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -2,10 +2,9 @@ #include #include -#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -15,12 +14,12 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // TODO: MLR // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to // read/write instead of read-only for developer mode. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW; + if (CONFIG(CHROMEOS)) + gnvs_set_ecfw_rw(); // the lid is open by default. gnvs->lids = 1; @@ -28,5 +27,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* EC handles all thermal and fan control on Butterfly. */ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; - } diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index bee1e86fe5..057f6a5a9e 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -4,102 +4,74 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console # No serial port on this motherboard -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu # hyper_threading not supported by the Celeron 847 on this board -#400 1 e 2 hyper_threading -#401 7 r 0 unused +#400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size - -#547 437 r 0 unused +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 0c63305bf1..2b9753a361 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/sandybridge # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms @@ -26,13 +26,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 23f437019c..7bccd7f4b4 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index df51f66518..c439fe2e73 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -7,9 +7,6 @@ #include #include #include -#if CONFIG(CHROMEOS) -#include -#endif void mainboard_late_rcba_config(void) { @@ -79,15 +76,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index fc38136015..d9cf1b9434 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -153,7 +153,6 @@ static void program_keyboard_type(u32 search_address, u32 search_length) } else printk(BIOS_DEBUG, "Error: Could not locate VPD area\n"); - printk(BIOS_DEBUG, "Setting Keyboard type in EC to "); printk(BIOS_DEBUG, (kbd_type == EC_KBD_JP) ? "Japanese" : "English"); printk(BIOS_DEBUG, ".\n"); @@ -181,8 +180,7 @@ static void mainboard_init(struct device *dev) } } } else { - vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, - &search_length); + vpd_file = cbfs_map("vpd.bin", &search_length); if (vpd_file) { search_address = (unsigned long)vpd_file; } else { diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig deleted file mode 100644 index 3f3f75607b..0000000000 --- a/src/mainboard/google/cheza/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ - -config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variants - def_bool n - -if BOARD_GOOGLE_CHEZA_COMMON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select COMMON_CBFS_SPI_WRAPPER - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_RTC - select EC_GOOGLE_CHROMEEC_SPI - select RTC - select SOC_QUALCOMM_SDM845 - select SPI_FLASH - select SPI_FLASH_WINBOND - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_TPM2 - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_VBNV_FLASH - -config MAINBOARD_DIR - string - default "google/cheza" - -config DRIVER_TPM_SPI_BUS - hex - default 0x5 - -config EC_GOOGLE_CHROMEEC_SPI_BUS - hex - default 0xa - -########################################################## -#### Update below when adding a new derivative board. #### -########################################################## - -config MAINBOARD_PART_NUMBER - string - default "Cheza" if BOARD_GOOGLE_CHEZA - -endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name deleted file mode 100644 index fbfe4c919b..0000000000 --- a/src/mainboard/google/cheza/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ - -config BOARD_GOOGLE_CHEZA - bool "Cheza" - select BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h deleted file mode 100644 index 0207537800..0000000000 --- a/src/mainboard/google/cheza/board.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H -#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H - -#include -#include - -#define GPIO_EC_IN_RW GPIO(11) -#define GPIO_AP_EC_INT GPIO(122) -#define GPIO_AP_SUSPEND GPIO(126) -#define GPIO_WP_STATE GPIO(128) -#define GPIO_H1_AP_INT GPIO(129) - -void setup_chromeos_gpios(void); - -#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */ diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c deleted file mode 100644 index 2a3684646e..0000000000 --- a/src/mainboard/google/cheza/boardid.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -uint32_t board_id(void) -{ - const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t ram_code(void) -{ - const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t sku_id(void) -{ - const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c deleted file mode 100644 index cb010919d9..0000000000 --- a/src/mainboard/google/cheza/chromeos.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include "board.h" - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - -void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_AP_EC_INT); - gpio_output(GPIO_AP_SUSPEND, 1); - gpio_input(GPIO_WP_STATE); - gpio_input_pullup(GPIO_H1_AP_INT); -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), - "EC in RW"}, - {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), - "EC interrupt"}, - {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), - "TPM interrupt"}, - }; - - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd deleted file mode 100644 index 23d2d87ae2..0000000000 --- a/src/mainboard/google/cheza/chromeos.fmd +++ /dev/null @@ -1,42 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -FLASH@0x0 8M { - WP_RO 4M { - RO_SECTION 0x184000 { - BOOTBLOCK 96K - COREBOOT(CBFS) - #TODO: Move FMAP to 2M or 3M once FSG can be smaller - FMAP@0x180000 0x1000 - GBB 0x2f00 - RO_FRID 0x100 - } - RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K - RO_FSG(PRESERVE) - } - - RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA - } - - RW_SECTION_A 1280K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 256 - } - - - RW_SECTION_B 1280K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 256 - } - - RW_LEGACY(CBFS) -} diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb deleted file mode 100644 index 717653b379..0000000000 --- a/src/mainboard/google/cheza/devicetree.cb +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/qualcomm/sdm845 - device cpu_cluster 0 on end -end diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c deleted file mode 100644 index e2d02de4b7..0000000000 --- a/src/mainboard/google/cheza/mainboard.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static struct usb_board_data usb1_board_data = { - .pll_bias_control_2 = 0x28, - .imp_ctrl1 = 0x08, - .port_tune1 = 0x20, -}; - -static void setup_usb(void) -{ - /* - * Primary USB is used only for DP functionality on cheza platform. - * Hence Setting up only Secondary USB DWC3 controller. - */ - setup_usb_host1(&usb1_board_data); - - gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */ -} - -static void mainboard_init(struct device *dev) -{ - setup_usb(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .name = CONFIG_MAINBOARD_PART_NUMBER, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c deleted file mode 100644 index 9b5810f20b..0000000000 --- a/src/mainboard/google/cheza/reset.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), - but this works well enough for our purposes. */ -void do_board_reset(void) -{ - google_chromeec_reboot(0, EC_REBOOT_COLD, 0); -} diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c deleted file mode 100644 index e4f72a691f..0000000000 --- a/src/mainboard/google/cheza/romstage.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static void prepare_usb(void) -{ - /* - * Do DWC3 core and phy reset. Kick these resets - * off early so they get at least 1ms to settle. - */ - reset_usb1(); -} - -void platform_romstage_main(void) -{ - prepare_usb(); - - /* QCLib: DDR init & train */ - qclib_load_and_run(); -} diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index a3db6d78d8..1e8f8c23ff 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN select SYSTEM_TYPE_LAPTOP select USE_GOOGLE_FSP + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 240baca958..e85e93775c 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -88,7 +88,6 @@ Scope (\_SB.PCI0.I2C2) } } - Scope (\_SB.PCI0.LPEA) { Name (GBUF, ResourceTemplate () diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 2f2f298f8e..e70290873b 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -3,13 +3,12 @@ #include #include #include +#include #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; @@ -24,6 +23,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* Disable PMIC I2C port for ACPI for all boards except cyan */ if (!CONFIG(BOARD_GOOGLE_CYAN)) gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; + + gnvs->bdid = board_id(); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 91e9795f9b..cec1682ed1 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -7,14 +7,9 @@ chip soc/intel/braswell # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" register "PcdCaMirrorEn" = "1" @@ -40,9 +35,6 @@ chip soc/intel/braswell register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -68,9 +60,7 @@ chip soc/intel/braswell register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index beb355a0e4..b751fa3eea 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 17f14a29a1..b8266b31dc 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -19,7 +19,6 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 1c08d9069a..21a298e88a 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -35,8 +35,7 @@ static void *get_spd_pointer(int *dual) int spd_index = 0; /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc index 5e3cf38f90..8a9cee84db 100644 --- a/src/mainboard/google/cyan/variants/banon/Makefile.inc +++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc @@ -5,8 +5,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += empty @@ -14,17 +12,3 @@ SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 6bc9e82dd3..b2d1cbe355 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl index 2cb4bf392d..e9d7524305 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 46 #define DPTF_TSR0_CRITICAL 60 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR1_PASSIVE 48 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 68 #define DPTF_TSR2_CRITICAL 80 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 11f918b79a..2f21fd93d5 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -5,21 +5,5 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE # Index0 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # Index1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 62ee365ef4..b385ad7c8d 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -66,7 +66,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index a1521d4234..a5e9dbab3d 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 @@ -14,17 +12,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 8eee5cbf7b..9491c25d99 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 3482e95ede..06c61f21e7 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -39,7 +39,6 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 0 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 - /* SD CARD gpio */ #define SDCARD_CD 81 diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index b3651eac90..91c0d97a40 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -5,8 +5,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE @@ -19,17 +17,3 @@ SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index f327e159dd..c1b43b88ec 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl index bbdcfc7d34..b261570ca8 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 45 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "R4303_CPU" #define DPTF_TSR1_PASSIVE 49 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index ff707b4dee..14db7537eb 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 @@ -16,17 +14,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 1f121048f5..4e4b01a5c1 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl index ca3415182e..5bf3322906 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 55 #define DPTF_TSR0_CRITICAL 68 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 55 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 53 #define DPTF_TSR2_CRITICAL 66 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index b45a2b229e..8b4a77645b 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -6,24 +6,8 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index ecc5c54d95..ece6c8058d 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl index 554e129905..df393b95e4 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Charger" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 48 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/relm/Makefile.inc b/src/mainboard/google/cyan/variants/relm/Makefile.inc index 3de47937e6..47e32bb32b 100644 --- a/src/mainboard/google/cyan/variants/relm/Makefile.inc +++ b/src/mainboard/google/cyan/variants/relm/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF @@ -15,17 +13,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index fca36bbaef..5a0c13a6a3 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl index 554e129905..df393b95e4 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Charger" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 48 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/setzer/Makefile.inc b/src/mainboard/google/cyan/variants/setzer/Makefile.inc index d99926b203..1735907d8e 100644 --- a/src/mainboard/google/cyan/variants/setzer/Makefile.inc +++ b/src/mainboard/google/cyan/variants/setzer/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD @@ -18,17 +16,3 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 7938855d75..cdf57a447b 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl index dbc3d42f31..bebc11dfcc 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 58 #define DPTF_TSR0_CRITICAL 66 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 57 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 59 #define DPTF_TSR2_CRITICAL 66 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc index af07a93bc7..6358081d66 100644 --- a/src/mainboard/google/cyan/variants/terra/Makefile.inc +++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc @@ -6,23 +6,7 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-GD-F-R SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF-107WT - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 4b970b2631..11071eb560 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/ultima/Makefile.inc b/src/mainboard/google/cyan/variants/ultima/Makefile.inc index 10500c43c2..7cb457ef6c 100644 --- a/src/mainboard/google/cyan/variants/ultima/Makefile.inc +++ b/src/mainboard/google/cyan/variants/ultima/Makefile.inc @@ -5,23 +5,7 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 741b73e986..cef45aa609 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl index 095a538d9e..40230f09e2 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 60 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_DDR" #define DPTF_TSR1_PASSIVE 55 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 42 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc index aa1621addb..b6ff0d058f 100644 --- a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc +++ b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc @@ -4,24 +4,8 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCE SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 300f7d6acc..6e993305bb 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -130,7 +129,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -200,7 +198,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -230,7 +227,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl index 273020cd34..c5914976b4 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 75 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 2f07937475..1df786db83 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -18,6 +17,7 @@ #include #include #include +#include #include "exynos5250.h" @@ -28,15 +28,6 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ -static struct edid edid = { - .mode.ha = 1366, - .mode.va = 768, - .framebuffer_bits_per_pixel = 16, - .x_resolution = 1366, - .y_resolution = 768, - .bytes_per_line = 2 * 1366 -}; - /* TODO: transplanted DP stuff, clean up once we have something that works */ static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ @@ -263,7 +254,7 @@ static void mainboard_init(struct device *dev) sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 2 * 1366, 16); lcd_vdd(); diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index a5b7d3c147..5dc9c3efb3 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -5,7 +5,6 @@ #include #include #include -#include const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e8b7cf5f88..94a0a90259 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,8 +1,11 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI @@ -11,6 +14,8 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,6 +25,10 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU + select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_DEDEDE + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -30,16 +39,25 @@ config BASEBOARD_DEDEDE_LAPTOP config CHROMEOS bool default y + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DEVICETREE string default "variants/baseboard/devicetree.cb" @@ -53,8 +71,8 @@ config DRIVER_TPM_SPI_BUS config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 config MAINBOARD_DIR string @@ -71,9 +89,16 @@ config MAINBOARD_PART_NUMBER default "Dedede" if BOARD_GOOGLE_DEDEDE default "Drawcia" if BOARD_GOOGLE_DRAWCIA default "Drawcia" if BOARD_GOOGLE_DRAWCIA_LEGACY + default "Madoo" if BOARD_GOOGLE_MADOO default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE + default "Magolor" if BOARD_GOOGLE_MAGOLOR + default "Metaknight" if BOARD_GOOGLE_METAKNIGHT + default "Lantis" if BOARD_GOOGLE_LANTIS + default "Galtic" if BOARD_GOOGLE_GALTIC + default "Sasuke" if BOARD_GOOGLE_SASUKE + default "Storo" if BOARD_GOOGLE_STORO config MAX_CPUS int @@ -98,14 +123,15 @@ config VARIANT_DIR default "dedede" if BOARD_GOOGLE_DEDEDE default "drawcia" if BOARD_GOOGLE_DRAWCIA default "drawcia" if BOARD_GOOGLE_DRAWCIA_LEGACY + default "madoo" if BOARD_GOOGLE_MADOO default "waddledoo" if BOARD_GOOGLE_WADDLEDOO default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE - -config VARIANT_HAS_CAMERA_ACPI - bool - default n - help - Select this option to enable camera ACPI support on the variant. + default "magolor" if BOARD_GOOGLE_MAGOLOR + default "metaknight" if BOARD_GOOGLE_METAKNIGHT + default "lantis" if BOARD_GOOGLE_LANTIS + default "galtic" if BOARD_GOOGLE_GALTIC + default "sasuke" if BOARD_GOOGLE_SASUKE + default "storo" if BOARD_GOOGLE_STORO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 071ae5b64b..334865529b 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -20,6 +20,9 @@ config BOARD_GOOGLE_DRAWCIA select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" @@ -27,6 +30,15 @@ config BOARD_GOOGLE_DRAWCIA_LEGACY select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_MADOO + bool "-> Madoo" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_WADDLEDOO bool "Waddledoo" @@ -35,7 +47,8 @@ config BOARD_GOOGLE_WADDLEDOO select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" @@ -47,3 +60,39 @@ config BOARD_GOOGLE_WHEELIE bool "Wheelie" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_MAGOLOR + bool "-> Magolor" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_INTEL_MIPI_CAMERA + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_METAKNIGHT + bool "-> Metaknight" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_LANTIS + bool "-> Lantis" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + +config BOARD_GOOGLE_GALTIC + bool "-> Galtic" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_SASUKE + bool "-> Sasuke" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + +config BOARD_GOOGLE_STORO + bool "-> Storo" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl deleted file mode 100644 index e7a8bf4ee5..0000000000 --- a/src/mainboard/google/dedede/acpi/mainboard.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include -#include - -Method (PGPM, 1, Serialized) -{ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - \_SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - PGPM (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - PGPM (0) - } -} diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index fdb4b5ff64..22d35d7475 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -3,7 +3,7 @@ #include #include -int board_info_get_fw_config(uint32_t *fw_config) +int board_info_get_fw_config(uint64_t *fw_config) { return google_chromeec_cbi_get_fw_config(fw_config); } diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 09b2abc208..ade48661c5 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -4,29 +4,30 @@ FLASH@0xff000000 0x1000000 { SI_ME@0x1000 0x380000 } SI_BIOS@0x381000 0xc7f000 { - RW_LEGACY(CBFS)@0x0 0x1000 - RW_SECTION_A@0x1000 0x420000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x40ffc0 - RW_FWID_A@0x41ffc0 0x40 + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x421000 0x420000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x40ffc0 - RW_FWID_B@0x41ffc0 0x40 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x841000 0x3e000 { + RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x3000 - RW_SHARED@0x33000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x37000 0x2000 - RW_NVRAM(PRESERVE)@0x39000 0x5000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd index 60ea3ded64..4b318610cd 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd @@ -10,13 +10,15 @@ FLASH@0xfe000000 0x2000000 { RW_LEGACY(CBFS)@0x0 0xf00000 RW_SECTION_A@0xf00000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x23ffc0 + RW_FWID_A@0x24ffc0 0x40 + ME_RW_A(CBFS)@0x250000 0x190000 } RW_SECTION_B@0x12e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x23ffc0 + RW_FWID_B@0x24ffc0 0x40 + ME_RW_B(CBFS)@0x250000 0x190000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 933ca1a503..39cc25e156 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -27,9 +27,6 @@ DefinitionBlock( #include #include } - - /* Mainboard hooks */ - #include "acpi/mainboard.asl" } #if CONFIG(VARIANT_HAS_CAMERA_ACPI) @@ -37,11 +34,6 @@ DefinitionBlock( #include #endif - - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include - /* Chrome OS specific */ #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f400..23b15969c8 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,20 +4,29 @@ #include #include #include +#include #include +#include +#include #include -__weak void variant_isst_override(void) +static void mainboard_update_soc_chip_config(void) { - /* - * Implement the override only if the board uses very early/initial revisions of - * Silicon. Otherwise nothing to override. - */ -} + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + int ret; -static void mainboard_config_isst(void *unused) -{ - variant_isst_override(); + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } } static void mainboard_init(void *chip_info) @@ -31,6 +40,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + mainboard_update_soc_chip_config(); } static void mainboard_dev_init(struct device *dev) @@ -55,6 +66,3 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, }; - -/* Configure ISST before CPU initialization */ -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL); diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index af79c809a8..02ebfac426 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -21,19 +21,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return false; - } - - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store); - return true; -} diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 0254810ef3..c50578da70 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -21,6 +21,8 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -36,3 +38,12 @@ void elog_gsmi_cb_mainboard_log_wake_source(void) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); } + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void __weak variant_smi_sleep(u8 slp_typ) +{ +} diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index d2bed28dbc..ebc11e5d8a 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -1,19 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/lp4x/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd -endif +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/$(f)) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e126129f11..bb76c9c9ed 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,3 +1,17 @@ +fw_config + field DB_PORTS 0 3 + option DB_PORTS_NONE 0 + option DB_PORTS_2C_2A 1 + option DB_PORTS_1C_LTE 2 + option DB_PORTS_1A_HDMI 3 + option DB_PORTS_1C_1A 4 + end + field TABLETMODE 10 + option TABLETMODE_DISABLED 0 + option TABLETMODE_ENABLED 1 + end +end + chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end @@ -16,9 +30,9 @@ chip soc/intel/jasperlake # - GPP_D0 - WWAN_HOST_WAKE # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_C" - register "pmc_gpe0_dw2" = "GPP_D" + register "pmc_gpe0_dw0" = "PMC_GPP_B" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -32,16 +46,12 @@ chip soc/intel/jasperlake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -126,14 +136,6 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" @@ -141,9 +143,6 @@ chip soc/intel/jasperlake register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" @@ -152,9 +151,6 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - # Enable processor thermal control - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C # chipset_lockdown configuration @@ -163,34 +159,87 @@ chip soc/intel/jasperlake # register "common_soc_config." = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR config settings + # Imon Slope correction specified in 1/100 increment values. Range is 0-200. + # Eg: 125 = 1.25 + register "ImonSlope" = "100" + + # Imon offset correction. Value is a 2's complement signed integer. + # Units 1/1000, Range 0-63999. + # For an offset = 12.580, use 12580 + register "ImonOffset" = "0" + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on + # Default DPTF Policy for all Dedede boards if not overridden chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 10000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000) + }" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 99, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN) + }" - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 6000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 6000, - .max_power = 20000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 1000,}" + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" device generic 0 on end end @@ -271,10 +320,12 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 1284bc5e34..1d8d21d788 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { /* B2 : PROCHOT_ODL */ PAD_NC(GPP_B2, NONE), /* B3 : TRACKPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, LEVEL, INVERT), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ @@ -224,9 +224,9 @@ static const struct pad_config gpio_table[] = { /* E16 : GPP_E16/DDI1_DDC_SDA */ PAD_NC(GPP_E16, NONE), /* E17 : HDMI_DDC_SCL */ - PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : HDMI_DDC_SDA */ - PAD_NC(GPP_E18, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ @@ -238,7 +238,6 @@ static const struct pad_config gpio_table[] = { /* E23 : CNV_RGI_RSP */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), - /* F4 : CNV_RF_RST_L */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F7 : EMMC_CMD */ @@ -341,7 +340,6 @@ static const struct pad_config gpio_table[] = { /* R7 : I2S_SPK_AUDIO */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), - /* S0 : RAM_STRAP_4 */ PAD_CFG_GPI(GPP_S0, NONE, DEEP), /* S1 : RSVD_STRAP */ @@ -359,7 +357,6 @@ static const struct pad_config gpio_table[] = { /* S7 : DMIC0_DATA */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - /* GPD0 : AP_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 : GPP_GPD1/ACPRESENT */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl deleted file mode 100644 index aca7d04cb5..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C3) -{ - Name (STA0, Zero) - - /* Method to turn off Power Rails */ - Method (POFF, 0) - { - /* Disable PP1200 lane */ - CTXS(GPP_D14) - /* Disable PP2800 lane */ - CTXS(GPP_D13) - } - - Method (PON, 0) - { - /* Enable PP2800 lane */ - STXS(GPP_D13) - /* Enable PP1200 lane */ - STXS(GPP_D14) - } - - PowerResource (FCPR, 0x00, 0x0000) - { - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - MCON(0, 1) /* Clock 0, 19.2MHz */ - IF(!STA1) - { - /* Other sensor is OFF, so turn on power signals. */ - PON() - } - /* Assert Reset */ - CTXS(GPP_D15) - Sleep(5) /* 5 us */ - /* Deassert Reset */ - STXS(GPP_D15) - Sleep(5) /* 5 us */ - STA0 = 1 - } - - Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ - { - MCOF(0) /* Clock 0 */ - /* Assert Reset */ - CTXS(GPP_D15) - IF(!STA1) - { - /* Other sensor is OFF, so turn off power signals. */ - POFF() - } - STA0 = 0 - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA0) - } - } - - Device (CAM0) - { - Name (_HID, "OVTI9734") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x01) - { - One - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 180000000 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - Zero, - Zero - } - } - } - }) - } -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl deleted file mode 100644 index ef2a2a0f2c..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ /dev/null @@ -1,308 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C3) -{ - Name (STA1, Zero) - - PowerResource (RCPR, 0x00, 0x0000) - { - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - MCON(1, 1) /* Clock 1, 19.2MHz */ - /* Check if another sensor is ON */ - IF(!STA0) - { - /* Other sensor is OFF, so turn on power signals. */ - PON() - } - /* Assert Reset */ - CTXS(GPP_D12) - Sleep(5) /* 5 us */ - /* DeAssert Reset */ - STXS(GPP_D12) - Sleep(5) /* 5 us */ - STA1 = 1 - } - - Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ - { - MCOF(1) /* Clock 1 */ - /* Assert Reset */ - CTXS(GPP_D12) - IF(!STA0) - { - /* Other sensor is OFF, so turn off power signals. */ - POFF() - } - STA1 = 0 - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA1) - } - } - - Device(CAM1) - { - Name (_HID, "OVTI8856") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x04) - { - One, - 0x02, - 0x03, - 0x04, - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x02) - { - 0x15752A00, - 0xABA9500 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } - - Device(VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - - Name (_UID, 0x00) /* _UID: Unique ID */ - - Name (_DDN, "DW9768 VCM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package (0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9768" - } - } - }) - } - - Device (NVM0) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - - Name (_UID, 0x01) /* _UID: Unique ID */ - - Name (_DDN, "AT24 EEPROM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status*/ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package (0x05) - { - Package (0x02) - { - "size", - 0x2800 - }, - - Package (0x02) - { - "pagesize", - One - }, - - Package (0x02) - { - "read-only", - One - }, - - Package (0x02) - { - "address-width", - 0x0E - }, - - Package (0x02) - { - "compatible", - "atmel,24c1024" - } - } - }) - } -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl deleted file mode 100644 index 51b4ebc046..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam0.asl" -#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl deleted file mode 100644 index 81cbf61b8c..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (_SB.PCI0.IPU0) -{ - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x01) - { - One, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C3.CAM0, - Zero, - Zero - } - } - } - }) - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x04) - { - One, - 0x02, - 0x03, - 0x04, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C3.CAM1, - Zero, - Zero - } - } - } - }) -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl deleted file mode 100644 index 34c3d4b906..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) /* _ADR: Address */ - - Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ - } -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x02) - { - Package (0x02) - { - "port0", - "PRT0" - }, - - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index 1074f15dd3..24fe264455 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ @@ -42,9 +38,12 @@ * 2. Power button * 3. Key press * 4. Mode change + * 5. AC Connect/Disconnect */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index e99aa42011..855ab6d869 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 1f4044366d..e7bfd868aa 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ @@ -25,7 +21,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); * @param fw_config Address where the fw_config is stored. * @return 0 on success or negative integer for errors. */ -int board_info_get_fw_config(uint32_t *fw_config); +int board_info_get_fw_config(uint64_t *fw_config); /* Return memory configuration structure. */ const struct mb_cfg *variant_memcfg_config(void); @@ -40,7 +36,7 @@ int variant_memory_sku(void); */ bool variant_mem_is_half_populated(void); -/* Variant Intel Speed Shift Technology override */ -void variant_isst_override(void); +/* Allow each variants to customize SMI sleep flow. */ +void variant_smi_sleep(u8 slp_typ); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index dc43ea59b5..aa52636233 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -36,12 +36,6 @@ static const struct mb_cfg baseboard_memcfg_cfg = { .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6}, .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6}, - /* WaddleDoo uses 100, 100 and 100 rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* WaddleDoo Rcomp target values */ - .rcomp_targets = {80, 40, 40, 40, 30}, - /* Disable Early Command Training */ .ect = 1, diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc new file mode 100644 index 0000000000..67a7ab235a --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c new file mode 100644 index 0000000000..eb5e3c3cc8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* D23 : AP_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_INT(GPP_E11, NONE, PLTRST, EDGE_BOTH), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h b/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc b/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc index 2c50412765..d0960c7768 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 1e75864922..ff7a4d6b3b 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -10,9 +10,9 @@ chip soc/intel/jasperlake #| | before memory is up | #| I2C0 | Trackpad | #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | + #| I2C2 | Touchscreen, Stylus | #| I2C4 | Audio | + #| I2C5 | P-Sensor | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -21,19 +21,202 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, }, }" - device domain 0 on end + + # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN901C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end # I2C 4 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + device i2c 28 on end + end + end # I2C 5 + device pci 1f.3 on end # Intel HDA + end end diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c new file mode 100644 index 0000000000..2540fc7f2a --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc new file mode 100644 index 0000000000..24c75d1d9a --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h index 08870e0627..27c930d4f2 100644 --- a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h @@ -5,4 +5,7 @@ #include +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index 573213b877..f6282bf04c 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index a825c3ae8c..856d016914 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -1,2 +1,4 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt index 20887c1b63..26c06b6f40 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt @@ -1 +1,3 @@ MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index bc10e1ff2b..59593432fe 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -24,22 +24,122 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "20" # TCC of 85C + + # Enable Acoustic noise mitigation and set slew rate to 1/4 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy4" + register "FastPkgCRampDisable" = "1" + device domain 0 on + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{1,4}" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end + + device pci 04.0 on + chip drivers/intel/dptf + # Default DPTF Policy for all drawcia boards if not overridden + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 119, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3800, + .max_power = 5800, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -74,7 +174,121 @@ chip soc/intel/jasperlake register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end end # I2C 2 + device pci 15.3 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "nvm_size" = "0x0400" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x08" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c new file mode 100644 index 0000000000..b5effbbfc5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + filename = "wifi_sar-drawcia.hex"; + + return filename; +} + +const char *mainboard_vbt_filename(void) +{ + if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI))) + return "vbt_drawman.bin"; + + return "vbt.bin"; +} diff --git a/src/mainboard/google/dedede/variants/galtic/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/Makefile.inc new file mode 100644 index 0000000000..eb2c9bc021 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c new file mode 100644 index 0000000000..79646b5e2e --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP3300_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc new file mode 100644 index 0000000000..048c4fd1f3 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE , MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt new file mode 100644 index 0000000000..570f6802b4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt new file mode 100644 index 0000000000..9fae769262 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -0,0 +1,10 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name +H9HCNNNBKMMLXR-NEE, 0 +MT53E512M32D2NP-046 WT:E, 0 +MT53E1G32D2NP-046 WT:A, 1 +H9HCNNNCPMMLXR-NEE, 2 diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb new file mode 100644 index 0000000000..e981541122 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -0,0 +1,117 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C2 | Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + }" + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2702"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0001"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 10 on end + end + end # I2C 2 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h new file mode 100644 index 0000000000..27c930d4f2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc new file mode 100644 index 0000000000..f6282bf04c --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt new file mode 100644 index 0000000000..856d016914 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt new file mode 100644 index 0000000000..26c06b6f40 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb new file mode 100644 index 0000000000..297a5c0a97 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -0,0 +1,168 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Discrete Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end #I2C 1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end #I2C 3 + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/madoo/Makefile.inc b/src/mainboard/google/dedede/variants/madoo/Makefile.inc new file mode 100644 index 0000000000..04eb9a4877 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/madoo/gpio.c b/src/mainboard/google/dedede/variants/madoo/gpio.c new file mode 100644 index 0000000000..314d39eb06 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/gpio.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h new file mode 100644 index 0000000000..d6c3859c91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc new file mode 100644 index 0000000000..693240ebaf --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2a158ee9ec --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt new file mode 100644 index 0000000000..2b339b6e07 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +H9HCNNNBKMMLXR-NEE +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb new file mode 100644 index 0000000000..e754882ee7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -0,0 +1,163 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 270, + .fall_time_ns = 270, + .data_hold_time_ns = 350, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 200, + .fall_time_ns = 200, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + }, + }, + }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "10" # TCC of 95C + + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "2" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 65, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "controls.power_limits.pl1" = "{ + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/madoo/variant.c b/src/mainboard/google/dedede/variants/madoo/variant.c new file mode 100644 index 0000000000..b8c3654ab0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + filename = "wifi_sar-madoo.hex"; + + return filename; +} diff --git a/src/mainboard/google/dedede/variants/magolor/Makefile.inc b/src/mainboard/google/dedede/variants/magolor/Makefile.inc new file mode 100644 index 0000000000..24c75d1d9a --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h b/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc new file mode 100644 index 0000000000..285df73c2e --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt new file mode 100644 index 0000000000..100c322e91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt new file mode 100644 index 0000000000..f05a5af118 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb new file mode 100644 index 0000000000..78d5ddea37 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -0,0 +1,303 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | TBD | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #| I2C5 | TBD | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 12000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "100" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + end # I2C 2 + device pci 15.3 on # I2C 3 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + end +end diff --git a/src/mainboard/google/dedede/variants/magolor/variant.c b/src/mainboard/google/dedede/variants/magolor/variant.c new file mode 100644 index 0000000000..e3b9599a91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + filename = "wifi_sar-magolor.hex"; + + return filename; +} diff --git a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc new file mode 100644 index 0000000000..67a7ab235a --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c new file mode 100644 index 0000000000..d6a7fd599f --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc new file mode 100644 index 0000000000..285df73c2e --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt new file mode 100644 index 0000000000..100c322e91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f05a5af118 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -0,0 +1,5 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb new file mode 100644 index 0000000000..322f72c788 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | TBD | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""World Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/metaknight/variant.c b/src/mainboard/google/dedede/variants/metaknight/variant.c new file mode 100644 index 0000000000..2540fc7f2a --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} diff --git a/src/mainboard/google/dedede/variants/sasuke/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc new file mode 100644 index 0000000000..eb2c9bc021 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c new file mode 100644 index 0000000000..cdce7764e1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B8 : WLAN_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_B8, NONE), + + /* C18 : AP_I2C_EMR_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + + /* D1 : WLAN_PERST_L ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : TOUCH_INT_ODL ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc new file mode 100644 index 0000000000..1d39fbc6b4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt new file mode 100644 index 0000000000..da0441c353 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt new file mode 100644 index 0000000000..e916160610 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb new file mode 100644 index 0000000000..d3b0dd74bf --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -0,0 +1,104 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "enable_delay_ms" = "20" + device usb 2.5 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on end + device pci 1c.7 on end + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/storo/include/variant/ec.h b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/storo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/storo/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc new file mode 100644 index 0000000000..c0e2fffb6b --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..ad6374dcce --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt new file mode 100644 index 0000000000..43363e7e0d --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb new file mode 100644 index 0000000000..404024b1d6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index eda535c992..e835c698be 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -2,4 +2,4 @@ romstage-y += memory.c -ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c new file mode 100644 index 0000000000..0905e8f217 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* E5 : AP_SUB_IO_2 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc index 37f25e0769..c6683e2e94 100644 --- a/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E -SPD_SOURCES += spd-7.hex # ID = 1(0b0001) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-7.hex # ID = 1(0b0001) Parts = NT6AP256T32AV-J2 diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index f070fa1b67..d594dbdeb7 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -21,22 +21,41 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" device domain 0 on + device pci 05.0 on end # IPU - MIPI Camera device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -59,7 +78,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" register "generic.wake" = "GPE0_DW0_03" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -70,7 +89,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""SIS6496"" register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" @@ -84,7 +103,36 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x00" device i2c 5c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end end # I2C 2 + device pci 15.3 on + chip drivers/i2c/gpiomux/mux + register "mux_gpio_count" = "1" + register "mux_gpio[0]" = "ACPI_GPIO_OUTPUT(GPP_E5)" + device generic 0 on + chip drivers/i2c/gpiomux/bus + device generic 0 on end # I2C Mux Bus 0 + end + chip drivers/i2c/gpiomux/bus + device generic 1 on end # I2C Mux Bus 1 + end + end # I2C MUX + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -110,6 +158,12 @@ chip soc/intel/jasperlake device i2c 29 on end end end + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/waddledee/variant.c b/src/mainboard/google/dedede/variants/waddledee/variant.c deleted file mode 100644 index ac3cf581d9..0000000000 --- a/src/mainboard/google/dedede/variants/waddledee/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index eda535c992..566f5cc767 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,5 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later romstage-y += memory.c - -ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc index 8552e95b45..be4a11895b 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-7.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 -SPD_SOURCES += spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-7.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:E diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 2936cddf6b..360f50adac 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -50,6 +50,21 @@ chip soc/intel/jasperlake }, }" device domain 0 on + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{1,4}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -87,13 +102,13 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""SIS6496"" register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "100" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "100" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "generic.enable_delay_ms" = "7" @@ -104,7 +119,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" @@ -122,8 +137,117 @@ chip soc/intel/jasperlake device i2c 10 on end end end # I2C 2 + device pci 15.3 on #I2C #3 CAM0 CAM1 and VCM0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 58 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI9734"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 9734 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "180000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D15" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end device pci 1c.7 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" device pci 00.0 on end end @@ -147,12 +271,12 @@ chip soc/intel/jasperlake device i2c 1a on end end end #I2C 4 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98360A"" + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" - device generic 0 on end - end - end # Intel HDA + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/waddledoo/variant.c b/src/mainboard/google/dedede/variants/waddledoo/variant.c deleted file mode 100644 index ac3cf581d9..0000000000 --- a/src/mainboard/google/dedede/variants/waddledoo/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc index 2c50412765..d0960c7768 100644 --- a/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index dafd593ab6..8d958493bd 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -90,7 +90,6 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/chromeos-gbe.fmd b/src/mainboard/google/deltaur/chromeos-gbe.fmd index 9b6fec3ab2..91918e88b9 100644 --- a/src/mainboard/google/deltaur/chromeos-gbe.fmd +++ b/src/mainboard/google/deltaur/chromeos-gbe.fmd @@ -7,9 +7,9 @@ FLASH@0xfe000000 0x2000000 { SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index bbec112b78..a84a448999 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -6,9 +6,9 @@ FLASH@0xfe000000 0x2000000 { SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index fac58bdf42..1bca44f26f 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -35,9 +35,6 @@ DefinitionBlock( /* VPD support */ #include - /* Low power idle table */ - #include - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index faca003ab7..e1cdb96959 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -7,7 +7,6 @@ #include #include - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 1af83259be..4a0c49f2aa 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -32,23 +32,19 @@ chip soc/intel/tigerlake register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" - register "SmbusEnable" = "1" # TODO: the lengths are all MID for right now. register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right) register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left) - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN) register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # PCIe root port 7 (Card Reader), clock 4 @@ -138,9 +134,6 @@ chip soc/intel/tigerlake register "gpio_pm[3]" = "0" register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics @@ -249,10 +242,12 @@ chip soc/intel/tigerlake device pci 14.1 off end # USB 3.2 1x1 xDCI HC device pci 14.2 on end # Shared SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi WiFi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi WiFi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h index b1abeb9eba..9ef6624cd2 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index ce79ebce3b..aadbbec56b 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 5bbcea604a..f5e5fb6b6d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/deltaur/variants/baseboard/sku.c b/src/mainboard/google/deltaur/variants/baseboard/sku.c index fb19e3c67f..3cd279ec10 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/sku.c +++ b/src/mainboard/google/deltaur/variants/baseboard/sku.c @@ -6,12 +6,12 @@ #include #include -static const uint32_t get_sku_index(void) +static uint32_t get_sku_index(void) { return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1)); } -const uint32_t sku_id(void) +uint32_t sku_id(void) { return skus[get_sku_index()].id; } diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h index e9dfb7431f..56873c02bd 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h index ac2ff9b622..60eb5aa447 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h index 46756990c4..d1c72ef360 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 01935c549b..44cc835d1f 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -31,7 +31,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.wake" = "GPE0_DW1_07" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h index e9dfb7431f..56873c02bd 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h index ac2ff9b622..60eb5aa447 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h index 50f5380046..27d8df849c 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index df67a8d18b..747010702c 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -16,12 +16,14 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMETLAKE + select SMBIOS_SERIAL_FROM_VPD if VPD + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_DRALLION @@ -92,7 +94,6 @@ config DEVICETREE config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ef2a94e1bd..92fa2b8318 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -6,13 +6,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -39,9 +39,6 @@ DefinitionBlock( #include - /* Low power idle table */ - #include - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 8725b83636..384e44bb57 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -2,33 +2,12 @@ #include #include -#include #include #include #include #include #include -#define VPD_KEY_SYSTEM_SERIAL "serial_number" -#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" -#define VPD_SERIAL_LEN 64 - -const char *smbios_system_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - -const char *smbios_mainboard_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index 99aea9c827..125413a1f3 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -1,21 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - ifeq ($(SPD_SOURCES),) SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) endif - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e9daf0d00d..90bd260207 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,8 +30,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s @@ -41,7 +39,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ @@ -153,9 +150,6 @@ chip soc/intel/cannonlake register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port @@ -163,7 +157,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -333,10 +326,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid @@ -364,7 +359,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" @@ -418,7 +413,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -445,12 +440,14 @@ chip soc/intel/cannonlake device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index 5ba7be722b..6219f271c8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -4,7 +4,7 @@ #define TS_PD GPP_E7 #define HDMI_PD GPP_E16 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b383ba..af5f8cd0fe 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -22,12 +22,12 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE + select HAVE_SPD_IN_CBFS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config CHROMEOS select DSAR_ENABLE @@ -62,10 +62,6 @@ config MAINBOARD_FAMILY string default "Google_Eve" -config MAX_CPUS - int - default 8 - config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_RT5514 @@ -75,4 +71,7 @@ config INCLUDE_NHLT_BLOBS config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n endif diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 3b1f22c8c1..c0531fa238 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -3,13 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "100" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" @@ -35,41 +36,20 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc0901" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -171,12 +151,9 @@ chip soc/intel/skylake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -248,7 +225,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, @@ -262,6 +238,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -311,6 +288,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" @@ -399,7 +377,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index b73dcb5129..0fface13f8 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 21d322275e..607486be4c 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -31,69 +31,69 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP41 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP44 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP45 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP67 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP42 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* TP43 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), +/* SPKR */ PAD_NC(GPP_B14, NONE), /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), -/* SMBCLK */ PAD_CFG_NC(GPP_C0), -/* SMBDATA */ PAD_CFG_NC(GPP_C1), -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SMBCLK */ PAD_NC(GPP_C0, NONE), +/* SMBDATA */ PAD_NC(GPP_C1, NONE), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, @@ -109,59 +109,59 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ /* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, UP_20K, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */ /* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */ -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP48 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP244 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -176,8 +176,8 @@ static const struct pad_config gpio_table[] = { DEEP), /* DISPLAY is master */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* TP109 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -189,38 +189,38 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, 20K_PU, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, UP_20K, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP26 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP25 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP15 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ /* Ensure UART pins are in native mode for H1 */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index 767281504d..8c4f005465 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = empty # 0b0000 SPD_SOURCES += samsung_dimm_K4E8E324EB # 0b0001 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b0010 @@ -11,17 +9,3 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB # 0b0011 SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0100 SPD_SOURCES += samsung_dimm_K4EBE304EB # 0b0101 SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0110 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 330ea5201c..e9405f08cb 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -82,8 +82,7 @@ uintptr_t mainboard_get_spd_data(void) printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 90a3dc4e62..afa8f90031 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -22,7 +22,6 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD select RT8168_SUPPORT_LEGACY_VPD_MAC select RT8168_SET_LED_MODE @@ -41,7 +40,6 @@ config OVERRIDE_DEVICETREE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config DRIVER_TPM_SPI_BUS default 0x1 @@ -62,10 +60,6 @@ config MAINBOARD_FAMILY default "Google_Kalista" if BOARD_GOOGLE_KARMA default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 @@ -97,4 +91,12 @@ config INCLUDE_NHLT_BLOBS_KARMA config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 83c77183a3..04c0d17a05 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index b8455fe9e9..e9d5a3544a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -1,12 +1,13 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" @@ -64,49 +65,28 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround # Intersil VR c-state issue workaround # send VR mailbox command for IA/GT/SA rails register "IslVrCmd" = "2" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -266,7 +246,6 @@ chip soc/intel/skylake register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear @@ -324,7 +303,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_psyspl2 = 90, .psys_pmax = 120, @@ -337,6 +315,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -392,6 +371,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2 @@ -417,7 +397,7 @@ chip soc/intel/skylake end end # PCI Express Port 3 device pci 1c.3 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index c6b0b01970..2ebc51ad04 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -7,46 +7,46 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, + EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -61,30 +61,30 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ -/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, UP_20K, DEEP), /* GPIO3 */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -96,55 +96,55 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ + PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP121 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP122 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP258 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -156,46 +156,46 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP191 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP192 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP190 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -204,20 +204,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -230,8 +230,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 432a180362..add697f941 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -7,187 +7,157 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, - DEEP), /* eSPI mode */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, - NF1), /* CLK_PCIE_LAN_REQ# */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, - NF1), /* PCIE_CLKREQ_SSD# */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU# */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, - NF1), /* PCIE_CLKREQ_POE# */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU1# */ -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, - NF1), /* PCIE_CLKREQ_WLAN# */ +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* PCIE_CLKREQ_POE# */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU1# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP44 */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP98 */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP44 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, - DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), -/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, - DEEP), /* SKU_ID0 */ -/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, - DEEP), /* SKU_ID1 */ -/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, - DEEP), /* SKU_ID2 */ -/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, - DEEP), /* SKU_ID3 */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP99 */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, - DEEP), /* SCREW_SPI_WP_STATUS */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP93 */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP104 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP105 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP91 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ -/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, - DEEP), /* OEM_ID1 */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, - DEEP), /* OEM_ID2 */ -/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, - DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP100 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP90 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP101 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP106 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP102 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP104 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP105 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP91 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP100 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP90 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP101 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, - NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, NONE), /* TPU_RST_PIN40 */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ /* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, NONE), /* TPU_RST_PIN42 */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, - NF1), /* Rear Dual-Stack USB Ports */ -/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, - NF1), /* Rear Single USB Port */ -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, - NF1), /* DDI1_HDMI_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, - NF1), /* DDI2_HDMI_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP96 */ +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), /* T1037 */ +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* T1025 */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */ +/* DDPD_HPD2 */ PAD_CFG_GPI_APIC_HIGH(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP43 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP48 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP42 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP37 */ -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP43 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP48 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP42 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP37 */ +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), /* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */ /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -196,20 +166,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP40 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP40 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP23 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP23 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP22 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP22 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP83 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP84 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP83 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP84 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 1d837934ac..3ca1648e0f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -49,15 +49,12 @@ chip soc/intel/skylake register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # None - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # None register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 309222b4f9..2735fed671 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -7,35 +7,35 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), /* TP104 */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* TP104 */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), /* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_SPK_EN */ -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ /* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, @@ -44,8 +44,8 @@ static const struct pad_config gpio_table[] = { NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -60,29 +60,29 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* V3P3_CCD_EN */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -94,60 +94,59 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCH_I2C0_8625_SDA */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCH_I2C0_8625_SCL */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, - PLTRST), /* HP_IRQ_GPIO */ +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* PCH_DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* PCH_DMIC_DATA0 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* BOOT_BEEP_OVERRIDE */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, - PLTRST), /* TOUCHSCREEN_INT# */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, + NONE), /* TOUCHSCREEN_INT# */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -159,12 +158,12 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ @@ -177,53 +176,53 @@ static const struct pad_config gpio_table[] = { DEEP), /* I2S_2_FS_LRC */ /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S_2_TX_DAC */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -236,8 +235,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 90d8c6578f..040b662f24 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -29,7 +29,6 @@ #endif - #if IPQ40XX_I2C1_PINGROUP_1 #define SCL_GPIO_I2C1 34 diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index d1cf1b3f15..9bdd307bc1 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -4,7 +4,6 @@ #include #include - #define TPM_RESET_GPIO 19 static void ipq_setup_tpm(void) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 9790552229..bd4e649fbe 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_GLADOS @@ -64,10 +65,6 @@ config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ @@ -85,4 +82,7 @@ config CONSOLE_SERIAL bool default n +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index 5162e48784..5b1c383ce7 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -10,7 +10,6 @@ config BOARD_GOOGLE_ASUKA config BOARD_GOOGLE_CAROLINE bool "-> Caroline (Samsung Chromebook Pro)" select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_INTEL_WIFI select DSAR_ENABLE select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS select SAR_ENABLE diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index f7be80d460..5a48c5db47 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -3,13 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" @@ -30,48 +31,24 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # Enable Root port 1 register "PcieRpEnable[0]" = "1" @@ -117,9 +94,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 @@ -134,7 +113,7 @@ chip soc/intel/skylake device pci 19.1 off end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 040c960ea0..42332428e4 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index b065cdd57e..9a968b16d4 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -10,7 +10,6 @@ #include "spd/spd_util.h" #include "spd/spd.h" - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 627dc3f4e5..9bfb202bb9 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -79,8 +79,7 @@ void spd_memory_init_params(FSPM_UPD *mupd, int spd_index) printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/glados/variants/asuka/Makefile.inc b/src/mainboard/google/glados/variants/asuka/Makefile.inc index ee3447823f..d1b4d16ba0 100644 --- a/src/mainboard/google/glados/variants/asuka/Makefile.inc +++ b/src/mainboard/google/glados/variants/asuka/Makefile.inc @@ -3,25 +3,9 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Single Channel 2GB SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0001 Dual Channel 4GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0010 Single Channel 2GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0011 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0100 Single Channel 2GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0101 Dual Channel 4GB - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index b6743dc47b..b4c65baa90 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -48,138 +48,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -192,14 +192,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -207,16 +207,16 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index a2545fcf08..6a942ee456 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -4,23 +4,7 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index SPD_SOURCES = samsung_dimm_K4E8E324EB-EGCF # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0001 SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0010 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 1f4bd6565a..24e7b33cc2 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -57,64 +57,64 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */ +/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* SD_CD_INT_L */ /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_CFG_GPI_SCI(GPP_B15, NONE, DEEP, EDGE_SINGLE, NONE), /* DIG EJECT */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -127,55 +127,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10), -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* TS_SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TS_SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -187,12 +187,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = { * SD write protect is not connected but is still sampled, so enable * native function and enable internal pull-down to disable. */ -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -224,16 +224,16 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index 7bee2e2a48..e213d027a4 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms @@ -10,19 +8,14 @@ chip soc/intel/skylake register "SlowSlewRateForIa" = "3" # Fast/16 register "SlowSlewRateForGt" = "3" # Fast/16 register "SlowSlewRateForSa" = "0" # Fast/2 - register "FastPkgCRampDisable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # PL2 override 15W register "power_limits_config" = "{ diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index 2f19b3fbd2..88e450ed6f 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = micron_4GiB_dimm_MT52L256M32D1PF # 0b0000 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 @@ -13,17 +11,3 @@ SPD_SOURCES += micron_8GiB_dimm_MT52L512M32D2PF # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 SPD_SOURCES += micron_16GiB_dimm_MT52L1G32D4PG # 0b0100 SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0101 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index e1c2d585fe..7d000f5d6e 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -53,65 +53,65 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -123,55 +123,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), - PAD_CFG_NC(GPP_D9), - PAD_CFG_NC(GPP_D10), - PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21), -/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22), +/* TS_SPI_IO2 */ PAD_NC(GPP_D21, NONE), +/* TS_SPI_IO3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */ /* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */ -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NC(GPP_E22), - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -181,14 +181,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,24 +208,24 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1), - PAD_CFG_NC(GPD7), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, UP_20K, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, UP_20K, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, UP_20K, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, UP_20K, DEEP, NF1), + PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index 9aeb78afa7..e77a2b4755 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -1,21 +1,15 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board) register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1 register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 # PL2 override 15W register "power_limits_config" = "{ diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index b820684b7c..53861e9839 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 @@ -18,17 +16,3 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0111 SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1000 SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR # 0b1001 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b1010 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 06c6e4a8f7..6d415ca30a 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -47,51 +47,51 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* SM1ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ @@ -100,11 +100,11 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */ /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */ /* SML0ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */ -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -117,55 +117,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), /* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -175,13 +175,13 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), @@ -194,15 +194,15 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* RSVD */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -210,18 +210,18 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), /* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index 3cf91e8f03..8858453cfc 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -4,24 +4,8 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = empty # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR # 0b0010 SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 5361744407..9ee00d2cf9 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -44,10 +44,10 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ /* GPP_A7 */ @@ -70,7 +70,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ /* GPP_B0 */ /* CORE_VID1 */ /* GPP_B1 */ /* VRALERT# */ /* GPP_B2 */ -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP), /* TRACKPAD */ /* CPU_GP3 */ /* GPP_B4 */ /* SRCCLKREQ0# */ /* GPP_B5 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ @@ -83,7 +83,7 @@ static const struct pad_config gpio_table[] = { /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ /* GPP_B14 */ /* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ /* GSPI0_MISO */ /* GPP_B17 */ /* GSPI0_MOSI */ /* GPP_B18 */ /* GSPI1_CS# */ /* GPP_B19 */ @@ -97,7 +97,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UART0_RXD */ /* GPP_C8 */ @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GPP_D0 */ /* GPP_D1 */ @@ -145,14 +145,14 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ /* GPP_E1 */ /* SATAXPCIE2 */ /* GPP_E2 */ /* CPU_GP0 */ /* GPP_E3 */ /* SATA_DEVSLP0 */ /* GPP_E4 */ /* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ /* SATALED# */ /* GPP_E8 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -160,8 +160,8 @@ static const struct pad_config gpio_table[] = { /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */ @@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* MIC_INT_L */ /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index c510e920a0..3a0fdd4418 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/lars/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc index e7ab2511f2..f295a360c2 100644 --- a/src/mainboard/google/glados/variants/lars/Makefile.inc +++ b/src/mainboard/google/glados/variants/lars/Makefile.inc @@ -3,8 +3,6 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 Single Channel 2GB SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 Dual Channel 8GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 Dual Channel 4GB @@ -21,17 +19,3 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1101 Dual Channel 8GB SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index d1785cea3c..3d00c353d7 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -43,124 +43,124 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* KEPLR_CLK_REQ */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_CLK_REQ */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), @@ -168,12 +168,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -186,14 +186,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -201,18 +201,18 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc index 019820a4b2..4de16c951a 100644 --- a/src/mainboard/google/glados/variants/sentry/Makefile.inc +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -3,8 +3,6 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0001 Dual Channel 4GB SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB @@ -21,18 +19,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 60d93d4308..717e930d24 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -51,137 +51,137 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -201,7 +201,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -209,17 +209,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb index 08d3dd3aba..36575f8856 100644 --- a/src/mainboard/google/glados/variants/sentry/overridetree.cb +++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 87a5009eb6..2aceb9f084 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -53,8 +53,7 @@ const struct rk3399_sdram_params *get_sdram_config() if (ramcode >= ARRAY_SIZE(sdram_configs) || !snprintf(config_file, sizeof(config_file), "%s-%d", sdram_configs[ramcode], get_sdram_target_mhz()) || - (cbfs_boot_load_file(config_file, ¶ms, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params))) + (cbfs_load(config_file, ¶ms, sizeof(params)) != sizeof(params))) die("Cannot load SDRAM parameter file!"); return ¶ms; diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig new file mode 100644 index 0000000000..40460e2dbd --- /dev/null +++ b/src/mainboard/google/guybrush/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_GUYBRUSH + def_bool n + +if BOARD_GOOGLE_BASEBOARD_GUYBRUSH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_CEZANNE + +config MAINBOARD_DIR + string + default "google/guybrush" + +config MAINBOARD_PART_NUMBER + string + default "Guybrush" if BOARD_GOOGLE_GUYBRUSH + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_FAMILY + string + default "Google_Guybrush" + +endif # BOARD_GOOGLE_BASEBOARD_GUYBRUSH diff --git a/src/mainboard/google/guybrush/Kconfig.name b/src/mainboard/google/guybrush/Kconfig.name new file mode 100644 index 0000000000..076516c03b --- /dev/null +++ b/src/mainboard/google/guybrush/Kconfig.name @@ -0,0 +1,5 @@ +comment "Guybrush" + +config BOARD_GOOGLE_GUYBRUSH + bool "-> Guybrush" + select BOARD_GOOGLE_BASEBOARD_GUYBRUSH diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc new file mode 100644 index 0000000000..1e8a88c95d --- /dev/null +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/guybrush/board_info.txt b/src/mainboard/google/guybrush/board_info.txt new file mode 100644 index 0000000000..008bcf7540 --- /dev/null +++ b/src/mainboard/google/guybrush/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Guybrush +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c new file mode 100644 index 0000000000..dd4c1516b1 --- /dev/null +++ b/src/mainboard/google/guybrush/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + /* TODO: Perform mainboard initialization */ +} diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd new file mode 100644 index 0000000000..be43e8a02d --- /dev/null +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -0,0 +1,33 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE(PRESERVE) 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c new file mode 100644 index 0000000000..3dc2c41d69 --- /dev/null +++ b/src/mainboard/google/guybrush/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static void mainboard_init(void *chip_info) +{ + /* TODO: Perform mainboard initialization */ +} + +static void mainboard_enable(struct device *dev) +{ + /* TODO: Enable mainboard */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..519bd07fab --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/cezanne + device domain 0 on + end # domain +end # chip soc/amd/cezanne diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h similarity index 58% rename from src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h rename to src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h index 102f5e12eb..b94afac4bf 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h @@ -1,8 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ -#include - #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..927af2f913 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3f0e83b426..d088341324 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,8 @@ config BOARD_GOOGLE_BASEBOARD_PUFF select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_INTEL_DPTF + select DPTF_USE_EISA_HID config BOARD_GOOGLE_HATCH_COMMON def_bool n @@ -28,6 +30,7 @@ config BOARD_GOOGLE_HATCH_COMMON select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -36,21 +39,23 @@ config BOARD_GOOGLE_HATCH_COMMON select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_DTT if BOARD_GOOGLE_HATCH_COMMON config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" @@ -76,10 +81,12 @@ config DIMM_SPD_SIZE config ROMSTAGE_SPD_CBFS bool default y if !ROMSTAGE_SPD_SMBUS + select HAVE_SPD_IN_CBFS config ROMSTAGE_SPD_SMBUS bool default n + select SPD_CACHE_IN_FMAP config DRIVER_TPM_SPI_BUS default 0x1 @@ -134,8 +141,10 @@ config MAINBOARD_PART_NUMBER default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE - default "Sushi" if BOARD_GOOGLE_SUSHI default "Wyvern" if BOARD_GOOGLE_WYVERN + default "Dooly" if BOARD_GOOGLE_DOOLY + default "Ambassador" if BOARD_GOOGLE_AMBASSADOR + default "Genesis" if BOARD_GOOGLE_GENESIS config OVERRIDE_DEVICETREE string @@ -167,12 +176,20 @@ config VARIANT_DIR default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE - default "sushi" if BOARD_GOOGLE_SUSHI default "wyvern" if BOARD_GOOGLE_WYVERN + default "dooly" if BOARD_GOOGLE_DOOLY + default "ambassador" if BOARD_GOOGLE_AMBASSADOR + default "genesis" if BOARD_GOOGLE_GENESIS config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC +config USE_PM_ACPI_TIMER + default n + +config TIANOCORE_BOOT_TIMEOUT + int + default 5 if BOARD_GOOGLE_BASEBOARD_PUFF + endif # BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3f803c5efc..7853c2ec31 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -90,10 +90,18 @@ config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH -config BOARD_GOOGLE_SUSHI - bool "-> Sushi" - select BOARD_GOOGLE_BASEBOARD_HATCH - config BOARD_GOOGLE_WYVERN bool "-> Wyvern" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + bool "-> Dooly" + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_AMBASSADOR + bool "-> Ambassador" + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_GENESIS + bool "-> Genesis" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index ffb7cfef66..d66844062f 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -26,6 +26,9 @@ DefinitionBlock( { #include #include +#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) + #include +#endif } } @@ -36,9 +39,6 @@ DefinitionBlock( #include - /* Low power idle table */ - #include - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { @@ -48,6 +48,7 @@ DefinitionBlock( #include } +#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) /* Dynamic Platform Thermal Framework */ Scope (\_SB) { @@ -56,4 +57,5 @@ DefinitionBlock( /* Include common dptf ASL files */ #include } +#endif } diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index af8810063c..93864b2ad1 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -8,7 +8,7 @@ #include #include -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { variant_devtree_update(); } diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a9a65e90af..f3c38bbf4f 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -56,29 +56,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } - -void mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - static enum { - PART_NUM_NOT_READ, - PART_NUM_AVAILABLE, - PART_NUM_NOT_IN_CBI, - } part_num_state = PART_NUM_NOT_READ; - - if (part_num_state == PART_NUM_NOT_READ) { - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - part_num_state = PART_NUM_NOT_IN_CBI; - } else { - part_num_state = PART_NUM_AVAILABLE; - } - } - - if (part_num_state == PART_NUM_NOT_IN_CBI) - return; - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store) + 1; -} diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index d21e86792d..e697379965 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc deleted file mode 100644 index dc1c9978a0..0000000000 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd -endif diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 0e3972813a..97a6eaf883 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -22,20 +22,12 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Unused - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # WWAN register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Unused - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -80,6 +72,9 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -180,7 +175,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -204,7 +199,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c new file mode 100644 index 0000000000..5a911fc4f9 --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h similarity index 78% rename from src/mainboard/google/hatch/variants/sushi/include/variant/ec.h rename to src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h index ce6fbfe1a4..59fb3783c5 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h @@ -3,6 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include +#include #endif diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb new file mode 100644 index 0000000000..7cc920d7ee --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -0,0 +1,489 @@ +chip soc/intel/cannonlake + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, + .thresholds={TEMP_PCT(70, 100), + TEMP_PCT(66, 90), + TEMP_PCT(62, 80), + TEMP_PCT(58, 70), + TEMP_PCT(53, 60), + TEMP_PCT(48, 50), + TEMP_PCT(43, 40), + TEMP_PCT(38, 30),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + register "PcieRpSlotImplemented[6]" = "1" + end # RTL8111H Ethernet NIC + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cb314ab6a2..7d9d1e64ca 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -18,10 +18,8 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x00fc0901" # FSP configuration - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST @@ -29,10 +27,6 @@ chip soc/intel/cannonlake register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable heci communication - register "HeciEnabled" = "0" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" # Enable DPTF @@ -58,8 +52,6 @@ chip soc/intel/cannonlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" - register "PmTimerDisabled" = "1" - # Select CPU PL2/PL4 config register "cpu_pl2_4_cfg" = "baseline" @@ -159,11 +151,8 @@ chip soc/intel/cannonlake register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 @@ -171,7 +160,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" @@ -303,16 +291,18 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -331,16 +321,19 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on # PCI Express Port 9 (X4 NVME) + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" device pci 00.0 on end end + register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl deleted file mode 100644 index 86bd8fc866..0000000000 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 85 -#define DPTF_CPU_ACTIVE_AC2 80 -#define DPTF_CPU_ACTIVE_AC3 75 -#define DPTF_CPU_ACTIVE_AC4 70 -#define DPTF_CPU_ACTIVE_AC5 65 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 15000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 64000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 537e3df102..d641405daa 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -35,10 +36,10 @@ static void wait_for_hpd(gpio_t gpio, long timeout) } /* - * For type-C chargers, set PL2 to 90% of max power to account for + * For type-C chargers, set PL2 to 97% of max power to account for * cable loss and FET Rdson loss in the path from the source. */ -#define SET_PSYSPL2(w) (9 * (w) / 10) +#define SET_PSYSPL2(w) (97 * (w) / 100) #define PUFF_U22_PL2 (35) #define PUFF_U62_U42_PL2 (51) #define PUFF_CELERON_PENTIUM_PSYSPL2 (65) @@ -65,7 +66,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) * +-------------+-----------------+---------+---------+-------+ * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | + * | n | min(0.97n, PL2) | 0.97n | 0.97n | 0.97n | * +-------------+-----+-----------+---------+---------+-------+ */ diff --git a/src/mainboard/google/hatch/variants/dooly/Makefile.inc b/src/mainboard/google/hatch/variants/dooly/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c new file mode 100644 index 0000000000..4406c060eb --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A17 : SD_VDD1_PWR_EN */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 */ + PAD_NC(GPP_A18, NONE), + /* A19 : GPP_A19 */ + PAD_NC(GPP_A19, NONE), + /* A20 : TOUCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A21 : FPMCU_PCH_BOOT0 */ + PAD_NC(GPP_A21, NONE), + /* A22 : FPMCU_PCH_INT_L */ + PAD_NC(GPP_A22, NONE), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : GPP_C3 */ + PAD_NC(GPP_C3, NONE), + /* C4 : GPP_C4 */ + PAD_NC(GPP_C4, NONE), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_NC(GPP_C7, NONE), + /* C11 : GPP_C11 */ + PAD_NC(GPP_C11, NONE), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C18 : GPP_C18 */ + PAD_NC(GPP_C18, NONE), + /* C19 : GPP_C19 */ + PAD_NC(GPP_C19, NONE), + + /* D16 : DMIC_ON_OFF MIC_SWITCH_L */ + PAD_CFG_GPI(GPP_D16, NONE, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + + /* F0 : GPP_F0 */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 */ + PAD_NC(GPP_F1, NONE), + /* F8 : GPP_F8 */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 */ + PAD_NC(GPP_F9, NONE), + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + + /* H3 : SPK_AMP_ON */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4: LVDS_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: LVDS_SDL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C_TOUCH_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TOUCH_SDL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h new file mode 100644 index 0000000000..7d280c6edf --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +#endif diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb new file mode 100644 index 0000000000..69d142886b --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -0,0 +1,434 @@ +chip soc/intel/cannonlake + + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 49, + }" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 0 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(3)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | ALC 1015 | + #| I2C2 | Lvds | + #| I2C3 | Touchscreen | + #| I2C4 | RT5682 | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(75, 60), + TEMP_PCT(65, 50), + TEMP_PCT(45, 40), + TEMP_PCT(30, 30),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 70, 60000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # 15-25W PL1 in 1000mW increments, avg over 28-32s interval + # 40-49W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + register "controls.power_limits.pl2" = "{ + .min_power = 40000, + .max_power = 49000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.3 on end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + chip drivers/usb/acpi + device usb 3.5 off end + end + end + end + end # USB xHCI + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end # I2C #0 ALC1015 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2 LVDS + device pci 15.3 on + chip drivers/i2c/hid + register "generic.hid" = ""WDHT2002"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C #3 Touchscreen + device pci 16.0 on end # Management Engine Interface 1 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index ccb5c0599b..f50f8f23a0 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -16,6 +16,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A19, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 2bfcc26c89..3605196c11 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -29,16 +29,16 @@ chip soc/intel/cannonlake # Intel Common SoC Config #+-------------------+---------------------------+ - #| Field | Value | + #| Field | Value | #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | FP MCU | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -47,18 +47,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 50, - .fall_time_ns = 15, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 25, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" @@ -69,6 +69,22 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -83,7 +99,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -111,7 +127,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -127,7 +143,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" @@ -169,6 +185,25 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "5" + device generic 0 on + chip drivers/i2c/generic + register "hid" = ""ACPI_DT_NAMESPACE_HID"" + register "name" = ""SBS0"" + register "uid" = "1" + register "compat_string" = ""sbs,sbs-battery"" + device i2c 0b on end + end + end + end + end + end + end # eSPI Interface device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 2f2b643951..25778f92cb 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -62,9 +66,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -268,6 +269,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(61, 80), + TEMP_PCT(57, 70), + TEMP_PCT(53, 60), + TEMP_PCT(49, 50), + TEMP_PCT(45, 40), + TEMP_PCT(41, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -369,6 +433,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -395,8 +460,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl deleted file mode 100644 index 2a94f94a85..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 90 -#define DPTF_CPU_CRITICAL 100 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 60 -#define DPTF_TSR0_CRITICAL 85 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 85 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 10000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 8aff8d192d..1ac9414c6a 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -70,8 +74,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # PL2303 - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -275,6 +277,35 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 73, 60000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 10000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -376,6 +407,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -402,8 +434,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/genesis/Makefile.inc b/src/mainboard/google/hatch/variants/genesis/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c new file mode 100644 index 0000000000..a095da1e11 --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/gpio.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : M2_SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : M2_TPU0_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : CLK_PCIE_REQ3 (not connected) */ + PAD_NC(GPP_B8, NONE), + /* B9 : M2_TPU1_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : M2_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h b/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h new file mode 100644 index 0000000000..59fb3783c5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h b/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb new file mode 100644 index 0000000000..1c05f52817 --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -0,0 +1,530 @@ +chip soc/intel/cannonlake + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # PCIe port 8 for WLAN + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # Uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "7" + register "PcieClkSrcClkReq[5]" = "5" + + # PCIe port 9 for TPU #0 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 10 for TPU #1 + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + # RP 10 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + # Disable the remaining port 12 + register "PcieRpEnable[11]" = "0" + + # PCIe port 13 for i350 NIC (x4) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "12" + # RP 13 does not use a source clock request line + # Disable the remaining ports 14-16 + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + # USB3 Port 5 is not populated + device usb 3.4 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 M.2 HDMI-to-USB"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 0)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on # PCI Express Port 7 (LAN) + chip drivers/net # RTL8111H Ethernet NIC + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end + device pci 1c.7 on # PCI Express Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot + end + device pci 1d.0 on # PCI Express Port 9 (TPU) + register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot + end + device pci 1d.1 on # PCI Express Port 10 (TPU) + register "PcieRpSlotImplemented[9]" = "1" # M.2 Slot + end + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.3 off end # PCI Express Port 12 (non-root) + device pci 1d.4 on # PCI Express Port 13 (X4 i350 NIC) + register "PcieRpSlotImplemented[12]" = "0" # Built-in + end + device pci 1d.5 off end # PCI Express Port 14 (non-root) + device pci 1d.6 off end # PCI Express Port 15 (non-root) + device pci 1d.7 off end # PCI Express Port 16 (non-root) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 76f634f0d7..01afa16000 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -68,6 +68,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -94,7 +97,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c index 38bca41bef..8282d1d398 100644 --- a/src/mainboard/google/hatch/variants/hatch/ramstage.c +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 34d235856e..c93562059a 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -36,7 +36,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, @@ -60,6 +60,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 6accd0cc92..129bb269f5 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -52,7 +52,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, @@ -76,6 +76,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f009202d..4029f062db 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ static const struct pad_config gpio_table[] = { * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h index 7eb6f11c13..593f89e942 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __JINLON_SKU_H__ #define __JINLON_SKU_H__ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6fde60278a..cf9344ee5a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,9 +1,7 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb854b0..16402af784 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -69,6 +69,9 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 02.0 on chip drivers/gfx/generic register "device_count" = "1" @@ -80,6 +83,19 @@ chip soc/intel/cannonlake device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -94,7 +110,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -122,7 +138,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -138,7 +154,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index 01691ff16c..50c6d0b1b1 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -62,9 +66,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -268,6 +269,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(61, 80), + TEMP_PCT(57, 70), + TEMP_PCT(53, 60), + TEMP_PCT(49, 50), + TEMP_PCT(45, 40), + TEMP_PCT(41, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -369,6 +433,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -395,8 +460,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index c75b7ba8c5..f27423f537 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -105,6 +105,9 @@ chip soc/intel/cannonlake register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -117,7 +120,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -156,7 +159,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6720ffce79..266346b3b5 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -27,21 +27,14 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -80,6 +73,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -161,7 +157,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.probed" = "1" register "generic.wake" = "GPE0_DW0_21" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 4e4d3888bd..74b3e1f4e8 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -88,6 +88,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -114,7 +117,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c index 38bca41bef..8282d1d398 100644 --- a/src/mainboard/google/hatch/variants/mushu/ramstage.c +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 951723ebeb..eb6217ded9 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -37,6 +37,8 @@ static const struct pad_config gpio_table[] = { /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, DN_20K, DEEP, NF1), /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ PAD_NC(GPP_E4, NONE), diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 3c184eb139..8805a324af 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -27,21 +27,11 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -131,6 +121,9 @@ chip soc/intel/cannonlake register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -215,7 +208,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN902C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c index d5a57af6e1..0e6eae644e 100644 --- a/src/mainboard/google/hatch/variants/nightfury/ramstage.c +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index cac7516000..cf6046224c 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -46,7 +48,6 @@ chip soc/intel/cannonlake .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "{ .enable = 1, .ocpin = OC0, @@ -55,9 +56,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -72,7 +70,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ @@ -195,6 +192,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(52, 80), + TEMP_PCT(50, 70), + TEMP_PCT(48, 60), + TEMP_PCT(46, 50), + TEMP_PCT(44, 40), + TEMP_PCT(42, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -284,6 +344,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -310,8 +371,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 115a593c85..3675375b28 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl index 13e251f576..1a704b3b15 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define DPTF_CPU_PASSIVE 0 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h index 34986c650a..978c738782 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h index 50b23f4fb5..a479a8c97e 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index c68c40cb72..5b802033b6 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 73cf0f21b9..b7f6ff2ca5 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -29,7 +29,7 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| I2C0 | Trackpad | #| I2C1 | Touchscreen | - #| I2C2 | 2nd Touchscreen | + #| I2C2 | 2nd Touchscreen | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -37,7 +37,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, @@ -57,6 +57,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl deleted file mode 100644 index 66940633a4..0000000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index c78364dc9e..0d9bf7237e 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -65,9 +63,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -207,6 +202,71 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -308,6 +368,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -334,8 +395,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 329efa3b2a..aa73ab6df3 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -18,20 +18,12 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -66,6 +58,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -180,7 +175,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl deleted file mode 100644 index fd3b5cfb4e..0000000000 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl deleted file mode 100644 index 66940633a4..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index c394977f6e..8ca9ce4683 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -1,10 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" + register "SataPortsEnable[0]" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -62,9 +62,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -202,6 +199,71 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -303,6 +365,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -329,8 +392,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7065081317..b04cc465fb 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" @@ -56,4 +52,11 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config PCIEXP_AER + def_bool n + +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index f824cd8f72..189f7f44de 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,16 +2,13 @@ #include #include -#include #include #include #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -25,18 +22,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 19d0c48e07..94fd8044c1 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,36 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -47,78 +17,102 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 77701987e5..05754ca5c0 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -17,7 +17,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include @@ -25,8 +25,8 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include - #include + #include + #include } } diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 3d19f99953..4dedb56c70 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -110,9 +110,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 1f03aed319..612901123e 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -11,7 +11,6 @@ #include #include "onboard.h" - void mainboard_pre_raminit(struct romstage_params *rp) { /* Fill out PEI DATA */ diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index a9ba0f5717..2c84782c9d 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -14,12 +14,12 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE - select STONEYRIDGE_UART + select AMD_SOC_CONSOLE_UART select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME select DRIVERS_GENERIC_BH720 diff --git a/src/mainboard/google/kahlee/acpi_tables.c b/src/mainboard/google/kahlee/acpi_tables.c new file mode 100644 index 0000000000..ab36f40a35 --- /dev/null +++ b/src/mainboard/google/kahlee/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index ebee0f7d07..c3ffd5bc56 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -5,9 +5,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index d67cdec6fd..570f20ce31 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -5,13 +5,12 @@ #include #include #include -#include #include #include +#include #include #include #include -#include #include #include #include @@ -160,20 +159,6 @@ static void kahlee_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - -static void mainboard_final(void *chip_info) -{ - struct global_nvs *gnvs; - - gnvs = acpi_get_gnvs(); - - if (gnvs) { - gnvs->tmps = CTL_TDP_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - } -} - int mainboard_get_xhci_oc_map(uint16_t *map) { return variant_get_xhci_oc_map(map); @@ -192,7 +177,6 @@ void mainboard_suspend_resume(void) struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = kahlee_enable, - .final = mainboard_final, }; /* Variants may override these functions so see definitions in variants/ */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 59d7631da2..8628074837 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -15,8 +15,8 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_4 - EN_PP3300_WLAN */ PAD_GPO(GPIO_4, HIGH), - /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), + /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI gets configured in ramstage */ + PAD_GPI(GPIO_6, PULL_UP), /* GPIO_9 - H1_PCH_INT_ODL */ PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), @@ -24,11 +24,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), - /* GPIO_22 - EC_SCI_ODL, SCI */ - PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + /* GPIO_22 - EC_SCI_ODL, SCI gets configured in ramstage */ + PAD_GPI(GPIO_22, PULL_UP), - /* GPIO_24 - EC_PCH_WAKE_L, SCI */ - PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* GPIO_24 - EC_PCH_WAKE_L, SCI gets configured in ramstage */ + PAD_GPI(GPIO_24, PULL_UP), /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), @@ -90,6 +90,9 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW), + /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ + PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), + /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -129,6 +132,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_21 - APU_PEN_INT_ODL, SCI */ PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW), + /* GPIO_22 - EC_SCI_ODL, SCI */ + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + + /* GPIO_24 - EC_PCH_WAKE_L, SCI */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* GPIO_25 - SD_CD */ PAD_NF(GPIO_25, SD0_CD, PULL_UP), diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index 72996cee68..4ed052cca4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -13,7 +13,6 @@ Name (PR0, Package() Package() { 0x0001FFFF, 2, INTE, 0 }, Package() { 0x0001FFFF, 3, INTF, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package() { 0x0002FFFF, 0, INTH, 0 }, Package() { 0x0002FFFF, 1, INTA, 0 }, @@ -74,7 +73,6 @@ Name (APR0, Package() Package() { 0x0011FFFF, 0, 0, 19 }, }) - /* GPP 0 */ Name (PS4, Package() { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index a3be62a3b8..a55e7a304d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 868253043a..860190a2b6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -78,7 +78,6 @@ void board_bh720(struct device *dev) write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; @@ -90,9 +89,7 @@ const char *smbios_mainboard_manufacturer(void) if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc index 482fdec085..1ec3342891 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc index ca459d270a..4c1da68f3d 100644 --- a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index d7772c442d..8c9f1cd47f 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -136,7 +136,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "generic.wake" = "7" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -147,7 +147,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" @@ -160,7 +160,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c index 3f20bc8881..ce98d62c18 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -90,7 +90,6 @@ void board_bh720(struct device *dev) BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; @@ -102,9 +101,7 @@ const char *smbios_mainboard_manufacturer(void) if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc index 2d3cd88581..e72c9e6d7a 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 1cc3d437cc..132172e750 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -136,7 +136,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "generic.wake" = "7" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -147,7 +147,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index 3f20bc8881..ce98d62c18 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -90,7 +90,6 @@ void board_bh720(struct device *dev) BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; @@ -102,9 +101,7 @@ const char *smbios_mainboard_manufacturer(void) if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc index 2d3cd88581..e72c9e6d7a 100644 --- a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index f3901470f3..ae1826326d 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -4,6 +4,13 @@ config BOARD_GOOGLE_KUKUI_COMMON def_bool n +config BOARD_GOOGLE_JACUZZI_COMMON + def_bool n + select BOARD_GOOGLE_KUKUI_COMMON + select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + # All Jacuzzi followers are using ANX7625 except the reference board. + select DRIVER_ANALOGIX_ANX7625 if !BOARD_GOOGLE_JACUZZI + if BOARD_GOOGLE_KUKUI_COMMON config VBOOT @@ -16,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_CAMERA select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH @@ -28,9 +36,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI - select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_DAMU || BOARD_GOOGLE_KAPPA || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_WILLOW - select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU config MAINBOARD_DIR string @@ -50,6 +56,10 @@ config MAINBOARD_PART_NUMBER default "Cerise" if BOARD_GOOGLE_CERISE default "Stern" if BOARD_GOOGLE_STERN default "Willow" if BOARD_GOOGLE_WILLOW + default "Esche" if BOARD_GOOGLE_ESCHE + default "Burnet" if BOARD_GOOGLE_BURNET + default "Fennel" if BOARD_GOOGLE_FENNEL + default "Katsu" if BOARD_GOOGLE_KATSU config DRIVER_TPM_SPI_BUS hex @@ -63,4 +73,29 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x2 +config BOARD_SDRAM_TABLE_OFFSET + hex + default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN + default 0x0 + +config BOARD_OVERRIDE_LCM_ID + hex + default 0x1 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_KAPPA || BOARD_GOOGLE_DAMU + default 0x1 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE + default 0x0 + +config SPEAKER_GPIO_NAME + string + # MAX98357A, should include KENZO in future. + default "speaker enable" if BOARD_GOOGLE_JACUZZI || BOARD_GOOGLE_JUNIPER + default "speaker enable" if BOARD_GOOGLE_WILLOW || BOARD_GOOGLE_DAMU + # MAX98360 + default "speaker enable" if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE + default "speaker enable" if BOARD_GOOGLE_KAPPA + # ALC1015Q (default for Jacuzzi followers) + default "rt1015p sdb" if BOARD_GOOGLE_KAKADU + default "rt1015p sdb" if BOARD_GOOGLE_JACUZZI_COMMON + # MAX98357A (default for Kukui followers) + default "speaker enable" + endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 55e0101ca0..072c93bb26 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -20,30 +20,48 @@ config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON +config BOARD_GOOGLE_KATSU + bool "-> Katsu" + select BOARD_GOOGLE_KUKUI_COMMON + +comment "Jacuzzi" + config BOARD_GOOGLE_JACUZZI bool "-> Jacuzzi" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_JUNIPER bool "-> Juniper" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_KAPPA bool "-> Kappa" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_DAMU bool "-> Damu" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_CERISE bool "-> Cerise" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_STERN bool "-> Stern" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_WILLOW bool "-> Willow" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_ESCHE + bool "-> Esche" + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_BURNET + bool "-> Burnet" + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_FENNEL + bool "-> Fennel" + select BOARD_GOOGLE_JACUZZI_COMMON diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 532712a6c1..7e065a3d8d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += sdram_params/ subdirs-y += panel_params/ -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += reset.c diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index c6865d1a67..04ae7db8f9 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -1,10 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* + * The boardid.c should provide board_id, sku_id, and ram_code. + * board_id is provided by ec/google/chromeec/ec_boardid.c. + * sku_id and ram_code are defined in this file. + */ + #include #include #include -#include +#include +#include +#include #include +#include +#include +#include +#include /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 @@ -57,7 +69,7 @@ static const int *adc_voltages[] = { static uint32_t get_adc_index(unsigned int channel) { - int value = auxadc_get_voltage(channel); + int value = auxadc_get_voltage_uv(channel); assert(channel < ARRAY_SIZE(adc_voltages)); const int *voltages = adc_voltages[channel]; @@ -72,7 +84,106 @@ static uint32_t get_adc_index(unsigned int channel) return id; } -/* board_id is provided by ec/google/chromeec/ec_boardid.c */ +static uint8_t eeprom_random_read(uint8_t bus, uint8_t slave, uint16_t offset, + uint8_t *data, uint16_t len) +{ + struct i2c_msg seg[2]; + uint8_t address[2]; + + address[0] = offset >> 8; + address[1] = offset & 0xff; + + seg[0].flags = 0; + seg[0].slave = slave; + seg[0].buf = address; + seg[0].len = sizeof(address); + seg[1].flags = I2C_M_RD; + seg[1].slave = slave; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + +/* Regulator for world facing camera. */ +#define PMIC_LDO_VCAMIO_CON0 0x1cb0 + +#define CROS_CAMERA_INFO_OFFSET 0x1f80 +#define MT8183_FORMAT 0x8183 +#define KODAMA_PID 0x00c7 + +/* Returns the ID for world facing camera. */ +static uint8_t wfc_id(void) +{ + if (!CONFIG(BOARD_GOOGLE_KODAMA)) + return 0; + + int i, ret; + uint8_t bus = 2; + uint8_t dev_addr = 0x50; /* at24c32/64 device address */ + + struct cros_camera_info data = {0}; + + const uint16_t sensor_pids[] = { + [0] = 0x5965, /* OV5965 */ + [1] = 0x5035, /* GC5035 */ + }; + + mtk_i2c_bus_init(bus); + + /* Turn on camera sensor EEPROM */ + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x1); + udelay(270); + + ret = eeprom_random_read(bus, dev_addr, CROS_CAMERA_INFO_OFFSET, + (uint8_t *)&data, sizeof(data)); + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x0); + + if (ret) { + printk(BIOS_ERR, + "Failed to read from EEPROM; using default WFC id 0\n"); + return 0; + } + + if (check_cros_camera_info(&data)) { + printk(BIOS_ERR, + "Failed to check camera info; using default WFC id 0\n"); + return 0; + } + + if (data.data_format != MT8183_FORMAT) { + printk(BIOS_ERR, "Incompatible camera format: %#04x\n", + data.data_format); + return 0; + } + if (data.module_pid != KODAMA_PID) { + printk(BIOS_ERR, "Incompatible module pid: %#04x\n", + data.module_pid); + return 0; + } + + printk(BIOS_DEBUG, "Camera sensor pid: %#04x\n", data.sensor_pid); + + for (i = 0; i < ARRAY_SIZE(sensor_pids); i++) { + if (data.sensor_pid == sensor_pids[i]) { + printk(BIOS_INFO, "Detected WFC id: %d\n", i); + return i; + } + } + + printk(BIOS_WARNING, "Unknown WFC id; using default id 0\n"); + return 0; +} + +/* Returns the ID for LCD module (type of panel). */ +static uint8_t lcm_id(void) +{ + /* LCM is unused on Jacuzzi followers. */ + if (CONFIG(BOARD_GOOGLE_JACUZZI_COMMON)) + return CONFIG_BOARD_OVERRIDE_LCM_ID; + + return get_adc_index(LCM_ID_CHANNEL); +} uint32_t sku_id(void) { @@ -98,11 +209,14 @@ uint32_t sku_id(void) /* * The SKU (later used for device tree matching) is combined from: + * World facing camera (WFC) ID. * ADC2[4bit/H] = straps on LCD module (type of panel). * ADC4[4bit/L] = SKU ID from board straps. */ - cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | + cached_sku_id = (wfc_id() << 8 | + lcm_id() << 4 | get_adc_index(SKU_ID_CHANNEL)); + return cached_sku_id; } @@ -110,7 +224,10 @@ uint32_t ram_code(void) { static uint32_t cached_ram_code = BOARD_ID_INIT; - if (cached_ram_code == BOARD_ID_INIT) + if (cached_ram_code == BOARD_ID_INIT) { cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + /* Model-specific offset - see sdram_configs.c for details. */ + cached_ram_code += CONFIG_BOARD_SDRAM_TABLE_OFFSET; + } return cached_ram_code; } diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index c5810d11aa..3f15a3fb91 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -23,7 +23,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, - {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, CONFIG_SPEAKER_GPIO_NAME}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 6622286135..7efa01b0cc 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -8,7 +8,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -55,6 +57,13 @@ static void configure_audio(void) gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); } +static void configure_ec(void) +{ + /* EC may need SKU ID to identify if it is clamshell or convertible. */ + if (CONFIG(BOARD_GOOGLE_JACUZZI_COMMON)) + google_chromeec_set_sku_id(sku_id()); +} + /* Default implementation for boards without panels defined yet. */ struct panel_description __weak *get_panel_description(int panel_id) { @@ -83,7 +92,7 @@ static void power_on_panel(struct panel_description *panel) gpio_output(GPIO_PPVARN_LCD_EN, 1); gpio_output(GPIO_PP1800_LCM_EN, 1); gpio_output(GPIO_PP3300_LCM_EN, 1); - mdelay(6); + mdelay(15); gpio_output(GPIO_LCM_RST_1V8, 1); mdelay(6); } @@ -104,8 +113,7 @@ struct panel_description *get_panel_from_cbfs(struct panel_description *desc) return NULL; snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_boot_load_file(cbfs_name, buffer.raw, sizeof(buffer), - CBFS_TYPE_STRUCT)) + if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) desc->s = &buffer.s; else printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); @@ -160,9 +168,15 @@ static bool configure_display(void) printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); return false; } + + if (panel->post_power_on) + panel->post_power_on(); + mtk_ddp_mode_set(edid); - set_vbe_mode_info_valid(edid, 0); - set_vbe_framebuffer_orientation(panel->s->orientation); + struct fb_info *info = fb_new_framebuffer_info_from_edid(edid, 0); + if (info) + fb_set_orientation(info, panel->s->orientation); + return true; } @@ -191,6 +205,7 @@ static void mainboard_init(struct device *dev) configure_emmc(); configure_usb(); configure_audio(); + configure_ec(); if (spm_init()) printk(BIOS_ERR, "SPM initialization failed, suspend/resume may fail.\n"); diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h index 7ae31dd791..174956551d 100644 --- a/src/mainboard/google/kukui/panel.h +++ b/src/mainboard/google/kukui/panel.h @@ -21,6 +21,7 @@ struct panel_description { const char *name; /* Panel name for constructing CBFS file name */ struct panel_serializable_data *s; void (*power_on)(void); /* Callback to turn on panel */ + void (*post_power_on)(void); /* Callback to run after panel is turned on */ }; /* Returns the panel description from given ID. */ diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index cae9edc041..aa22cf3edf 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -9,6 +9,32 @@ #include "panel.h" +#define ANX7625_I2C_BUS 4 + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static void dummy_power_on(void) +{ + /* + * The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static void start_anx7625(void) +{ + if (anx7625_dp_start(ANX7625_I2C_BUS, &anx7625_data.edid) < 0) + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); +} + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, + .post_power_on = start_anx7625, +}; static void power_on_anx7625(void) { @@ -28,43 +54,21 @@ static void power_on_anx7625(void) gpio_output(GPIO_PP3300_LCM_EN, 1); } -static void dummy_power_on(void) -{ - /* The panel has been already powered on when getting panel information - * so we should do nothing here. - */ -} - -static struct panel_serializable_data anx7625_data = { - .orientation = LB_FB_ORIENTATION_NORMAL, - .init = { INIT_END_CMD }, -}; - -static struct panel_description anx7625_panel = { - .s = &anx7625_data, - .power_on = dummy_power_on, -}; - struct panel_description *get_panel_description(int panel_id) { /* To read panel EDID, we have to first power on anx7625. */ power_on_anx7625(); - u8 i2c_bus = 4; - mtk_i2c_bus_init(i2c_bus); + mtk_i2c_bus_init(ANX7625_I2C_BUS); - if (anx7625_init(i2c_bus)) { + if (anx7625_init(ANX7625_I2C_BUS)) { printk(BIOS_ERR, "Can't init ANX7625 bridge.\n"); return NULL; } - struct edid *edid = &anx7625_data.edid; - if (anx7625_dp_get_edid(i2c_bus, edid)) { + + if (anx7625_dp_get_edid(ANX7625_I2C_BUS, &anx7625_data.edid)) { printk(BIOS_ERR, "Can't get panel's edid.\n"); return NULL; } - if (anx7625_dp_start(i2c_bus, edid) < 0) { - printk(BIOS_ERR, "Can't start display via ANX7625.\n"); - return NULL; - } return &anx7625_panel; } diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 6b8015108b..f758e749ce 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -9,7 +9,6 @@ #include "panel.h" - static void power_on_ps8640(void) { /* Disable backlight before turning on bridge */ diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1a2127d735..b9c0d2c834 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -57,7 +57,7 @@ void platform_romstage_main(void) mt6358_init(); /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); - mt_pll_raise_ca53_freq(1989 * MHz); + mt_pll_raise_little_cpu_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(&dparam_ops); diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index c1e75ef6f6..57f5e6e765 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -5,16 +5,32 @@ #include #include +/* + * The RAM_CODE ADC on Kukui can support only 12 different levels. Each model + * can create its own mapping if needed, with an offset (0x10, 0x20, ..., + * defined as CONFIG_BOARD_SDRAM_TABLE_OFFSET) applied in ram_code(). + */ static const char *const sdram_configs[] = { - [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", - [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", - [3] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", - [4] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", - [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", - [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", - [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", - [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", - [10] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + /* Standard table. */ + [0x00] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x01] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x02] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x03] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", + [0x04] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [0x05] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [0x06] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [0x07] = "sdram-lpddr4x-SDADA4CR-128G-4GB", + [0x08] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x09] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + [0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + + /* Table shared by Burnet and its variants, offset = 0x10 */ + [0x10] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", }; static struct sdram_params params; @@ -22,11 +38,14 @@ static struct sdram_params params; const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = ram_code(); + const char *name = NULL; - if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], ¶ms, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) - die("Cannot load SDRAM parameter file!"); + if (ramcode < ARRAY_SIZE(sdram_configs)) + name = sdram_configs[ramcode]; + + if (!name || cbfs_load(name, ¶ms, sizeof(params)) != sizeof(params)) + die("Cannot load SDRAM parameter file for RAM code %#02x: %s!", + ramcode, name ? name : "unknown"); return ¶ms; } diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index af13aa1d79..e2b4be22d7 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,13 +1,17 @@ sdram-params := -sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB -sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB -sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB +sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-MT53E2G32D4NQ-046-8GB sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB -sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB +sdram-params += sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB +sdram-params += sdram-lpddr4x-MT53E1G32D2NP-046-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index cf5c4d2b16..ddc829fd5c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c index cf5c4d2b16..77edc7f36a 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .frequency = 1600, + .rank_num = 2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c new file mode 100644 index 0000000000..b440c7f65c --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4, + .frequency = 1600, + .rank_num = 2, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_BYTE_MODE1, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index e95df6c613..0125c9c6f9 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .rank_num = 2, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c new file mode 100644 index 0000000000..3c4c09083e --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, + [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x6, 0x5}, + [CHANNEL_B] = {0x6, 0x6} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x58}, + [CHANNEL_B] = {0x58, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index a9844780b2..1ee43472ef 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 95e909195e..b52f7dd189 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .rank_num = 2, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 3792182dfb..6a13e8a13c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 301128383c..158df284c3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c new file mode 100644 index 0000000000..86c3e8f04e --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .rank_num = 1, + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 81887b5a96..5248db99b7 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c new file mode 100644 index 0000000000..8d53d5f451 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .frequency = 1600, + .rank_num = 2, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index eaebc752bd..448122ffc4 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 2c3076dadc..427e99de9c 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 35893ee1a7..12b14530f2 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -7,7 +7,7 @@ Method(_PTS,1) { /* Disable WWAN */ - Store (Zero, GP36) + GP36 = 0 } /* The _WAK method is called on system wakeup */ @@ -15,16 +15,16 @@ Method(_PTS,1) Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDS + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index 28fa4907cc..7ea38ae6cd 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -15,10 +15,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -32,33 +32,33 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from TIN9/PECI via EC - Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TIN9 // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } } @@ -77,10 +77,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -106,34 +106,34 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -142,7 +142,7 @@ Scope (\_TZ) /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -155,19 +155,19 @@ Scope (\_TZ) PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 \_SB.PCI0.MCHC.STND () Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 \_SB.PCI0.MCHC.STDN () Notify (\_TZ.THRM, 0x81) } @@ -176,18 +176,18 @@ Scope (\_TZ) PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f37f37e6cf..cc3f9a8d68 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -2,11 +2,9 @@ #include #include -#include -#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -16,11 +14,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = CTDP_SENSOR_ID; gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 0cf582192b..5cfca4f15f 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -4,99 +4,71 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size - -#547 437 r 0 unused +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 477cd47c32..a99d618eb8 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms @@ -25,13 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 23f437019c..7bccd7f4b4 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 8360f2ac24..de8f749770 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -66,8 +66,7 @@ static uint8_t *locate_spd(void) int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -86,15 +85,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c index 8cd84f0417..1f54222ae0 100644 --- a/src/mainboard/google/link/hda_verb.c +++ b/src/mainboard/google/link/hda_verb.c @@ -110,7 +110,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(3, 0x07, 0x18560030), }; - const u32 pc_beep_verbs[] = { 0x00170500, /* power up codec */ 0x00270500, /* power up DAC */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 1438c7f720..c4b621ac7a 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -105,8 +105,6 @@ static int int15_handler(void) } #endif - - static void mainboard_init(struct device *dev) { uint32_t board_version = 0; diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index e89bc6bf21..cd17edebe1 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -18,6 +18,7 @@ #include #include #include +#include enum { CODEC_I2C_BUS = 0, @@ -224,7 +225,7 @@ static void display_startup(void) } mtk_ddp_mode_set(&edid); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index e1d3747686..2d62980420 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -28,9 +28,9 @@ void platform_romstage_main(void) /* Set to maximum frequency */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) - mt_pll_raise_ca53_freq(1600 * MHz); + mt_pll_raise_little_cpu_freq(1600 * MHz); else - mt_pll_raise_ca53_freq(1700 * MHz); + mt_pll_raise_little_cpu_freq(1700 * MHz); mtk_mmu_after_dram(); } diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d01d95f7fc..7e8e277e17 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -1,7 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS def_bool n - select SOC_INTEL_GLK + select SOC_INTEL_GEMINILAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS @@ -46,7 +47,6 @@ config CHROMEOS default y select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH config MAINBOARD_DIR @@ -97,10 +97,6 @@ config MAINBOARD_FAMILY string default "Google_Octopus" -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 6e3dbf493c..64f7649227 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -34,12 +34,14 @@ config BOARD_GOOGLE_BOBBA select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP bool "-> Meep" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_AMPTON bool "-> Ampton" diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 315cf7c30f..513db663fe 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -25,6 +25,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index e6dbd0330b..91d29cf61c 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -8,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +24,9 @@ #include #include +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_da7219_ops; + static bool is_cnvi_held_in_reset(void) { struct device *dev = pcidev_path_on_root(PCH_DEVFN_CNVI); @@ -46,6 +51,41 @@ static void disable_wifi_wake(void) gpio_configure_pads(wifi_wake_gpio, ARRAY_SIZE(wifi_wake_gpio)); } +/* + * GPIO_137 for two audio codecs right now has the different configuration so + * if SSFC indicates that codec is different than default one then GPIO_137 + * needs to be overridden for the corresponding second source. + */ +static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) +{ + /* For RT5682, GPIO 137 should be set as EDGE_BOTH. */ + const struct pad_config rt5682_gpio_137 = PAD_CFG_GPI_APIC_IOS(GPIO_137, + NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, DISPUPD); + + if (table == NULL || num == 0) + return; + + /* + * Currently we only have the case of RT5682 as the second source. And + * in case of Ampton which used RT5682 as the default source, it didn't + * provide override_table right now so it will be returned ealier since + * table above is NULL. + */ + if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) + return; + + while (num--) { + if (table->pad == GPIO_137) { + *table = rt5682_gpio_137; + printk(BIOS_INFO, + "Configure GPIO 137 based on SSFC.\n"); + return; + } + + table++; + } +} + static void mainboard_init(void *chip_info) { int boardid; @@ -58,6 +98,8 @@ static void mainboard_init(void *chip_info) base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); + gpio_modification_by_ssfc((struct pad_config *)override_pads, + override_num); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); @@ -128,10 +170,47 @@ static void wifi_device_update(void) dev->enabled = 0; } +/* + * Base on SSFC value in the CBI from EC to enable one of audio codec sources in + * the device tree. + */ +static void audio_codec_device_update(void) +{ + struct device *audio_dev = NULL; + struct bus *audio_i2c_bus = + pcidev_path_on_root(PCH_DEVFN_I2C5)->link_list; + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); + + while ((audio_dev = dev_bus_each_child(audio_i2c_bus, audio_dev))) { + if (audio_dev->chip_info == NULL) + continue; + + if ((audio_dev->chip_ops == &drivers_i2c_da7219_ops) && + (codec == SSFC_AUDIO_CODEC_DA7219)) { + printk(BIOS_INFO, "enable DA7219.\n"); + continue; + } + + if ((audio_dev->chip_ops == &drivers_i2c_generic_ops) && + (codec == SSFC_AUDIO_CODEC_RT5682)) { + struct drivers_i2c_generic_config *cfg = + audio_dev->chip_info; + + if (cfg != NULL && !strcmp(cfg->hid, "10EC5682")) { + printk(BIOS_INFO, "enable RT5682.\n"); + continue; + } + } + + audio_dev->enabled = 0; + } +} + void mainboard_devtree_update(struct device *dev) { /* Apply common devtree updates. */ wifi_device_update(); + audio_codec_device_update(); /* Defer to variant for board-specific updates. */ variant_update_devtree(dev); diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 2c68045685..488ba07cc4 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -3,15 +3,22 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include #include +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + void mainboard_smi_gpi_handler(const struct gpi_status *sts) { if (gpi_status_get(sts, EC_SMI_GPI)) @@ -54,3 +61,27 @@ void __weak variant_smi_sleep(u8 slp_typ) { /* Leave for the variant to implement if necessary. */ } + +void power_off_lte_module(void) +{ + + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 10ff7d74f7..cfc5e8ac78 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -121,6 +121,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end end diff --git a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc index 63b03a6118..f28c3d6ce5 100644 --- a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc @@ -4,5 +4,6 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += cbi_ssfc.c smm-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c new file mode 100644 index 0000000000..589f92e139 --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static int get_ssfc(uint32_t *val) +{ + static uint32_t known_value; + static enum { + SSFC_NOT_READ, + SSFC_AVAILABLE, + } ssfc_state = SSFC_NOT_READ; + + if (ssfc_state == SSFC_AVAILABLE) { + *val = known_value; + return 0; + } + + /* + * If SSFC field is not in the CBI then the value of SSFC will be 0 for + * further processing later since 0 of each bits group means default + * component in a variant. For more detail, please refer to cbi_ssfc.h. + */ + if (google_chromeec_cbi_get_ssfc(&known_value) != 0) { + printk(BIOS_DEBUG, "SSFC not set in CBI\n"); + return -1; + } + + ssfc_state = SSFC_AVAILABLE; + *val = known_value; + printk(BIOS_INFO, "SSFC 0x%x.\n", known_value); + + return 0; +} + +static unsigned int extract_field(uint32_t mask, int shift) +{ + uint32_t ssfc; + + /* On errors nothing is assumed to be set. */ + if (get_ssfc(&ssfc)) + return 0; + + return (ssfc >> shift) & mask; +} + +static enum ssfc_audio_codec ssfc_get_default_audio_codec(void) +{ + /* + * Octopus has two reference boards; yorp is with DA7219 and bip is with + * RT5682. Currently only AMPTON derived from bip so only it uses + * RT5682 as the default source in the first MP devices. + */ + if (CONFIG(BOARD_GOOGLE_AMPTON)) + return SSFC_AUDIO_CODEC_RT5682; + + return SSFC_AUDIO_CODEC_DA7219; +} + +enum ssfc_audio_codec ssfc_get_audio_codec(void) +{ + uint32_t codec = extract_field( + SSFC_AUDIO_CODEC_MASK, SSFC_AUDIO_CODEC_OFFSET); + + if (codec != SSFC_AUDIO_CODEC_DEFAULT) + return codec; + + return ssfc_get_default_audio_codec(); +} diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 80e4873694..3dbc5ef080 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -112,12 +112,16 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 off end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Gaussian Mixture Model (GMM) - chip drivers/intel/wifi - register "wake" = "GPE0A_CNVI_PME_STS" - device pci 0c.0 on end # - CNVi + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" end + device pci 03.0 on end # - Gaussian Mixture Model (GMM) + device pci 0c.0 on + chip drivers/wifi/generic + register "wake" = "GPE0A_CNVI_PME_STS" + device generic 0 on end + end + end # - CNVi device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - Fast SPI @@ -136,7 +140,7 @@ chip soc/intel/apollolake device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_11" device pci 00.0 on end end @@ -273,8 +277,8 @@ chip soc/intel/apollolake # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff); + # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); + # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field @@ -285,4 +289,8 @@ chip soc/intel/apollolake # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # 101=50ms, 110=75ms, 111=100ms (default) register "PmicPmcIpcCtrl" = "0x5e4302f8" + + # FSP UPD to modify the Integrated Filter (IF) value + # Set it to default value: 0x12 + register "ModPhyIfValue" = "0x12" end diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h new file mode 100644 index 0000000000..84020d7eb3 --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OCTOPUS_CBI_SSFC__H_ +#define _OCTOPUS_CBI_SSFC__H_ + +#include + +/**************************************************************************** + * Octopus CBI Second Source Factory Cache + * + * SSFC was introduced after variants were MPed already so we can expect there + * can be devices in the field without SSFC field in the CBI. For devices + * without SSFC field in the CBI, the value of SSFC will be 0 set by get_ssfc() + * in the cbi_ssfc.c. + * + * On the other hand, taking audio codec as the example there are two sources - + * DA7219 and RT5682 used in the MPed devices before introducing SSFC. As a + * result, the value 0 of each bits group for a specific component is defined as + * DEFAULT and different variants should transform this DEFAULT to one of + * sources they used as the first sources. In the example here, either DA7219 or + * RT5682 should be transformed. + */ + +/* + * Audio Codec (Bits 9-11) + * + */ +enum ssfc_audio_codec { + SSFC_AUDIO_CODEC_DEFAULT, + SSFC_AUDIO_CODEC_DA7219, + SSFC_AUDIO_CODEC_RT5682, +}; +#define SSFC_AUDIO_CODEC_OFFSET 9 +#define SSFC_AUDIO_CODEC_MASK 0x7 + +enum ssfc_audio_codec ssfc_get_audio_codec(void); + +#endif /* _OCTOPUS_CBI_SSFC__H_ */ diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index ecc9355138..fa86170f78 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -54,9 +54,6 @@ * ACPI related definitions for ASL code. */ -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 206ce8bd90..f39a786f11 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -50,4 +50,8 @@ bool no_touchscreen_sku(uint32_t sku_id); /* allow each variants to customize smi sleep flow. */ void variant_smi_sleep(u8 slp_typ); +/* LTE power off sequence: + * GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 */ +void power_off_lte_module(void); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index f1304f4720..9c9316c67a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,8 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); + /* 2 Channel DMIC array. */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); @@ -19,13 +22,13 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints. */ - if (CONFIG(NHLT_DA7219)) { + if (CONFIG(NHLT_DA7219) && codec == SSFC_AUDIO_CODEC_DA7219) { /* Dialog for Headset codec */ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (CONFIG(NHLT_RT5682)) { + if (CONFIG(NHLT_RT5682) && codec == SSFC_AUDIO_CODEC_RT5682) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 0212bea46d..7c22ce7a09 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -41,44 +41,44 @@ chip soc/intel/apollolake # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. register "emmc_rx_strobe_cntl" = "0x0b0b" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C5 | Audio | - #| I2C6 | Trackpad | - #| I2C7 | Touchscreen | - #+-------------------+---------------------------+ + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "10" - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - .i2c[6] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 66, - .fall_time_ns = 90, - .data_hold_time_ns = 350, - }, - .i2c[7] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 44, - .fall_time_ns = 90, - }, + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, - }" + }" device domain 0 on device pci 16.0 off end # - I2C 0 @@ -124,34 +124,34 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 10 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "generic.has_power_resource" = "1" - register "generic.enable_delay_ms" = "10" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" - register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "generic.reset_delay_ms" = "50" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 40 on end - end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.has_power_resource" = "1" + register "generic.enable_delay_ms" = "10" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index fd94377582..11fe9b5eec 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -17,6 +17,10 @@ enum { static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), @@ -28,6 +32,10 @@ static const struct pad_config lte_override_table[] = { /* Default override table. */ PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 20c376a713..73adfef9ab 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -165,6 +165,19 @@ chip soc/intel/apollolake register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic @@ -178,7 +191,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -210,6 +223,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 97c77a95dc..2d09270148 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -16,41 +16,12 @@ enum { SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/ }; -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} - const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || - sku_id == 42 || sku_id == 43 || sku_id == 44) + if (sku_id >= 33 && sku_id <= 44) filename = "wifi_sar-droid.hex"; return filename; @@ -68,14 +39,13 @@ void variant_smi_sleep(u8 slp_typ) case SKU_38_DROID: case SKU_39_DROID: case SKU_40_DROID: - power_off_lte_module(slp_typ); + power_off_lte_module(); return; default: return; } } - void variant_update_devtree(struct device *dev) { struct soc_intel_apollolake_config *cfg = NULL; diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 2f2f80bd28..a09bcbb9e1 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -137,6 +137,18 @@ chip soc/intel/apollolake register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end end # - I2C 6 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index e1f12cf08f..465078f8c3 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -112,7 +112,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -144,6 +144,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index dda24f8330..1a8a37164a 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -16,35 +16,6 @@ enum { SKU_4_WIFI_2CAM = 4, /* Wifi + dual camera */ }; -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} - - void variant_smi_sleep(u8 slp_typ) { /* Currently use cases here all target to S5 therefore we do early return @@ -55,7 +26,7 @@ void variant_smi_sleep(u8 slp_typ) switch (google_chromeec_get_board_sku()) { case SKU_1_LTE: case SKU_3_LTE_2CAM: - power_off_lte_module(slp_typ); + power_off_lte_module(); return; default: return; diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index 9fb63f5f43..2835934d6e 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -1,3 +1,7 @@ bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c + +smm-y += variant.c diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 4d92630cac..8148dcef2d 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -10,8 +10,10 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), - PAD_NC(GPIO_67, UP_20K), - PAD_NC(GPIO_117, UP_20K), + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), @@ -21,7 +23,8 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), - PAD_NC(GPIO_161, UP_20K), + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), PAD_NC(GPIO_213, DN_20K), PAD_NC(GPIO_214, DN_20K), @@ -33,3 +36,21 @@ const struct pad_config *variant_override_gpio_table(size_t *num) return default_override_table; } + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; +} diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 60c53dc649..29aee4f5ff 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -5,4 +5,9 @@ #include +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)) + #endif diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 1d1a67ad33..77cce86be7 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -84,6 +84,10 @@ chip soc/intel/apollolake }, }" + # Disable compliance mode + register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid @@ -128,6 +132,15 @@ chip soc/intel/apollolake register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end # - I2C 6 device pci 17.3 on chip drivers/i2c/generic @@ -145,7 +158,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" @@ -156,9 +169,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end - - # Disable compliance mode - register "DisableComplianceMode" = "1" end diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c new file mode 100644 index 0000000000..5554fb3388 --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define MIN_LTE_SKU 4 + +static bool is_lte_sku(void) +{ + return (google_chromeec_get_board_sku() >= MIN_LTE_SKU); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + if (is_lte_sku()) + power_off_lte_module(); +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (!is_lte_sku()) + filename = "wifi_sar-fleex.hex"; + + return filename; +} + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + // Force disable_xhci_lfps_pm to update if it is LTE sku + if (cfg != NULL && is_lte_sku()) + cfg->disable_xhci_lfps_pm = 1; +} diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index 4ec6fee1c9..4161090aa6 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -126,7 +126,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -137,7 +137,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -150,7 +150,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc index ba865e9f82..7ee7e70d4b 100644 --- a/src/mainboard/google/octopus/variants/garg/Makefile.inc +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index dca07f609a..d7affc7234 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -66,10 +66,12 @@ const struct pad_config *variant_override_gpio_table(size_t *num) case SKU_9_HDMI: case SKU_19_HDMI_TS: case SKU_50_HDMI: + case SKU_52_HDMI_TS: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 3ab69881a1..96e9c5301d 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -12,8 +12,11 @@ enum { SKU_20_2A2C_TS = 20, SKU_37_2A2C_360 = 37, SKU_38_2A2C_360_TS_NO_STYLUES = 38, + SKU_39_1A2C_360_LTE_TS_NO_STYLUES = 39, SKU_49_2A2C_TS = 49, SKU_50_HDMI = 50, + SKU_51_2A2C = 51, + SKU_52_HDMI_TS = 52, }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index f3c580d2c0..38e5cdd1ab 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -141,7 +141,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -176,7 +176,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" @@ -192,4 +192,5 @@ chip soc/intel/apollolake # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 5188be6433..00e5d326e1 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -8,34 +8,7 @@ #include #include #include - -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} +#include const char *mainboard_vbt_filename(void) { @@ -47,6 +20,7 @@ const char *mainboard_vbt_filename(void) case SKU_9_HDMI: case SKU_19_HDMI_TS: case SKU_50_HDMI: + case SKU_52_HDMI_TS: return "vbt_garg_hdmi.bin"; default: return "vbt.bin"; @@ -63,9 +37,29 @@ void variant_smi_sleep(u8 slp_typ) switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: - power_off_lte_module(slp_typ); + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: + power_off_lte_module(); return; default: return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { + switch (google_chromeec_get_board_sku()) { + case SKU_17_LTE: + case SKU_18_LTE_TS: + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index 3ade35402f..e2b35cb598 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -52,7 +52,7 @@ chip soc/intel/apollolake #| I2C5 | Audio | #| I2C6 | Trackpad | #+-------------------+---------------------------+ - register "tcc_offset" = "15" + register "tcc_offset" = "15" register "common_soc_config" = "{ .gspi[0] = { @@ -104,7 +104,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 31cd64e209..3aa8d9dac2 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -10,6 +10,10 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), @@ -24,6 +28,11 @@ static const struct pad_config hdmi_sku_override_table[] = { /* HV_DDI1_DDC_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 8881c9d98f..87521413d1 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -181,6 +181,19 @@ chip soc/intel/apollolake register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic @@ -208,7 +221,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" @@ -222,7 +235,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index b80d0317c8..fb2936ac67 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -126,7 +126,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -149,7 +149,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -159,18 +159,32 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "enable_delay_ms" = "50" - register "has_power_resource" = "1" - device i2c 39 on end - end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "70" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl index 2265c82bbb..d13b0bd5c5 100644 --- a/src/mainboard/google/parrot/acpi/superio.asl +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -3,7 +3,6 @@ /* mainboard configuration */ #include "../ec.h" - #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 3332286a29..2a2e24222a 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include "ec.h" @@ -12,7 +11,7 @@ #include "thermal.h" #include "onboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -22,11 +21,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (CONFIG(CHROMEOS) && !parrot_ec_running_ro()) + gnvs_set_ecfw_rw(); /* EC handles all active thermal and fan control on Parrot. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 0cf582192b..5cfca4f15f 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -4,99 +4,71 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size - -#547 437 r 0 unused +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index c39a399f0c..a384d87387 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "500" # 50ms register "gpu_panel_power_down_delay" = "150" # 15ms @@ -25,13 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 3164c8134a..16f16dc0ea 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 3c5c36369b..b7ed73c6cf 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,21 +54,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index d98edecb01..f4187eb4f2 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -7,7 +7,6 @@ #include #include "ec.h" - void parrot_ec_init(void) { printk(BIOS_DEBUG, "Parrot EC Init\n"); @@ -18,18 +17,18 @@ void parrot_ec_init(void) /* Report EC info */ /* EC version: cmd 0x51 - returns three bytes */ ec_kbc_write_cmd(0x51); - printk(BIOS_DEBUG," EC version %x.%x.%x\n", + printk(BIOS_DEBUG, " EC version %x.%x.%x\n", ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* EC Project name: cmd 0x52, 0xA0 - returns five bytes */ ec_kbc_write_cmd(0x52); ec_kbc_write_ib(0xA0); - printk(BIOS_DEBUG," EC Project: %c%c%c%c%c\n", - ec_kbc_read_ob(),ec_kbc_read_ob(),ec_kbc_read_ob(), + printk(BIOS_DEBUG, " EC Project: %c%c%c%c%c\n", + ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* Print the hardware revision */ - printk(BIOS_DEBUG," Parrot Revision %x\n", parrot_rev()); + printk(BIOS_DEBUG, " Parrot Revision %x\n", parrot_rev()); /* US Keyboard */ ec_kbc_write_cmd(0x59); @@ -53,7 +52,6 @@ void parrot_ec_init(void) ec_kbc_write_ib(0xA2); } - /* Parrot Hardware Revision */ u8 parrot_rev(void) { diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index 9d58a0e46d..1c838a390b 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -23,7 +23,6 @@ const u32 cim_verb_data[] = { 0x10250742, // Subsystem ID 0x0000000E, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10250742 */ AZALIA_SUBVENDOR(0, 0x10250742), diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 4e031d3dfb..16695dbeb8 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -18,7 +18,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_ACPI_ENABLE); } - static void mainboard_init(struct device *dev) { /* Initialize the Embedded Controller */ diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a359e06af3..e0192cec53 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -18,7 +18,7 @@ static u8 mainboard_smi_ec(void) ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); - printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src); + printk(BIOS_DEBUG, "%s src: %x\n", __func__, src); switch (src) { case EC_BATTERY_CRITICAL: @@ -36,12 +36,11 @@ static u8 mainboard_smi_ec(void) void mainboard_smi_gpi(u32 gpi_sts) { - printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); + printk(BIOS_DEBUG, "%s: %x\n", __func__, gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ - while (mainboard_smi_ec() != EC_NO_EVENT); - } - else if (gpi_sts & (1 << EC_LID_GPI)) { + do {} while (mainboard_smi_ec() != EC_NO_EVENT); + } else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ @@ -51,16 +50,13 @@ void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_sleep(u8 slp_typ) { - printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); + printk(BIOS_DEBUG, "%s: %x\n", __func__, slp_typ); /* Disable SCI and SMI events */ - /* Clear pending events that may trigger immediate wake */ - /* Enable wake events */ - /* Tell the EC to Disable USB power */ if (gnvs->s3u0 == 0 && gnvs->s3u1 == 0) { ec_kbc_write_cmd(0x45); @@ -70,7 +66,7 @@ void mainboard_smi_sleep(u8 slp_typ) int mainboard_smi_apmc(u8 apmc) { - printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); + printk(BIOS_DEBUG, "%s: %x\n", __func__, apmc); switch (apmc) { case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 8b54b9977a..ab3c0f5b35 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -23,20 +22,12 @@ #include #include #include +#include /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB -static struct edid edid = { - .mode.ha = 1366, - .mode.va = 768, - .framebuffer_bits_per_pixel = 16, - .x_resolution = 1366, - .y_resolution = 768, - .bytes_per_line = 2 * 1366 -}; - /* from the fdt */ static struct vidinfo vidinfo = { .vl_freq = 60, @@ -231,7 +222,6 @@ static void parade_dp_bridge_setup(void) udelay(10); gpio_set_value(dp_rst_l, 1); - gpio_set_pull(dp_hpd, GPIO_PULL_NONE); gpio_cfg_pin(dp_hpd, GPIO_INPUT); @@ -254,7 +244,7 @@ static void parade_dp_bridge_setup(void) * we're out of here. * If it's not ready after a second, then we're in big trouble. */ - for(i = 0; i < 1000; i++){ + for (i = 0; i < 1000; i++){ if (gpio_get_value(dp_hpd)) break; mdelay(1); @@ -403,7 +393,7 @@ static void mainboard_init(struct device *dev) sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 2 * 1366, 16); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index d99db809ef..83d38fa142 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -129,13 +129,13 @@ static unsigned long primitive_mem_test(void) unsigned long *l = (void *)0x40000000; int bad = 0; unsigned long i; - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); l[i] = 0xffffffff - i; } - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); if (l[i] != (0xffffffff - i)){ @@ -176,8 +176,7 @@ static void simple_spi_test(void) return; } - - for(i = 0; i < amt; i += 4){ + for (i = 0; i < amt; i += 4){ if (rdev_readat(boot_dev, &in, i, 4) < 4) { printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 74b4da6fbc..134246c173 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_POPPY @@ -107,10 +108,6 @@ config MAINBOARD_PART_NUMBER default "Rammus" if BOARD_GOOGLE_RAMMUS default "Soraka" if BOARD_GOOGLE_SORAKA -config MAX_CPUS - int - default 8 - config OEM_BIN_FILE string "OEM ID table" default "" @@ -207,10 +204,13 @@ config VARIANT_SPECIFIC_OPTIONS_SORAKA config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index a51207e990..5dd1e9877e 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -9,7 +9,6 @@ #include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 29dbb5890b..10e17d9b86 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 0c1fc02133..7fd4409401 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -112,8 +112,7 @@ static uintptr_t mainboard_get_spd_data(enum memory_type type, bool use_sec_spd) printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map(spd_bin, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index dd57835739..997352cd0c 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -1,5 +1,4 @@ -SPD_BIN = $(obj)/spd.bin SEC_SPD_BIN = $(obj)/sec-spd.bin define gen_spd_bin @@ -17,16 +16,8 @@ add_spd_to_cbfs= \ ifeq ($(SPD_SOURCES),) SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) endif -# Include SPD ROM data -$(SPD_BIN): $(SPD_DEPS) - $(call gen_spd_bin, $@, $+) - -$(call add_spd_to_cbfs, spd.bin, $(SPD_BIN)) - # Add optional secondary SPD ROM data if present ifneq ($(SEC_SPD_SOURCES),) diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex new file mode 100644 index 0000000000..168f15e37b --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 08 00 50 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 08 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ce943c486c..d3e351ad4f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -3,12 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "50" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" @@ -41,35 +43,21 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, @@ -77,15 +65,6 @@ chip soc/intel/skylake }" register "tcc_offset" = "10" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -168,17 +147,12 @@ chip soc/intel/skylake # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty # USB 3.0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -263,6 +237,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi @@ -290,6 +266,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" @@ -314,7 +291,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A19_IRQ)" register "generic.wake" = "GPE0_DW0_23" # GPP_A23 register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end @@ -365,7 +342,7 @@ chip soc/intel/skylake end end # I2C #4 - Audio device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index c459bad90a..d3ea6b537b 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -10,73 +10,73 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_A23, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_A23, NONE, DEEP, EDGE_SINGLE, INVERT), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -86,40 +86,40 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_C11), + PAD_NC(GPP_C11, NONE), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -133,9 +133,9 @@ static const struct pad_config gpio_table[] = { /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* C18 : I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_C18), + PAD_NC(GPP_C18, NONE), /* C19 : I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_C19), + PAD_NC(GPP_C19, NONE), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -143,24 +143,24 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D7, NONE, PLTRST), /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ PAD_CFG_GPO(GPP_D8, 0, DEEP), /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ @@ -172,9 +172,9 @@ static const struct pad_config gpio_table[] = { /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */ PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ @@ -184,30 +184,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> DISPLAY_DCR_EN */ PAD_CFG_GPO(GPP_E6, 1, DEEP), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -215,29 +215,29 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -246,7 +246,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */ @@ -260,7 +260,7 @@ static const struct pad_config gpio_table[] = { /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, UP_20K, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* F12 : EMMC_CMD */ @@ -286,7 +286,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -312,23 +312,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -388,19 +388,18 @@ static const struct pad_config ish_enabled_gpio_table[] = { PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1), }; - static const struct pad_config ish_disabled_gpio_table[] = { /* A19 : GPP_A19 ==> TRACKPAD_INT_L * trackpad interrupt to PCH */ - PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A19, NONE, PLTRST), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl index ddd05f1273..b973200ffe 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl @@ -65,7 +65,6 @@ Scope (\_SB.PCI0.I2C3) Name (_PR0, Package (0x01) { FCPR }) Name (_PR3, Package (0x01) { FCPR }) - /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index 5e377f2168..50afd42956 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -32,12 +32,14 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* - * EC can wake from S3 with lid or power button or key press or - * mode change event. + * EC can wake from S3 with lid, power button, key press, + * mode change event, or AC plug/unplug. */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d57070e61a..4bfac6d78b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,42 +31,20 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -167,7 +145,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -266,7 +243,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -283,9 +259,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -376,7 +355,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 072b7618a0..dd97d1c6c4 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,30 +37,30 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */ @@ -68,54 +68,54 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> FP_INT */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C8, NONE, PLTRST), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ @@ -145,12 +145,12 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> EN_PP3300_DX_LTE */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D1 : SPI1_CLK ==> PEN_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP), /* D3 : SPI1_MOSI ==> PEN_RST_L */ @@ -162,23 +162,23 @@ static const struct pad_config gpio_table[] = { /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> PEN_EJECT_ODL -- for notification */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, UP_20K, DEEP), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> PEN_EJECT_ODL -- for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_D12, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> LTE_OFF_ODL */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D17 : DMIC_CLK1 */ @@ -197,23 +197,23 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config * __weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl index 8f3ae536b4..2d5dd0a289 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -23,8 +23,8 @@ Scope (\_SB.PCI0.I2C2) ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVTH }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVTH }) + Name (_PR0, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH}) + Name (_PR3, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH}) /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl index 7e205752ea..c41ebca7fe 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -23,8 +23,8 @@ Scope (\_SB.PCI0.I2C4) ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVFI }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVFI }) + Name (_PR0, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVFI}) + Name (_PR3, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVFI}) /* Port0 of CAM1 is connected to port1 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5ad10effa8..842005abd7 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -313,76 +313,50 @@ Scope (\_SB.PCI0.I2C2) PODV, 32, } - /* CLE0 and CLE1 are used to determine if both the clocks - are enabled or disabled. */ - Mutex (MUTC, 0) - Name (CLE0, 0) - Name (CLE1, 0) - Method (CLKE, 0, Serialized) { - /* save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) - /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - /* Enable clocks only when a sensor is turned on and - both the clocks are disabled */ - If (LNot (LOr (CLE0, CLE1))) { - /* Set boost clock divider */ - BODI = 3 - /* Set buck clock divider */ - BUDI = 2 - /* Set the PLL_REF_CLK cyles */ - PSWR = 19 - /* Set the reference crystal divider */ - XTDV = 170 - /* Set PLL feedback divider */ - PLDV = 32 - /* Set PLL output divider for HCLK_A */ - PODV = 1 - /* Set PLL output divider for HCLK_B */ - PDV2 = 1 - /* Enable clocks for both the sensors - * CFG1: output selection for HCLK_A and - * HCLK_B. - * CFG2: set drive strength for HCLK_A - * and HCLK_B. - */ - CFG2 = 5 - CFG1 = 10 - /* Enable PLL output, crystal oscillator - * input capacitance control and set - * Xtal oscillator as clock source. - */ - PCTL = 209 - Sleep(1) - } - Release (MUTC) - } - } - - /* Clocks need to be disabled only if both the sensors are - turned off */ - Method (CLKD, 0, Serialized) { - /* save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) - /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - If (LNot (LOr (CLE0, CLE1))) { - BODI = 0 - BUDI = 0 - PSWR = 0 - XTDV = 0 - PLDV = 0 - PODV = 0 - PDV2 = 0 - /* Disable clocks for both the - sensors */ - CFG2 = 0 - CFG1 = 0 - PCTL = 0 - } - Release (MUTC) + Method (CLK, 1, Serialized) { + If (LEqual (Arg0, Zero)) { + BODI = 0 + BUDI = 0 + PSWR = 0 + XTDV = 0 + PLDV = 0 + PODV = 0 + PDV2 = 0 + /* Disable clocks for both the + sensors */ + CFG2 = 0 + CFG1 = 0 + PCTL = 0 + Sleep(1) + } ElseIf (LEqual (Arg0, 1)) { + /* Set boost clock divider */ + BODI = 3 + /* Set buck clock divider */ + BUDI = 2 + /* Set the PLL_REF_CLK cyles */ + PSWR = 19 + /* Set the reference crystal divider */ + XTDV = 170 + /* Set PLL feedback divider */ + PLDV = 32 + /* Set PLL output divider for HCLK_A */ + PODV = 1 + /* Set PLL output divider for HCLK_B */ + PDV2 = 1 + /* Enable clocks for both the sensors + * CFG1: output selection for HCLK_A and + * HCLK_B. + * CFG2: set drive strength for HCLK_A + * and HCLK_B. + */ + CFG2 = 5 + CFG1 = 10 + /* Enable PLL output, crystal oscillator + * input capacitance control and set + * Xtal oscillator as clock source. + */ + PCTL = 209 + Sleep(1) } } @@ -425,17 +399,43 @@ Scope (\_SB.PCI0.I2C2) } } - /* Power resource methods for CAM0 */ - PowerResource (OVTH, 0, 0) { + /* Power resource methods for both CAMs */ + PowerResource (OVCM, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { /* Enable VSIO regulator + daisy chain */ DOVD(1) + CLK(1) + STA = 1 + } + } + } + Method (_OFF, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 1)) { + CLK(0) + Sleep(2) + DOVD(0) + } + } + STA = 0 + } + Method (_STA, 0, NotSerialized) { + Return (STA) + } + } + + /* Power resource methods for CAM0 */ + PowerResource (OVTH, 0, 1) { + Name (STA, 0) + Method (_ON, 0, Serialized) { + /* TODO: Read Voltage and Sleep values from Sensor Obj */ + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 0)) { \_SB.PCI0.I2C2.PMIC.CGP1() \_SB.PCI0.I2C2.PMIC.CGP2() @@ -447,9 +447,6 @@ Scope (\_SB.PCI0.I2C2) DCVA = 12 VDCT = 1 - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE0 = 1 - /* * Wait for all regulator * outputs to settle. @@ -472,9 +469,6 @@ Scope (\_SB.PCI0.I2C2) Method (_OFF, 0, Serialized) { If (LEqual (AVBL, 1)) { If (LEqual (STA, 1)) { - Sleep(2) - CLE0 = 0 - \_SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) \_SB.PCI0.I2C2.PMIC.CRST(0) Sleep(3) @@ -482,7 +476,6 @@ Scope (\_SB.PCI0.I2C2) Sleep(3) VACT = 0 Sleep(1) - DOVD(0) } } STA = 0 @@ -493,16 +486,12 @@ Scope (\_SB.PCI0.I2C2) } /* Power resource methods for CAM1 */ - PowerResource (OVFI, 0, 0) { + PowerResource (OVFI, 0, 1) { Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { - /* Enable VSIO regulator + - daisy chain */ - DOVD(1) - /* Set VAUX2 as 1.8006 V */ AX2V = 52 VAX2 = 1 /* Enable VAUX2 */ @@ -522,9 +511,6 @@ Scope (\_SB.PCI0.I2C2) /* Wait for VDD to settle. */ Sleep(1) - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE1 = 1 - \_SB.PCI0.I2C2.PMIC.CGP5(1) /* * Ensure 10 ms between @@ -539,9 +525,6 @@ Scope (\_SB.PCI0.I2C2) Method (_OFF, 0, Serialized) { If (LEqual (AVBL, 1)) { If (LEqual (STA, 1)) { - Sleep(2) - CLE1 = 0 - \_SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) \_SB.PCI0.I2C2.PMIC.CGP5(0) Sleep(3) @@ -551,7 +534,6 @@ Scope (\_SB.PCI0.I2C2) Sleep(1) VAX2 = 0 Sleep(1) - DOVD(0) } STA = 0 } diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index a4dcad0d85..25d720e584 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,46 +31,24 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "SaImguEnable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # Intersil VR c-state issue workaround # send VR mailbox command for IA/GT/SA rails register "IslVrCmd" = "2" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -285,8 +263,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" - register "tcc_offset" = "3" # TCC of 97C register "power_limits_config" = "{ .psys_pmax = 101, @@ -298,9 +274,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -338,7 +317,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" register "generic.enable_delay_ms" = "45" @@ -350,7 +329,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "generic.reset_delay_ms" = "50" @@ -373,7 +352,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" register "generic.wake" = "GPE0_DW2_16" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -381,19 +360,19 @@ chip soc/intel/skylake end end # I2C #1 device pci 15.2 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM005C"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" + chip drivers/i2c/hid + register "generic.hid" = ""WCOM005C"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "generic.wake" = "GPE0_DW2_01" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)" @@ -443,7 +422,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 62d1780c28..6dba783920 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -9,59 +9,59 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP22) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP24) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP15) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP23) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP46) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN#_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> PCH_SPK_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> NC(T3) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(T4) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */ @@ -71,15 +71,15 @@ static const struct pad_config gpio_table[] = { /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */ PAD_CFG_GPO(GPP_B9, 0, RSMRST), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> PM_SLP_R_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST#_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -89,34 +89,34 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(TP26) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(TP27) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(TP28) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(TP30) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SOC_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SOC_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC(TP917) */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ PAD_CFG_GPO(GPP_C7, 1, DEEP), /* C8 : UART0_RXD ==> NC(TP31) */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC(TP32) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */ @@ -142,44 +142,44 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> NC(TP926) */ - PAD_CFG_NC(GPP_C22), + PAD_NC(GPP_C22, NONE), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> PEN_IRQ# */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT# */ - PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D2, NONE, PLTRST), /* D3 : SPI1_MOSI ==> PEN_RST# */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ @@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_1_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> EMR_GARAGE_DET# - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E3, NONE, PLTRST), /* E4 : SATA_DEVSLP0 ==> BT_OFF# */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> EMR_GARAGE_DET# - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP), /* E9 : USB2_OCO# ==> USB_C0_OC# */ @@ -218,15 +218,15 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> DDR_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ @@ -238,9 +238,9 @@ static const struct pad_config gpio_table[] = { /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E22, NONE, DEEP, EDGE_SINGLE, INVERT), /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ @@ -250,7 +250,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -260,13 +260,13 @@ static const struct pad_config gpio_table[] = { /* F7 : I2C3_SCL ==> I2C_3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ - PAD_CFG_NC(GPP_F8), + PAD_NC(GPP_F8, NONE), /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ - PAD_CFG_NC(GPP_F9), + PAD_NC(GPP_F9, NONE), /* F10 : I2C5_SDA ==> NC */ - PAD_CFG_NC(GPP_F10), + PAD_NC(GPP_F10, NONE), /* F11 : I2C5_SCL ==> NC */ - PAD_CFG_NC(GPP_F11), + PAD_NC(GPP_F11, NONE), /* F12 : EMMC_CMD ==> EMMC_1_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ @@ -290,24 +290,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_1_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> NC */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 ==> NC */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 ==> NC */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 ==> NC */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 ==> NC */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# ==> NC */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK ==> NC */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP ==> SD_WP (not needed) */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -316,23 +316,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP44) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP41) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP38) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -353,13 +353,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, DN_20K, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -383,23 +383,23 @@ static const struct pad_config nami_default_sku_gpio_table[] = { static const struct pad_config no_dmic1_sku_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), }; static const struct pad_config pantheon_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), }; static const struct pad_config fpmcu_gpio_table[] = { /* B0 : CORE_VID0 ==> FPMCU_INT_L */ - PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_B0, NONE, DEEP), /* B1 : CORE_VID1 ==> FPMCU_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ @@ -417,7 +417,7 @@ static const struct pad_config fpmcu_gpio_table[] = { /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 158f0d1a8c..5486670adf 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -22,15 +22,15 @@ #define SKU_0_SYNDRA 0x2BC63 #define SKU_1_SYNDRA 0x2BC62 #define SKU_2_SYNDRA 0x2BC61 -#define SKU_3_SYNDRA 0X2BC60 -#define SKU_4_SYNDRA 0X6BC63 -#define SKU_5_SYNDRA 0X6BC62 -#define SKU_6_SYNDRA 0X6BC61 -#define SKU_7_SYNDRA 0X6BC60 +#define SKU_3_SYNDRA 0x2BC60 +#define SKU_4_SYNDRA 0x6BC63 +#define SKU_5_SYNDRA 0x6BC62 +#define SKU_6_SYNDRA 0x6BC61 +#define SKU_7_SYNDRA 0x6BC60 #define SKU_0_EKKO 0x10118E3 #define SKU_1_EKKO 0x10018E3 #define SKU_2_EKKO 0x10118E1 -#define SKU_3_EKKO 0X10018E1 +#define SKU_3_EKKO 0x10018E1 #define SKU_4_EKKO 0x10118E2 #define SKU_5_EKKO 0x10018E2 #define SKU_6_EKKO 0x10118E0 @@ -38,9 +38,9 @@ #define SKU_0_BARD 0x1019CE3 #define SKU_1_BARD 0x1009CE3 #define SKU_2_BARD 0x1019CE1 -#define SKU_3_BARD 0X1009CE1 -#define SKU_4_BARD 0X1009CE0 -#define SKU_5_BARD 0X1009CE2 +#define SKU_3_BARD 0x1009CE1 +#define SKU_4_BARD 0x1009CE0 +#define SKU_5_BARD 0x1009CE2 #define SKU_6_BARD 0x1019CE0 #define SKU_7_BARD 0x1019CE2 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 8d5d0c482b..1387716298 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -155,9 +155,8 @@ const char *smbios_mainboard_manufacturer(void) if (oem_id == OEM_UNKNOWN) return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data), - CBFS_TYPE_RAW); + oem_data_size = cbfs_load("oem.bin", oem_bin_data, + sizeof(oem_bin_data)); while ((curr < oem_data_size) && ((oem_data_size - curr) >= sizeof(*oem_entry))) { diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 3e482a9f27..6faca2b133 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index a5f997a427..9563298518 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,42 +31,20 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Slew rate setting for improving audible noise register "AcousticNoiseMitigation" = "1" @@ -159,8 +137,8 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" + # RP 1 uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism @@ -287,7 +265,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -304,14 +281,17 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""SYTS7813"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "45" @@ -404,7 +384,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 555b532b2c..37378f93a7 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -9,25 +9,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -38,81 +38,81 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A21, NONE, PLTRST), /* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A22, NONE, PLTRST), /* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP722) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> CHP3_TP_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT3_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* B20 : GSPI1_CLK ==> LTE3_STRAP# - for SAR sensor presence */ - PAD_CFG_GPI(GPP_B20, 20K_PD, DEEP), + PAD_CFG_GPI(GPP_B20, DN_20K, DEEP), /* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE), + PAD_CFG_GPI_SCI(GPP_B21, NONE, DEEP, EDGE_SINGLE, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> CHP3_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> CHP3_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> CPU3_EC_IN_RW */ - PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ @@ -144,38 +144,38 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> NC */ - PAD_CFG_NC(GPP_D10), + PAD_NC(GPP_D10, NONE), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,51 +190,51 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB3_C1_OC1_L */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */ - PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP766) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> CHP1_CABC */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */ @@ -244,15 +244,15 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */ - PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, UP_5K, DEEP, NF1), /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */ - PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, UP_5K, DEEP, NF1), /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */ @@ -284,7 +284,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -301,7 +301,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> CHP3_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -310,23 +310,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> CHP3_SLPS3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> CHP3_SLPS4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP725) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> CHP3_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP724) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP742) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -343,10 +343,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -363,20 +363,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num) static const struct pad_config nautilus_default_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ - PAD_CFG_NF(GPP_E11, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E11, UP_5K, DEEP, NF1), }; static const struct pad_config lte_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> LTE1_P_SENSOR_INT_L */ - PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_A18, NONE, DEEP), /* D0 : SPI1_CS# ==> LTE_PWROFF# */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */ diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl index a390b61584..cfc84b5334 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl @@ -22,8 +22,8 @@ Scope (\_SB.PCI0.I2C2) ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVTH }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVTH }) + Name (_PR0, Package () { ^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH }) + Name (_PR3, Package () { ^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH }) /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 8819350dce..899990de0b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,36 +36,21 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - # Set speed_shift_enable to 1 to enable P-States, and 0 to disable - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 18, @@ -73,15 +58,6 @@ chip soc/intel/skylake }" register "tcc_offset" = "10" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -162,34 +138,29 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" - # Root port 9 (x2) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + # Root port 9 (x2) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ2# + # PcieRpClkSrcNumber: Uses 3 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty # USB 3.0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -283,7 +254,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -315,18 +287,19 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST_PLUS" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0a on end @@ -424,7 +397,7 @@ chip soc/intel/skylake end end # I2C #4 - Audio device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_01" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index d5888dd6f2..f5344584ba 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -8,60 +8,60 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0_R */ /* A2 : ESPI_IO1_R */ /* A3 : ESPI_IO2_R */ /* A4 : ESPI_IO3_R */ /* A5 : ESPI_CS_L_R */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK_R */ - PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : ISH_GP6 */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : SPKR_RST_L */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), /* A20 : ISH_GP2 ==> ISH_UART0_RXD */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* B1 : CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> FCAM_PWR_EN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B6, NONE, DEEP), /* B7 : SRCCLKREQ2# ==> PCIE_NVME_CLKREQ_ODL */ @@ -69,17 +69,17 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* B19 : GSPI1_CS# ==> PCH_FPMCU_SPI_CS_L_R */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_FPMCU_SPI_CLK_R */ @@ -97,32 +97,32 @@ static const struct pad_config gpio_table[] = { /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SM1ALERT# ==> PCHHOT# */ - PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# */ - PAD_CFG_NF(GPP_C5, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_C5, DN_20K, DEEP, NF1), /* C6 : SM1CLK ==> EC_IN_RW_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> FPMCU_INT */ - PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, EDGE_SINGLE, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C11, UP_20K, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -146,34 +146,34 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> RCAM_PWR_EN */ PAD_CFG_GPO(GPP_D7, 0, DEEP), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> PCH_FCAM_CLK_EN */ PAD_CFG_GPO(GPP_D13, 0, DEEP), /* D14 : ISH_UART0_TXD ==> PCH_RCAM_CLK_EN */ @@ -183,46 +183,46 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> NC */ - PAD_CFG_NC(GPP_D23), + PAD_NC(GPP_D23, NONE), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> WLAN_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E3 : DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ - PAD_CFG_TERM_GPO(GPP_E11, 0, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 0, DN_20K, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ @@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = { /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD_3V3 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> DDPB_CTRLDATA */ - PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> DDPC_CTRLDATA */ - PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -253,11 +253,11 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> NC */ - PAD_CFG_NC(GPP_F4), + PAD_NC(GPP_F4, NONE), /* F5 : I2C2_SCL ==> NC */ - PAD_CFG_NC(GPP_F5), + PAD_NC(GPP_F5, NONE), /* F6 : I2C3_SDA ==> PCH_I2C3_FCAM_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_FCAM_1V8_SCL */ @@ -293,24 +293,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -350,7 +350,7 @@ static const struct pad_config early_gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ @@ -359,10 +359,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 0d835cbe88..2baeb52494 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -4,6 +4,8 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 +SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 bootblock-y += gpio.c diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index de7023dacb..162b437f32 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -3,12 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 500, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" @@ -41,42 +43,20 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "SaImguEnable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -172,7 +152,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -245,7 +224,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 18W for AML-Y register "power_limits_config" = "{ .tdp_pl2_override = 18, @@ -262,6 +240,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -298,6 +278,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" @@ -371,7 +352,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 off end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 9bb497ec95..8e9e5c01c5 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(T0804) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(T0805) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(T0501) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(T0806) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(T0913) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,48 +37,48 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> TRACKPAD_INT_L for wakeup event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -88,38 +88,38 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(T0807) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(T0808) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(T0809) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(T0810) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> BT_OFF# */ PAD_CFG_GPO(GPP_C8, 1, DEEP), /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC(T0817) */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ @@ -145,105 +145,105 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC(T0818) */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC(T0819) */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC(T0820) */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC(T0815) */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC(T0816) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : ISH_UART0_CTS# ==> DMIC_CLK1_PCH */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 ==> NC(T0703) */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> DMIC_CLK0_PCH */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> DMIC_DATA0_PCH */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN I2C OPERATION ENABLE/DISABLE. */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> NC(T0504) */ - PAD_CFG_NC(GPP_E11), + PAD_NC(GPP_E11, NONE), /* E12 : USB2_OC3# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD_ODL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(T0602) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK ==> SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP ==> NC(T0701) */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(T0912) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(T0911) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(T0905) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -356,10 +356,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8c22adea2f..6a37b8a4bc 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,42 +31,20 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -167,7 +145,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -267,7 +244,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -284,9 +260,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOMCOHO"" @@ -350,7 +329,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 33bdb290e1..9d52773271 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,87 +37,87 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ @@ -145,42 +145,42 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,30 +190,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 3 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -354,10 +354,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index aa1c977f2a..4748d45d83 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -14,6 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_NINJA && !BOARD_GOOGLE_SUMO + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index a9a0885507..161f68d749 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -2,16 +2,11 @@ #include #include -#include -#include #include #include -#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; @@ -27,20 +22,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->dpte = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index da1b185c7e..77ff74375e 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -4,85 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index a54a646f13..1a6a1b922e 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 0f729bf87a..41d9795c5e 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -5,7 +5,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include #include #include "ec.h" @@ -14,10 +13,6 @@ #include #include -void mainboard_suspend_resume(void) -{ -} - #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 6487f43121..28496b15ba 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -48,8 +48,7 @@ void mainboard_fill_mrc_params(struct mrc_params *mp) void *spd_file; size_t spd_fsize; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); + spd_file = cbfs_map("spd.bin", &spd_fsize); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc index 1d6619bf8f..6711c2e760 100644 --- a/src/mainboard/google/rambi/variants/banjo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -16,17 +14,3 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc index 4630519b4e..4e8c9017ef 100644 --- a/src/mainboard/google/rambi/variants/candy/Makefile.inc +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -29,17 +27,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc index 2a641ba881..91d23af976 100644 --- a/src/mainboard/google/rambi/variants/clapper/Makefile.inc +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index db313c07ea..1386ae1369 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -197,7 +197,6 @@ static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, }; - static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, }; diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc index 5b7d58b8e3..57f72800a5 100644 --- a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc +++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc index da99edce4c..c54f901f49 100644 --- a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -26,17 +24,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc index eb87d0c619..f17db16e68 100644 --- a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc index 8a9adf3d81..eacc7b5a09 100644 --- a/src/mainboard/google/rambi/variants/heli/Makefile.inc +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # RAM_ID Vendor Vendor_PN Freq Size Total_size channel @@ -26,17 +24,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc index bf95c739e8..d9c872ab56 100644 --- a/src/mainboard/google/rambi/variants/kip/Makefile.inc +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125a SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/ninja/Makefile.inc b/src/mainboard/google/rambi/variants/ninja/Makefile.inc index 723a5e592d..739eb7ea7a 100644 --- a/src/mainboard/google/rambi/variants/ninja/Makefile.inc +++ b/src/mainboard/google/rambi/variants/ninja/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index e5688df0f2..1304071444 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -109,9 +109,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc index 2c2496ebc9..0412c537c5 100644 --- a/src/mainboard/google/rambi/variants/orco/Makefile.inc +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc index 2c0127cbef..d729475686 100644 --- a/src/mainboard/google/rambi/variants/quawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/rambi/Makefile.inc b/src/mainboard/google/rambi/variants/rambi/Makefile.inc index 5bddd5c15a..012206eb18 100644 --- a/src/mainboard/google/rambi/variants/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/variants/rambi/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -16,17 +14,3 @@ SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc index 2c0127cbef..d729475686 100644 --- a/src/mainboard/google/rambi/variants/squawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc index 723a5e592d..739eb7ea7a 100644 --- a/src/mainboard/google/rambi/variants/sumo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 53bd4fb02f..29bc0fe336 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -109,9 +109,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc index 7269afd299..94702622ce 100644 --- a/src/mainboard/google/rambi/variants/swanky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -12,17 +10,3 @@ SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc index 105684f7eb..27b8a6a42a 100644 --- a/src/mainboard/google/rambi/variants/winky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb @@ -16,17 +14,3 @@ SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA SPD_SOURCES += HT_micron_HTTC4G63CFR-PBA_x16_4Gb SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 2455101171..9744d74738 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -18,7 +18,6 @@ config BOARD_GOOGLE_BASEBOARD_REEF select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION - select DRIVERS_INTEL_WIFI select USE_SAR select SAR_ENABLE select DSAR_ENABLE @@ -44,7 +43,6 @@ config TPM_TIS_ACPI_INTERRUPT config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH if BASEBOARD_REEF_LAPTOP config MAINBOARD_DIR @@ -82,10 +80,6 @@ config MAINBOARD_FAMILY default "Google_Coral" if BOARD_GOOGLE_CORAL default "Google_Reef" -config MAX_CPUS - int - default 8 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 315cf7c30f..ecd44f6c92 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -25,6 +25,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 4c35bd25da..9aadc9ed52 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -125,7 +125,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC @@ -139,6 +141,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 @@ -146,7 +149,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index aac160bc06..6b267c90cc 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -138,6 +138,13 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "K4F8E3S4HD-MGCL", }, + /* NT6AN256T32AV-J2 - both logical channels */ + [9] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "NT6AN256T32AV-J2", + }, }; static const struct lpddr4_cfg lp4cfg = { diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index f987e1da02..e8f8cc334a 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -125,7 +125,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC @@ -139,6 +141,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 @@ -146,7 +149,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end @@ -219,7 +222,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "generic.wake" = "GPE0_DW1_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 1282edb9ba..af459bebef 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -134,7 +134,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC @@ -148,6 +150,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 @@ -155,7 +158,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index dfe936faaf..1cc9b99361 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -5,7 +5,6 @@ #include #include - static const struct lpddr4_sku skus[] = { /* * K4F6E304HB-MGCJ - both logical channels While the parts diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index ad76a9194d..91555ad6c8 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -121,7 +121,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC @@ -135,6 +137,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 @@ -142,7 +145,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/sand/include/variant/ec.h b/src/mainboard/google/reef/variants/sand/include/variant/ec.h index 8d0105f15e..87d2887135 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/ec.h @@ -60,7 +60,6 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index a82400ff60..d4e9705fc3 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -130,7 +130,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC @@ -144,6 +146,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 @@ -151,7 +154,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end @@ -235,7 +238,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "130" @@ -249,7 +252,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index df5e5b8420..444234af45 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -2,13 +2,13 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BH720 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -16,13 +16,13 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_SARIEN select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_ARCADA - select TPM2 select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_SARIEN select USE_SAR @@ -95,7 +95,6 @@ config DEVICETREE config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index eea7f472e6..e7bfc53aa0 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += bootblock.c +ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-y += sku.c diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index b666fbc4f6..664305eeef 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -6,13 +6,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -39,9 +39,6 @@ DefinitionBlock( #include - /* Low power idle table */ - #include - #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/mainboard.c b/src/mainboard/google/sarien/mainboard.c new file mode 100644 index 0000000000..5399e6cd78 --- /dev/null +++ b/src/mainboard/google/sarien/mainboard.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + printk(BIOS_DEBUG, "mainboard: %s init\n", __func__); + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +} diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index f4704faf86..de97c686ee 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -2,33 +2,12 @@ #include #include -#include #include #include #include #include #if CONFIG(GENERATE_SMBIOS_TABLES) -#define VPD_KEY_SYSTEM_SERIAL "serial_number" -#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" -#define VPD_SERIAL_LEN 64 - -const char *smbios_system_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - -const char *smbios_mainboard_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a84e73a826..c975b9906c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,12 +15,9 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s @@ -30,7 +27,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" @@ -133,8 +129,6 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "{ .enable = 1, \ @@ -152,8 +146,6 @@ chip soc/intel/cannonlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -310,10 +302,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid @@ -340,9 +334,9 @@ chip soc/intel/cannonlake device i2c 2c on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2a on end @@ -350,7 +344,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -378,11 +372,19 @@ chip soc/intel/cannonlake device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[9]" = "1" end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.2 on # PCI Express Port 11 + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 6bc145ace3..96783ca0a3 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -3,7 +3,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240993..6a807a36b6 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,16 +15,13 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s @@ -33,7 +30,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" @@ -140,7 +136,6 @@ chip soc/intel/cannonlake register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH @@ -152,7 +147,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -320,16 +314,18 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" @@ -369,7 +365,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -386,22 +382,38 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 (USB) + device pci 1c.0 on # PCI Express Port 1 (USB) + register "PcieRpSlotImplemented[0]" = "1" + end device pci 1c.1 off end # PCI Express Port 2 (USB) device pci 1c.2 off end # PCI Express Port 3 (USB) device pci 1c.3 off end # PCI Express Port 4 (USB) device pci 1c.4 off end # PCI Express Port 5 (USB) device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 + device pci 1c.7 on # PCI Express Port 8 + register "PcieRpSlotImplemented[7]" = "1" + end device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.1 on # PCI Express Port 10 + register "PcieRpSlotImplemented[9]" = "1" + end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 6bc145ace3..96783ca0a3 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -3,7 +3,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 37c11e047f..c9ca334a8d 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY def_bool n select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP @@ -18,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select DRIVERS_I2C_RTD2132 if BOARD_GOOGLE_LEON + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 3435c28111..023107e528 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -3,14 +3,12 @@ #include #include #include -#include -#include #include #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -23,12 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index da1b185c7e..77ff74375e 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -4,85 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index e22a41ebc2..d98954535f 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -11,9 +11,6 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - register "ec_present" = "true" register "usb_xhci_on_resume" = "true" @@ -23,14 +20,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end @@ -40,15 +29,6 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" @@ -61,8 +41,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 805363fce2..8ca683dcb2 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 2a819d3a35..90f28e7ec2 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -16,8 +16,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_FINALIZE); } - - static void mainboard_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc index 6d1ee81ec7..d8d748b726 100644 --- a/src/mainboard/google/slippy/variants/falco/Makefile.inc +++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) @@ -13,16 +10,4 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl index d395a317ed..0ee0eb0796 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index c163202e99..fc77345dab 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,12 +1,13 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + register "panel_cfg" = "{ + .up_delay_ms = 60, + .down_delay_ms = 60, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index eba4a8b648..516b26c9c5 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -21,8 +21,7 @@ void copy_spd(struct pei_data *peid) size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/leon/Makefile.inc b/src/mainboard/google/slippy/variants/leon/Makefile.inc index 3dab895e9c..213dadb006 100644 --- a/src/mainboard/google/slippy/variants/leon/Makefile.inc +++ b/src/mainboard/google/slippy/variants/leon/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -12,16 +9,4 @@ SPD_SOURCES += Micron_4KTF25664HZ # 4: space holder SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 SPD_SOURCES += Samsung_K4B4G1646Q # 6: 2GB / CH0 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl index bf4adfdcbf..e149559a6a 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index f3b5c4a257..1d50086c58 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,12 +1,13 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 2b1b5ca6bd..e24dcb9808 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -20,8 +20,7 @@ void copy_spd(struct pei_data *peid) size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc index c19326e0c5..f8c5b0d88f 100644 --- a/src/mainboard/google/slippy/variants/peppy/Makefile.inc +++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -13,16 +10,4 @@ SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1 SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6CFR6A # 7: 2GB / CH0 + CH1 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index 8bbb19a2ed..babf9a0a37 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } @@ -82,7 +82,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } @@ -122,7 +122,7 @@ Scope (\_SB.PCI0.I2C1) Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index cd6a0df9ad..e732a9270c 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,12 +1,13 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 230595e205..92e1e8dd5e 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -24,8 +24,7 @@ void copy_spd(struct pei_data *peid) uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc index 3306b797f0..cd38d98051 100644 --- a/src/mainboard/google/slippy/variants/wolf/Makefile.inc +++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -11,16 +8,4 @@ SPD_SOURCES += Micron_4KTF25664HZ # 3: 2GB / CH0 SPD_SOURCES += Hynix_HMT425S6AFR6A # 4: 2GB / CH0 SPD_SOURCES += Samsung_K4B4G1646B # 4: 2GB / CH0 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl index bf4adfdcbf..e149559a6a 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index 5ccca1d821..824694720d 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,12 +1,13 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 405e86acef..a0b5055457 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -21,8 +21,7 @@ void copy_spd(struct pei_data *peid) size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index f547fd01f1..852e73de67 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -203,8 +203,8 @@ struct chip_operations mainboard_ops = { void lb_board(struct lb_header *header) { -#if CONFIG(CHROMEOS) - lb_table_add_serialno_from_vpd(header); -#endif + if (CONFIG(CHROMEOS)) + lb_table_add_serialno_from_vpd(header); + soc_add_mtc(header); } diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 57fc1d07fa..6a89be04df 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -110,8 +110,7 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); -#if CONFIG(CHROMEOS) /* Retrieve the switch interface MAC addresses. */ - lb_table_add_macs_from_vpd(header); -#endif + if (CONFIG(CHROMEOS)) + lb_table_add_macs_from_vpd(header); } diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 27b6eca1f6..88ff2aecd3 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include "ec.h" @@ -13,7 +12,7 @@ #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -23,11 +22,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (CONFIG(CHROMEOS) && !get_recovery_mode_switch()) + gnvs_set_ecfw_rw(); /* EC handles all thermal and fan control on Stout. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 0cf582192b..5cfca4f15f 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -4,99 +4,71 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size - -#547 437 r 0 unused +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index a03a0a6dc7..5461b15dd9 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms register "gpu_panel_power_down_delay" = "150" # T3: 15ms @@ -27,13 +27,9 @@ chip northbridge/intel/sandybridge register "tcc_offset" = "5" # TCC of 95C - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 96bbb9c565..5aef3604d7 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e71d0eec78..f2f21bc0d2 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,15 +91,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 6e9b490917..05ff973a47 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -55,14 +55,12 @@ void stout_ec_finalize_smm(void) critical_shutdown = 1; } - /* Thermal Device Error : Peripheral Status 3 (0x35) bit 8 */ if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; } - /* Critical Battery Error */ ec_reg = ec_read(EC_MBAT_STATUS); @@ -75,7 +73,6 @@ void stout_ec_finalize_smm(void) printk(BIOS_ERR, " EC Read Battery Error\n"); } - if (critical_shutdown) { printk(BIOS_ERR, "EC critical_shutdown"); diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 29a6923726..7f4e29d2e8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -17,8 +17,6 @@ void mainboard_suspend_resume(void) ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); } - - static void mainboard_init(struct device *dev) { struct device *ethernet_dev = NULL; diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 6a0f912c00..b3ec4b59a4 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC_SPI if !BOARD_GOOGLE_BUBS select RTC if !BOARD_GOOGLE_BUBS select MISSING_BOARD_RESET if BOARD_GOOGLE_BUBS + select DRIVERS_TI_SN65DSI86BRIDGE select SOC_QUALCOMM_SC7180 select SPI_FLASH select SPI_FLASH_WINBOND @@ -51,6 +52,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config MAINBOARD_PART_NUMBER string default "Bubs" if BOARD_GOOGLE_BUBS + default "Coachz" if BOARD_GOOGLE_COACHZ default "Lazor" if BOARD_GOOGLE_LAZOR default "Pompom" if BOARD_GOOGLE_POMPOM default "Trogdor" if BOARD_GOOGLE_TROGDOR diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index b7c03f92e5..174c795d87 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,17 +1,28 @@ comment "Trogdor" +if USE_QC_BLOBS + config BOARD_GOOGLE_BUBS - bool "Bubs" + bool "-> Bubs" + select BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_GOOGLE_COACHZ + bool "-> Coachz" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_LAZOR - bool "Lazor" + bool "-> Lazor" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_POMPOM - bool "Pompom" + bool "-> Pompom" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_TROGDOR - bool "Trogdor" + bool "-> Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON + +endif + +comment "(Trogdor requires 'Allow QC blobs repository')" + depends on !USE_QC_BLOBS diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index cab44032eb..ebce3b56c5 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -9,11 +9,17 @@ #define GPIO_EC_IN_RW GPIO(118) #define GPIO_AP_EC_INT GPIO(94) -#define GPIO_WP_STATE GPIO(42) #define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) #define GPIO_SD_CD_L GPIO(69) #define GPIO_AMP_ENABLE GPIO(23) +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : \ + (CONFIG(BOARD_GOOGLE_COACHZ) ? (board_id() == 0 ? GPIO(52) : \ + GPIO(67)) : GPIO(30))) + void setup_chromeos_gpios(void); #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index c1a48925fa..edde164746 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -2,6 +2,7 @@ #include #include +#include uint32_t board_id(void) { @@ -15,14 +16,28 @@ uint32_t board_id(void) return id; } +/* Some boards/revisions use one GPIO mapping and others use another. There's no real rhyme or + reason to it. Don't try to think about it too much... */ +static bool use_old_pins(void) +{ + return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || + CONFIG(BOARD_GOOGLE_LAZOR) || + (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); +} + uint32_t ram_code(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t old_pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t pins[] = {[2] = GPIO(5), [1] = GPIO(3), [0] = GPIO(1)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } @@ -31,10 +46,15 @@ uint32_t sku_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t old_pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t pins[] = {[2] = GPIO(2), [1] = GPIO(90), [0] = GPIO(58)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 9c45dfe71e..989bf6902e 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -5,16 +5,10 @@ #include "board.h" #include -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); gpio_input_pullup(GPIO_AP_EC_INT); - gpio_input(GPIO_WP_STATE); gpio_input_pullup(GPIO_SD_CD_L); gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); gpio_output(GPIO_AMP_ENABLE, 0); diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 3aa047309f..f6960761ef 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -2,22 +2,22 @@ FLASH@0x0 8M { WP_RO 4M { - RO_SECTION 0x3c4000 { + RO_SECTION 0x3e4000 { BOOTBLOCK 96K COREBOOT(CBFS) - FMAP@0x3c0000 0x1000 + FMAP@0x3e0000 0x1000 GBB 0x2f00 RO_FRID 0x100 } - RO_VPD(PRESERVE) 228K - RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K + RO_VPD(PRESERVE) } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K + UNIFIED_MRC_CACHE(PRESERVE) 16K { + RECOVERY_MRC_CACHE 8K + RW_MRC_CACHE 8K + } RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index c82eaa0e02..0f469e065b 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,9 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include +#include +#include +#include +#include +#include #include +#include #include +#include "board.h" + +#define BRIDGE_BUS 0x2 +#define BRIDGE_CHIP 0x2d + static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, .imp_ctrl1 = 0x08, @@ -12,26 +26,27 @@ static struct usb_board_data usb0_board_data = { static void setup_usb(void) { + /* Assert EN_PP3300_HUB for those board variants that use it. */ + gpio_output(GPIO(84), 1); + setup_usb_host0(&usb0_board_data); } static void qi2s_configure_gpios(void) { - gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(50), GPIO50_FUNC_MI2S_1_WS, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(51), GPIO51_FUNC_MI2S_1_DATA0, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); } static void load_qup_fw(void) { qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_SPI, MIXED); /* ESIM SPI */ - qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* EDP Bridge I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_UART, FIFO); /* BT UART */ qupv3_se_fw_load_and_init(QUPV3_0_SE4, SE_PROTOCOL_I2C, MIXED); /* Pen Detect I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* SAR I2C */ @@ -48,11 +63,60 @@ static void load_qup_fw(void) qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */ } +static void configure_display(void) +{ + printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); + + /* Bridge Enable GPIO */ + gpio_output(GPIO_EDP_BRIDGE_ENABLE, 1); + + /* PP3300 EDP power supply */ + gpio_output(GPIO_EN_PP3300_DX_EDP, 1); +} + +static void display_init(struct edid *edid) +{ + uint32_t dsi_bpp = 24; + uint32_t lanes = 4; + + if (mdss_dsi_config(edid, lanes, dsi_bpp)) + return; + + sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp); + mdp_dsi_video_config(edid); + mdss_dsi_video_mode_config(edid, dsi_bpp); + mdp_dsi_video_on(); +} + +static void display_startup(void) +{ + static struct edid ed; + enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; + + i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */ + if (display_init_required()) { + configure_display(); + mdelay(250); /* Delay for the panel to be up */ + sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); + if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0) + return; + + printk(BIOS_INFO, "display init!\n"); + + /* Configure backlight */ + gpio_output(GPIO_BACKLIGHT_ENABLE, 1); + display_init(&ed); + fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0); + } else + printk(BIOS_INFO, "Skipping display init.\n"); +} + static void mainboard_init(struct device *dev) { setup_usb(); qi2s_configure_gpios(); load_qup_fw(); + display_startup(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 562e329d0e..8b6f1dec8d 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -3,6 +3,7 @@ #include #include #include +#include static void prepare_usb(void) { @@ -17,6 +18,8 @@ void platform_romstage_main(void) { prepare_usb(); + check_wdog(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 4c9587abc0..95158bf9ee 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -11,7 +11,6 @@ #define GPIO_RECOVERY_SERVO GPIO(0, B, 1) #define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1) - void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 16834ae199..c776ba1912 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -1,17 +1,21 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A + select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 + select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID @@ -22,26 +26,38 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 + select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS bool default y + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH select VBOOT_EARLY_EC_SYNC +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select GEO_SAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DIMM_SPD_SIZE int default 512 @@ -57,6 +73,14 @@ config OVERRIDE_DEVICETREE config DRIVER_TPM_SPI_BUS default 0x1 +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + config MAINBOARD_DIR string default "google/volteer" @@ -67,14 +91,23 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string + default "Delbin" if BOARD_GOOGLE_DELBIN + default "Eldrid" if BOARD_GOOGLE_ELDRID default "Halvor" if BOARD_GOOGLE_HALVOR + default "Lindar" if BOARD_GOOGLE_LINDAR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Terrador" if BOARD_GOOGLE_TERRADOR + default "Todor" if BOARD_GOOGLE_TODOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 + default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL - default "Delbin" if BOARD_GOOGLE_DELBIN + default "Boldar" if BOARD_GOOGLE_BOLDAR + default "Elemi" if BOARD_GOOGLE_ELEMI + default "Voema" if BOARD_GOOGLE_VOEMA + default "Drobit" if BOARD_GOOGLE_DROBIT + default "Copano" if BOARD_GOOGLE_COPANO config MAX_CPUS int @@ -100,14 +133,23 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string + default "delbin" if BOARD_GOOGLE_DELBIN + default "eldrid" if BOARD_GOOGLE_ELDRID default "halvor" if BOARD_GOOGLE_HALVOR + default "lindar" if BOARD_GOOGLE_LINDAR default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR + default "todor" if BOARD_GOOGLE_TODOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 + default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL - default "delbin" if BOARD_GOOGLE_DELBIN + default "boldar" if BOARD_GOOGLE_BOLDAR + default "elemi" if BOARD_GOOGLE_ELEMI + default "voema" if BOARD_GOOGLE_VOEMA + default "drobit" if BOARD_GOOGLE_DROBIT + default "copano" if BOARD_GOOGLE_COPANO config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 06bbc58f59..0dcb64ff28 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,44 +1,104 @@ comment "Volteer" +config BOARD_GOOGLE_DELBIN + bool "-> Delbin" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_ELDRID + bool "-> Eldrid" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + config BOARD_GOOGLE_HALVOR bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM + +config BOARD_GOOGLE_LINDAR + bool "-> Lindar" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MALEFOR bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select SOC_INTEL_CSE_LITE_SKU +config BOARD_GOOGLE_TODOR + bool "-> Todor" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM + config BOARD_GOOGLE_TRONDO bool "-> Trondo" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER2 bool "-> Volteer2" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVER_I2C_TPM_ACPI + +# Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board +config BOARD_GOOGLE_VOLTEER2_TI50 + bool "-> Volteer2_Ti50" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA + select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVER_I2C_TPM_ACPI config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU -config BOARD_GOOGLE_DELBIN - bool "-> Delbin" +config BOARD_GOOGLE_BOLDAR + bool "-> Boldar" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + +config BOARD_GOOGLE_ELEMI + bool "-> Elemi" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA + select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_DROBIT + bool "-> Drobit" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_COPANO + bool "-> Copano" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c index ff9c5ed9f5..328480e3bc 100644 --- a/src/mainboard/google/volteer/bootblock.c +++ b/src/mainboard/google/volteer/bootblock.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 09642a05ba..abd50c57ba 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 60ea3ded64..6f833fefdc 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -1,46 +1,48 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x4ff000 +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME } - SI_BIOS@0x500000 0x1b00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xf00000 - RW_SECTION_A@0xf00000 0x3e0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + SI_BIOS 27M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3M } - RW_SECTION_B@0x12e0000 0x3e0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K } - RW_MISC@0x16c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + # Starts at 16M boundary in the SPI flash. + # No region can be placed across the 16M boundary + # because the SPI flash is mapped into separate + # non-contiguous mmap windows + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3M } # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x1700000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index ddbc10f4e4..ba9541ee5d 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "variant/ec.h" @@ -11,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -31,6 +27,9 @@ DefinitionBlock( #include #include #include +#if CONFIG(VARIANT_HAS_MIPI_CAMERA) + #include +#endif } /* Mainboard hooks */ #include "mainboard.asl" @@ -39,10 +38,6 @@ DefinitionBlock( // Chrome OS specific #include - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include - // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { @@ -56,7 +51,6 @@ DefinitionBlock( #if CONFIG(VARIANT_HAS_MIPI_CAMERA) /* Camera */ - #include #include #endif /* VARIANT_HAS_MIPI_CAMERA */ } diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c index b47e49756b..92fb9442ce 100644 --- a/src/mainboard/google/volteer/ec.c +++ b/src/mainboard/google/volteer/ec.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4cf8..1025119658 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -33,7 +33,7 @@ static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S3, NONE), }; -static const struct pad_config i2s_enable_pads[] = { +static const struct pad_config i2s_up3_enable_pads[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SCLK */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ @@ -45,6 +45,15 @@ static const struct pad_config i2s_enable_pads[] = { PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ }; +static const struct pad_config i2s_up4_enable_pads[] = { + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SCLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ +}; + static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_A23, NONE), PAD_NC(GPP_D19, NONE), @@ -57,8 +66,19 @@ static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_R7, NONE), }; +static const struct pad_config sd_power_enable_pads[] = { + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + static void fw_config_handle(void *unused) { + if (!fw_config_is_provisioned()) { + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + return; + } + if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); @@ -72,11 +92,26 @@ static void fw_config_handle(void *unused) gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { - printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); + gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_UP4))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP4.\n"); + gpio_configure_pads(i2s_up4_enable_pads, ARRAY_SIZE(i2s_up4_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + } + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_RTS5227S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_GL9750)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_OZ711LV2LN))) { + printk(BIOS_INFO, "Configure GPIOs for SD power enable.\n"); + gpio_configure_pads(sd_power_enable_pads, ARRAY_SIZE(sd_power_enable_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl index c360fcfb76..0e9bb8c1c8 100644 --- a/src/mainboard/google/volteer/mainboard.asl +++ b/src/mainboard/google/volteer/mainboard.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include @@ -33,7 +30,7 @@ Method (MWAK, 1, Serialized) /* * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM + * Called from \_SB.PEPD._DSM */ Method (MS0X, 1, Serialized) { diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1ede7f2b49..4d65245066 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,28 +1,137 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include +#include #include -#include +#include +#include +#include +#include #include +#include +#include #include #include +#include + +#include "drivers/intel/pmc_mux/conn/chip.h" + +extern struct chip_operations drivers_intel_pmc_mux_conn_ops; + +static bool is_port1(struct device *dev) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 1 + && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static void typec_orientation_fixup(void) +{ + /* + * TODO: This is an ugly hack, see if there's a better way to accomplish this same thing + * via fw_config + devicetree, i.e., change a register's value depending on fw_config + * probing. + */ + const struct device *pmc; + const struct device *mux; + const struct device *conn; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list->children) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return; + } + + /* + * Find port 1 underneath PMC.MUX; some variants may not have this defined, so it's okay + * to just silently return here. + */ + mux = pmc->link_list->children; + conn = dev_find_matching_device_on_bus(mux->link_list, is_port1); + if (!conn) + return; + + if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) + || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) + || fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { + struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; + + if (config) { + printk(BIOS_INFO, + "Configure Right Type-C port orientation for retimer\n"); + config->sbu_orientation = TYPEC_ORIENTATION_NORMAL; + } + } +} static void mainboard_init(struct device *dev) { mainboard_ec_init(); + typec_orientation_fixup(); + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ +} + +static void add_fw_config_oem_string(const struct fw_config *config, void *arg) +{ + struct smbios_type11 *t; + char buffer[64]; + + t = (struct smbios_type11 *)arg; + + snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name); + t->count = smbios_add_string(t->eos, buffer); +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + fw_config_for_each_found(add_fw_config_oem_string, t); } static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->get_smbios_strings = mainboard_smbios_strings; +} + +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) +{ + int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via SPI. I2C is only + * used on reworked prototypes on which the TPM is replaced with Dauntless under + * development, it will use long pulses by default, or use the interrupt line in + * a different way altogether. + */ + return; + } + + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (cr50_is_long_interrupt_pulse_enabled()) { + printk(BIOS_INFO, "Enabling S0i3.4\n"); + } else { + /* + * Disable S0i3.4, preventing the GPIO block from switching to + * slow clock. + */ + printk(BIOS_INFO, "Not enabling S0i3.4\n"); + cfg->LpmStateDisableMask |= LPM_S0i3_4; + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } } static void mainboard_chip_init(void *chip_info) @@ -34,8 +143,26 @@ static void mainboard_chip_init(void *chip_info) base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); - gpio_configure_pads_with_override(base_pads, base_num, - override_pads, override_num); + gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + /* + * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set + * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure + * the attached device is not mis-detected on resume from S0ix. + */ + if (gpio_get(GPP_A12)) { + const struct pad_config gpio_pedet_nvme[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1), + }; + gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme)); + printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n"); + } else { + const struct pad_config gpio_pedet_sata[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0), + }; + gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata)); + printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n"); + } } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index d35bbb5bea..67d3489b03 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -15,11 +11,10 @@ #include #include - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct ddr_memory_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, @@ -27,23 +22,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - /* Disable HDA device if no audio board is present. */ - if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) - mem_cfg->PchHdaEnable = 0; - - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); -} - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; - } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; + meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index 58e038eb87..adb60fedbe 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,11 +1,9 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include +#include #include #include @@ -26,3 +24,8 @@ int mainboard_smi_apmc(u8 apmc) MAINBOARD_EC_SMI_EVENTS); return 0; } + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index e12599420f..eb8e6ff355 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -2,19 +2,10 @@ ## ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/tigerlake/spd/lp4x/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +ifeq ($(SPD_SOURCE_PATH),) +SPD_SOURCE_PATH := src/soc/intel/tigerlake/spd +endif + +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SPD_SOURCE_PATH)/$(f)) + endif diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e0d3beaaa2..d74476af16 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -6,6 +6,7 @@ fw_config option USB4_GEN3 3 option USB3_PASSIVE 4 option USB3_NO_A 5 + option USB3_NO_C 6 end field THERMAL 4 7 end field AUDIO 8 10 @@ -13,6 +14,9 @@ fw_config option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 + option MAX98373_ALC5682I_I2S_UP4 4 + option MAX98360_ALC5682I_I2S 5 + option RT1011_ALC5682I_I2S 6 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 @@ -22,10 +26,37 @@ fw_config option LTE_ABSENT 0 option LTE_PRESENT 1 end + field KB_BL 14 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field NUMPAD 15 + option NUMPAD_ABSENT 0 + option NUMPAD_PRESENT 1 + end field DB_SD 16 19 option SD_ABSENT 0 option SD_GL9755S 1 option SD_RTS5261 2 + option SD_RTS5227S 3 + option SD_GL9750 4 + option SD_OZ711LV2LN 5 + end + field KB_LAYOUT 20 21 + option KB_LAYOUT_DEFAULT 0 + option KB_LAYOUT_1 1 + end + field BOOT_DEVICE_EMMC 22 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end + field BOOT_DEVICE_NVME 23 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_DEVICE_SATA 24 + option BOOT_SATA_DISABLED 0 + option BOOT_SATA_ENABLED 1 end end @@ -55,9 +86,6 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth @@ -81,7 +109,7 @@ chip soc/intel/tigerlake # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" - register "HybridStorageMode" = "1" + register "HybridStorageMode" = "0" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" @@ -97,10 +125,10 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[1]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA register "SataEnable" = "1" @@ -136,8 +164,8 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -148,6 +176,40 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Set the minimum assertion width + # PchPmSlpS3MinAssert: + # - 1: 60us + # - 2: 1ms + # - 3: 50ms + # - 4: 2s + register "PchPmSlpS3MinAssert" = "3" # 50ms + # PchPmSlpS4MinAssert: + # - 1 = 1s + # - 2 = 2s + # - 3 = 3s + # - 4 = 4s + register "PchPmSlpS4MinAssert" = "1" # 1s + # PchPmSlpSusMinAssert: + # - 1 = 0ms + # - 2 = 500ms + # - 3 = 1s + # - 4 = 4s + register "PchPmSlpSusMinAssert" = "3" # 1s + # PchPmSlpAMinAssert + # - 1 = 0ms + # - 2 = 4s + # - 3 = 98ms + # - 4 = 2s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -159,20 +221,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkSndwEnable[1]" = "0" # TCSS USB3 + register "UsbTcPortEn" = "0x3" register "TcssXhciEn" = "1" - register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" - register "IomTypeCPortPadCfg[2]" = "0x09000000" - register "IomTypeCPortPadCfg[3]" = "0x09000000" - register "IomTypeCPortPadCfg[4]" = "0x09000000" - register "IomTypeCPortPadCfg[5]" = "0x09000000" - register "IomTypeCPortPadCfg[6]" = "0x09000000" - register "IomTypeCPortPadCfg[7]" = "0x09000000" - - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "0" + register "TcssAuxOri" = "0" # DP port register "DdiPortAConfig" = "1" # eDP @@ -194,38 +245,39 @@ chip soc/intel/tigerlake register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" # Enable DPTF register "dptf_enable" = "1" - register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 60, - .tdp_pl4 = 105, - }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 38, .tdp_pl4 = 71, }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" register "Device4Enable" = "1" register "tcc_offset" = "10" # TCC of 90 + register "CnviBtAudioOffload" = "FORCE_ENABLE" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -280,91 +332,93 @@ chip soc/intel/tigerlake }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref igpu on end + device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(85, 90), - TEMP_PCT(80, 69), - TEMP_PCT(75, 56), - TEMP_PCT(70, 46), - TEMP_PCT(65, 36),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" - register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" - register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" - register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" - register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" ## Power Limits Control - # 10-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is fixed at 64W, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 60000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 15 to 60W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 60000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" # Fan options register "options.fan.fine_grained_control" = "1" @@ -373,81 +427,81 @@ chip soc/intel/tigerlake device generic 0 on end end end # DPTF 0x9A03 - device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 on end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B - - # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - - device pci 12.0 off end # SensorHUB 0xA0FC - device pci 12.6 off end # GSPI2 0x34FB - - device pci 13.0 off end # GSPI3 0xA0FD - - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 off end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - - device pci 17.0 on end # SATA 0xA0D3 - - device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 off end # UART2 0xA0C7 - - device pci 1c.0 on end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 off end # RP3 0xA0BA - device pci 1c.3 off end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # WWAN RP6 0xA0BD - device pci 1c.6 on end # RP7 0xA0BE - device pci 1c.7 on end # SD Card RP8 0xA0BF - - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - - device pci 1e.0 on end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + device generic 0 on end + end + end + device ref gna on end + device ref north_xhci on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + # MIPI camera devices are on I2C buses 2 and 3 + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN + end + end + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + register "is_external" = "1" + device generic 1 on + probe DB_SD SD_RTS5261 + end + end + end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -456,18 +510,18 @@ chip soc/intel/tigerlake register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 off end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682_SNDW + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + probe AUDIO MAX98360_ALC5682I_I2S + end end end diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index fde4017c6d..2030f31b8a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -264,6 +260,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F9, NONE), /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> NC */ PAD_NC(GPP_F12, NONE), /* F13 : GSXDOUT ==> NC */ @@ -310,7 +308,7 @@ static const struct pad_config gpio_table[] = { /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H11 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H11, NONE), /* H12 : M2_SKT2_CFG0 ==> NONE */ @@ -402,7 +400,9 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), @@ -424,9 +424,6 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index dad762affb..d0d1c2862a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -146,64 +146,58 @@ Scope (\_SB.PCI0.IPU0) Scope (\_SB.PCI0.I2C3) { + /* Reference counter to track power control by RCAM and VCM */ + Name (REFC, 0) PowerResource (RCPR, 0x00, 0x0000) { - Name (STA, Zero) + Name (STA, 0) Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { - If ((STA == Zero)) + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull SNRPWR_EN high */ + STXS(GPP_H14) + + If (REFC == 0) { - /* Enable IMG_CLK */ - MCON(3,1) /* Clock 3, 19.2MHz */ - - /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif - - /* Pull SNRPWR_EN high */ - STXS(GPP_H14) - /* Pull PWREN high */ STXS(GPP_H20) - Sleep(2) /* reset pulse width */ - - /* Pull RST high */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - STXS(GPP_F15) -#else - STXS(GPP_D4) -#endif - Sleep(1) /* t2 */ - - Store(1,STA) } + Sleep(2) /* reset pulse width */ + + REFC++ + + /* Pull RST high */ + STXS(GPP_F15) + + Sleep(1) /* t2 */ + + STA = 1 } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ + CTXS(GPP_F15) + + If (REFC == 1) { - /* Disable IMG_CLK */ - Sleep(1) /* t0+t1 */ - MCOF(3) /* Clock 3 */ - - /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif - /* Pull PWREN low */ CTXS(GPP_H20) - - /* Pull SNRPWR_EN low */ - CTXS(GPP_H14) - - Store(0,STA) } + REFC-- + + /* Pull SNRPWR_EN low */ + CTXS(GPP_H14) + + STA = 0 } Method (_STA, 0, NotSerialized) /* _STA: Status */ { @@ -247,7 +241,7 @@ Scope (\_SB.PCI0.I2C3) } }, ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) + Package (0x03) { Package (0x02) { @@ -261,6 +255,11 @@ Scope (\_SB.PCI0.I2C3) { VCM0 } + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 } } }) @@ -334,6 +333,35 @@ Scope (\_SB.PCI0.I2C3) }) } + PowerResource (VCPR, 0x00, 0x0000) + { + Name (STA, 0) + Method (_ON, 0, Serialized) /* VCPR_ON_: VCM Power On */ + { + If (REFC == 0) + { + /* Pull PWREN high */ + STXS(GPP_H20) + } + REFC++ + STA = 1 + } + Method (_OFF, 0, Serialized) /* VCPR_OFF: VCM Power Off */ + { + If (REFC == 1) + { + /* Pull PWREN low */ + CTXS(GPP_H20) + } + REFC-- + STA = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (VCM0) { Name (_HID, "PRP0001") /* _HID: Hardware ID */ @@ -356,21 +384,26 @@ Scope (\_SB.PCI0.I2C3) }) Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { - RCPR + VCPR }) Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { - RCPR + VCPR }) Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) + Package (0x02) { Package (0x02) { "compatible", "dongwoon,dw9768" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 } } }) @@ -406,7 +439,7 @@ Scope (\_SB.PCI0.I2C3) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, - Package (0x05) + Package (0x06) { Package (0x02) { @@ -432,6 +465,11 @@ Scope (\_SB.PCI0.I2C3) { "compatible", "atmel,24c1024" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 } } }) @@ -440,12 +478,12 @@ Scope (\_SB.PCI0.I2C3) Scope (\_SB.PCI0.I2C2) { + Name (STA, Zero) PowerResource (FCPR, 0x00, 0x0000) { - Name (STA, Zero) Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(2,1) /* Clock 2, 19.2MHz */ @@ -464,12 +502,12 @@ Scope (\_SB.PCI0.I2C2) STXS(GPP_D4) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -484,7 +522,7 @@ Scope (\_SB.PCI0.I2C2) /* Pull SNRPWR_EN low */ CTXS(GPP_D18) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -529,13 +567,18 @@ Scope (\_SB.PCI0.I2C2) } }, ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) + Package (0x02) { Package (0x02) { "clock-frequency", 0x0124F800 - } + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } } }) Name (PRT0, Package (0x04) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 2d04380e6f..1428ec8a32 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ @@ -38,7 +34,9 @@ /* EC can wake from S3 with lid, power button or mode change event */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h index 3c2999294c..4e2733eb50 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 44dcd5b3b5..4d5dc87cb9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ @@ -22,7 +18,10 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct ddr_memory_cfg *variant_memory_params(void); int variant_memory_sku(void); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index f9c544fb2b..dafeb3b3a6 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -1,14 +1,10 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include -static const struct lpddr4x_cfg baseboard_memcfg = { +static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { /* DQ CPU<>DRAM map */ .dq_map = { [0] = { @@ -60,7 +56,12 @@ static const struct lpddr4x_cfg baseboard_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &baseboard_lpddr4x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h b/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h similarity index 51% rename from src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h rename to src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h index d08b33bca2..b5fa8c5485 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H @@ -7,9 +7,9 @@ /* Memory configuration board straps */ /* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 #endif diff --git a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc new file mode 100644 index 0000000000..ed894fee62 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) Parts = EMPTY diff --git a/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2e3fcbc4b5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +EMPTY 0 (0000) diff --git a/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt new file mode 100644 index 0000000000..7f7204cf5f --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +EMPTY diff --git a/src/mainboard/google/hatch/variants/sushi/overridetree.cb b/src/mainboard/google/volteer/variants/boldar/overridetree.cb similarity index 54% rename from src/mainboard/google/hatch/variants/sushi/overridetree.cb rename to src/mainboard/google/volteer/variants/boldar/overridetree.cb index abbcaaa08c..32204c58e7 100644 --- a/src/mainboard/google/hatch/variants/sushi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/boldar/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/cannonlake +chip soc/intel/tigerlake device domain 0 on end diff --git a/src/mainboard/google/volteer/variants/copano/Makefile.inc b/src/mainboard/google/volteer/variants/copano/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/copano/gpio.c b/src/mainboard/google/volteer/variants/copano/gpio.c new file mode 100644 index 0000000000..d5498d0748 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/gpio.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/copano/memory.c b/src/mainboard/google/volteer/variants/copano/memory.c new file mode 100644 index 0000000000..7821157a58 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg copano_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &copano_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc new file mode 100644 index 0000000000..7b9a85e0d6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53D512M64D4NW-046 WT:F, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53D1G64D4NW-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNFBMBLPR-NEE diff --git a/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt new file mode 100644 index 0000000000..413301e52c --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53D512M64D4NW-046 WT:F 0 (0000) +H9HCNNNCRMBLPR-NEE 0 (0000) +MT53D1G64D4NW-046 WT:A 1 (0001) +H9HCNNNFBMBLPR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt new file mode 100644 index 0000000000..c1d262300c --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53D512M64D4NW-046 WT:F +H9HCNNNCRMBLPR-NEE +MT53D1G64D4NW-046 WT:A +H9HCNNNFBMBLPR-NEE diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f51b3af398 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb new file mode 100644 index 0000000000..d4e07460a2 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -0,0 +1,212 @@ +chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0000"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/delbin/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c new file mode 100644 index 0000000000..5571ee87ca --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_NC(GPP_A20, NONE), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h b/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h index 5839395456..b5fa8c5485 100644 --- a/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c new file mode 100644 index 0000000000..9d8ad405ce --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg delbin_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &delbin_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc new file mode 100644 index 0000000000..c0e2fffb6b --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt new file mode 100644 index 0000000000..b5bd3ef2b6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b99b811053 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 9b5ae62bba..5e9600b26f 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -1,5 +1,298 @@ chip soc/intel/tigerlake - device domain 0 on - end + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + #These settings improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "{ + .enable = 1, + .tx_bias = USB2_BIAS_28P15MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_56P3MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, + }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(57, 90), + TEMP_PCT(47, 80), + TEMP_PCT(40, 70), + TEMP_PCT(36, 60), + TEMP_PCT(34, 50), + TEMP_PCT(30, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 51000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 5200, 220, 2200, }, + [1] = { 80, 4900, 180, 1800, }, + [2] = { 70, 4600, 145, 1450, }, + [3] = { 60, 4200, 115, 1150, }, + [4] = { 50, 3800, 90, 900, }, + [5] = { 40, 3400, 55, 550, }, + [6] = { 30, 2900, 30, 300, }, + [7] = { 20, 2300, 15, 150, }, + [8] = { 10, 1600, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end + end end diff --git a/src/mainboard/google/volteer/variants/drobit/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c new file mode 100644 index 0000000000..8feadff3c0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : USB_C0_AUXP_DC ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E13 : USB_C0_AUXN_DC ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT# */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/memory.c b/src/mainboard/google/volteer/variants/drobit/memory.c new file mode 100644 index 0000000000..9d8ad405ce --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg delbin_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &delbin_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc new file mode 100644 index 0000000000..c0e2fffb6b --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt new file mode 100644 index 0000000000..b5bd3ef2b6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b99b811053 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb new file mode 100644 index 0000000000..96c109fbb5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | MISC | + #| I2C3 | Camera | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2701"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c new file mode 100644 index 0000000000..d2b08bc63e --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E23, 1, DEEP), + + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_CFG_GPI(GPP_F7, NONE, DEEP), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */ + PAD_CFG_GPI(GPP_F10, NONE, DEEP), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_CFG_GPI(GPP_H1, NONE, DEEP), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_CFG_GPI(GPP_H2, NONE, DEEP), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> NC */ + PAD_NC(GPP_E12, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/eldrid/include/variant/acpi/dptf.asl similarity index 100% rename from src/mainboard/google/volteer/variants/delbin/include/variant/acpi/dptf.asl rename to src/mainboard/google/volteer/variants/eldrid/include/variant/acpi/dptf.asl diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h new file mode 100644 index 0000000000..5839395456 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c new file mode 100644 index 0000000000..577734dbcf --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg eldrid_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &eldrid_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc new file mode 100644 index 0000000000..b966612076 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = H5AN8G6NDJR-XNC, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-2.hex # ID = 2(0b0010) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE, MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt new file mode 100644 index 0000000000..3e298dc618 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +DRAM Part Name ID to assign +H5AN8G6NDJR-XNC 0 (0000) +MT40A512M16TB-062E:J 1 (0001) +H5ANAG6NCMR-XNC 2 (0010) +K4A8G165WC-BCWE 0 (0000) +K4AAG165WA-BCWE 3 (0011) +MT40A1G16KD-062E:E 3 (0011) +H5ANAG6NCJR-XNC 4 (0100) diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt new file mode 100644 index 0000000000..dbe7ecb967 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt @@ -0,0 +1,7 @@ +H5AN8G6NDJR-XNC,0 +MT40A512M16TB-062E:J,1 +H5ANAG6NCMR-XNC,2 +K4A8G165WC-BCWE +K4AAG165WA-BCWE +MT40A1G16KD-062E:E +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb new file mode 100644 index 0000000000..08d013e941 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -0,0 +1,283 @@ +chip soc/intel/tigerlake + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + + register "tcc_offset" = "5" # TCC of 95 + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + + #Disable Type-A Port A1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + + #Disable M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + + #improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + + #lower camera driving + register "usb2_ports[4]" = "{ + .enable = 1, + .tx_bias = 0, + .tx_emp_enable = 0, + .pre_emp_bias = 0, + .pre_emp_bit = 0, + }" + + device domain 0 on + device ref dptf on + # DPTF Policy for Eldrid board + chip drivers/intel/dptf + + ## Disable Active Policy from baseboard + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 51000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "30" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end # PMC + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c new file mode 100644 index 0000000000..ecb3c1985f --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : EMMC_PE_WAKE_ODL*/ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : EMMC_PERST_L*/ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_NC(GPP_C5, DN_20K), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> WLAN_PERST_L*/ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> EMMC_CLKREQ_ODL*/ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B4 : CPU_GP3==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* H10 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h b/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h b/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c new file mode 100644 index 0000000000..32b7abca17 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg elemi_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &elemi_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc new file mode 100644 index 0000000000..0a9e3f90d3 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-9.hex # ID = 3(0b0011) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt new file mode 100644 index 0000000000..e85149b345 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +DRAM Part Name ID to assign +H5ANAG6NCMR-XNC 0 (0000) +MT40A1G16KD-062E:E 1 (0001) +K4AAG165WA-BCWE 1 (0001) +H5AN8G6NDJR-XNC 2 (0010) +MT40A512M16TB-062E:J 2 (0010) +K4A8G165WC-BCWE 2 (0010) +H5ANAG6NCJR-XNC 3 (0011) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b110e929ac --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt @@ -0,0 +1,7 @@ +H5ANAG6NCMR-XNC +MT40A1G16KD-062E:E +K4AAG165WA-BCWE +H5AN8G6NDJR-XNC +MT40A512M16TB-062E:J +K4A8G165WC-BCWE +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb new file mode 100644 index 0000000000..c30dce39b4 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -0,0 +1,243 @@ +chip soc/intel/tigerlake + + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + + # Enable EMMC PCIE 5 using clk 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 75, + .sda_hold = 36, + }, + + }, + }" + + device domain 0 on + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pcie_rp5 on end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end # PMC + end +end diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db5ec..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -2,4 +2,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 2a986882e6..378c150202 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -23,8 +23,20 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* A10 : I2S2_RXD ==> I2S1_RXD */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : DDSP_HPD3 ==> USB_C2_DP_HPD */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), + /* A16 : USB_OC3# ==> USB_C0_OC_OD# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> NC */ PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), /* A23 : I2S1_SCLK ==> HP_INT_L */ @@ -42,6 +54,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> I2C_SENSOR_SCL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* C1 : SMBDATA ==> FPMCU_BOOT1 */ PAD_CFG_GPO(GPP_C1, 0, DEEP), @@ -53,9 +75,17 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C11, NONE), /* C13 : UART1_TXD ==> NC */ PAD_NC(GPP_C13, NONE), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> TBT_LSX2_TXD */ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), /* D10 : ISH_SPI_CLK ==> TBT_LSX2_RXD */ @@ -64,6 +94,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ PAD_NC(GPP_D12, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -75,10 +107,14 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E5, NONE), /* E10 : SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* E12 : SPI1_MISO_IO1 ==> NC */ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> NC */ PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), /* E16 : ISH_GP7 ==> SD_PRSNT# */ PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> NC */ @@ -96,6 +132,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F11, NONE), /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> NC */ PAD_NC(GPP_F14, NONE), /* F15 : GSXSRESET# ==> NC */ @@ -109,6 +147,8 @@ static const struct pad_config gpio_table[] = { /* F19 : SRCCLKREQ6# ==> NC */ PAD_NC(GPP_F19, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H6 : I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C3_SCL */ @@ -125,6 +165,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H16, NONE), /* H17 : DDPB_CTRLDATA ==> NC */ PAD_NC(GPP_H17, NONE), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H23 : IMGCLKOUT4 ==> NC */ PAD_NC(GPP_H23, NONE), @@ -156,7 +198,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num) static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), @@ -184,6 +228,9 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000000..edbb681a4e --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &halvor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc index be3cfc8d35..d4c7d0c6ca 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = H9HKNNNCRMBVAR-NEH -SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G64D4SQ-046 WT:A +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HKNNNCRMBVAR-NEH +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G64D4SQ-046 WT:A diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c100..568ca73c3b 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -1,24 +1,17 @@ chip soc/intel/tigerlake - register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" # Type-A / Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A / Type-C Port 2 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 2 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT register "SaGv" = "SaGv_Disabled" device domain 0 on - device pci 15.0 on + # Baseboard does not have these on, so they must be enabled here. + device ref tbt_pcie_rp2 on end # TBT_PCIe2 + device ref tbt_dma1 on end # TBT DMA1 0x9A1D + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -37,7 +30,9 @@ chip soc/intel/tigerlake register "uid" = "0" register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" - device i2c 31 on end + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end end chip drivers/i2c/max98373 register "vmon_slot_no" = "2" @@ -45,14 +40,16 @@ chip soc/intel/tigerlake register "uid" = "1" register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" - device i2c 32 on end + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end end - end # I2C #0 0xA0E8 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -67,7 +64,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -78,8 +75,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -110,8 +107,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -120,14 +117,66 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" - register "sdmode_delay" = "5" - device generic 0 on end + end + device ref hda on end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port3 on end + end + end end - end # Intel HD audio 0xA0C8-A0CF + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc new file mode 100644 index 0000000000..b7e69440fd --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt new file mode 100644 index 0000000000..dc87e04ace --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:F 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt new file mode 100644 index 0000000000..d0273dc39b --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c new file mode 100644 index 0000000000..1d3d693e46 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NOT USED */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E15 : ISH_GP6 ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c new file mode 100644 index 0000000000..11bcf4ca89 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg lindar_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &lindar_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc new file mode 100644 index 0000000000..8c96e06187 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt new file mode 100644 index 0000000000..9bf0bd9af0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt new file mode 100644 index 0000000000..a226d2f741 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb new file mode 100644 index 0000000000..d3be955626 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -0,0 +1,253 @@ +chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # USB Port Config + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + + register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + # Baseboard has these on, so they must be disabled here. + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_dma0 off end + + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO RT1011_ALC5682I_I2S + end + end + chip drivers/i2c/rt1011 + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + register "name" = ""RTL"" + device i2c 38 on + probe AUDIO RT1011_ALC5682I_I2S + end + end + chip drivers/i2c/rt1011 + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + register "name" = ""RTR"" + device i2c 39 on + probe AUDIO RT1011_ALC5682I_I2S + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms + register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A22)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follows CC + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index cdffb60dd9..2498981654 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -155,7 +155,9 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), @@ -183,8 +185,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 5444c6fdd3..2c879e09b4 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -54,7 +54,12 @@ static const struct lpddr4x_cfg malefor_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &malefor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) { - return &malefor_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc index 4c95819cb9..8c96e06187 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index c84ed833c5..95dc3f7b45 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -2,23 +2,19 @@ chip soc/intel/tigerlake # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used register "SaGv" = "SaGv_Disabled" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -30,11 +26,12 @@ chip soc/intel/tigerlake }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 15.0 on + # Baseboard has these on, so they must be disabled here. + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_dma0 off end + + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -47,12 +44,12 @@ chip soc/intel/tigerlake register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -65,8 +62,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - end # I2C1 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -97,8 +94,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -107,14 +104,77 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HD audio + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index e49e2dccf5..79722d8391 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -20,17 +20,13 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ @@ -54,10 +50,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), - /* C3 : SML0CLK ==> USB4_SMB_SCL */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : SML0DATA ==> USB4_SMB_SDA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ PAD_NC(GPP_C5, DN_20K), /* C7 : SML1DATA ==> EN_USI_CHARGE */ @@ -147,7 +139,7 @@ static const struct pad_config override_gpio_table[] = { /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -197,9 +189,14 @@ const struct pad_config *variant_override_gpio_table(size_t *num) static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ @@ -218,6 +215,9 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 773e88561d..7d95658891 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -54,7 +54,12 @@ static const struct lpddr4x_cfg terrador_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &terrador_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) { - return &terrador_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc index fc2631cab7..3c8ea4876f 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index c1c386a621..039dc85c8d 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -10,17 +10,61 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" device domain 0 on - device pci 15.0 on + device ref dptf on + chip drivers/intel/dptf + ## Disable Active Policy + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 40000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -41,6 +85,7 @@ chip soc/intel/tigerlake register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end chip drivers/i2c/max98373 @@ -50,81 +95,156 @@ chip soc/intel/tigerlake register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end - end # I2C #0 0xA0E8 - device pci 15.1 on - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end - end + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR0 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "0" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C2 0xA0EA - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" - register "wake" = "GPE0_DW2_15" - register "probed" = "1" + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2700"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end - end # I2C5 0xA0C6 + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/todor/Makefile.inc b/src/mainboard/google/volteer/variants/todor/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c new file mode 100644 index 0000000000..03919641d6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/ec.h b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h new file mode 100644 index 0000000000..4a9a461191 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h new file mode 100644 index 0000000000..fe512d8c4a --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 + +#endif diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c new file mode 100644 index 0000000000..c8b4ab4e3c --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg todor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &todor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc new file mode 100644 index 0000000000..3c8ea4876f --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt new file mode 100644 index 0000000000..02e7443467 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) diff --git a/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b74da4a5f0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb new file mode 100644 index 0000000000..be1b250429 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -0,0 +1,160 @@ +chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + + register "SaGv" = "SaGv_Disabled" + + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Disable Active Policy + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 40000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2700"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/trondo/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/Makefile.inc index c9a128d72a..13269db5ec 100644 --- a/src/mainboard/google/volteer/variants/trondo/Makefile.inc +++ b/src/mainboard/google/volteer/variants/trondo/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = - bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc new file mode 100644 index 0000000000..f40fba6751 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..8d472df850 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt new file mode 100644 index 0000000000..5ddd52ebba --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index 0932b6484c..7169932ae4 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -1,11 +1,12 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + device domain 0 on - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -20,7 +21,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -31,8 +32,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -63,8 +64,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -73,6 +74,69 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB3_NO_C + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB3_NO_C + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c new file mode 100644 index 0000000000..5bf6fad108 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> PCH_FPMCU_BOOT1 */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> CAM_DET_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> CAM_SEN_EN */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl similarity index 51% rename from src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl rename to src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl index 66940633a4..418f2e04ba 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h new file mode 100644 index 0000000000..166c06ce08 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c new file mode 100644 index 0000000000..b611af5161 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg voema_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &voema_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc new file mode 100644 index 0000000000..7b69aa4504 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E, H9HCNNNFBMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53D1G64D4NW-046 WT:A diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt new file mode 100644 index 0000000000..840f71a47a --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) +H9HCNNNCRMBLPR-NEE 0 (0000) +H9HCNNNFBMBLPR-NEE 1 (0001) +MT53D1G64D4NW-046 WT:A 2 (0010) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt new file mode 100644 index 0000000000..c74fe433ba --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -0,0 +1,5 @@ +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E +H9HCNNNCRMBLPR-NEE +H9HCNNNFBMBLPR-NEE +MT53D1G64D4NW-046 WT:A diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb new file mode 100644 index 0000000000..86b71ee9a4 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -0,0 +1,184 @@ +chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 1 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 0 + + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + + # Disable WLAN PCIE 7 + register "PcieRpEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "0" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + # Disable SD Card PCIE 8 + register "PcieRpEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "0" + register "PcieRpHotPlug[7]" = "0" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + + device domain 0 on + device ref ipu on end # IPU + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + register "generic.stop_delay_ms" = "300" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port3 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 2b99e52029..0d230fd96c 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -30,7 +30,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST), /* B5 : ISH_I2C0_CVF_SDA */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* B6 : ISH_I2C0_CVF_SCL */ @@ -91,18 +91,18 @@ static const struct pad_config override_gpio_table[] = { /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, NONE), /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ @@ -125,7 +125,7 @@ static const struct pad_config override_gpio_table[] = { /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ @@ -154,7 +154,7 @@ static const struct pad_config override_gpio_table[] = { /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -164,7 +164,7 @@ static const struct pad_config override_gpio_table[] = { /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), + PAD_CFG_GPO(GPP_H20, 0, DEEP), /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ @@ -210,6 +210,9 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), @@ -231,8 +234,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc index c2abb9ef0d..37e4c227f5 100644 --- a/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL -SPD_SOURCES += spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 094476525f..f23ef76393 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,7 +1,68 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + + register "HybridStorageMode" = "1" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on - device pci 15.0 on + device ref ipu on end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -38,18 +99,24 @@ chip soc/intel/tigerlake end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 14 on end @@ -57,7 +124,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -68,8 +135,21 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -100,8 +180,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -110,8 +190,8 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -141,7 +221,14 @@ chip soc/intel/tigerlake end end end - device pci 1f.2 hidden + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -150,30 +237,118 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on - probe DB_USB USB4_GEN2 + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on probe DB_USB USB3_ACTIVE - probe DB_USB USB4_GEN3 probe DB_USB USB3_NO_A - end - end - chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU & HSL follow CC - device generic 1 on probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end end end end - end # PMC + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc index 13269db5ec..04af3aec1a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 2b99e52029..cfd9e8b1f6 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -19,9 +19,9 @@ static const struct pad_config override_gpio_table[] = { /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ @@ -29,6 +29,8 @@ static const struct pad_config override_gpio_table[] = { /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B5 : ISH_I2C0_CVF_SDA */ @@ -91,18 +93,18 @@ static const struct pad_config override_gpio_table[] = { /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ @@ -125,7 +127,7 @@ static const struct pad_config override_gpio_table[] = { /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ @@ -154,7 +156,7 @@ static const struct pad_config override_gpio_table[] = { /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -164,7 +166,7 @@ static const struct pad_config override_gpio_table[] = { /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), + PAD_CFG_GPO(GPP_H20, 0, DEEP), /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ @@ -210,6 +212,9 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), @@ -231,8 +236,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), @@ -243,6 +248,11 @@ static const struct pad_config early_gpio_table[] = { /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), + + /* The two signals used for I2C communication with Ti50 on the + * volteer2_ti50 variant. */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc index c2abb9ef0d..37e4c227f5 100644 --- a/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL -SPD_SOURCES += spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index c32b80e9ec..916777c0a3 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -1,6 +1,121 @@ chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 153, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + + register "HybridStorageMode" = "1" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on - device pci 15.0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}}" + device generic 0 on end + end + end + device ref ipu on end # IPU 0x9A19 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -37,18 +152,24 @@ chip soc/intel/tigerlake end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 14 on end @@ -56,7 +177,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -67,8 +188,26 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device i2c 50 off end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -99,8 +238,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -109,8 +248,8 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -140,7 +279,22 @@ chip soc/intel/tigerlake end end end - device pci 1f.2 hidden + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -149,17 +303,118 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end - end # PMC + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/variant.c b/src/mainboard/google/volteer/variants/volteer2/variant.c new file mode 100644 index 0000000000..057bb8ad65 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +extern struct chip_operations drivers_i2c_tpm_ops; + +static bool match_i2c_tpm(DEVTREE_CONST struct device *dev) +{ + return dev->chip_ops == &drivers_i2c_tpm_ops; +} + +/* + * This function runs only on the volteer_ti50 variant, which has the GSC on a + * reworked I2C bus. + */ +static void devtree_enable_i2c_tpm(void) +{ + struct device *spi_tpm = pcidev_path_on_root(PCH_DEVFN_GSPI0)->link_list->children; + struct device *i2c_tpm = dev_find_matching_device_on_bus( + pcidev_path_on_root(PCH_DEVFN_I2C1)->link_list, match_i2c_tpm); + if (!i2c_tpm || !spi_tpm) + return; + spi_tpm->enabled = 0; + i2c_tpm->enabled = 1; +} + +void variant_devtree_update(void) +{ + if (CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)) + devtree_enable_i2c_tpm(); +} diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index 13269db5ec..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -2,4 +2,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index a460ffff8f..d6df489f0d 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -18,10 +18,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ @@ -29,8 +25,8 @@ static const struct pad_config override_gpio_table[] = { /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC(TP18) */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B5 : ISH_I2C0_CVF_SDA */ @@ -58,20 +54,20 @@ static const struct pad_config override_gpio_table[] = { /* C0 : SMBCLK ==> EN_PP3300_WLAN */ PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ - PAD_CFG_GPO(GPP_C1, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), /* C3 : SML0CLK ==> USB4_SMB_SCL */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* C4 : SML0DATA ==> USB4_SMB_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C5 : SML0ALERT# ==> NC(TP93) */ + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ PAD_NC(GPP_C5, DN_20K), - /* C7 : SML1DATA ==> EN_USI_CHARGE */ + /* C7 : SML1DATA ==> EN_PP5000_PEN */ PAD_CFG_GPO(GPP_C7, 1, DEEP), /* C10 : UART0_RTS# ==> USI_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ @@ -87,6 +83,16 @@ static const struct pad_config override_gpio_table[] = { /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ @@ -107,7 +113,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_D17, 1, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ @@ -117,21 +123,19 @@ static const struct pad_config override_gpio_table[] = { /* E3 : CPU_GP0 ==> USI_REPORT_EN */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ PAD_CFG_GPO(GPP_E8, 0, DEEP), - /* E10 : SPI1_CS# ==> NC(TP94508) */ - PAD_NC(GPP_E10, NONE), /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E11, NONE, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* E13 : SPI1_MOSI_IO0 ==> NC(TP94507) */ - PAD_NC(GPP_E13, NONE), + /* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ - PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + PAD_CFG_GPO(GPP_E17, 1, DEEP), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), @@ -143,10 +147,16 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ @@ -164,9 +174,13 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), - /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), @@ -174,8 +188,14 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), @@ -219,9 +239,14 @@ const struct pad_config *variant_override_gpio_table(size_t *num) static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ @@ -240,8 +265,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c new file mode 100644 index 0000000000..40b108660d --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg voxel_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &voxel_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc index d18a906b34..f40fba6751 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc @@ -2,6 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR -SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0e38..82f0bfd09e 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,6 +1,75 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 + + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on - device pci 15.0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(98, 100),}}, + [1] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(64, 100), + TEMP_PCT(60, 90), + TEMP_PCT(56, 80), + TEMP_PCT(52, 70), + TEMP_PCT(47, 60), + TEMP_PCT(42, 50), + TEMP_PCT(35, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 51000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -32,12 +101,12 @@ chip soc/intel/tigerlake device i2c 32 on end end - end # I2C #0 0xA0E8 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -52,7 +121,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -63,8 +132,22 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -95,8 +178,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -105,8 +188,37 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.2 hidden + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -116,17 +228,80 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end - end # PMC + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 75b3e01345..88d6e97651 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO + select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select VGA_BIOS select BOARD_ROMSIZE_KB_16384 select DRIVERS_AMD_I2S_MACHINE_DEV @@ -19,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9324 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_AUDIO_CODEC select EC_GOOGLE_CHROMEEC_BOARDID @@ -32,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS - select PICASSO_CONSOLE_UART + select AMD_SOC_CONSOLE_UART select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_ASPM @@ -69,6 +71,9 @@ config VARIANT_DIR default "berknip" if BOARD_GOOGLE_BERKNIP default "vilboz" if BOARD_GOOGLE_VILBOZ default "woomax" if BOARD_GOOGLE_WOOMAX + default "dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "shuboz" if BOARD_GOOGLE_SHUBOZ + default "gumboz" if BOARD_GOOGLE_GUMBOZ config MAINBOARD_PART_NUMBER string @@ -79,6 +84,9 @@ config MAINBOARD_PART_NUMBER default "Berknip" if BOARD_GOOGLE_BERKNIP default "Vilboz" if BOARD_GOOGLE_VILBOZ default "Woomax" if BOARD_GOOGLE_WOOMAX + default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "Shuboz" if BOARD_GOOGLE_SHUBOZ + default "Gumboz" if BOARD_GOOGLE_GUMBOZ config DEVICETREE string @@ -93,10 +101,6 @@ config MAINBOARD_FAMILY string default "Google_Zork" -config MAX_CPUS - int - default 8 - config ONBOARD_VGA_IS_PRIMARY bool default y @@ -104,6 +108,7 @@ config ONBOARD_VGA_IS_PRIMARY config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH + select VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_VBNV_OFFSET hex @@ -127,32 +132,20 @@ config DRIVER_TPM_I2C_ADDR config PICASSO_FW_A_POSITION hex - default 0xFF031040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + default 0xFF012040 + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_A region. This is the start of the RW-A region + 64 bytes for the cbfs header. config PICASSO_FW_B_POSITION hex - default 0xFF3CF040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + default 0xFF312040 + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_B region. This is the start of the RW-A region + 64 bytes for the cbfs header. -config VARIANT_HAS_FW_CONFIG - bool - help - Honor FW_CONFIG in CBI. - -config VARIANT_BOARD_VER_FW_CONFIG_VALID - int - default 256 - depends on VARIANT_HAS_FW_CONFIG - help - Which board version did FW_CONFIG become valid in CBI. - config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS bool default y if BOARD_GOOGLE_TREMBYLE @@ -167,6 +160,34 @@ config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS longer has to support pre-v3 schematics, `default y` entry for it can be dropped. +config VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + bool + default y if BOARD_GOOGLE_TREMBYLE + default y if BOARD_GOOGLE_EZKINIL + default y if BOARD_GOOGLE_MORPHIUS + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_DALBOZ + default y if BOARD_GOOGLE_WOOMAX + default y if BOARD_GOOGLE_VILBOZ + default y if BOARD_GOOGLE_DIRINBOZ + default n + +config VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS + int + depends on VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + default 4 if BOARD_GOOGLE_TREMBYLE + default 3 if BOARD_GOOGLE_EZKINIL + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 3 if BOARD_GOOGLE_DALBOZ + default 1 if BOARD_GOOGLE_WOOMAX + default 2 if BOARD_GOOGLE_VILBOZ + default 2 if BOARD_GOOGLE_DIRINBOZ + default 256 + help + Minimum board version where the variant starts supporting + v3.6+ version of reference schematics. + config VARIANT_MIN_BOARD_ID_V3_SCHEMATICS int depends on VARIANT_SUPPORTS_PRE_V3_SCHEMATICS @@ -208,20 +229,43 @@ config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW Minimum board version where the variant starts supporting active low power enable for WiFi. -config VBOOT_STARTS_BEFORE_BOOTBLOCK - bool "PSP verstage" - default y if VBOOT +config VARIANT_HAS_FPMCU + bool + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_MORPHIUS + default n help - Firmware verification happens before the main processor is brought - online. + Select y if any SKU of the board has a fingerprint sensor -config VBOOT_STARTS_IN_BOOTBLOCK - bool "X86 verstage (in bootblock)" - depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE +config VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER + int + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 0 help - Firmware verification happens during the end of or right after the - bootblock. This implies that a static VBOOT2_WORK() buffer must be - allocated in memlayout. + Last board version that needs the extra delay for FPMCU init. + +config EFS_SPI_READ_MODE + int + default 0 if EM100 # Normal read mode + default 2 # Dual IO (1-1-2) + +config EFS_SPI_SPEED + int + default 3 if EM100 # 16.66 MHz + default 0 # 66.66 MHz + +config EFS_SPI_MICRON_FLAG + int + default 0 + +config CHROMEOS_WIFI_SAR + bool + default y if CHROMEOS + select DRIVERS_WIFI_GENERIC + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select GEO_SAR_ENABLE endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 801c1b7b39..6c6657cecd 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -27,3 +27,15 @@ config BOARD_GOOGLE_BERKNIP config BOARD_GOOGLE_WOOMAX bool "-> Woomax" select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_DIRINBOZ + bool "-> Dirinboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_SHUBOZ + bool "-> Shuboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_GUMBOZ + bool "-> Gumboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 88aef867de..96c97b68d3 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -9,11 +9,7 @@ ramstage-y += chromeos.c ramstage-y += ec.c ramstage-y += sku_id.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-y += verstage.c -else -verstage-y += chromeos.c -endif smm-y += smihandler.c diff --git a/src/mainboard/google/zork/acpi_tables.c b/src/mainboard/google/zork/acpi_tables.c new file mode 100644 index 0000000000..ab36f40a35 --- /dev/null +++ b/src/mainboard/google/zork/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index a7636de702..87e028573c 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -2,16 +2,15 @@ #include #include +#include void bootblock_mainboard_early_init(void) { size_t num_gpios; const struct soc_amd_gpio *gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - program_gpios(gpios, num_gpios); - } + gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); + program_gpios(gpios, num_gpios); variant_pcie_gpio_configure(); } diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 90cd2d7f90..be43e8a02d 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,37 +1,32 @@ -FLASH@0xFF000000 0x1000000 { - SI_BIOS@0x0 0x1000000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RW_MRC_CACHE@0x0 0x10000 - MRC_CACHE_HOLE@0x10000 0x11000 +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE(PRESERVE) 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 } - RW_SECTION_A@0x21000 0x39E000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x38DFC0 - RW_FWID_A@0x39DFC0 0x40 + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 } - RW_SECTION_B@0x3BF000 0x39E000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x38DFC0 - RW_FWID_B@0x39DFC0 0x40 + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_ELOG(PRESERVE)@0x75D000 0x4000 - RW_SHARED@0x761000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x765000 0x2000 - RW_NVRAM(PRESERVE)@0x767000 0x5000 - RW_UNUSED@0x76C000 0x14000 - SMMSTORE(PRESERVE)@0x780000 0x20000 - RW_LEGACY(CBFS)@0x7A0000 0x460000 - WP_RO@0xC00000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3FC000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7C0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x38B000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 08ea5cf1c7..a96d47c089 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -6,9 +6,9 @@ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c index d770d27040..f4f441c7a1 100644 --- a/src/mainboard/google/zork/ec.c +++ b/src/mainboard/google/zork/ec.c @@ -11,6 +11,7 @@ void mainboard_ec_init(void) .log_events = MAINBOARD_EC_LOG_EVENTS, .sci_events = MAINBOARD_EC_SCI_EVENTS, .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s3_device_events = MAINBOARD_EC_S3_DEVICE_EVENTS, .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index f3ef5c5a98..1de593ed49 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -6,16 +6,16 @@ #include #include #include -#include +#include #include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -28,6 +28,12 @@ #include #include +#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" +#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" +#define METHOD_MAINBOARD_INI "\\_SB.MINI" +#define METHOD_MAINBOARD_WAK "\\_SB.MWAK" +#define METHOD_MAINBOARD_PTS "\\_SB.MPTS" + /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and @@ -42,43 +48,31 @@ static uint8_t fch_apic_routing[0x80]; _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); -/* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - /* * This controls the device -> IRQ routing. - * The PIC values are limited to 0,1, 3 - 12, 14, 15. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 <- ec/google/chromeec/acpi/superio.asl + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + * 12: i8042 <- ec/google/chromeec/acpi/superio.asl */ static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; uint8_t apic_irq_num; } fch_pirq[] = { - { PIRQ_A, 6, 16 }, - { PIRQ_B, 6, 17 }, - { PIRQ_C, 14, 18 }, - { PIRQ_D, 15, 19 }, + { PIRQ_A, 6, PIRQ_NC }, + { PIRQ_B, 13, PIRQ_NC }, + { PIRQ_C, 14, PIRQ_NC }, + { PIRQ_D, 15, PIRQ_NC }, + { PIRQ_E, 15, PIRQ_NC }, + { PIRQ_F, 14, PIRQ_NC }, + { PIRQ_G, 13, PIRQ_NC }, + { PIRQ_H, 6, PIRQ_NC }, + { PIRQ_SCI, 9, 9 }, { PIRQ_EMMC, 5, 5 }, { PIRQ_GPIO, 7, 7 }, @@ -113,9 +107,6 @@ static void init_tables(void) static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } @@ -135,13 +126,13 @@ static void mainboard_configure_gpios(void) static void mainboard_devtree_update(void) { variant_audio_update(); + variant_bluetooth_update(); + variant_touchscreen_update(); variant_devtree_update(); } static void mainboard_init(void *chip_info) { - const struct sci_source *gpes; - size_t num; int boardid; mainboard_ec_init(); @@ -152,25 +143,58 @@ static void mainboard_init(void *chip_info) /* Update DUT configuration */ mainboard_devtree_update(); - - /* - * Some platforms use SCI not generated by a GPIO pin (event above 23). - * For these boards, gpe_configure_sci() is still needed, but all GPIO - * generated events (23-0) must be removed from gpe_table[]. - * For boards that only have GPIO generated events, table gpe_table[] - * must be removed, and get_gpe_table() should return NULL. - */ - gpes = variant_gpe_table(&num); - if (gpes != NULL) - gpe_configure_sci(gpes, num); } -void mainboard_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - variant_get_pcie_ddi_descriptors(pcie_descs, pcie_num, ddi_descs, ddi_num); + variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num); +} + +static void mainboard_write_blken(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0); + acpigen_soc_clear_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_blkdis(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0); + acpigen_soc_set_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_mini(void) +{ + acpigen_write_method(METHOD_MAINBOARD_INI, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mwak(void) +{ + acpigen_write_method(METHOD_MAINBOARD_WAK, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mpts(void) +{ + acpigen_write_method(METHOD_MAINBOARD_PTS, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE); + acpigen_pop_len(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + mainboard_write_blken(); + mainboard_write_blkdis(); + mainboard_write_mini(); + mainboard_write_mpts(); + mainboard_write_mwak(); } /************************************************* @@ -184,33 +208,13 @@ static void zork_enable(struct device *dev) pirq_setup(); dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; -static const struct soc_amd_gpio gpio_set_bl[] = { - PAD_GPO(GPIO_85, LOW), -}; - -static void reset_backlight_gpio(void *unused) -{ - printk(BIOS_DEBUG, "Reset backlight GPIO\n"); - /* Re-Enable backlight - GPIO 85 active low */ - /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ - program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ } static void mainboard_final(void *chip_info) { - struct global_nvs *gnvs; - - gnvs = acpi_get_gnvs(); - - reset_backlight_gpio(NULL); - - if (gnvs) { - gnvs->tmps = CTL_TDP_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - } + finalize_gpios(acpi_get_sleep_type()); } struct chip_operations mainboard_ops = { @@ -229,5 +233,3 @@ __weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) *size = 0; return NULL; } - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 12a3b64c20..1c26d45bca 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -33,5 +33,6 @@ int mainboard_smi_apmc(u8 apmc) if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + return 0; } diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index 7ae89df525..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B4 EF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex deleted file mode 100644 index 8d9fd4d9bf..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 EF F6 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex deleted file mode 100644 index af9ba32181..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 10 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 E7 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex deleted file mode 100644 index 56677fa37a..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 85 21 10 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 55 24 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index cc1ca7384b..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B3 E1 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex deleted file mode 100644 index 3b1a73e7b8..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 3C 41 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index 07342ab8fc..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 4C 24 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-template.spd.hex b/src/mainboard/google/zork/spd/DDR4-template.spd.hex deleted file mode 100644 index 6198f3daf1..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-template.spd.hex +++ /dev/null @@ -1,336 +0,0 @@ -# Generic DDR4 SPD template -# Fields that are not required should be set to zero -# CRC will be calculated when generating SPDs from this template, so no need -# to update here - -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization -01 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -00 - -# Connector to SDRAM Bit Mapping (DQ4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ8-11) -00 - -# Connector to SDRAM Bit Mapping (DQ12-15) -00 - -# Connector to SDRAM Bit Mapping (DQ16-19) -00 - -# Connector to SDRAM Bit Mapping (DQ20-23) -00 - -# Connector to SDRAM Bit Mapping (DQ24-27) -00 - -# Connector to SDRAM Bit Mapping (DQ28-31) -00 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -00 - -# Connector to SDRAM Bit Mapping (DQ36-39) -00 - -# Connector to SDRAM Bit Mapping (DQ40-43) -00 - -# Connector to SDRAM Bit Mapping (DQ44-47) -00 - -# Connector to SDRAM Bit Mapping (DQ48-51) -00 - -# Connector to SDRAM Bit Mapping (DQ52-55) -00 - -# Connector to SDRAM Bit Mapping (DQ56-59) -00 - -# Connector to SDRAM Bit Mapping (DQ60-63) -00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (blank) -00 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -00 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -00 - -# RC Extension, Module Nominal Height -00 - -# Module Maximum Thickness -00 - -# Reference Raw Card Used -00 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -00 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (blank) -00 - -# Module Manufacturer's ID Code, MSB (blank) -00 - -# Module Manufacturing Location (blank) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (blank) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (blank) -00 - -# DRAM Manufacturer's ID code, MSB (blank) -00 - -# DRAM Stepping (Undefined) -00 - -# Module Manufacturer's Specific Data (blank) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index e401fa6fdc..d6ae475b12 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -3,27 +3,22 @@ # This directory SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# TODO: Remove channel suffix when b:141434940 is fixed -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += empty # 0b0011 -APCB_SOURCES += empty # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATION)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/google/zork/spd/ddr4-spd-1.hex similarity index 62% rename from src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex rename to src/mainboard/google/zork/spd/ddr4-spd-1.hex index 49db2374f4..32d141f21f 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex +++ b/src/mainboard/google/zork/spd/ddr4-spd-1.hex @@ -1,27 +1,27 @@ -23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08 -00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20 -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31 -34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE -00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00 -01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-2.hex b/src/mainboard/google/zork/spd/ddr4-spd-2.hex new file mode 100644 index 0000000000..85b203599b --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-2.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-3.hex b/src/mainboard/google/zork/spd/ddr4-spd-3.hex new file mode 100644 index 0000000000..d2869eab1b --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-3.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-4.hex b/src/mainboard/google/zork/spd/ddr4-spd-4.hex new file mode 100644 index 0000000000..b6769928da --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-4.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 FC 3F 00 00 6D 6D 6D 11 00 6D F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-5.hex b/src/mainboard/google/zork/spd/ddr4-spd-5.hex new file mode 100644 index 0000000000..d72bf1ed05 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-5.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 A8 18 2B 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 B5 00 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-6.hex b/src/mainboard/google/zork/spd/ddr4-spd-6.hex new file mode 100644 index 0000000000..71cfff96d5 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-6.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-7.hex b/src/mainboard/google/zork/spd/ddr4-spd-7.hex new file mode 100644 index 0000000000..7f92cd8529 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-7.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-8.hex b/src/mainboard/google/zork/spd/ddr4-spd-8.hex new file mode 100644 index 0000000000..aca688e99d --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-8.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-9.hex b/src/mainboard/google/zork/spd/ddr4-spd-9.hex new file mode 100644 index 0000000000..1ce7c21d4c --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-empty.hex b/src/mainboard/google/zork/spd/ddr4-spd-empty.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt new file mode 100644 index 0000000000..21565c66b6 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -0,0 +1,16 @@ +H5AN8G6NDJR-XNC,ddr4-spd-1.hex +MT40A512M16TB-062E:J,ddr4-spd-1.hex +H5ANAG6NCMR-XNC,ddr4-spd-2.hex +HMA851S6CJR6N-VK,ddr4-spd-3.hex +K4A8G165WC-BCTD,ddr4-spd-3.hex +H5AN8G6NCJR-VKC,ddr4-spd-3.hex +MT40A1G16KNR-075:E,ddr4-spd-4.hex +K4AAG165WB-MCTD,ddr4-spd-5.hex +H5ANAG6NCMR-VKC,ddr4-spd-6.hex +K4A8G165WC-BCWE,ddr4-spd-1.hex +MT40A1G16KD-062E:E,ddr4-spd-7.hex +K4AAG165WA-BCWE,ddr4-spd-7.hex +H5AN8G6NCJR-XNC,ddr4-spd-1.hex +K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex diff --git a/src/mainboard/google/zork/spd/empty.spd.hex b/src/mainboard/google/zork/spd/empty.spd.hex deleted file mode 100644 index 0d22dd0cf0..0000000000 --- a/src/mainboard/google/zork/spd/empty.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -#Empty SPD - placeholder file -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex deleted file mode 100644 index 1c5e87f9d4..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx16) -02 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -87 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -2E - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (C0) -02 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -C0 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -E2 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (H5AN8G6NCJR-VKC ) -48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20 -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex deleted file mode 100644 index 144c8e3f08..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5AN8G6NDJR-XNC -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 -0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 -4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex deleted file mode 100644 index e75e4c12d9..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5ANAG6NCMR-VKC -23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 -36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex deleted file mode 100644 index 3cfb32cfc8..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5ANAG6NCMR-XNC -23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 -4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex deleted file mode 100644 index 7ad9466cf4..0000000000 --- a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx16) -02 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -87 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -2E - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (C0) -02 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -C0 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -E2 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (HMA851S6CJR6N-VK ) -48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex deleted file mode 100644 index ff166d6e75..0000000000 --- a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (DDP) -91 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx8) -01 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -FD - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -EE - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (ZZ0) -1F - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -7D - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -21 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (HMAA1GS6CMR6N-VK ) -48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex deleted file mode 100644 index 17778473af..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Micron MT40A1G16KD-062E:E -23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 -31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C -45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex deleted file mode 100644 index 988ea54b23..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Micron MT40A1G16KNR-075:E -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60 -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 -31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C -45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex deleted file mode 100644 index 67640fe849..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# MT40A512M16TB-062E:J -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 -0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 -32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex deleted file mode 100644 index e16d2f729b..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4A8G165WC-BCTD -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e -0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 -35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex deleted file mode 100644 index 4fb1561c6a..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4A8G165WC-BCWE -23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 -0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 -35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex deleted file mode 100644 index ede001a4d5..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4AAG165WB-MCTD -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B -34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index c9e3657f4b..2764a89b08 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -7,10 +7,8 @@ bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c verstage-y += gpio_baseboard_common.c verstage-y += helpers.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -endif verstage-y += tpm_tis.c romstage-y += gpio_baseboard_common.c @@ -44,11 +42,15 @@ endif #($(CONFIG_USE_OEM_BIN),y) # GPIO_NUMBER: FCH GPIO number # GPIO_IO_MUX: Value write to IOMUX to configure this GPIO # GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. +# Trembyle based boards select 1 or 2 channels based on AGPIO84 +# Dalboz based boards only support 1 channel ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) APCB_BOARD_ID_GPIO0 = 121 1 0 APCB_BOARD_ID_GPIO1 = 120 1 0 APCB_BOARD_ID_GPIO2 = 131 3 0 APCB_BOARD_ID_GPIO3 = 116 1 0 +APCB_POPULATE_2ND_CHANNEL = true else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y) APCB_BOARD_ID_GPIO0 = 132 1 0 APCB_BOARD_ID_GPIO1 = 90 1 0 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index e355b5b14a..0b64855dad 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -3,41 +3,34 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_REMOTE_POWER_ON" + # See table 5-34 ACPI 6.3 spec + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_ms" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" @@ -47,88 +40,108 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" - register "xhci0_force_gen1" = "0" + register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default - register "usb_2_port_0_tune_params" = "{ + register "usb_2_port_tune_params[0]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port1 Default - register "usb_2_port_1_tune_params" = "{ + register "usb_2_port_tune_params[1]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port2 Default - register "usb_2_port_2_tune_params" = "{ + register "usb_2_port_tune_params[2]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port3 Default - register "usb_2_port_3_tune_params" = "{ + register "usb_2_port_tune_params[3]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller1 Port0 Default - register "usb_2_port_4_tune_params" = "{ + register "usb_2_port_tune_params[4]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller1 Port1 Default - register "usb_2_port_5_tune_params" = "{ + register "usb_2_port_tune_params[5]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ @@ -177,6 +190,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end @@ -188,7 +210,12 @@ chip soc/amd/picasso device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 @@ -234,6 +261,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" device usb 2.5 on end end chip drivers/usb/acpi @@ -279,11 +307,11 @@ chip soc/amd/picasso device generic 0.0 on end end end # Audio - device pci 0.6 on end # HDA + device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Internal GPP Bridge 0 to Bus B - device pci 0.0 on end # AHCI + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI end device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge @@ -298,11 +326,14 @@ chip soc/amd/picasso register "name" = ""RT58"" register "uid" = "1" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" - register "property_count" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" device i2c 1a on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 283e7a07a4..4181b4ad81 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -3,41 +3,34 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_REMOTE_POWER_ON" + # See table 5-34 ACPI 6.3 spec + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_ms" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" @@ -47,84 +40,96 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" - register "xhci0_force_gen1" = "0" + register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default - register "usb_2_port_0_tune_params" = "{ + register "usb_2_port_tune_params[0]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port1 Default - register "usb_2_port_1_tune_params" = "{ + register "usb_2_port_tune_params[1]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port2 Default - register "usb_2_port_2_tune_params" = "{ + register "usb_2_port_tune_params[2]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller0 Port3 Default - register "usb_2_port_3_tune_params" = "{ + register "usb_2_port_tune_params[3]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x6, + .tx_vref_tune = 0x6, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller1 Port0 Default - register "usb_2_port_4_tune_params" = "{ + register "usb_2_port_tune_params[4]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" # Controller1 Port1 Default - register "usb_2_port_5_tune_params" = "{ + register "usb_2_port_tune_params[5]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, - .rx_vref_tune = 0x5, + .tx_vref_tune = 0x5, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" @@ -138,6 +143,14 @@ chip soc/amd/picasso .read_mode = SPI_READ_MODE_DUAL122, }" + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + # eSPI Configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, @@ -177,6 +190,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end @@ -188,7 +210,12 @@ chip soc/amd/picasso device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 @@ -262,6 +289,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.5 on end end end @@ -281,6 +309,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.1 on end end chip drivers/usb/acpi @@ -307,11 +336,11 @@ chip soc/amd/picasso device generic 0.0 on end end end # Audio - device pci 0.6 on end # HDA + device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Internal GPP Bridge 0 to Bus B - device pci 0.0 on end # AHCI + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI end device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge @@ -326,11 +355,14 @@ chip soc/amd/picasso register "name" = ""RT58"" register "uid" = "1" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" - register "property_count" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_29)" + register "property_count" = "2" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" device i2c 1a on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index b0037090c7..4be866d6bc 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -4,66 +4,64 @@ #include #include -void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); } -static const fsp_pcie_descriptor pcie_descriptors[] = { +static const fsp_dxio_descriptor dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = NVME_START_LANE, - .end_lane = NVME_END_LANE, + .start_logical_lane = 4, + .end_logical_lane = 5, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ2, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = WLAN_START_LANE, - .end_lane = WLAN_END_LANE, + .start_logical_lane = 0, + .end_logical_lane = 0, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = SD_START_LANE, - .end_lane = SD_END_LANE, + .start_logical_lane = 1, + .end_logical_lane = 1, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) { - *num = ARRAY_SIZE(pcie_descriptors); - return pcie_descriptors; + *num = ARRAY_SIZE(dxio_descriptors); + return dxio_descriptors; } const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index df42f6b87e..49d8ade7f4 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -5,12 +5,12 @@ #include #include -void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); } @@ -18,109 +18,106 @@ void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_de * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. * Those parts need to be configured as Type 2. */ -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 3, + .start_logical_lane = 0, + .end_logical_lane = 3, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, + .clk_req = CLK_REQ4, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = NVME_START_LANE, - .end_lane = NVME_END_LANE, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ4, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = WLAN_START_LANE, - .end_lane = WLAN_END_LANE, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = SD_START_LANE, - .end_lane = SD_END_LANE, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) { /* Type 2 or Type 1 fused like Type 2. */ if (soc_is_reduced_io_sku()) { - *num = ARRAY_SIZE(dali_pcie_descriptors); - return dali_pcie_descriptors; + *num = ARRAY_SIZE(dali_dxio_descriptors); + return dali_dxio_descriptors; } else { /* Type 1 */ - *num = ARRAY_SIZE(pco_pcie_descriptors); - return pco_pcie_descriptors; + *num = ARRAY_SIZE(pco_dxio_descriptors); + return pco_dxio_descriptors; } } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index a4e86487bd..0b658a4129 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -8,17 +8,17 @@ static const struct soc_amd_gpio early_gpio_table[] = { /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L (may be unused) */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 3ab3e10add..12d2890ce2 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -14,8 +14,10 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ @@ -28,18 +30,23 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), + /* GPIO_13 - GPIO_15: Not available */ /* USB_OC0_L - USB C0/A0 */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), /* USB_OC1_L - USB C1 */ PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), /* WIFI_DISABLE */ PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* EMMC_CMD */ PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), /* EC_FCH_SCI_ODL */ @@ -48,44 +55,63 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* EC_FCH_WAKE_L */ PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* GPIO_27: Configured in bootblock. */ + /* GPIO_28: Not available */ + /* GPIO_29: Handled in bootblock for wifi power/reset control. */ + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* TP */ - PAD_NC(GPIO_32), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, LOW), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ /* DMIC_SEL */ /* * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash * access will be very slow. */ PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET */ - PAD_GPO(GPIO_68, LOW), - /* RAM ID 3*/ + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* RAM ID 3 */ PAD_GPI(GPIO_69, PULL_NONE), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ /* EMMC_DATA4 */ PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), /* EMMC_DATA6 */ PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, HIGH), - /* UNUSED */ - PAD_GPO(GPIO_84, HIGH), - /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ - PAD_GPO(GPIO_85, HIGH), - /* RAM ID 2 */ - PAD_GPI(GPIO_86, PULL_NONE), + /* GPIO_77 - GPIO_83: Not available */ + /* HP_INT_ODL */ + PAD_GPI(GPIO_84, PULL_NONE), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* RAM ID 2 - Keep High */ + PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* EN_DEV_BEEP_L */ - PAD_GPO(GPIO_89, HIGH), + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), /* RAM ID 1 */ PAD_GPI(GPIO_90, PULL_NONE), - /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ /* EMMC_DATA0 */ PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), /* EMMC_DATA1 */ @@ -94,33 +120,46 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), /* EMMC_DATA3 */ PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), /* EMMC_DS */ PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ /* I2C2_SCL - USI/Touchpad */ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), /* I2C2_SDA - USI/Touchpad */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_128: Not available */ /* KBRST_L */ PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* GPIO_130 - GPIO_131: Not available */ /* RAM ID 0 */ PAD_GPI(GPIO_132, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* BIOS_FLASH_WP_ODL */ PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET */ - PAD_GPO(GPIO_140, HIGH), + /* USI_RESET_L */ + PAD_GPO(GPIO_140, LOW), /* USB_HUB_RST_L */ PAD_GPO(GPIO_141, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), /* BT_DISABLE */ PAD_GPO(GPIO_143, LOW), - /* - * USI_REPORT_EN - TODO: Driver resets this later. - * Do we want it high or low initially? - */ - PAD_GPO(GPIO_144, HIGH), + /* USI_REPORT_EN */ + PAD_GPO(GPIO_144, LOW), }; const __weak @@ -130,18 +169,6 @@ struct soc_amd_gpio *variant_base_gpio_table(size_t *size) return gpio_set_stage_ram; } -/* - * This function is still needed for boards that sets gevents above 23 - * that will generate SCI or SMI. Normally this function - * points to a table of gevents and what needs to be set. The code that - * calls it was modified so that when this function returns NULL then the - * caller does nothing. - */ -const __weak struct sci_source *variant_gpe_table(size_t *num) -{ - return NULL; -} - static void wifi_power_reset_configure_active_low_power(void) { /* @@ -252,7 +279,19 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ +} + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + *size = 0; + return NULL; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index c2d290ad91..a2ad51755f 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include +#include #include #include #include @@ -14,36 +16,41 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ - PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW), + PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), /* I2S_SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, HIGH), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_13, HIGH), /* BT_DISABLE */ PAD_GPO(GPIO_14, LOW), + /* GPIO_15: Not available */ /* USB_OC0_L - USB C0 + USB A0 */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), /* USB_OC1_L - USB C1 + USB A1 */ PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), /* WIFI_DISABLE */ PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* EMMC_CMD */ PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), /* EC_FCH_SCI_ODL */ @@ -52,40 +59,63 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* EC_FCH_WAKE_L */ PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L (unused) */ + PAD_NC(GPIO_27), + /* GPIO_28: Not available */ + /* GPIO_29: HP_INT_ODL */ + PAD_GPI(GPIO_29, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ /* DMIC SEL */ /* * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash * access will be very slow. */ PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET */ - PAD_GPO(GPIO_68, LOW), - /* FPMCU_BOOT0 - TODO: Check this */ + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* FPMCU_BOOT0 */ PAD_GPO(GPIO_69, LOW), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ /* EMMC_DATA4 */ PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), /* EMMC_DATA6 */ PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, HIGH), - /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ - PAD_GPO(GPIO_85, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* EN_DEV_BEEP_L */ - PAD_GPO(GPIO_89, HIGH), - /* Testpoint */ - PAD_NC(GPIO_90), - /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, LOW), + /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ /* EMMC_DATA0 */ PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), /* EMMC_DATA1 */ @@ -94,31 +124,54 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), /* EMMC_DATA3 */ PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), /* EMMC_DS */ PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ /* I2C2_SCL - USI/Touchpad */ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), /* I2C2_SDA - USI/Touchpad */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* GPIO_117 - GPIO_119: Not available */ + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* GPIO_122 - GPIO_128: Not available */ /* KBRST_L */ PAD_NF(GPIO_129, KBRST_L, PULL_NONE), /* EC_IN_RW_OD */ PAD_GPI(GPIO_130, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* BIOS_FLASH_WP_ODL */ PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET */ - PAD_GPO(GPIO_140, HIGH), + /* USI_RESET_L */ + PAD_GPO(GPIO_140, LOW), /* UART1_RXD - FPMCU */ PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), /* UART1_TXD - FPMCU */ PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), /* USI_REPORT_EN */ - /* TODO: Driver resets this later. Do we want it high or low initially? */ - PAD_GPO(GPIO_144, HIGH), + PAD_GPO(GPIO_144, LOW), }; const __weak @@ -128,26 +181,14 @@ struct soc_amd_gpio *variant_base_gpio_table(size_t *size) return gpio_set_stage_ram; } -/* - * This function is still needed for boards that sets gevents above 23 - * that will generate SCI or SMI. Normally this function - * points to a table of gevents and what needs to be set. The code that - * calls it was modified so that when this function returns NULL then the - * caller does nothing. - */ -const __weak struct sci_source *variant_gpe_table(size_t *num) -{ - return NULL; -} - static void wifi_power_reset_configure_active_low_power(void) { /* * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. * - Enable power to WiFi using EN_PWR_WIFI_L. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET_L. + * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) + * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET_L */ @@ -157,8 +198,6 @@ static void wifi_power_reset_configure_active_low_power(void) }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - mdelay(50); - gpio_set(GPIO_86, 1); } static void wifi_power_reset_configure_active_high_power(void) @@ -245,15 +284,79 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ + if (variant_has_fingerprint() && slp_typ != ACPI_S3) { + + if (fpmcu_needs_delay()) + mdelay(550); + + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + +static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + if (variant_has_fingerprint()) { + if (slp_typ == ACPI_S3) + return NULL; + + *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); + return gpio_fingerprint_bootblock_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); + return gpio_no_fingerprint_bootblock_table; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), }; +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), + + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) { + if (slp_typ == SLP_TYP_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 0a1cf5ccd1..00e7a033cb 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -40,50 +40,27 @@ enum { /* SD controller type */ FW_CONFIG_MASK_SD_CTRLR = 0x7, FW_CONFIG_SHIFT_SD_CTRLR = 20, - /* SPI speed value */ - FW_CONFIG_MASK_SPI_SPEED = 0xf, - FW_CONFIG_SHIFT_SPI_SPEED = 23, + /* SAR presence */ + FW_CONFIG_MASK_SAR = 0x7, + FW_CONFIG_SHIFT_SAR = 23, /* Fan information */ FW_CONFIG_MASK_FAN = 0x3, FW_CONFIG_SHIFT_FAN = 27, + /* WWAN presence */ + FW_CONFIG_MASK_WWAN = 0x1, + FW_CONFIG_SHIFT_WWAN = 29, }; -int variant_fw_config_valid(void) +static int get_fw_config(uint64_t *val) { - static uint32_t board_version; - const uint32_t bv_valid = CONFIG_VARIANT_BOARD_VER_FW_CONFIG_VALID; - - if (!CONFIG(VARIANT_HAS_FW_CONFIG)) - return 0; - - /* Fast path for non-zero board version. */ - if (board_version >= bv_valid) - return 1; - - if (google_chromeec_cbi_get_board_version(&board_version)) { - printk(BIOS_ERR, "Unable to obtain board version for FW_CONFIG\n"); - return 0; - } - - if (board_version >= bv_valid) - return 1; - - return 0; -} - -static int get_fw_config(uint32_t *val) -{ - static uint32_t known_value; - - if (!variant_fw_config_valid()) - return -1; + static uint64_t known_value; if (known_value) { *val = known_value; return 0; } - if (google_chromeec_cbi_get_fw_config(&known_value)) { + if (google_chromeec_cbi_get_fw_config(&known_value) != 0) { printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); return -1; } @@ -93,9 +70,9 @@ static int get_fw_config(uint32_t *val) return 0; } -static unsigned int extract_field(uint32_t mask, int shift) +static unsigned int extract_field(uint64_t mask, int shift) { - uint32_t fw_config; + uint64_t fw_config; /* On errors nothing is assumed to be set. */ if (get_fw_config(&fw_config)) @@ -104,6 +81,11 @@ static unsigned int extract_field(uint32_t mask, int shift) return (fw_config >> shift) & mask; } +int variant_gets_sar_config(void) +{ + return extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR); +} + int variant_has_emmc(void) { return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC); @@ -114,6 +96,11 @@ int variant_has_nvme(void) return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME); } +int variant_has_wwan(void) +{ + return !!extract_field(FW_CONFIG_MASK_WWAN, FW_CONFIG_SHIFT_WWAN); +} + bool variant_uses_v3_schematics(void) { uint32_t board_version; @@ -121,7 +108,7 @@ bool variant_uses_v3_schematics(void) if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_SCHEMATICS)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS) @@ -130,6 +117,31 @@ bool variant_uses_v3_schematics(void) return true; } +bool variant_uses_v3_6_schematics(void) +{ + uint32_t board_version; + + if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS)) + return true; + + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + return false; + + if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS) + return false; + + return true; +} + +/* + * pre-v3.6, CODEC_GPI was used as headphone jack interrupt. + * Starting v3.6 this was changed to a separate GPIO. + */ +bool variant_uses_codec_gpi(void) +{ + return !variant_uses_v3_6_schematics(); +} + bool variant_has_active_low_wifi_power(void) { uint32_t board_version; @@ -137,7 +149,7 @@ bool variant_has_active_low_wifi_power(void) if (!CONFIG(VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) @@ -145,3 +157,36 @@ bool variant_has_active_low_wifi_power(void) return true; } + +int variant_get_daughterboard_id(void) +{ + return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); +} + +bool variant_has_fingerprint(void) +{ + if (CONFIG(VARIANT_HAS_FPMCU)) + return true; + + return false; +} + +bool fpmcu_needs_delay(void) +{ + /* + * Older board versions need an extra delay here to finish resetting + * the FPMCU. The resistor value in the glitch prevention circuit was + * sized so that the FPMCU doesn't turn of for ~1 second. On newer + * boards, that's been updated to ~30ms, which allows the FPMCU's + * reset to be completed in the time between bootblock and finalize. + */ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER) + return true; + + return false; +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl index 8f5aa6ab5e..dec33ec5dd 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -21,10 +21,10 @@ Scope (\_TZ) /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,23 +50,23 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { /* Get temperature from EC in deci-kelvin */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) /* Critical temperature in deci-kelvin */ - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 /* Wait 1 second for EC to re-poll */ Sleep (1000) /* Re-read temperature from EC */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index ff42989286..46177fccfb 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -38,7 +38,8 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ @@ -46,6 +47,9 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* EC device events to enable and log in S3 */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS 0 + /* Enable LID switch */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN EC_WAKE_GPI diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h index 84433e0622..389f0e832a 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -7,31 +7,10 @@ #include #include -#define WLAN_CLKREQ CLK_REQ0 -#define SD_CLKREQ CLK_REQ1 - -#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) -#define NVME_START_LANE 4 -#define NVME_END_LANE 5 -#define WLAN_START_LANE 0 -#define WLAN_END_LANE 0 -#define SD_START_LANE 1 -#define SD_END_LANE 1 -#else -#define NVME_START_LANE 0 -#define NVME_END_LANE 1 -#define WLAN_START_LANE 4 -#define WLAN_END_LANE 4 -#define SD_START_LANE 5 -#define SD_END_LANE 5 -#endif - #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) #define EC_IN_RW_OD GPIO_130 -#define NVME_CLKREQ CLK_REQ4 #else #define EC_IN_RW_OD GPIO_11 -#define NVME_CLKREQ CLK_REQ2 #endif /* SPI Write protect */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 90e8b04212..ac600de255 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ @@ -10,7 +9,6 @@ #include #include "chip.h" -const struct sci_source *variant_gpe_table(size_t *num); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* * This function provides base GPIO configuration table. It is typically provided by @@ -25,46 +23,67 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); */ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); +/* This function provides GPIO init in bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ); + /* * This function provides GPIO table for the pads that need to be configured when entering * sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* Program any required GPIOs at the finalize phase */ +void finalize_gpios(int slp_typ); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ void variant_audio_update(void); +/* Update bluetooth configuration in devicetree during ramstage. */ +void variant_bluetooth_update(void); +/* Update touchscreen configuration in devicetree during ramstage. */ +void variant_touchscreen_update(void); /* Configure PCIe GPIOs as per variant sequencing requirements. */ void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and * overrideable by the variant. */ -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); /* Provide the descriptors for the associated baseboard for the variant. These functions * can be used for obtaining the baseboard's descriptors if the variant followed the * baseboard. */ -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num); +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num); const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); /* Retrieve attributes from FW_CONFIG in CBI. */ -/* Return 1 if FW_CONFIG expected to be valid, else 0. */ -int variant_fw_config_valid(void); +/* Return value of SAR config. */ +int variant_gets_sar_config(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_emmc(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_nvme(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_wwan(void); /* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ int boot_is_factory_unprovisioned(void); /* Return true if variant uses v3 version of reference schematics. */ bool variant_uses_v3_schematics(void); -/* Return true if variant has active low power enable fow WiFi. */ +/* Return true if variant uses v3.6 version of reference schematics. */ +bool variant_uses_v3_6_schematics(void); +/* Return true if variant uses CODEC_GPI pin for headphone jack interrupt. */ +bool variant_uses_codec_gpi(void); +/* Return true if variant has active low power enable for WiFi. */ bool variant_has_active_low_wifi_power(void); +/* Return value of daughterboard ID */ +int variant_get_daughterboard_id(void); +/* Return true if the board has a fingerprint sensor. */ +bool variant_has_fingerprint(void); +/* Return true if the board needs an extra fpmcu delay. */ +bool fpmcu_needs_delay(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 511d60d0b8..a9414b92e0 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -2,48 +2,261 @@ #include #include +#include +#include #include +#include +#include +#include #include #include +#include #include extern struct chip_operations drivers_amd_i2s_machine_dev_ops; +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_hid_ops; -void variant_audio_update(void) +static void update_hp_int_odl(void) { - const struct device *gpp_a_dev; - const struct device *acp_dev; - struct device *machine_dev = NULL; + static const struct device_path rt5682_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = LPC_DEVFN + }, + { + .type = DEVICE_PATH_PNP, + .pnp.port = 0xc09, + .pnp.device = 0x0 + }, + { + .type = DEVICE_PATH_GENERIC, + .generic.id = 0, + .generic.subid = 0 + }, + { + .type = DEVICE_PATH_I2C, + .i2c.device = 0x1a + } + }; + + const struct device *rt5682_dev; + struct drivers_i2c_generic_config *cfg; + struct acpi_gpio *gpio; + struct soc_amd_picasso_config *soc_cfg; + + if (!variant_uses_codec_gpi()) + return; + + rt5682_dev = find_dev_nested_path( + pci_root_bus(), rt5682_path, ARRAY_SIZE(rt5682_path)); + if (!rt5682_dev) { + printk(BIOS_ERR, "%s: Failed to find audio device\n", + __func__); + return; + } + + if (rt5682_dev->chip_ops != &drivers_i2c_generic_ops) { + printk(BIOS_ERR, "%s: Incorrect device found\n", __func__); + return; + } + + cfg = config_of(rt5682_dev); + gpio = &cfg->irq_gpio; + gpio->pins[0] = 62; + + /* + * When using CODEC_GPI for headphone jack interrupt, ACP_PME_EN and ACP_I2S_WAKE_EN + * need to be set to trigger I2S_WAKE event for headphone jack. + */ + soc_cfg = config_of_soc(); + soc_cfg->acp_i2s_wake_enable = 1; + soc_cfg->acp_pme_enable = 1; +} + +static void update_dmic_gpio(void) +{ + static const struct device_path acp_machine_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = AUDIO_DEVFN + }, + { + .type = DEVICE_PATH_GENERIC, + .generic.id = 0, + .generic.subid = 0 + } + }; + + const struct device *machine_dev; + struct drivers_amd_i2s_machine_dev_config *cfg; + struct acpi_gpio *gpio; if (variant_uses_v3_schematics()) return; - gpp_a_dev = pcidev_path_on_root(PCIE_GPP_A_DEVFN); - if (gpp_a_dev == NULL) + machine_dev = find_dev_nested_path( + pci_root_bus(), acp_machine_path, ARRAY_SIZE(acp_machine_path)); + if (!machine_dev) { + printk(BIOS_ERR, "%s: Failed to find ACP machine device\n", __func__); + return; + } + + if (machine_dev->chip_ops != &drivers_amd_i2s_machine_dev_ops) { + printk(BIOS_ERR, "%s: Incorrect device found\n", __func__); + return; + } + + cfg = config_of(machine_dev); + gpio = &cfg->dmic_select_gpio; + + if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) + gpio->pins[0] = GPIO_13; + else + gpio->pins[0] = GPIO_6; + +} + +void variant_audio_update(void) +{ + update_dmic_gpio(); + update_hp_int_odl(); +} + +/* + * Removes reset_gpio from usb device in device tree. + * + * debug_device_name is used for debug messaging only. + */ +static void remove_usb_device_reset_gpio(const struct device_path usb_path[], + size_t path_length, const char *debug_device_name) +{ + + const struct device *usb_dev; + struct drivers_usb_acpi_config *usb_cfg; + + usb_dev = find_dev_nested_path(pci_root_bus(), usb_path, path_length); + if (!usb_dev) { + printk(BIOS_ERR, "%s: Failed to find %s!", __func__, debug_device_name); + return; + } + /* config_of dies on failure, so a NULL check is not required */ + usb_cfg = config_of(usb_dev); + usb_cfg->reset_gpio.pin_count = 0; +} + +/* + * The bluetooth device may be on XHCI0 or XHCI1 depending on SOC. + * There's no harm in removing reset_gpio from both here. + */ +static void baseboard_trembyle_remove_bluetooth_reset_gpio(void) +{ + static const struct device_path xhci0_bt_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = XHCI0_DEVFN + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 0, + .usb.port_id = 0 + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 2, + .usb.port_id = 5 + } + }; + static const struct device_path xhci1_bt_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = XHCI1_DEVFN + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 0, + .usb.port_id = 0 + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 2, + .usb.port_id = 1 + } + }; + + remove_usb_device_reset_gpio(xhci0_bt_path, ARRAY_SIZE(xhci0_bt_path), + "XHCI0 Bluetoth USB Device"); + remove_usb_device_reset_gpio(xhci1_bt_path, ARRAY_SIZE(xhci1_bt_path), + "XHCI1 Bluetoth USB Device"); +} + +void variant_bluetooth_update(void) +{ + if (CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) || variant_uses_v3_schematics()) return; - acp_dev = pcidev_path_behind(gpp_a_dev->link_list, AUDIO_DEVFN); - if (acp_dev == NULL) + baseboard_trembyle_remove_bluetooth_reset_gpio(); +} + +void variant_touchscreen_update(void) +{ + DEVTREE_CONST struct device *mmio_dev = NULL; + struct device *child = NULL; + + /* + * By default, devicetree/overridetree entries for touchscreen device are configured to + * match v3.6 of reference schematics. So, if the board is using v3.6+ schematics, no + * additional work is required here. For maintaining support for pre-v3.6 boards, rest + * of the code in this function finds all entries that correspond to touchscreen + * devices (identified by reset_gpio being set to GPIO_140) and updates them as per + * pre-v3.6 version of schematics: + * 1. reset_gpio is marked as active high. + */ + if (variant_uses_v3_6_schematics()) return; - while ((machine_dev = dev_bus_each_child(acp_dev->link_list, machine_dev)) != NULL) { - struct drivers_amd_i2s_machine_dev_config *cfg; - struct acpi_gpio *gpio; + while (1) { + mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO); + if (mmio_dev == NULL) + break; + if (mmio_dev->path.mmio.addr == APU_I2C2_BASE) + break; + } - if (machine_dev->chip_info == NULL) + if (mmio_dev == NULL) + return; + + while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + struct drivers_i2c_generic_config *cfg; + + if (child->chip_ops == &drivers_i2c_generic_ops) { + cfg = config_of(child); + } else if (child->chip_ops == &drivers_i2c_hid_ops) { + struct drivers_i2c_hid_config *hid_cfg; + hid_cfg = config_of(child); + cfg = &hid_cfg->generic; + } else { + continue; + } + + /* If reset_gpio is set to GPIO_140, assume that this is touchscreen device. */ + if (cfg->reset_gpio.pins[0] != GPIO_140) continue; - if (machine_dev->chip_ops != &drivers_amd_i2s_machine_dev_ops) - continue; - - cfg = machine_dev->chip_info; - gpio = &cfg->dmic_select_gpio; - - if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) - gpio->pins[0] = GPIO_13; - else - gpio->pins[0] = GPIO_6; - - break; + cfg->reset_gpio.active_low = 0; + cfg->enable_gpio.pin_count = 0; + cfg->enable_gpio.pins[0] = 0; } } diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc index 57e7136ddc..51d19fe9ba 100644 --- a/src/mainboard/google/zork/variants/berknip/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index 2a50d74b8b..ae2d02a48d 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -8,18 +8,48 @@ #include static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio berknip_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -31,14 +61,17 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { *size = ARRAY_SIZE(berknip_bid1_gpio_set_stage_ram); return berknip_bid1_gpio_set_stage_ram; + } else if (board_version <= 2) { + *size = ARRAY_SIZE(berknip_bid2_gpio_set_stage_ram); + return berknip_bid2_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(berknip_gpio_set_stage_ram); + return berknip_gpio_set_stage_ram; } diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index ead39cb8bd..4745b45c60 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -6,27 +6,77 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # System config index - register "system_config" = "3" + register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "25000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "90" - register "telemetry_vddcr_vdd_slope" = "62451" #mA + register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "27301" #mA + register "telemetry_vddcr_soc_slope_mA" = "29788" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + # USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, .rise_time_ns = 3, .fall_time_ns = 2, + .data_hold_time_ns = 400, }" # Enable I2C3 for H1 400kHz @@ -37,6 +87,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -54,7 +110,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -65,9 +121,14 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -75,7 +136,9 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -83,9 +146,11 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" @@ -99,7 +164,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index f53e66294d..1f871a983b 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -1,26 +1,13 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = samsung-K4A8G165WC-BCTD_x2 # 0b0000 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b0001 -# b/149596178: We can't use dual channel channel until the PSP supports missing -# channels. -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0101 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0110 -APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-8.hex # ID = 1(0b0001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt new file mode 100644 index 0000000000..2522cdb3de --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt @@ -0,0 +1,9 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCTD 0 (0000) +MT40A512M16TB-062E:J 2 (0010) +H5AN8G6NDJR-XNC 3 (0011) +K4A8G165WC-BCWE 5 (0101) +MT40A1G16KD-062E:E 6 (0110) +H5ANAG6NCMR-XNC 7 (0111) +K4AAG165WA-BCWE 8 (1000) +K4AAG165WA-BCTD 1 (0001) diff --git a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt new file mode 100644 index 0000000000..1e5ee8a961 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCTD, 0 +MT40A512M16TB-062E:J, 2 +H5AN8G6NDJR-XNC, 3 +K4A8G165WC-BCWE, 5 +MT40A1G16KD-062E:E, 6 +H5ANAG6NCMR-XNC, 7 +K4AAG165WA-BCWE, 8 +K4AAG165WA-BCTD diff --git a/src/mainboard/google/zork/variants/berknip/variant.c b/src/mainboard/google/zork/variants/berknip/variant.c new file mode 100644 index 0000000000..092ff260b3 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; +} diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index a4813e90fb..2b46938e9b 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -12,18 +12,30 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC /* USB_OC2_L - USB A0 & A1 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* TP */ + PAD_NC(GPIO_32), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), /* Unused */ - PAD_GPI(GPIO_143, PULL_DOWN), + PAD_NC(GPIO_143), }; static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC + /* TP */ + PAD_NC(GPIO_32), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -35,7 +47,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 98a93eda0c..d047211f30 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -9,17 +9,17 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_slope_mA" = "30231" register "telemetry_vddcr_vdd_offset" = "0-1" - register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_slope_mA" = "22644" register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad @@ -48,9 +48,12 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -58,7 +61,7 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -66,9 +69,9 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -78,10 +81,13 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end @@ -97,7 +103,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc index 7baf8be205..e8ed39da29 100644 --- a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc @@ -1,25 +1,9 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 -APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010 -APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = HMA851S6CJR6N-VK +SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-5.hex # ID = 3(0b0011) Parts = K4AAG165WB-MCTD +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE diff --git a/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..f70d7f34d4 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +HMA851S6CJR6N-VK 0 (0000) +H5ANAG6NCMR-VKC 1 (0001) +K4A8G165WC-BCTD 2 (0010) +K4AAG165WB-MCTD 3 (0011) +K4A8G165WC-BCWE 4 (0100) diff --git a/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..5a104d7bf1 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt @@ -0,0 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +HMA851S6CJR6N-VK, 0 +H5ANAG6NCMR-VKC, 1 +K4A8G165WC-BCTD, 2 +K4AAG165WB-MCTD, 3 +K4A8G165WC-BCWE, 4 diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c index ceef2895a0..21aaec829a 100644 --- a/src/mainboard/google/zork/variants/dalboz/variant.c +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -10,6 +10,8 @@ #include #define EC_PNP_ID 0x0c09 +#define DALBOZ_DB_USBC 0x0 +#define DALBOZ_DB_HDMI 0x1 /* Look for an EC device of type PNP with id 0x0c09 */ static bool match_ec_dev(DEVTREE_CONST struct device *dev) @@ -104,34 +106,38 @@ static void update_audio_configuration(void) cfg->remote_bus = 5; } -static int sku_has_emmc(void) -{ - uint32_t board_sku = sku_id(); - - /* Factory flow requires all OS boot media to be enabled. */ - if (boot_is_factory_unprovisioned()) - return 1; - - /* FIXME: This needs to be fw_config controlled. */ - /* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */ - if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN) - return 1; - - return 0; -} - void variant_devtree_update(void) { + uint32_t board_version; struct soc_amd_picasso_config *cfg; cfg = config_of_soc(); - if (sku_has_emmc()) { - if (sku_id() == 0x5A800003) - /* rev0 boards have issues with HS400 */ - cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + /* + * If CBI board version cannot be read, assume this is an older revision + * of hardware. + */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (variant_has_emmc() || boot_is_factory_unprovisioned()) { + if (board_version <= 2) { + /* + * rev0 and rev1 boards have issues with HS400 + * + * There is a tuning fix with ES which shows promise + * for some boards, and a HW fix with stitching vias. + * There were also concerns that these boards did not + * have good margins for certain skus. + * + * But these original boards have none of these fixes. + * So we keep the speed low here, with the intent that + * other variants implement these corrections. + */ + cfg->emmc_config.timing = SD_EMMC_EMMC_HS200; + } } else { - cfg->sd_emmc_config = SD_EMMC_DISABLE; + cfg->emmc_config.timing = SD_EMMC_DISABLE; } update_audio_configuration(); @@ -179,19 +185,20 @@ static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { } }; -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - uint32_t board_sku = sku_id(); + uint32_t daughterboard_id = variant_get_daughterboard_id(); - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); - /* SKU 1, A, and D DB have HDMI, as well as unknown */ - /* FIXME: this needs to be fw_config controlled. */ - if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001) - || (board_sku == CROS_SKU_UNKNOWN)) { + /* + * Get daughterboard id from FW_CONFIG and configure descriptors accordingly. + * For unprovisioned boards use DB_HDMI as default. + */ + if ((daughterboard_id == DALBOZ_DB_HDMI) || boot_is_factory_unprovisioned()) { *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } else { diff --git a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc new file mode 100644 index 0000000000..51d19fe9ba --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c new file mode 100644 index 0000000000..7f9582c9b6 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), + /* TP */ + PAD_NC(GPIO_32), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h similarity index 58% rename from util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h index 189cafea4c..9e61a440cf 100644 --- a/util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h similarity index 58% rename from src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h index 189cafea4c..dfaeec3ae1 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h similarity index 58% rename from src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h index 189cafea4c..2af647973d 100644 --- a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb new file mode 100644 index 0000000000..3032984551 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "1640" + register "sustained_power_limit_mW" = "4800" + + register "telemetry_vddcr_vdd_slope_mA" = "42465" + register "telemetry_vddcr_vdd_offset" = "69" + register "telemetry_vddcr_soc_slope_mA" = "42667" + register "telemetry_vddcr_soc_offset" = "167" + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc new file mode 100644 index 0000000000..6d8a906c98 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-2.hex # ID = 6(0b0110) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 7(0b0111) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-8.hex # ID = 9(0b1001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..d6d5d09194 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt @@ -0,0 +1,10 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCTD 2 (0010) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +H5ANAG6NCMR-XNC 6 (0110) +MT40A512M16TB-062E:J 7 (0111) +MT40A1G16KD-062E:E 8 (1000) +K4AAG165WA-BCTD 9 (1001) +K4AAG165WA-BCWE 10 (1010) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..5a6541f8a4 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -0,0 +1,18 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCTD, 2 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +H5ANAG6NCMR-XNC, 6 +MT40A512M16TB-062E:J, 7 +MT40A1G16KD-062E:E, 8 +K4AAG165WA-BCTD, 9 +K4AAG165WA-BCWE, 10 +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/dirinboz/variant.c b/src/mainboard/google/zork/variants/dirinboz/variant.c new file mode 100644 index 0000000000..ff57f503a5 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/variant.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index d8c8edd1c0..f86d926e2e 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -8,38 +8,64 @@ #include static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { - /* FPMCU_RST_L Change NC */ - PAD_GPI(GPIO_11, PULL_UP), + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* FPMCU_BOOT0 Change NC */ - PAD_GPI(GPIO_69, PULL_UP), + PAD_NC(GPIO_69), /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ - PAD_GPI(GPIO_86, PULL_UP), + PAD_NC(GPIO_86), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { - /* FPMCU_RST_L Change NC */ - PAD_GPI(GPIO_11, PULL_UP), + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* FPMCU_BOOT0 Change NC */ - PAD_GPI(GPIO_69, PULL_UP), + PAD_NC(GPIO_69), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -51,7 +77,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index a4cdac6c4b..b7fee3949f 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -9,20 +9,50 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62413" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration - register "xhci0_force_gen1" = "1" + register "usb3_port_force_gen1" = "{ + .ports.xhci0_port0 = 1, + .ports.xhci0_port1 = 1, + .ports.xhci0_port2 = 1, + .ports.xhci0_port3 = 1, + }" + + #USB 2.0 strength + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ @@ -39,6 +69,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -56,7 +92,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -67,19 +103,31 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.probed" = "1" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "10" + register "generic.stop_delay_ms" = "300" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc index cd912726c4..10dea1cd35 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -1,25 +1,9 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x2 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 -APCB_SOURCES += micron-MT40A1G16KNR-075-E_x2 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCTD_x2 # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-3.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCTD diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt new file mode 100644 index 0000000000..7e54cc1b08 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +H5AN8G6NCJR-VKC 0 (0000) +MT40A512M16TB-062E:J 2 (0010) +MT40A1G16KD-062E:E 3 (0011) +K4A8G165WC-BCTD 4 (0100) diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt new file mode 100644 index 0000000000..b4b16015fb --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +H5AN8G6NCJR-VKC,0 +MT40A512M16TB-062E:J,2 +MT40A1G16KD-062E:E,3 +K4A8G165WC-BCTD,4 diff --git a/src/mainboard/google/zork/variants/ezkinil/variant.c b/src/mainboard/google/zork/variants/ezkinil/variant.c index d7cf5a8803..f76ab62035 100644 --- a/src/mainboard/google/zork/variants/ezkinil/variant.c +++ b/src/mainboard/google/zork/variants/ezkinil/variant.c @@ -5,30 +5,15 @@ #include #include -static int sku_has_emmc(void) -{ - uint32_t board_sku = sku_id(); - - /* Factory flow requires all OS boot media to be enabled. */ - if (boot_is_factory_unprovisioned()) - return 1; - - if ((board_sku == 0x5A020000) || - (board_sku == 0x5A020001) || (board_sku == 0x5A020002) || - (board_sku == 0x5A020005) || (board_sku == 0x5A020006) || - (board_sku == 0x5A020009) || (board_sku == 0x5A02000A) || - (board_sku == 0x5A02000D) || (board_sku == 0x5A02000E)) - return 1; - - return 0; -} - void variant_devtree_update(void) { struct soc_amd_picasso_config *cfg; cfg = config_of_soc(); - if (!sku_has_emmc()) - cfg->sd_emmc_config = SD_EMMC_DISABLE; + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; } diff --git a/src/mainboard/google/zork/variants/gumboz/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/Makefile.inc new file mode 100644 index 0000000000..51d19fe9ba --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c new file mode 100644 index 0000000000..aac25bb353 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h similarity index 58% rename from src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/gumboz/include/variant/ec.h index 189cafea4c..9e61a440cf 100644 --- a/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb new file mode 100644 index 0000000000..a9dbc10495 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" + + register "telemetry_vddcr_vdd_slope_mA" = "42465" + register "telemetry_vddcr_vdd_offset" = "69" + register "telemetry_vddcr_soc_slope_mA" = "42667" + register "telemetry_vddcr_soc_offset" = "167" + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc new file mode 100644 index 0000000000..6d8a906c98 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-2.hex # ID = 6(0b0110) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 7(0b0111) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-8.hex # ID = 9(0b1001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..d6d5d09194 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -0,0 +1,10 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCTD 2 (0010) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +H5ANAG6NCMR-XNC 6 (0110) +MT40A512M16TB-062E:J 7 (0111) +MT40A1G16KD-062E:E 8 (1000) +K4AAG165WA-BCTD 9 (1001) +K4AAG165WA-BCWE 10 (1010) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..e5cd7e2998 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -0,0 +1,19 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +# Gumboz shares the same DRAM IDs as Dirinboz since two variants use the same PCB. +K4A8G165WC-BCTD, 2 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +H5ANAG6NCMR-XNC, 6 +MT40A512M16TB-062E:J, 7 +MT40A1G16KD-062E:E, 8 +K4AAG165WA-BCTD, 9 +K4AAG165WA-BCWE, 10 +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/gumboz/variant.c b/src/mainboard/google/zork/variants/gumboz/variant.c new file mode 100644 index 0000000000..ff57f503a5 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/variant.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc index 57e7136ddc..51d19fe9ba 100644 --- a/src/mainboard/google/zork/variants/morphius/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 4cb98a3481..9b36e3747e 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -11,32 +11,53 @@ static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* DMIC_AD_EN */ PAD_GPO(GPIO_84, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = { + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -48,7 +69,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { @@ -57,6 +78,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) } else if (board_version <= 2) { *size = ARRAY_SIZE(morphius_bid2_gpio_set_stage_ram); return morphius_bid2_gpio_set_stage_ram; + } else if (board_version <= 3) { + *size = ARRAY_SIZE(morphius_bid3_gpio_set_stage_ram); + return morphius_bid3_gpio_set_stage_ram; } *size = 0; diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index e177507e22..3564d542cd 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -4,3 +4,18 @@ /* Enable PS/2 Mouse */ #define SIO_EC_ENABLE_PS2M + +/* Enable DPTC support */ +#define EC_ENABLE_AMD_DPTC_SUPPORT + +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#undef MAINBOARD_EC_S3_DEVICE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) +/* Enable trackpoint S3 wakeups */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS \ + (EC_DEVICE_EVENT_MASK(EC_DEVICE_EVENT_TRACKPAD)) diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index eaabd588cf..bee59e6a1f 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -9,19 +9,45 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcr_vdd_slope" = "78709" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62641" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29035" #mA + register "telemetry_vddcr_soc_slope_mA" = "28333" register "telemetry_vddcr_soc_offset" = "0" + # Set STAPM confiuration for tablet mode + register "dptc_enable" = "1" + register "slow_ppt_limit_tablet_mode_mW" = "20000" + register "fast_ppt_limit_tablet_mode_mW" = "24000" + register "sustained_power_limit_tablet_mode_mW" = "12000" + register "thermctl_limit_tablet_mode_degreeC" = "70" + # End : OPN Performance Configuration + register "usb3_port_force_gen1" = "{ + .ports.xhci0_port1 = 1, /* Left USB3A port 1 */ + .ports.xhci0_port2 = 1, /* Left USB3A port 2 */ + }" + + # USB 2.0 strength + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xd, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -37,6 +63,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -54,19 +86,24 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end chip drivers/i2c/hid - register "generic.hid" = ""GTCH7375L"" - register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" @@ -92,7 +129,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 080d468e91..805ede4975 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -1,26 +1,14 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = samsung-K4AAG165WA-BCWE_x2 # 0b0000 -APCB_SOURCES += empty # 0b0001 -# b/149596178: We can't use dual channel channel until the PSP supports missing -# channels. -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0010 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111 -APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 6(0b0110) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 7(0b0111) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-2.hex # ID = 8(0b1000) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = K4A8G165WC-BCWE diff --git a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt new file mode 100644 index 0000000000..b061000337 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt @@ -0,0 +1,10 @@ +DRAM Part Name ID to assign +MT40A512M16TB-062E:J 2 (0010) +MT40A1G16KD-062E:E 3 (0011) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +MT40A512M16TB-062E:J 6 (0110) +K4AAG165WA-BCWE 7 (0111) +H5ANAG6NCMR-XNC 8 (1000) +K4A8G165WC-BCWE 9 (1001) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt new file mode 100644 index 0000000000..87bbb36613 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -0,0 +1,18 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +MT40A512M16TB-062E:J, 2 +MT40A1G16KD-062E:E, 3 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +MT40A512M16TB-062E:J, 6 +K4AAG165WA-BCWE, 7 +H5ANAG6NCMR-XNC, 8 +K4A8G165WC-BCWE, 9 +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/morphius/variant.c b/src/mainboard/google/zork/variants/morphius/variant.c new file mode 100644 index 0000000000..092ff260b3 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; +} diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc new file mode 100644 index 0000000000..e5ec76de14 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c new file mode 100644 index 0000000000..0fd867e8d4 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio bid_gpio_set_stage_ram[] = { + /* AGPIO_5 - NC */ + PAD_NC(GPIO_5), + /* EGPIO141 - NC */ + PAD_NC(GPIO_141), + /* EGPIO144 - NC (etk5515 not used) */ + PAD_NC(GPIO_144), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(bid_gpio_set_stage_ram); + return bid_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb new file mode 100644 index 0000000000..e3462ca89a --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + end # device +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc new file mode 100644 index 0000000000..87b5aa9797 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..8019b2e2f6 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) +H5AN8G6NCJR-XNC 1 (0001) +MT40A1G16KD-062E:E 2 (0010) +K4AAG165WA-BCWE 3 (0011) diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..1faa641dea --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +MT40A512M16TB-062E:J, 0 +H5AN8G6NCJR-XNC, 1 +MT40A1G16KD-062E:E, 2 +K4AAG165WA-BCWE, 3 diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c new file mode 100644 index 0000000000..8a84a75f2f --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/Makefile.inc index 0b6bc4b349..57e7136ddc 100644 --- a/src/mainboard/google/zork/variants/trembyle/Makefile.inc +++ b/src/mainboard/google/zork/variants/trembyle/Makefile.inc @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index ce7e5dd5c6..4d73ea0122 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -11,32 +11,44 @@ static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* DMIC_AD_EN */ PAD_GPO(GPIO_84, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -48,7 +60,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 2) { diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 4cd53eea45..de38ab7887 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -9,19 +9,23 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + # USB OC pin mapping: existing trembyle boards are based on old schematics version + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1 + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -54,7 +58,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -65,9 +69,14 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -75,7 +84,7 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -88,7 +97,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc new file mode 100644 index 0000000000..6508c26b28 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC +SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC diff --git a/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt new file mode 100644 index 0000000000..20232a3378 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +H5AN8G6NCJR-VKC 0 (0000) +H5ANAG6NCMR-VKC 1 (0001) diff --git a/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt new file mode 100644 index 0000000000..7316ee04a0 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +H5AN8G6NCJR-VKC, 0 +H5ANAG6NCMR-VKC, 1 diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index dc1e4117f9..af38c8828d 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c new file mode 100644 index 0000000000..c6ef161647 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* TP */ + PAD_NC(GPIO_32), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { + /* P sensor INT */ + PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_RST_L */ + PAD_GPO(GPIO_89, HIGH), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram); + return vilboz_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 49d21d569a..f484e9a713 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -10,14 +10,22 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" # mW - register "fast_ppt_limit" = "9000" # mW - register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "2500" # second - register "sustained_power_limit" = "4800" # mW + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "1400" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration + register "telemetry_vddcr_vdd_slope_mA" = "26939" + register "telemetry_vddcr_vdd_offset" = "125" + register "telemetry_vddcr_soc_slope_mA" = "20001" + register "telemetry_vddcr_soc_offset" = "168" + + # USB OC pin mapping + register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -28,11 +36,17 @@ chip soc/amd/picasso # I2C3 for H1 register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 110, + .fall_time_ns = 5, .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -86,14 +100,48 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.reset_delay_ms" = "120" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_delay_ms" = "160" + register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -105,11 +153,58 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on end + end end end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index c9a91083d8..c7890d0e1a 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -1,26 +1,12 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# TODO: Remove channel suffix when b:141434940 is fixed -# Alternatively, generated APCBs stored at -# CONFIG_APCB_BLOB_DIR/APCB_{NAME}.bin can be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0010 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0100 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b0101 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 5(0b0101) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..8afd9563ad --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCWE 2 (0010) +H5AN8G6NDJR-XNC 3 (0011) +MT40A512M16TB-062E:J 4 (0100) +K4AAG165WA-BCWE 5 (0101) +MT40A1G16KD-062E:E 6 (0110) +H5ANAG6NDMR-XNC 7 (0111) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..2b8d6df374 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCWE, 2 +H5AN8G6NDJR-XNC, 3 +MT40A512M16TB-062E:J, 4 +K4AAG165WA-BCWE, 5 +MT40A1G16KD-062E:E, 6 +H5ANAG6NDMR-XNC, 7 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 5573837f9d..3816aac203 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -2,6 +2,8 @@ #include #include +#include +#include static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP @@ -21,13 +23,70 @@ static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { } }; -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *soc_cfg; + soc_cfg = config_of_soc(); + + /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ + if (variant_has_wwan()) + soc_cfg->acp_i2s_use_external_48mhz_osc = 1; +} + +/* ++----------+------+--------+--------+------+--+---------+--+---------+ +| |Vilboz|Vilboz14|Vilboz14|Vilboz|NA|Vilboz360|NA|Vilboz360| +| |WiFi |WiFi |LTE |LTE | |WiFi | |LTE | ++----------+------+--------+--------+------+--+---------+--+---------+ +|SAR[26] |0 |0 |0 |0 |0 |0 |0 |0 | +|SAR[25] |0 |0 |0 |0 |1 |1 |1 |1 | +|SAR[24] |0 |0 |1 |1 |0 |0 |1 |1 | +|SAR[23] |0 |1 |0 |1 |0 |1 |0 |1 | ++----------+------+--------+--------+------+--+---------+--+---------+ +|SAR_config|0 |1 |2 |3 |4 |5 |6 |7 | ++----------+------+--------+--------+------+--+---------+--+---------+ +*/ + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + int sar_config; + + sar_config = variant_gets_sar_config(); + + switch (sar_config) { + case 1: + filename = "wifi_sar-vilboz-0.hex"; + break; + case 3: + /* + TODO: Set default first. It will be replaced after the + new table is generated. + */ + filename = "wifi_sar_defaults.hex"; + break; + case 5: + filename = "wifi_sar-vilboz-1.hex"; + break; + case 7: + /* + TODO: Set default first. It will be replaced after the + new table is generated. + */ + filename = "wifi_sar_defaults.hex"; + break; + } + + return filename; +} diff --git a/src/mainboard/google/zork/variants/woomax/Makefile.inc b/src/mainboard/google/zork/variants/woomax/Makefile.inc index 9dc5159c53..57e7136ddc 100644 --- a/src/mainboard/google/zork/variants/woomax/Makefile.inc +++ b/src/mainboard/google/zork/variants/woomax/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c new file mode 100644 index 0000000000..329e7dddb3 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_NC(GPIO_4), + /* GPIO_5 NC */ + PAD_NC(GPIO_5), + /* GPIO_6 NC */ + PAD_NC(GPIO_6), + /* GPIO_69 NC */ + PAD_NC(GPIO_69), + /* RAM_ID_4 */ + PAD_NC(GPIO_84), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), + /* GPIO_141 NC */ + PAD_NC(GPIO_141), + /* GPIO_143 NC */ + PAD_NC(GPIO_143), +}; + +static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_NC(GPIO_4), + /* GPIO_5 NC */ + PAD_NC(GPIO_5), + /* GPIO_6 NC */ + PAD_NC(GPIO_6), + /* GPIO_69 NC */ + PAD_NC(GPIO_69), + /* RAM_ID_4 */ + PAD_NC(GPIO_84), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), + /* GPIO_141 NC */ + PAD_NC(GPIO_141), + /* GPIO_143 NC */ + PAD_NC(GPIO_143), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* If board version cannot be read, assume it is board_version 0. */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 0; + + if (board_version == 0) { + *size = ARRAY_SIZE(woomax_bid0_gpio_set_stage_ram); + return woomax_bid0_gpio_set_stage_ram; + } + *size = ARRAY_SIZE(woomax_gpio_set_stage_ram); + return woomax_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 077e983f85..15d6ee8476 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -10,18 +10,45 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "101070" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "24560" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping + register "usb_port_overcurrent_pin[2]" = "USB_OC_NONE" # NC # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ @@ -33,16 +60,54 @@ chip soc/amd/picasso # Enable I2C3 for H1 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 37, /* 1.26v to 0 */ + .rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 34, /* 1.26v to 0 */ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + device usb 3.2 off end + end end # domain - device mmio 0xfedc4000 on end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc new file mode 100644 index 0000000000..91ef5e5bae --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 2(0b0010) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 5(0b0101) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 6(0b0110) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 7(0b0111) +SPD_SOURCES += ddr4-spd-1.hex # ID = 8(0b1000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 11(0b1011) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt new file mode 100644 index 0000000000..c0583f495a --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) +H5AN8G6NCJR-XNC 1 (0001) +MT40A512M16TB-062E:J 8 (1000) +H5AN8G6NCJR-XNC 9 (1001) +MT40A1G16KD-062E:E 10 (1010) +K4AAG165WA-BCWE 11 (1011) diff --git a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt new file mode 100644 index 0000000000..65988e95da --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +MT40A512M16TB-062E:J, 0 +H5AN8G6NCJR-XNC, 1 +MT40A512M16TB-062E:J, 8 +H5AN8G6NCJR-XNC, 9 +MT40A1G16KD-062E:E, 10 +K4AAG165WA-BCWE, 11 diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index 24b54c9ef9..59677a7360 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout index e26a347b0e..3edda3b7dc 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -4,94 +4,67 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused -400 3 h 0 psu_fan_lvl -#403 5 r 0 unused +395 4 e 6 debug_level +400 3 h 0 psu_fan_lvl # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 10 r 0 unused +421 1 e 9 sata_mode # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 7bd312803e..fbff203d68 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -8,12 +8,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig new file mode 100644 index 0000000000..545a67bae9 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig @@ -0,0 +1,50 @@ +if BOARD_HP_FOLIO_9480M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + # The board has a 16MB flash, but the end of the flash needs + # to be reserved, so we use 12MB as default + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/folio_9480m" + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook Folio 9480m" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +config EC_HP_KBC1126_GPE + hex + default 0x6 + +endif diff --git a/src/mainboard/hp/folio_9480m/Kconfig.name b/src/mainboard/hp/folio_9480m/Kconfig.name new file mode 100644 index 0000000000..67c671d4c2 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_FOLIO_9480M + bool "EliteBook Folio 9480m" diff --git a/src/mainboard/hp/folio_9480m/Makefile.inc b/src/mainboard/hp/folio_9480m/Makefile.inc new file mode 100644 index 0000000000..ebe01aea99 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/hp/folio_9480m/acpi/ec.asl similarity index 54% rename from src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl rename to src/mainboard/hp/folio_9480m/acpi/ec.asl index 66940633a4..baa17a4181 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ b/src/mainboard/hp/folio_9480m/acpi/ec.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl new file mode 100644 index 0000000000..8023ae826c --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/folio_9480m/acpi/superio.asl b/src/mainboard/hp/folio_9480m/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c new file mode 100644 index 0000000000..c7fd96e0e5 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi_tables.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/folio_9480m/board_info.txt b/src/mainboard/hp/folio_9480m/board_info.txt new file mode 100644 index 0000000000..fdd0d60142 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926 +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/hp/folio_9480m/data.vbt b/src/mainboard/hp/folio_9480m/data.vbt new file mode 100644 index 0000000000..1a62a07a93 Binary files /dev/null and b/src/mainboard/hp/folio_9480m/data.vbt differ diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb new file mode 100644 index 0000000000..a56a48b1ee --- /dev/null +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -0,0 +1,81 @@ +chip northbridge/intel/haswell + register "dq_pins_interleaved" = "true" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" + register "usb_xhci_on_resume" = "true" + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x22da inherit + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "xhci_default" = "1" + register "sata_port1_gen3_dtle" = "0x6" + # SATA(1), M.2(3) + register "sata_port_map" = "0xa" + device pci 13.0 off end # Intel Smart Sound DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1322, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl new file mode 100644 index 0000000000..b5343726ff --- /dev/null +++ b/src/mainboard/hp/folio_9480m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/hp/folio_9480m/gma-mainboard.ads b/src/mainboard/hp/folio_9480m/gma-mainboard.ads new file mode 100644 index 0000000000..85e9ded77b --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DP1/HDMI1: DisplayPorts on board and dock + HDMI1, + DP2, -- DP2: VGA ports on board and dock + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9480m/gpio.c b/src/mainboard/hp/folio_9480m/gpio.c new file mode 100644 index 0000000000..cb32f4f733 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = LP_GPIO_OUT_HIGH, + [4] = LP_GPIO_OUT_HIGH, + [5] = LP_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = LP_GPIO_OUT_HIGH, + [10] = LP_GPIO_OUT_HIGH, + [11] = LP_GPIO_OUT_HIGH, + [12] = LP_GPIO_NATIVE, + [13] = LP_GPIO_OUT_HIGH, + [14] = LP_GPIO_OUT_HIGH, + [15] = LP_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_OUT_HIGH, + [23] = LP_GPIO_OUT_HIGH, + [24] = LP_GPIO_OUT_HIGH, + [25] = LP_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_HIGH, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = LP_GPIO_OUT_HIGH, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = LP_GPIO_OUT_HIGH, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = LP_GPIO_OUT_HIGH, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_HIGH, + [65] = LP_GPIO_OUT_LOW, + [66] = LP_GPIO_OUT_HIGH, + [67] = LP_GPIO_OUT_HIGH, + [68] = LP_GPIO_OUT_HIGH, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = LP_GPIO_OUT_HIGH, + [87] = LP_GPIO_OUT_HIGH, + [88] = LP_GPIO_OUT_HIGH, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = LP_GPIO_OUT_HIGH, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c new file mode 100644 index 0000000000..9ee6de01a8 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c22db, /* Subsystem ID */ + 57, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c22db), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* The following is from the OEM firmware */ + 0x02050007, 0x0204c200, 0x02050063, 0x02044800, + 0x02050066, 0x02040809, 0x02050015, 0x02048842, + 0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd, + 0x02050065, 0x02042000, 0x0205001c, 0x0204c900, + 0x02050018, 0x02043788, 0x02050008, 0x02048210, + 0x02050068, 0x02043022, 0x02050006, 0x02040800, + 0x02050061, 0x02040403, 0x02050061, 0x02040403, + 0x0205005f, 0x02040800, 0x02050060, 0x02040800, + 0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4, + 0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8, + 0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad, + 0x02050036, 0x0204cbd2, 0x02050037, 0x02041605, + 0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f, + 0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54, + 0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000, + 0x02050030, 0x02041f5c, 0x02050031, 0x02040111, + 0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9, + 0x0205002f, 0x02040000, 0x02050042, 0x0204c66e, + 0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad, + 0x02050044, 0x0204ccdd, 0x02050045, 0x02041549, + 0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79, + 0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54, + 0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000, + 0x0205003f, 0x02041f4d, 0x02050040, 0x02040129, + 0x02050041, 0x02041f51, 0x02050049, 0x02041f61, + 0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4, + 0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad, + 0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98, + 0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e, + 0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54, + 0x02050053, 0x02040b73, 0x0205003d, 0x02040000, + 0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a, + 0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0, + 0x0205002f, 0x02040000, 0x02050058, 0x0204c17a, + 0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad, + 0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e, + 0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899, + 0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54, + 0x0205005e, 0x02041444, 0x0205003d, 0x02040000, + 0x02050055, 0x02041fd8, 0x02050056, 0x02040045, + 0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2, + 0x02050026, 0x02042828, 0x02050029, 0x02040250, + 0x02050004, 0x0204c09e, 0x0205000e, 0x02045001, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c new file mode 100644 index 0000000000..7eeb7bd747 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* dock */ + { 1, USB_OC_PIN_SKIP }, /* left */ + { 1, USB_OC_PIN_SKIP }, /* right */ + { 0, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index dd4c42b968..1fb15968c1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -7,8 +7,7 @@ #include #include -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -41,10 +40,9 @@ static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { {0xff, 0xffffffff} }; -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +static const CODEC_TBL_LIST CodecTableList[] = { + {0x10ec0272, (CODEC_ENTRY *)&Parmer_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} }; #define FAN_INPUT_INTERNAL_DIODE 0 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 95f2c93004..b6cdc867ae 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -183,15 +183,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) * data from the table. Otherwise, it will use its default conservative settings */ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END + PSO_END }; void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3aad89c15e..a3553c0dc7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout index 87858cb0a9..1f3fc0a38a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout +++ b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout @@ -1,42 +1,42 @@ entries -#start-bit length config config-ID name +#start-bit length config config-ID name # RTC_BOOT_BYTE (coreboot hardcoded) -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter # southbridge/amd/agesa/hudson should use this but it doesn't -400 1 e 1 power_on_after_fail +400 1 e 1 power_on_after_fail # The only option that is actually used -412 4 e 6 debug_level +412 4 e 6 debug_level # southbridge/amd/agesa/hudson should use this but it doesn't -444 1 e 1 nmi +444 1 e 1 nmi -984 16 h 0 check_sum +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 4cd6a31844..da03899e09 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -5,9 +5,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index c620be253e..e4c60d15c9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -8,20 +8,30 @@ #include u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F + 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F }; u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 }; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) @@ -73,20 +83,20 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + for (byte = 0x0; byte < sizeof(picr_data); byte++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data); byte++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 2409348115..812c630b13 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -11,6 +11,8 @@ config BOARD_HP_SNB_IVB_LAPTOPS select SERIRQ_CONTINUOUS_MODE select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 if BOARD_HP_SNB_IVB_LAPTOPS @@ -20,22 +22,26 @@ config MAINBOARD_DIR config VARIANT_DIR string + default "2560p" if BOARD_HP_2560P default "2570p" if BOARD_HP_2570P default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M + default "probook_6360b" if BOARD_HP_PROBOOK_6360B default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 config MAINBOARD_PART_NUMBER string + default "EliteBook 2560p" if BOARD_HP_2560P default "EliteBook 2570p" if BOARD_HP_2570P default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M + default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 config OVERRIDE_DEVICETREE @@ -54,12 +60,14 @@ config VGA_BIOS_ID config USBDEBUG_HCD_INDEX int + default 1 if BOARD_HP_2560P default 2 if BOARD_HP_2570P default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M + default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this endif diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c01555fd13..85f95b27bf 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -1,5 +1,17 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_HP_2560P + bool "EliteBook 2560p" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_HP_2570P bool "EliteBook 2570p" @@ -30,8 +42,6 @@ config BOARD_HP_8460P select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_LPC47N217 @@ -66,21 +76,33 @@ config BOARD_HP_FOLIO_9470M select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_C216 +config BOARD_HP_PROBOOK_6360B + bool "ProBook 6360b" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_4096 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + config BOARD_HP_REVOLVE_810_G1 bool "EliteBook Revolve 810 G1" select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c index 8999b7297c..20a67f70b2 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c +++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 858dc4e69e..f7a9390101 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -4,97 +4,70 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused - -440 8 h 0 volume +432 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 4c291a8bd1..c1e80c858b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" @@ -17,12 +17,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x02880288" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end @@ -47,7 +44,11 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # HD Audio controller device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt new file mode 100644 index 0000000000..a3e8a7be06 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt new file mode 100644 index 0000000000..ee23b34f79 Binary files /dev/null and b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c new file mode 100644 index 0000000000..29e9e0f827 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* back bottom USB port, USB debug */ + { 1, 1, 0 }, /* back upper USB port */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* webcam */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 1, 0, 3 }, + { 1, 0, 3 }, /* smartcard */ + { 1, 1, 4 }, /* fingerprint reader */ + { 1, 1, 4 }, /* WWAN */ + { 0, 0, 5 }, + { 1, 0, 5 }, /* docking */ + { 0, 0, 6 }, + { 0, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); + kbc1126_disable4e(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads new file mode 100644 index 0000000000..21de0db952 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- both on board and dock DP are DP1/HDMI1 + HDMI1, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c new file mode 100644 index 0000000000..30fd1f76e9 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c new file mode 100644 index 0000000000..eba1fb9729 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162b, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c162b), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x103c3066), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb new file mode 100644 index 0000000000..d69a21e9a1 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000155" + register "gpu_pch_backlight" = "0x02880288" + + device domain 0 on + subsystemid 0x103c 0x162b inherit + + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # mailbox at 0x200/0x201 and PM1 at 0x220 + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 0, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4), dock eSATA(5) + register "sata_port_map" = "0x33" + + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on # PCIe Port #2, ExpressCard + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end + device pci 1c.2 on end # PCIe Port #3, SD/MMC Host Controller + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7, WWAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + end + end +end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index e7e5dec181..357e24ad90 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -49,9 +49,6 @@ chip northbridge/intel/sandybridge end device pnp 4e.5 off end # COM2 end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 7c12fd3fbb..b8ddd698f2 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -40,9 +40,6 @@ chip northbridge/intel/sandybridge register "ec_fan_ctrl_value" = "0x44" device pnp ff.1 off end end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt new file mode 100644 index 0000000000..9f32b2703f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-probook-6360b-notebook-pc/5045581 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt new file mode 100644 index 0000000000..14ed640d2a Binary files /dev/null and b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c new file mode 100644 index 0000000000..95243016e6 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* left front */ + { 1, 1, 0 }, /* left rear, debug */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* webcam */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, /* fingerprint reader */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, /* right */ + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads new file mode 100644 index 0000000000..3df1e37f3e --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c new file mode 100644 index 0000000000..c281dcd5b9 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c new file mode 100644 index 0000000000..40de8bc56b --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1620, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1620), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x103c3066), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb new file mode 100644 index 0000000000..3289588132 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x0000014a" + + device domain 0 on + subsystemid 0x103c 0x1621 inherit + + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), docking(3, 5), eSATA(4) + # FIXME: ports 3, 5 are untested + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on # PCIe Port #2, ExpressCard + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end + device pci 1c.2 on end # PCIe Port #3, SD/MMC and FireWire + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6e" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index a7c894beb8..65a18199e7 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -39,8 +39,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index cdf7ff3dea..af43af7c97 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -40,9 +40,6 @@ chip northbridge/intel/sandybridge register "ec_fan_ctrl_value" = "0x70" device pnp ff.1 off end end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index b1cf89cea7..12643bd114 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select GFX_GMA_ANALOG_I2C_HDMI_B + select MAINBOARD_USES_IFD_GBE_REGION config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout index 33b2068e2b..1fc83b1a55 100644 --- a/src/mainboard/hp/z220_sff_workstation/cmos.layout +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -4,96 +4,69 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused -400 3 h 0 psu_fan_lvl -#403 5 r 0 unused +395 4 e 6 debug_level +400 3 h 0 psu_fan_lvl # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 10 r 0 unused +421 1 e 9 sata_mode # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +432 3 e 11 gfx_uma_size -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 263d595d0e..61535df242 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -8,13 +8,10 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0x0 on end + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0x0 on end device lapic 0xacac off end end end diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c index 0d62faed7c..75dc3302a5 100644 --- a/src/mainboard/hp/z220_sff_workstation/mainboard.c +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include #include #include diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 94c4e23781..66d85f396b 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG - select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 30e4d2c6b8..cf73fc1d6a 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -20,12 +20,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index 52c2fbbec1..6970dfc45e 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index e51185bc8f..499fc2ccea 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -4,148 +4,120 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -#928 40 r 0 unused +416 512 s 0 boot_devices # coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature -968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 - -#971 13 r 0 unused +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed -#8 2 Thermal +8 0 Disabled +8 1 Speed +#8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (°C/°F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 -#10 10 60/140 -#10 11 63/145 -#10 12 66/150 -#10 13 69/156 -#10 14 72/161 -#10 15 75/167 -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 98113bfc5e..a8e94fe38a 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 88a569993f..1799f9a2df 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -41,7 +41,7 @@ void bootblock_mainboard_early_init(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + // pnp_write_config(dev, PNP_IDX_MSC1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard @@ -49,7 +49,7 @@ void bootblock_mainboard_early_init(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); + //pnp_write_config(dev, PNP_IDX_MSC0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_GPIO2); @@ -59,9 +59,10 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, PNP_IDX_MSC1, 0x00); // GPIO bit 2 is 0 + // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, PNP_IDX_EN, 0x03); dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000000..ef89e0f1dd --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,101 @@ +if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select SOC_INTEL_ALDERLAKE + select HAVE_SPD_IN_CBFS + select DRIVERS_SOUNDWIRE_ALC711 + select PCIEXP_HOTPLUG + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" if BOARD_INTEL_ADLRVP_P + default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice + prompt "ON BOARD EC" + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT +endchoice + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000000..0d54bb9a27 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_P_EXT_EC + bool "Alderlake-P RVP with Chrome EC" + select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000000..de924067d1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += early_gpio.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c +romstage-y += memory.c + +smm-y += smihandler.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c +ramstage-y += gpio.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000000..b8bd6dcd9b --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,499 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C1.CAM0, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C1) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_R5) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_R5) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + /* Pull RST low */ + CTXS(GPP_R5) + /* Pull PWREN low */ + CTXS(GPP_B23) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_E16) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_E15) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_E15) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + /* Pull RST low */ + CTXS(GPP_E15) + /* Pull PWREN low */ + CTXS(GPP_E16) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c new file mode 100644 index 0000000000..332ba1b7ae --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + } + } + } + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h new file mode 100644 index 0000000000..2988127e9b --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/cannonlake_rvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt similarity index 76% rename from src/mainboard/intel/cannonlake_rvp/board_info.txt rename to src/mainboard/intel/adlrvp/board_info.txt index 2fe64680dd..be99df80a3 100644 --- a/src/mainboard/intel/cannonlake_rvp/board_info.txt +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Intel -Board name: Cannonlake rvp +Board name: Alderlake rvp Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c similarity index 54% rename from src/mainboard/google/cheza/bootblock.c rename to src/mainboard/intel/adlrvp/bootblock.c index 05e53a64bb..95f7497c2d 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include "board.h" void bootblock_mainboard_init(void) { - setup_chromeos_gpios(); + variant_configure_early_gpio_pads(); } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c similarity index 79% rename from src/mainboard/intel/cannonlake_rvp/chromeos.c rename to src/mainboard/intel/adlrvp/chromeos.c index 98205bc62a..d963c73651 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include -#include -#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -14,20 +12,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) int get_lid_switch(void) { - /* Lid always open */ - return 1; + /* Lid always open */ + return 1; } int get_recovery_mode_switch(void) { - return 0; + return 0; } +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ int get_write_protect_state(void) { diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000000..ee27e2f7cf --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 32M { + SI_ALL@0x0 0x1000000 { + SI_DESC 0x1000 + SI_EC 0x80000 + SI_ME + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A 0x368000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x357fc0 + RW_FWID_A 0x40 + } + RW_SECTION_B 0x368000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x357fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 0x100000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb new file mode 100644 index 0000000000..cf9afaf68c --- /dev/null +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -0,0 +1,295 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 2 + register "PchPcieRpEnable[4]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcUsage[2]" = "0x4" + register "PcieRpClkReqDetect[4]" = "1" + + # Enable PCH PCIE RP 6 using CLK 5 + register "PchPcieRpEnable[5]" = "1" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcUsage[5]" = "0x5" + register "PcieRpClkReqDetect[5]" = "1" + + # Enable PCH PCIE RP 8 using CLK 6 + register "PchPcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 + register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK + register "PcieRpClkReqDetect[6]" = "1" + + # Enable PCH PCIE RP 9 using CLK 1 + register "PchPcieRpEnable[8]" = "1" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcUsage[1]" = "0x8" + register "PcieRpClkReqDetect[8]" = "1" + + # Enable PCH PCIE RP 11 for optane + register "PchPcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + + # Enable CPU PCIE RP 1 using CLK 0 + register "CpuPcieRpEnable[0]" = "1" + register "PcieClkSrcUsage[0]" = "0x40" + + # Enable CPU PCIE RP 2 using CLK 3 + register "CpuPcieRpEnable[1]" = "1" + register "PcieClkSrcUsage[3]" = "0x41" + + # Enable CPU PCIE RP 3 using CLK 4 + register "CpuPcieRpEnable[2]" = "1" + register "PcieClkSrcUsage[4]" = "0x42" + + # W/A to FSP issue where FSP is using PCH PCIE port + # enable UPD to download FW on CPU PCIE + register "PchPcieRpEnable[0]" = "1" + register "PchPcieRpEnable[2]" = "1" + register "PchPcieRpEnable[3]" = "1" + + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below + register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + # Enable HDMI in Port B + register "DdiPortBDdc" = "1" + register "DdiPortBHpd" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG10 + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 06.2 on end # PEG62 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 off end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 off end # RP2 + device pci 1c.2 on end # RP3 # W/A to FSP issue + device pci 1c.3 on end # RP4 # W/A to FSP issue + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 off end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 off end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 off end # RP12 + device pci 1e.0 on end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000000..6e7ccd1d7c --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + + /* global NVS and variables */ + #include + + #include + + Device (\_SB.PCI0) { + #include + #include + #include + #include + } + + /* Camera */ + #include + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +#endif + + #include +} diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c new file mode 100644 index 0000000000..11938ed883 --- /dev/null +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c new file mode 100644 index 0000000000..14760017ef --- /dev/null +++ b/src/mainboard/intel/adlrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c new file mode 100644 index 0000000000..3131cc0c05 --- /dev/null +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_NC(GPP_H23, NONE), + + /* A21 : HDMI CRLS CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : HDMI CRLS CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h new file mode 100644 index 0000000000..c01829936d --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h new file mode 100644 index 0000000000..de0adf6cff --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h new file mode 100644 index 0000000000..9cb8640860 --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include +#include + +enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + ADL_P_LP4_1 = 0x10, + ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5 = 0x12, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5 = 0x13, + /* ADL-P DDR4 RVPs */ + ADL_P_DDR4_1 = 0x14, + ADL_P_DDR4_2 = 0x3F, +}; + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c new file mode 100644 index 0000000000..fb2557836a --- /dev/null +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board_id.h" + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c new file mode 100644 index 0000000000..80ec14aa17 --- /dev/null +++ b/src/mainboard/intel/adlrvp/memory.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "board_id.h" +#include +#include + +static const struct mb_cfg ddr4_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = false, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lpddr4_mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, + { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, + { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, + { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, + { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, + { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, + { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, + { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lp5_mem_config = { + + /* DQ byte map */ + .dq_map = { + { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, + { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, + { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, + { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, + { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, + { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, + { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, + { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = false, /* Early Command Training */ + + .lp5_ccc_config = 0xff, + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg ddr5_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {50, 30, 30, 30, 27}, + + .dq_pins_interleaved = false, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + switch (board_id) { + case ADL_P_LP4_1: + case ADL_P_LP4_2: + return &lpddr4_mem_config; + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + return &ddr4_mem_config; + case ADL_P_DDR5: + return &ddr5_mem_config; + case ADL_P_LP5: + return &lp5_mem_config; + default: + die("unsupported board id : 0x%x\n", board_id); + } +} diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c new file mode 100644 index 0000000000..2f03cb4e84 --- /dev/null +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board_id.h" + +#define SPD_ID_MASK 0x7 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = get_board_id(); + const bool half_populated = false; + + const struct spd_info lp4_lp5_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = get_spd_index(), + }; + + const struct spd_info ddr4_ddr5_spd_info = { + .read_type = READ_SMBUS, + .spd_spec = { + .spd_smbus_address = { + [0] = 0xa0, + [1] = 0xa2, + [8] = 0xa4, + [9] = 0xa6, + }, + }, + }; + + switch (board_id) { + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + case ADL_P_DDR5: + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); + break; + case ADL_P_LP4_1: + case ADL_P_LP4_2: + case ADL_P_LP5: + memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +} diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c new file mode 100644 index 0000000000..a3b43231ec --- /dev/null +++ b/src/mainboard/intel/adlrvp/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc new file mode 100644 index 0000000000..10ce42ef4c --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = adlrvp_lp4 # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += empty # 0b002 +SPD_SOURCES += adlrvp_lp5 # 0b003 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex similarity index 87% rename from src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex rename to src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index d298629342..e1d338edbc 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex new file mode 100644 index 0000000000..2f2a31a33d --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/adlrvp/spd/empty.spd.hex similarity index 100% rename from src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex rename to src/mainboard/intel/adlrvp/spd/empty.spd.hex diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb new file mode 100644 index 0000000000..9130a126a1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/alderlake + + device domain 0 on + device pci 1f.0 on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end + end + end # eSPI + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 2 alias conn2 on end + end + end + end + end # PMC + end +end diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index f7e82a06ca..dd12a5b8c3 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 32852629f3..6806a8d1b9 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 8268891186..b2d06539da 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index 487b7417f5..c1bb1163ed 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -20,10 +20,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,7 +52,7 @@ Scope (\_TZ) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -60,7 +60,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -68,7 +68,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -76,7 +76,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -84,7 +84,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -100,20 +100,20 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -121,20 +121,20 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -142,20 +142,20 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -163,20 +163,20 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -184,20 +184,20 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index fe44d08ff4..4aee97a3f9 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -3,13 +3,12 @@ #include #include #include -#include #include #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -25,12 +24,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - -#if CONFIG(CHROMEOS) - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 7c4d614196..77ff74375e 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -4,81 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 157f393454..37cff88f30 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -16,14 +16,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end @@ -32,15 +24,6 @@ chip northbridge/intel/haswell device pci 02.0 on end # vga controller chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) @@ -50,8 +33,6 @@ chip northbridge/intel/haswell register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 388d109ef0..5971917f9d 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig deleted file mode 100644 index 32c9487052..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select GENERIC_SPD_BIN - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98373 - select DRIVERS_GENERIC_MAX98357A - select SOC_INTEL_CANNONLAKE - select MAINBOARD_USES_IFD_EC_REGION - select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_LPC_TPM - -config MAINBOARD_DIR - string - default "intel/cannonlake_rvp" - -config VARIANT_DIR - string - default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU - default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY - -config MAINBOARD_PART_NUMBER - string - default "Cannonlake RVP" - -config MAINBOARD_FAMILY - string - default "Intel_cannonlake_rvp" - -config MAX_CPUS - int - default 8 - -config DEVICETREE - string - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config INCLUDE_SND_MAX98357_DA7219_NHLT - bool "Include blobs for audio with MAX98357_DA7219" - select NHLT_DMIC_4CH_16B - select NHLT_DMIC_2CH_16B - select NHLT_DA7219 - select NHLT_MAX98357 - -config INCLUDE_SND_MAX98373_NHLT - bool "Include blobs for audio with MAX98373" - select NHLT_DMIC_4CH_16B - select NHLT_DMIC_2CH_16B - select NHLT_MAX98373 - -config DIMM_SPD_SIZE - int - default 512 - -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA - -config UART_FOR_CONSOLE - int - default 2 -endif diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name deleted file mode 100644 index 29d1bd8d21..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -config BOARD_INTEL_CANNONLAKE_RVPU - bool "Cannonlake U LPDDR4 RVP" -config BOARD_INTEL_CANNONLAKE_RVPY - bool "Cannonlake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd deleted file mode 100644 index 39bd6c5237..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ /dev/null @@ -1,45 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x380000 { - SI_DESC@0x0 0x1000 - SI_EC@0x01000 0x80000 - SI_ME@0x81000 0x2ff000 - } - SI_BIOS@0x380000 0xc80000 { - RW_SECTION_A@0x0 0x368000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 - } - RW_SECTION_B@0x368000 0x368000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 - } - RW_MISC@0x6d0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - SMMSTORE(PRESERVE)@0x700000 0x40000 - RW_LEGACY(CBFS)@0x740000 0x1c0000 - WP_RO@0x900000 0x380000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x280000 - } - } - } -} diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c deleted file mode 100644 index 950e24d88b..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void mainboard_init(void *chip_info) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - -static unsigned long mainboard_write_acpi_tables(const struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - variant_nhlt_init(nhlt); - - end_addr = nhlt_soc_serialize(nhlt, start_addr); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c deleted file mode 100644 index 5b7445f067..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "spd/spd.h" -#include - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; - u8 spd_index; - - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; - - struct region_device spd_rdev; - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found\n"); - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; -} diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c deleted file mode 100644 index 734ab8ce8c..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - gnvs->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc deleted file mode 100644 index 48e6375819..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -romstage-y += spd_util.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB -SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB -SPD_SOURCES += empty # 0b011 -SPD_SOURCES += empty # 0b100 -SPD_SOURCES += empty # 0b101 -SPD_SOURCES += empty # 0b110 -SPD_SOURCES += empty # 0b111 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h deleted file mode 100644 index 978f01daa5..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr); -void mainboard_fill_dq_map_ch1(void *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -#endif diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c deleted file mode 100644 index e4b4b383b9..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "spd.h" - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(void *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; - - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; - - if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); -} - -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; - - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; - - if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[5] = { 80, 40, 40, 40, 30 }; - - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c deleted file mode 100644 index d5449b077f..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ /dev/null @@ -1,308 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { - /* GPPC */ - /* A0 : RCINB_TIME_SYNC_1 */ - /* A1 : ESPI_IO_0 */ - /* A2 : ESPI_IO_1 */ - /* A3 : ESPI_IO_2 */ - /* A4 : ESPI_IO_3 */ - /* A5 : ESPI_CSB */ - /* A6 : SERIRQ */ - /* A7 : PRIQAB_GSP10_CS1B */ - PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), - /* A8 : CLKRUNB */ - PAD_CFG_GPO(GPP_A8, 1, PLTRST), - /* A9 : CLKOUT_LPC_0_ESPI_CLK */ - /* A10 : CLKOUT_LPC_1 */ - /* A11 : PMEB_GSP11_CS1B */ - PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL), - /* A12 : BM_BUSYB_ISH__GP_6 */ - /* A13 : SUSWARNB_SUSPWRDNACK */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - /* A14 : SUS_STATB_ESPI_RESETB */ - /* A15 : SUSACKB */ - PAD_CFG_GPO(GPP_A15, 1, PLTRST), - /* A16 : SD_1P8_SEL */ - PAD_CFG_GPO(GPP_A16, 0, PLTRST), - /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ - /* A18 : ISH_GP_0 */ - PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), - /* A19 : ISH_GP_1 */ - PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), - /* A20 : aduio codec irq */ - PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP), - /* A21 : ISH_GP_3 */ - PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), - /* A22 : ISH_GP_4 */ - PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1), - /* A23 : ISH_GP_5 */ - PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), - - /* B0 : CORE_VID_0 */ - /* B1 : CORE_VID_1 */ - /* B2 : VRALERTB */ - PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), - /* B3 : CPU_GP_2 */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), - /* B4 : CPU_GP_3 */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* B5 : SRCCLKREQB_0 */ - /* B6 : SRCCLKREQB_1 */ - /* B7 : SRCCLKREQB_2 */ - /* B8 : SRCCLKREQB_3 */ - /* B9 : SRCCLKREQB_4 */ - /* B10 : SRCCLKREQB_5 */ - /* B11 : EXT_PWR_GATEB */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), - /* B12 : SLP_S0B */ - /* B13 : PLTRSTB */ - /* B14 : SPKR */ - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* B15 : GSPI0_CS0B */ - PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* B16 : GSPI0_CLK */ - PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), - /* B17 : GSPI0_MISO */ - PAD_CFG_GPO(GPP_B17, 1, PLTRST), - /* B18 : GSPI0_MOSI */ - PAD_CFG_GPO(GPP_B18, 1, PLTRST), - /* B19 : GSPI1_CS0B */ - /* B20 : GSPI1_CLK_NFC_CLK */ - /* B21 : GSPI1_MISO_NFC_CLKREQ */ - /* B22 : GSP1_MOSI */ - /* B23 : SML1ALERTB_PCHHOTB */ - PAD_CFG_GPO(GPP_B23, 1, DEEP), - - /* C0 : SMBCLK */ - /* C1 : SMBDATA */ - /* C2 : SMBALERTB */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), - /* C3 : SML0CLK */ - /* C4 : SML0DATA */ - /* C5 : SML0ALERTB */ - PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), - /* C6 : SML1CLK */ - /* C7 : SML1DATA */ - /* C8 : UART0_RXD */ - PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), - /* C9 : UART0_TXD */ - PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), - /* C10 : UART0_RTSB */ - PAD_CFG_GPO(GPP_C10, 0, PLTRST), - /* C11 : UART0_CTSB */ - PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL), - /* C12 : UART1_RXD_ISH_UART1_RXD */ - PAD_CFG_GPO(GPP_C12, 1, PLTRST), - /* C13 : UART1_RXD_ISH_UART1_TXD */ - /* C14 : UART1_RXD_ISH_UART1_RTSB */ - /* C15 : UART1_RXD_ISH_UART1_CTSB */ - PAD_CFG_GPO(GPP_C15, 1, PLTRST), - /* C16 : I2C0_SDA */ - /* C17 : I2C0_SCL */ - /* C18 : I2C1_SDA */ - /* C19 : I2C1_SCL */ - /* C20 : UART2_RXD */ - /* C21 : UART2_TXD */ - /* C22 : UART2_RTSB */ - /* C23 : UART2_CTSB */ - - /* D0 : SPI1_CSB_BK_0 */ - /* D1 : SPI1_CLK_BK_1 */ - /* D2 : SPI1_MISO_IO_1_BK_2 */ - /* D3 : SPI1_MOSI_IO_0_BK_3 */ - /* D4 : IMGCLKOUT_0_BK_4 */ - /* D5 : ISH_I2C0_SDA */ - /* D6 : ISH_I2C0_SCL */ - /* D7 : ISH_I2C1_SDA */ - /* D8 : ISH_I2C1_SCL */ - /* D9 : ISH_SPI_CSB */ - PAD_CFG_GPO(GPP_D9, 1, PLTRST), - /* D10 : ISH_SPI_CLK */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE), - /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ - PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), - /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ - /* D13 : ISH_UART0_RXD_SML0BDATA */ - PAD_CFG_GPO(GPP_D13, 1, DEEP), - /* D14 : ISH_UART0_TXD_SML0BCLK */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ - /* D16 : ISH_UART0_CTSB_SML0BALERTB */ - PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), - /* D17 : DMIC_CLK_1_SNDW3_CLK */ - PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), - /* D18 : DMIC_DATA_1_SNDW3_DATA */ - PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), - /* D19 : DMIC_CLK_0_SNDW4_CLK */ - PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), - /* D20 : DMIC_DATA_0_SNDW4_DATA */ - PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), - /* D21 : SPI1_IO_2 */ - PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), - /* D22 : SPI1_IO_3 */ - PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), - /* D23 : SPP_MCLK */ - PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), - /* E0 : SATAXPCIE_0_SATAGP_0 */ -#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), -#endif - /* E1 : SATAXPCIE_1_SATAGP_1 */ - /* E2 : SATAXPCIE_2_SATAGP_2 */ - PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), - /* E3 : CPU_GP_0 */ - PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), - /* E4 : SATA_DEVSLP_0 */ - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP_1 */ - /* E6 : SATA_DEVSLP_2 */ - PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), - /* E7 : CPU_GP_1 */ - PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), - /* E8 : SATA_LEDB */ - /* E9 : USB2_OCB_0_GP_BSSB_CLK */ - /* E10 : USB2_OCB_1_GP_BSSB_DI */ - /* E11 : USB2_OCB_2 */ - /* E12 : USB2_OCB_3 */ - /* E13 : DDSP_HPD_0_DISP_MISC_0 */ - /* E14 : DDSP_HPD_0_DISP_MISC_1 */ - /* E15 : DDSP_HPD_0_DISP_MISC_2 */ - /* E16 : EMMC_EN */ - PAD_CFG_GPO(GPP_E16, 1, PLTRST), - /* E17 : EDP_HPD_DISP_MISC_4 */ - /* E18 : DDPB_CTRLCLK */ - /* E19 : DDPB_CTRLDATA */ - /* E20 : DDPC_CTRLCLK */ - /* E21 : DDPC_CTRLDATA */ - /* E22 : DDPD_CTRLCLK */ - /* E23 : DDPD_CTRLDATA */ - - /* F0 : CNV_GNSS_PA_BLANKING */ - PAD_CFG_GPI(GPP_F0, NONE, PLTRST), - /* F1 : CNV_GNSS_FAT */ - PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), - /* F2 : CNV_GNSS_SYSCK */ - PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), - /* F3 : GPP_F_3 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), - /* F4 : CNV_BRI_DT_UART0_RTSB */ - /* F5 : CNV_BRI_RSP_UART0_RXD */ - /* F6 : CNV_RGI_DT_UART0_TXD */ - /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ - /* F8 : CNV_MFUART2_RXD */ - PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), - /* F9 : CNV_MFUART2_TXD */ - PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1), - /* F10 : GPP_F_10 */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* F11 : EMMC_CMD */ - /* F12 : EMMC_DATA0 */ - /* F13 : EMMC_DATA1 */ - /* F14 : EMMC_DATA2 */ - /* F15 : EMMC_DATA3 */ - /* F16 : EMMC_DATA4 */ - /* F17 : EMMC_DATA5 */ - /* F18 : EMMC_DATA6 */ - /* F19 : EMMC_DATA9 */ - /* F20 : EMMC_RCLK */ - /* F21 : EMMC_CLK */ - /* F22 : EMMC_RESETB */ - /* F23 : BIOS_REC */ - PAD_CFG_GPI(GPP_F23, UP_20K, DEEP), - /* G0 : SD3_D2 */ - /* G1 : SD3_D0_SD4_RCLK_P */ - /* G2 : SD3_D1_SD4_RCLK_N */ - /* G3 : SD3_D2 */ - /* G4 : SD3_D3 */ - /* G5 : SD3_CDB */ - PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1), - /* G6 : SD3_CLK */ - /* G7 : SD3_WP */ - PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), - - /* H0 : SSP2_SCLK */ - /* H1 : SSP2_SFRM */ - /* H2 : SSP2_TXD */ - /* H3 : SSP2_RXD */ - /* H4 : I2C2_SDA */ - /* H5 : I2C2_SCL */ - /* H6 : I2C3_SDA */ - PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1), - /* H7 : I2C3_SCL */ - PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1), - /* H8 : I2C4_SDA */ - /* H9 : I2C4_SCL */ - /* H10 : I2C5_SDA_ISH_I2C2_SDA */ - PAD_CFG_GPO(GPP_H10, 1, PLTRST), - /* H11 : I2C5_SCL_ISH_I2C2_SCL */ - PAD_CFG_GPO(GPP_H11, 1, PLTRST), - /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */ - PAD_CFG_GPO(GPP_H12, 1, PLTRST), - /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* H14 : M2_SKT2_CFG_2 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), - /* H15 : M2_SKT2_CFG_3 */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* H16 : CAM5_PWR_EN */ - PAD_CFG_GPO(GPP_H16, 1, PLTRST), - /* H17 : CAM5_FLASH_STROBE */ - PAD_CFG_GPO(GPP_H17, 1, PLTRST), - /* H18 : BOOTMPC */ - /* H19 : TIMESYNC_0 */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - /* H20 : IMGCLKOUT_1 */ - /* H21 : GPPC_H_21 */ - /* H22 : GPPC_H_22 */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - /* H23 : GPPC_H_23 */ - - /* GPD */ - /* GPD_0 : BATLOWB */ - /* GPD_1 : ACPRESENT */ - /* GPD_2 : LAN_WAKEB */ - /* GPD_3 : PWRBTNB */ - /* GPD_4 : SLP_S3B */ - /* GPD_5 : SLP_S4B */ - /* GPD_6 : SLP_AB */ - /* GPD_7 : GPD_7 */ - /* GPD-8 : SUSCLK */ - /* GPD-9 : SLP_WLANB */ - /* GPD-10 : SLP_5B */ - /* GPD_11 : LANPHYPC */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - - -}; - -const struct pad_config *__weak variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__weak - variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c deleted file mode 100644 index 6599cbd1cb..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void __weak variant_nhlt_init(struct nhlt *nhlt) -{ - /* 1-dmic configuration */ - if (CONFIG(NHLT_DMIC_1CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 1)) - printk(BIOS_ERR, "Added 1CH DMIC array.\n"); - /* 2-dmic configuration */ - if (CONFIG(NHLT_DMIC_2CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Added 2CH DMIC array.\n"); - /* 4-dmic configuration */ - if (CONFIG(NHLT_DMIC_4CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - - if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) - { - /* Dialog for Headset codec. - * Headset codec is bi-directional but uses the same configuration - * settings for render and capture endpoints. - */ - if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) - printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); - - /* MAXIM Smart Amps for left and right speakers. */ - if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); - } - - if (CONFIG(INCLUDE_SND_MAX98373_NHLT) && - !nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Maxim_98373 codec.\n"); -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb deleted file mode 100644 index e5f867cbdc..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ /dev/null @@ -1,156 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "interleave_mode" = "1" - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb deleted file mode 100644 index 53c677b64e..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ /dev/null @@ -1,179 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0001"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "hid_desc_reg_offset" = "0x1" - device i2c 2C on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h deleted file mode 100644 index 33ccb11351..0000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc index 9bd017393c..3da456e436 100644 --- a/src/mainboard/intel/cedarisland_crb/Makefile.inc +++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc @@ -1,2 +1,3 @@ bootblock-y += bootblock.c romstage-y += romstage.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 6f408b36da..d880d5416d 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -21,12 +21,11 @@ DefinitionBlock( { Device (PCI0) { - #include + #include #include } - Device (UNC0) { Name (_HID, EisaId ("PNP0A03")) diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index e005913393..da2175d669 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -10,27 +10,27 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - ESPI_ALERT1# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), /* GPP_A1 - ESPI_IO0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), /* GPP_A2 - ESPI_IO1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), /* GPP_A3 - ESPI_IO2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), /* GPP_A4 - ESPI_IO3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), /* GPP_A5 - ESPI_CS0# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF3), /* GPP_A6 - ESPI_CS1# */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), /* GPP_A7 - ESPI_ALERT0# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF3), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - ESPI_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { /* GPP_A13 - GPIO */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* GPP_A14 - ESPI_RESET# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), /* GPP_A15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ @@ -59,9 +59,9 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, RSMRST, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, RSMRST, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPP_B3 - GPIO */ @@ -84,9 +84,9 @@ static const struct pad_config gpio_table[] = { /* GPP_B12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, RSMRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPP_B16 - GPIO */ @@ -104,19 +104,19 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - SATAXPCIE3 */ - PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F0, NONE, RSMRST, NF1), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F1, NONE, RSMRST, NF1), /* GPP_F2 - SATAXPCIE5 */ - PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F2, NONE, RSMRST, NF1), /* GPP_F3 - SATAXPCIE6 */ - PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F3, NONE, RSMRST, NF1), /* GPP_F4 - SATAXPCIE7 */ - PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F4, NONE, RSMRST, NF1), /* GPP_F5 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPP_F6 - GPIO */ @@ -128,33 +128,33 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, RSMRST, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, RSMRST, NF1), /* GPP_F12 - SATA_SDATAOUT1 */ - PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F12, NONE, RSMRST, NF1), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, RSMRST, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, RSMRST, NF3), /* GPP_F15 - USB_OC4# */ - PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F15, NONE, RSMRST, NF1), /* GPP_F16 - USB_OC5# */ - PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F16, NONE, RSMRST, NF1), /* GPP_F17 - USB_OC6# */ - PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F17, NONE, RSMRST, NF1), /* GPP_F18 - USB_OC7# */ - PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F18, NONE, RSMRST, NF1), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, RSMRST, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, RSMRST, NF1), /* GPP_F21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, RSMRST, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, RSMRST, NF3), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ @@ -165,7 +165,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - SML0ALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C5, NONE, RSMRST, NF1), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ @@ -225,17 +225,17 @@ static const struct pad_config gpio_table[] = { /* GPP_D9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPP_D10 - SSATA_DEVSLP4 */ - PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D10, NONE, RSMRST, NF3), /* GPP_D11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI), /* GPP_D12 - SSATA_SDATAOUT1 */ - PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF3), /* GPP_D13 - SML0BCLK_IE */ - PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D13, NONE, RSMRST, NF3), /* GPP_D14 - SML0BDATA_IE */ - PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF3), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, RSMRST, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - GPIO */ @@ -255,13 +255,13 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E0, NONE, RSMRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E1, NONE, RSMRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI), /* GPP_E5 - GPIO */ @@ -271,31 +271,31 @@ static const struct pad_config gpio_table[] = { /* GPP_E7 - GPIO */ PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, RSMRST, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1), /* GPP_E10 - USB_OC1# */ - PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E10, NONE, RSMRST, NF1), /* GPP_E11 - USB_OC2# */ - PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E11, NONE, RSMRST, NF1), /* GPP_E12 - USB_OC3# */ - PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E12, NONE, RSMRST, NF1), /* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - ACPRESENT */ - PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* GPD2 - GBE_WAKE# */ - PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - SLP_A# */ - PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* GPD7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ @@ -303,20 +303,20 @@ static const struct pad_config gpio_table[] = { /* GPD9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - SLP_S5# */ - PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, RSMRST, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, RSMRST, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, RSMRST, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2), /* GPP_I4 - GPIO */ _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | @@ -327,11 +327,11 @@ static const struct pad_config gpio_table[] = { /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, RSMRST, NF2), /* GPP_I8 - PCI_DIS */ - PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I8, NONE, RSMRST, NF2), /* GPP_I9 - LAN_DIS */ - PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I9, NONE, RSMRST, NF2), /* GPP_I10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI), @@ -394,27 +394,27 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - LAN_NCSI_CLK_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_K0, NONE, RSMRST, NF1), /* GPP_K1 - LAN_NCSI_TXD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K1, NONE, RSMRST, NF1), /* GPP_K2 - LAN_NCSI_TXD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K2, NONE, RSMRST, NF1), /* GPP_K3 - LAN_NCSI_TX_EN */ - PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K3, NONE, RSMRST, NF1), /* GPP_K4 - LAN_NCSI_CRS_DV */ - PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K4, NONE, RSMRST, NF1), /* GPP_K5 - LAN_NCSI_RXD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K5, NONE, RSMRST, NF1), /* GPP_K6 - LAN_NCSI_RXD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K6, NONE, RSMRST, NF1), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, RSMRST, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, RSMRST, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, RSMRST, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -453,16 +453,16 @@ static const struct pad_config gpio_table[] = { /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, RSMRST, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, RSMRST, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, RSMRST, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPP_G22 - n/a */ - PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G22, NONE, RSMRST, NF3), /* GPP_G23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI), @@ -491,14 +491,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ - PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1), /* GPP_H7 - GPIO */ _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H8 - SRCCLKREQ14# */ - PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1), /* GPP_H9 - GPIO */ _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | @@ -519,54 +519,54 @@ static const struct pad_config gpio_table[] = { /* GPP_H19 - GPIO */ PAD_CFG_GPO(GPP_H19, 0, RSMRST), /* GPP_H20 - SSATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2), /* GPP_H21 - GPIO */ PAD_CFG_GPO(GPP_H21, 0, RSMRST), /* GPP_H22 - SSATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H22, NONE, RSMRST, NF2), /* GPP_H23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - TESTCH0_D0 */ - PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L2, NONE, RSMRST, NF1), /* GPP_L3 - TESTCH0_D1 */ - PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L3, NONE, RSMRST, NF1), /* GPP_L4 - TESTCH0_D2 */ - PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L4, NONE, RSMRST, NF1), /* GPP_L5 - TESTCH0_D3 */ - PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L5, NONE, RSMRST, NF1), /* GPP_L6 - TESTCH0_D4 */ - PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L6, NONE, RSMRST, NF1), /* GPP_L7 - TESTCH0_D5 */ - PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L7, NONE, RSMRST, NF1), /* GPP_L8 - TESTCH0_D6 */ - PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L8, NONE, RSMRST, NF1), /* GPP_L9 - TESTCH0_D7 */ - PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L9, NONE, RSMRST, NF1), /* GPP_L10 - TESTCH0_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L10, NONE, RSMRST, NF1), /* GPP_L11 - TESTCH1_D0 */ - PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L11, NONE, RSMRST, NF1), /* GPP_L12 - TESTCH1_D1 */ - PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L12, NONE, RSMRST, NF1), /* GPP_L13 - TESTCH1_D2 */ - PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L13, NONE, RSMRST, NF1), /* GPP_L14 - TESTCH1_D3 */ - PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L14, NONE, RSMRST, NF1), /* GPP_L15 - TESTCH1_D4 */ - PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L15, NONE, RSMRST, NF1), /* GPP_L16 - TESTCH1_D5 */ - PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L16, NONE, RSMRST, NF1), /* GPP_L17 - TESTCH1_D6 */ - PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L17, NONE, RSMRST, NF1), /* GPP_L18 - TESTCH1_D7 */ - PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L18, NONE, RSMRST, NF1), /* GPP_L19 - TESTCH1_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L19, NONE, RSMRST, NF1), }; #endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index e82d26b1e1..03e28a1678 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,25 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - void *start = (void *) m_cfg; - // BoardId - write8(start + 140, 0x1d); - - // BoardTypeBitmask - write32(start + 104, 0x11111111); - - // DebugPrintLevel - write8(start + 45, 8); - - // KtiLinkSpeedMode - write8(start + 64, 0); - - // KtiPrefetchEn - write8(start + 53, 2); + m_cfg->KtiLinkSpeedMode = 0; } diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 81bfc93bc1..0f8075bf4f 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE @@ -16,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_GENERIC_MAX98357A select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 519cd50dc1..e03e862636 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -14,4 +14,4 @@ config BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COFFEELAKE config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index a3061e3db5..77f06913fa 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -10,7 +10,7 @@ romstage-y += memory.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 121012e888..b415336ec1 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/intel/coffeelake_rvp/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/hda_verb.c deleted file mode 100644 index c26029774e..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/hda_verb.c +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "variant/hda_verb.h" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 01d970ca56..12b1c47f33 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - # HECI - register "HeciEnabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" @@ -46,9 +43,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 3c753915f9..5700f064b0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -579,8 +579,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c similarity index 98% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c index e276cf7f6e..cbe8f0be21 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef HDA_VERB_H -#define HDA_VERB_H - #include const u32 cim_verb_data[] = { @@ -183,4 +180,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 989b5cd4ea..a1455848e9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -99,12 +99,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c similarity index 98% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c index e276cf7f6e..cbe8f0be21 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef HDA_VERB_H -#define HDA_VERB_H - #include const u32 cim_verb_data[] = { @@ -183,4 +180,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index a63d4c0364..af5fc2de94 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -15,12 +15,10 @@ chip soc/intel/cannonlake register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" register "usb2_ports[10]" = "USB2_PORT_MID(OC3)" register "usb2_ports[11]" = "USB2_PORT_MID(OC6)" register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" - register "usb2_ports[13]" = "USB2_PORT_EMPTY" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" @@ -94,10 +92,12 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[10]" = "10" device domain 0 on - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 @@ -107,12 +107,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 x4 SLOT 1 + device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -120,11 +126,21 @@ chip soc/intel/cannonlake device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on end # PCI Express Port 17 - device pci 1b.1 on end # PCI Express Port 18 - device pci 1b.2 on end # PCI Express Port 19 - device pci 1b.3 on end # PCI Express Port 20 - device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 + device pci 1b.0 on # PCI Express Port 17 + register "PcieRpSlotImplemented[16]" = "1" + end + device pci 1b.1 on # PCI Express Port 18 + register "PcieRpSlotImplemented[17]" = "1" + end + device pci 1b.2 on # PCI Express Port 19 + register "PcieRpSlotImplemented[18]" = "1" + end + device pci 1b.3 on # PCI Express Port 20 + register "PcieRpSlotImplemented[19]" = "1" + end + device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2 + register "PcieRpSlotImplemented[20]" = "1" + end device pci 1e.1 off end # UART #1 device pci 1f.6 on end # GbE end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index c5c291df9f..f4b82ab657 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -61,10 +61,12 @@ chip soc/intel/cannonlake }" device domain 0 on - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 @@ -84,12 +86,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/hda_verb.c similarity index 99% rename from src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h rename to src/mainboard/intel/coffeelake_rvp/variants/cml_u/hda_verb.c index 7233250105..01012dde1b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef HDA_VERB_H -#define HDA_VERB_H - #include const u32 cim_verb_data[] = { @@ -684,4 +681,3 @@ const u32 cim_verb_data[] = { const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 93b5af9394..55b340caf3 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -80,13 +80,15 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 17.0 on end # SATA @@ -94,12 +96,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c similarity index 99% rename from src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h rename to src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c index 7233250105..01012dde1b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef HDA_VERB_H -#define HDA_VERB_H - #include const u32 cim_verb_data[] = { @@ -684,4 +681,3 @@ const u32 cim_verb_data[] = { const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 1e388240a6..dc8874afe6 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -65,10 +65,12 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 @@ -78,12 +80,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index cd6260bbae..6e7552cb53 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c deleted file mode 100644 index 496d4190c6..0000000000 --- a/src/mainboard/intel/d510mo/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 0a329956af..a2298978b3 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -3,71 +3,65 @@ # ----------------------------------------------------------------- entries - # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: cpu -#945 7 r 0 unused # coreboot config options: northbridge -952 3 e 11 gfx_uma_size +952 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 8M -11 1 16M -11 2 32M -11 3 48M -11 4 64M -11 5 128M -11 6 256M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 6e4ecfc7ea..5e74be86e9 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 30e4d2c6b8..cf73fc1d6a 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -20,12 +20,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } diff --git a/src/mainboard/intel/d945gclf/acpi/superio.asl b/src/mainboard/intel/d945gclf/acpi/superio.asl index bd70025c66..84dd30dcab 100644 --- a/src/mainboard/intel/d945gclf/acpi/superio.asl +++ b/src/mainboard/intel/d945gclf/acpi/superio.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Device (SIO1) { Name (_HID, EISAID("PNP0A05")) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c deleted file mode 100644 index 496d4190c6..0000000000 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index e0d6ec5244..41f967d7ab 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -4,95 +4,69 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 94684d093a..80c5ff44c6 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index 43e5062bb8..ac2f3fb5be 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -4,7 +4,7 @@ #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 by default */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index b865d1a49e..7a5684447e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -17,13 +17,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" end end device domain 0x0 on diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index e81b4b66b4..391d1f23b2 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,15 +14,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index 9eef15936a..7206526637 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index 4905f1d133..11a078e35c 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -4,85 +4,59 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 65db55f5cb..0d0b24c55f 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 79bb1b8956..9f5012adb4 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -4,92 +4,67 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -10 0 AHCI -10 1 Compatible -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index de2d71dd29..bb2456f537 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -22,7 +22,6 @@ chip northbridge/intel/x4x # Northbridge # Set AHCI mode. register "sata_port_map" = "0x1f" register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0xb" diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index de548d1939..71f501bba8 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig new file mode 100644 index 0000000000..e8206ade5b --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -0,0 +1,50 @@ +if BOARD_INTEL_ELKHARTLAKE_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_ELKHARTLAKE + +config MAINBOARD_DIR + string + default "intel/elkhartlake_crb" + +config VARIANT_DIR + string + default "ehlcrb" if BOARD_INTEL_ELKHARTLAKE_CRB + +config MAINBOARD_PART_NUMBER + string + default "ehlcrb" + +config MAINBOARD_FAMILY + string + default "Intel_ehlcrb" + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + +endif diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig.name b/src/mainboard/intel/elkhartlake_crb/Kconfig.name new file mode 100644 index 0000000000..3a20b883cc --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ELKHARTLAKE_CRB + bool "Elkhartlake LPDDR4x CRB" diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc new file mode 100644 index 0000000000..382ec2e354 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/elkhartlake_crb/board_info.txt b/src/mainboard/intel/elkhartlake_crb/board_info.txt new file mode 100644 index 0000000000..a1f291391a --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Intel +Board name: Elkhartlake CRB +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/elkhartlake_crb/bootblock.c similarity index 91% rename from src/mainboard/intel/cannonlake_rvp/bootblock.c rename to src/mainboard/intel/elkhartlake_crb/bootblock.c index 22d63b973c..c39a8ff9ba 100644 --- a/src/mainboard/intel/cannonlake_rvp/bootblock.c +++ b/src/mainboard/intel/elkhartlake_crb/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include void bootblock_mainboard_init(void) { diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.fmd b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd new file mode 100644 index 0000000000..05f45922e2 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x57F000 + } + SI_BIOS@0x600000 0xA00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl similarity index 53% rename from src/mainboard/intel/cannonlake_rvp/dsdt.asl rename to src/mainboard/intel/elkhartlake_crb/dsdt.asl index 5a06a45ddd..9dd33a8ab7 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl @@ -1,33 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include + DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision + 0x20110725 /* OEM revision */ ) { - #include + #include - // global NVS and variables + /* global NVS and variables */ #include + /* CPU */ + #include + Scope (\_SB) { Device (PCI0) { #include - #include + #include } } - #if CONFIG(CHROMEOS) - // Chrome OS specific - #include - #endif - #include - } diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c new file mode 100644 index 0000000000..c63beb74c3 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c new file mode 100644 index 0000000000..324083411c --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static struct spd_info ehlcrb_spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + ehlcrb_spd_info.read_type = READ_SPD_CBFS; + ehlcrb_spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &ehlcrb_spd_info, half_populated); +} diff --git a/src/mainboard/google/hatch/variants/sushi/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc similarity index 59% rename from src/mainboard/google/hatch/variants/sushi/Makefile.inc rename to src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc index a115aa9c89..70494b5651 100644 --- a/src/mainboard/google/hatch/variants/sushi/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +SPD_SOURCES = ehlcrb # 0b000 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex new file mode 100644 index 0000000000..71e5456542 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/spd.h b/src/mainboard/intel/elkhartlake_crb/spd/spd.h new file mode 100644 index 0000000000..f667e7422e --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/spd.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..bf057651d3 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include + +/* The following 2 functions return the gpio table and fill in the number + * of entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +/* This function returns SPD related FSP-M mainboard configs */ +const struct mb_cfg *variant_memcfg_config(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc new file mode 100644 index 0000000000..641e814351 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb new file mode 100644 index 0000000000..bf66e4b70f --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 08.0 off end # GNA + device pci 09.0 off end # CPU Intel Trace Hub + + device pci 10.0 on end # I2C6 + device pci 10.1 on end # I2C7 + device pci 10.5 on end # Integrated Error Handler + + device pci 11.0 off end # Intel PSE UART0 + device pci 11.1 off end # Intel PSE UART1 + device pci 11.2 off end # Intel PSE UART2 + device pci 11.3 off end # Intel PSE UART3 + device pci 11.4 off end # Intel PSE UART4 + device pci 11.5 off end # Intel PSE UART5 + device pci 11.6 off end # Intel PSE IS20 + device pci 11.7 off end # Intel PSE IS21 + + device pci 12.0 on end # GSPI2 + device pci 12.3 on end # Management Engine UMA Access + device pci 12.4 on end # Management Engine PTT DMA Controller + device pci 12.5 off end # UFS0 + device pci 12.7 off end # UFS1 + + device pci 13.0 off end # Intel PSE GSPI0 + device pci 13.1 off end # Intel PSE GSPI1 + device pci 13.2 off end # Intel PSE GSPI2 + device pci 13.3 off end # Intel PSE GSPI3 + device pci 13.4 off end # Intel PSE GPIO0 + device pci 13.5 off end # Intel PSE GPIO1 + + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI (OTG) + + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.4 on end # Management Engine Interface 3 + device pci 16.5 on end # Management Engine Interface 4 + + device pci 17.0 on end # SATA + + device pci 18.0 off end # Intel PSE I2C7 + device pci 18.1 off end # Intel PSE CAN0 + device pci 18.2 off end # Intel PSE CAN1 + device pci 18.3 off end # Intel PSE QEP0 + device pci 18.4 off end # Intel PSE QEP1 + device pci 18.5 off end # Intel PSE QEP2 + device pci 18.6 off end # Intel PSE QEP3 + + device pci 19.0 on end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 off end # SD + device pci 1a.3 off end # Intel Safety Island + + device pci 1b.0 off end # Intel PSE I2C0 + device pci 1b.1 off end # Intel PSE I2C1 + device pci 1b.2 off end # Intel PSE I2C2 + device pci 1b.3 off end # Intel PSE I2C3 + device pci 1b.4 off end # Intel PSE I2C4 + device pci 1b.5 off end # Intel PSE I2C5 + device pci 1b.6 off end # Intel PSE I2C6 + + device pci 1c.0 on end # RP1 (pcie0 single VC) + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.3 on end # RP4 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) + device pci 1c.5 on end # RP6 (pcie2 multi VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1d.0 off end # Intel PSE IPC (local host to PSE) + device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 + device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.3 off end # Intel PSE DMA0 + device pci 1d.4 off end # Intel PSE DMA1 + device pci 1d.5 off end # Intel PSE DMA2 + device pci 1d.6 off end # Intel PSE PWM + device pci 1d.7 off end # Intel PSE ADC + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 on end # GSPI1 + device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.6 on end # HPET + device pci 1e.7 on end # IOAPIC + + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 off end # Intel cAVS/HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI (flash & TPM) + device pci 1f.7 off end # PCH Intel Trace Hub + end +end diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c new file mode 100644 index 0000000000..003a6a557e --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ToDo: Fill gpio configurations */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* ToDo: Fill early gpio configurations */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c new file mode 100644 index 0000000000..8a2b8f9217 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &ehlcrb_lpddr4x_memcfg_cfg; +} diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index 9568641fcf..9858fda223 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -8,16 +8,16 @@ Method(_PTS,1) { // NVS has a flag to determine USB policy in S3 if (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 if (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl index 39d61b2a13..0a3bb49732 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl @@ -21,10 +21,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,28 +50,28 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (\F2ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -79,7 +79,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -87,7 +87,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -95,7 +95,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -103,7 +103,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -119,20 +119,20 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -140,20 +140,20 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -161,20 +161,20 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -182,20 +182,20 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -203,20 +203,20 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 302966a7d6..f0b11c6721 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -3,12 +3,11 @@ #include #include #include -#include #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -44,7 +43,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; - - // Stumpy has no arms^H^H^H^HEC. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 8c19c753b1..7301ef9d5d 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -4,99 +4,71 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size - -#547 437 r 0 unused +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 3b4ee6532a..b2f4e6b544 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -17,13 +17,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 8b9744f60a..8cd857fa68 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 119346efb7..a2aaf33bb0 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl index d18004d82b..0f4cc02689 100644 --- a/src/mainboard/intel/galileo/dsdt.asl +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20160220 // OEM revision diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 8ed2afff3a..172dfa2e97 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -1,7 +1,7 @@ config BOARD_INTEL_BASEBOARD_GLKRVP def_bool n - select SOC_INTEL_GLK + select SOC_INTEL_GEMINILAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -45,7 +45,6 @@ config CHROMEOS config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select EC_GOOGLE_CHROMEEC_SWITCHES if GLK_CHROME_EC config MAINBOARD_DIR @@ -68,10 +67,6 @@ config MAINBOARD_FAMILY string default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 315cf7c30f..f87b96282e 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index d110c281a2..05a8d2d405 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -19,6 +19,7 @@ config MAINBOARD_PART_NUMBER config ENABLE_FSP_MEMORY_DOWN bool "Enable Memory Down" default n + select HAVE_SPD_IN_CBFS help Select this option to enable Memory Down function. diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index c51bd69872..c3f90dac6b 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -8,12 +8,8 @@ #include #include -extern const unsigned char AmlCode[]; - -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Disable USB ports in S5 */ gnvs->s5u0 = 0; gnvs->s5u1 = 0; diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 4cab4cdf8a..875e664ecc 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index fbad79836f..0373c01c60 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -12,7 +12,7 @@ /* * Define platform specific Memory Down Configure structure. * - * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG + * If CONFIG(ENABLE_FSP_MEMORY_DOWN) is enabled, the MEMORY_DOWN_CONFIG * structure should be customized to match the design. * * .SlotState indicates the memory down state of the specific channel/DIMM. diff --git a/src/mainboard/intel/harcuvar/spd/Makefile.inc b/src/mainboard/intel/harcuvar/spd/Makefile.inc index 55a6aef7a8..ec07cfb845 100644 --- a/src/mainboard/intel/harcuvar/spd/Makefile.inc +++ b/src/mainboard/intel/harcuvar/spd/Makefile.inc @@ -2,23 +2,8 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do echo -e -n "\\x$$c"; \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) spd.bin-position := $(CONFIG_SPD_LOC) -spd.bin-type := spd diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index a70bb5f39b..a66c10b032 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -15,8 +15,7 @@ uint8_t *mainboard_find_spd_data() spd_index = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 2743384967..69559edcea 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -4,11 +4,11 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select EC_ACPI - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index a3c93e2c5f..4beeabae4d 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -46,8 +46,4 @@ DefinitionBlock( #endif #include - - // Mainboard specific - #include "acpi/mainboard.asl" - } diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc index 3114eebaf5..8e3ce25085 100644 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = empty # 0b000 SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 SPD_SOURCES += empty # 2b010 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 40f17cebe5..10284d411f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -152,9 +152,6 @@ chip soc/intel/icelake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" @@ -280,10 +277,12 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid @@ -309,7 +308,7 @@ chip soc/intel/icelake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index c00df81863..286753a820 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index b12c0f7b6c..cbee3ce65d 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -152,9 +152,6 @@ chip soc/intel/icelake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" @@ -280,10 +277,12 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid @@ -309,7 +308,7 @@ chip soc/intel/icelake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index c00df81863..286753a820 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index b56e22a35c..7bfd15878c 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -3,18 +3,24 @@ if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DPTF_USE_EISA_HID select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_JASPERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU config MAINBOARD_DIR string @@ -53,7 +59,6 @@ config CHROMEOS select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig.name b/src/mainboard/intel/jasperlake_rvp/Kconfig.name index 5c7a0077d8..68419ac1f5 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig.name +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig.name @@ -7,5 +7,5 @@ config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC" select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select EC_GOOGLE_CHROMEEC_SWITCHES + select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index a1cd12c136..2ac1b07bef 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -17,7 +17,6 @@ ramstage-y += board_id.c smm-y += smihandler.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.h b/src/mainboard/intel/jasperlake_rvp/board_id.h index 55b4f52d53..85c7c85f40 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.h +++ b/src/mainboard/intel/jasperlake_rvp/board_id.h @@ -3,7 +3,6 @@ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ - /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 827e4484ca..e4e0b242e0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,42 +1,45 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x100000 - WP_RO@0x6d0000 0x330000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x32c000 { + RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x23c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index f47424f996..83ef3af4e8 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -45,12 +45,5 @@ DefinitionBlock( } #endif - /* Camera */ - #include - #include - - /* Mainboard specific */ - #include "acpi/mainboard.asl" - } diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 3b9dff990a..315d47d2b0 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -3,10 +3,14 @@ #include #include #include +#include #include +#include #include #include +#define SERIAL_IO_PCR_GPPRVRW4 0x60C + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -14,6 +18,9 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA)) + pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index 3c8040c7c2..ef1eaabd90 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,5 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = jslrvp # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl deleted file mode 100644 index 14139981a9..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C5) -{ - PowerResource (FCPR, 0x00, 0x0000) - { - Name (STA, Zero) - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - If ((STA == Zero)) - { - /* Enable CLK1 */ - MCON(1, 1) // Clock 1, 19.2MHz - /* Pull PWREN(GPIO R6) high */ - STXS(GPP_D4) - Sleep(5) /* 5 us */ - /* Pull RST(GPIO H12) low */ - CTXS(GPP_C19) - Sleep(5) /* 5 us */ - /* Pull RST high */ - STXS(GPP_C19) - Sleep(5) /* 5 us */ - STA = 1 - } - } - - Method (_OFF, 0, Serialized) /* _OFF: Power Off */ - { - If ((STA == One)) - { - /* Pull RST low */ - CTXS(GPP_C19) - /* Pull PWREN low */ - CTXS(GPP_D4) - /* Disable CLK0 */ - MCOF(1) /* Clock 1 */ - STA = 0 - } - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA) - } - } - - Device (CAM1) - { - Name (_HID, "OVTI5675") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02 - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 0x1AD27480 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } - - Device (VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hadware ID */ - - Name (_UID, 0x03) /* _UID: Unique ID */ - - Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ - { - I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ - { - FCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package(0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9714" - } - } - }) - } -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl deleted file mode 100644 index 48650c9360..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl deleted file mode 100644 index cebf15e753..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (_SB.PCI0.IPU0) -{ - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C5.CAM1, - Zero, - Zero - } - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl deleted file mode 100644 index 013b26f3c6..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) // _ADR: Address - - Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name - } -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 14ca4a5abd..abb5dc83a1 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -55,6 +55,9 @@ chip soc/intel/jasperlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" @@ -91,7 +94,7 @@ chip soc/intel/jasperlake [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" @@ -119,12 +122,15 @@ chip soc/intel/jasperlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" + # Add PL1 and PL2 values + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + # Enable S0ix register "s0ix_enable" = "1" @@ -146,16 +152,67 @@ chip soc/intel/jasperlake .sda_hold = 36, } }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, + .speed = I2C_SPEED_FAST, + }, }" + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 05.0 on end #IPU + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device + + device pci 05.0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 @@ -239,45 +296,47 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end end # I2C #0 Audio device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 @@ -289,18 +348,110 @@ chip soc/intel/jasperlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 Cam 0 - device pci 19.1 on end # I2C #5 Cam 1 and VCM + device pci 19.0 on # I2C #4 Cam 0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI2740"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + end + device pci 19.1 on # I2C #5 Cam 1 and VCM + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + device i2c 0C on end + end + end + device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 - WLAN + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 - NVMe + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -314,7 +465,7 @@ chip soc/intel/jasperlake end # GSPI #1 device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index d67f4a44e4..21e25ab896 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -31,6 +31,9 @@ static const struct pad_config gpio_table[] = { /* PMC_PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), @@ -76,9 +79,18 @@ static const struct pad_config gpio_table[] = { /* CAM2_PWREN */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* CAM1_PWREN */ + PAD_CFG_GPO(GPP_D5, 0, PLTRST), + /*LAN_RST_N*/ PAD_CFG_GPO(GPP_D6, 1, PLTRST), + /* I2C4B_SDA */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF3), + + /* I2C4B_SCL */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* AVS_I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), @@ -97,6 +109,9 @@ static const struct pad_config gpio_table[] = { /* I2C5_SCL */ PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + /* IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), + /* IMGCLKOUT_1 */ PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl deleted file mode 100644 index 318b0dea04..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 434e9dd86a..bea9cd80d4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -42,7 +43,7 @@ static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { /* Baseboard Rcomp target values */ .rcomp_targets = {0, 0, 0, 0, 0}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ @@ -87,7 +88,7 @@ static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = { */ .rcomp_targets = {80, 40, 40, 40, 30}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index d7209c58da..fcce402d85 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 @@ -43,10 +43,6 @@ config MAINBOARD_FAMILY string default "Intel_Kblrvp" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ @@ -84,4 +80,9 @@ config DIMM_SPD_SIZE config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n if BOARD_INTEL_KBLRVP3 + default n if BOARD_INTEL_KBLRVP7 + endif diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index 763163afe7..af3ae57c8d 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -8,8 +8,6 @@ #define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC4 50 - - Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index fa55794139..26108a2592 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -23,46 +23,45 @@ Scope (\_SB.PCI0.I2C2) Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP1) + AVP1 = 1 } Else { - Store (0, AVP1) + AVP1 = 0 } } @@ -163,9 +162,9 @@ Scope (\_SB.PCI0.I2C2) Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -197,9 +196,9 @@ Scope (\_SB.PCI0.I2C2) Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -220,26 +219,26 @@ Scope (\_SB.PCI0.I2C2) Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 2 */ - If (LLess (VSIC, 2)) { + If (VSIC < 2) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { VSIO = 3 } - Increment (VSIC) + VSIC++ } } @@ -251,18 +250,18 @@ Scope (\_SB.PCI0.I2C2) PowerResource (OVTH, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -270,7 +269,7 @@ Scope (\_SB.PCI0.I2C2) Sleep(3) VACT = 1 - if (LNotEqual (ACVA, 109)) { + if (ACVA != 109) { /* Set ANA at 2.8152V */ ACVA = 109 } @@ -279,7 +278,7 @@ Scope (\_SB.PCI0.I2C2) \_SB.PCI0.I2C2.PMIC.CLKE() VDCT = 1 - if (LNotEqual (DCVA, 12)) { + if (DCVA != 12) { /* Set CORE at 1.2V */ DCVA = 12 } @@ -293,8 +292,8 @@ Scope (\_SB.PCI0.I2C2) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) @@ -319,17 +318,17 @@ Scope (\_SB.PCI0.I2C2) PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -338,7 +337,7 @@ Scope (\_SB.PCI0.I2C2) /* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { + if (VCMV != 109) { /* Set VCM value at 2.8152 V */ VCMV = 109 @@ -351,8 +350,8 @@ Scope (\_SB.PCI0.I2C2) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -522,46 +521,45 @@ Scope (\_SB.PCI0.I2C3) Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP2) + AVP2 = 1 } Else { - Store (0, AVP2) + AVP2 = 0 } } @@ -669,9 +667,9 @@ Scope (\_SB.PCI0.I2C3) Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -703,9 +701,9 @@ Scope (\_SB.PCI0.I2C3) Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -726,13 +724,13 @@ Scope (\_SB.PCI0.I2C3) Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { VSIO = 0 - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { VSIO = 3 } Release (MUTV) @@ -743,15 +741,15 @@ Scope (\_SB.PCI0.I2C3) PowerResource (OVFI, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 0)) { + If (AVP2 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { + if (AX2V != 52) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 @@ -761,7 +759,7 @@ Scope (\_SB.PCI0.I2C3) \_SB.PCI0.I2C3.PMIC.CLKE() VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { + if (AX1V != 19) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } @@ -778,8 +776,8 @@ Scope (\_SB.PCI0.I2C3) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 1)) { + If (AVP2 == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C3.PMIC.CLKD() Sleep(2) diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 354f488736..4f3773a3ee 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -41,7 +41,4 @@ DefinitionBlock( #endif #include - - // Mainboard specific - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index a3fb285d54..79206e00c8 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -10,7 +10,6 @@ #include #include "board_id.h" - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index d04269969a..887e4f16fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = rvp3 # 0b000 Dual Channel 4GB SPD_SOURCES += empty # 0b001 SPD_SOURCES += empty # 0b010 diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b14fe31db6..e17c8b71f3 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -16,31 +16,17 @@ chip soc/intel/skylake # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" + register "HeciEnabled" = "0" + register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PchHdaVcType" = "Vc1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "2" @@ -130,6 +116,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -168,7 +155,7 @@ chip soc/intel/skylake device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index 0417543d31..4f7f002bff 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -60,7 +60,7 @@ static const struct pad_config gpio_table[] = { /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* EC_HID_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), /* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), @@ -72,14 +72,14 @@ static const struct pad_config gpio_table[] = { /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* GPP_A23 */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), /* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP), /* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP), /* HSJ_MIC_DET */ /* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), -/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* M.2 BT UART wake */ PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP), /* WIFI_CLK_REQ */ /* KEPLR_CLK_REQ */ /* SRCCLKREQ3# */ /* GPP_B8 */ @@ -88,9 +88,9 @@ static const struct pad_config gpio_table[] = { /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES), +/* GPP_B_14_SPKR */ PAD_CFG_GPI_SMI(GPP_B14, NONE, DEEP, EDGE_SINGLE, INVERT), /* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP), /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), @@ -167,14 +167,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), /* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP), /* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP), -/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP), +/* I2C2_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, DEEP), /* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP), /* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP), /* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP), -/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F9, NONE, DEEP), /* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP), /* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), -/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES), +/* EMMC_CMD */ PAD_CFG_GPI_SCI(GPP_F12, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), @@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = { /* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), /* GPP_F23 */ -/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP), +/* SD_CMD */ PAD_CFG_GPI_APIC_HIGH(GPP_G0, DN_20K, DEEP), /* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* SD_DATA2 */ PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT), /* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), -/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP), +/* SD_WP */ PAD_CFG_GPI_APIC_HIGH(GPP_G7, NONE, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP), -/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* TBD */ PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT), /* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), /* TBD */ /* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP), -/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES), +/* TBD */ PAD_CFG_GPI_SCI(GPP_G18, NONE, DEEP, EDGE_SINGLE, INVERT), /* TBD */ /* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP), -/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP), +/* TBD */ PAD_CFG_GPI_APIC_HIGH(GPP_G21, DN_20K, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP), @@ -240,7 +240,7 @@ static const struct pad_config gpio_table[] = { /* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), -/* DDSP_HPD_3 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDSP_HPD_3 */ PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT), /* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), /* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fa502834af..ad7c4abdba 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,15 +1,8 @@ chip soc/intel/skylake # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" - register "IoBufferOwnership" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -50,8 +43,6 @@ chip soc/intel/skylake # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1" @@ -84,7 +75,6 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -115,15 +105,13 @@ chip soc/intel/skylake .tdp_pl2_override = 60, }" - # Power Limit Related - register "PowerLimit4" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" device domain 0 on + device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA device pci 19.1 on end # I2C #5 device pci 1e.1 on end # UART #1 @@ -131,6 +119,7 @@ chip soc/intel/skylake device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard + device pci 1f.3 on end # Intel HDA device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 1ed86b74f9..e0292cfa86 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -28,35 +28,35 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), -/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), -/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* V0.85A_VID0 */ PAD_NC(GPP_B0, NONE), +/* V0.85A_VID1 */ PAD_NC(GPP_B1, NONE), /* GP_VRALERTB */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT0 */ PAD_NC(GPP_B5, NONE), /* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), @@ -67,22 +67,22 @@ static const struct pad_config gpio_table[] = { /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), /* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* TBT_CIO */ PAD_CFG_NC(GPP_B17), -/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* TBT_CIO */ PAD_NC(GPP_B17, NONE), +/* SLOT1_WAKE */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, PLTRST), /* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), @@ -91,8 +91,8 @@ static const struct pad_config gpio_table[] = { /* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -117,35 +117,35 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), /* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP), /* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, PLTRST), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), @@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* UIM_SIM_DET */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -186,7 +186,7 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01458..397155b789 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,13 +7,7 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0201" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "0" - register "HeciEnabled" = "0" - register "PmTimerDisabled" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" + register "DspEnable" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -98,8 +92,6 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -124,6 +116,8 @@ chip soc/intel/skylake }" device domain 0 on + device pci 05.0 on end # SA IMGU + device pci 14.3 on end # Camera device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 @@ -134,5 +128,6 @@ chip soc/intel/skylake device pnp 0c31.0 on end end end # LPC Interface + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index a658b91545..ff4647f1d2 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -17,7 +17,6 @@ #define IO_EXPANDER_P2DOUT 0x06 #define IO_EXPANDER_1_ADDR 0x23 - /* GPE_EC_WAKE */ #define GPE_EC_WAKE GPE0_LAN_WAK @@ -49,10 +48,10 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), /* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), @@ -60,33 +59,33 @@ static const struct pad_config gpio_table[] = { /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* ISH_GP5 */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP), /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES), -/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES), -/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES), +/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, PLTRST, EDGE_SINGLE, INVERT), +/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_SCI(GPP_B17, UP_20K, PLTRST, EDGE_SINGLE, INVERT), +/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, EDGE_SINGLE, INVERT), /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), /* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, DEEP), /* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), @@ -121,13 +120,13 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), /* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, DN_20K, DEEP), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST), @@ -139,15 +138,15 @@ static const struct pad_config gpio_table[] = { /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), -/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), @@ -171,7 +170,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -183,7 +182,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -200,7 +199,6 @@ static const struct pad_config early_gpio_table[] = { /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), }; - #endif #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 07d7385943..e649ed72e7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake # SATA port 0 - register "EnableSata" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" @@ -13,10 +12,6 @@ chip soc/intel/skylake # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" - # FSP Configuration - register "HeciEnabled" = "0" - register "PmTimerDisabled" = "1" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -118,25 +113,25 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index efa9d67aa0..37193cfcda 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -44,28 +44,28 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), -/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), -/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), -/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), -/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), +/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), +/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), +/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), +/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), /* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), /* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), /* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), +/* PCHHOTB */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), @@ -85,8 +85,8 @@ static const struct pad_config gpio_table[] = { /* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), -/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), /* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), @@ -94,14 +94,14 @@ static const struct pad_config gpio_table[] = { /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), -/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1), -/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES), +/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, UP_20K, DEEP,NF1), +/* SATA_DEVSLP_3 */ PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, INVERT), /* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* SATA_SCLOCK */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), -/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP), -/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP), -/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP), +/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC_HIGH(GPP_F12, NONE, DEEP), +/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, DEEP), +/* H_SKTOCC_N */ PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP), /* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), @@ -110,44 +110,44 @@ static const struct pad_config gpio_table[] = { /* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), /* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), /* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), -/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), -/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* FAN_TACH_2 */ PAD_CFG_GPI_SCI(GPP_G2, NONE, DEEP, EDGE_SINGLE, INVERT), +/* FAN_TACH_3 */ PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT), /* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), -/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP), -/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES), +/* FAN_TACH_5 */ PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, DEEP), +/* FAN_TACH_6 */ PAD_CFG_GPI_SCI(GPP_G6, NONE, DEEP, EDGE_SINGLE, INVERT), /* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), -/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* GSXDOUT */ PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT), /* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), -/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES), +/* GSXDIN */ PAD_CFG_GPI_SCI(GPP_G14, NONE, DEEP, EDGE_SINGLE, INVERT), /* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), /* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), -/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP), +/* NMIB */ PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, DEEP), /* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), -/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP), -/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), +/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, DEEP), +/* P_INTF_N */ PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), /* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), /* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), /* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), /* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), -/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP), -/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP), -/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP), +/* SML3CLK */ PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, DEEP), +/* SML3DATA */ PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, DEEP), +/* SML3ALERTB */ PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, DEEP), /* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), /* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), /* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), -/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDSP_HPD_1 */ PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, DN_20K, DEEP, NF1), /* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), -/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -165,6 +165,5 @@ static const struct pad_config early_gpio_table[] = { /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), }; - #endif #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 91abfe6f03..115e338199 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -5,11 +5,7 @@ chip soc/intel/skylake register "deep_s3_enable_dc" = "0" # FSP Configuration - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -127,7 +123,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "1" # Enable SSIC for WWAN - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -174,6 +169,7 @@ chip soc/intel/skylake device pci 1e.2 on end # GSPI #0 device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC + device pci 1e.6 off end # SDXC device pci 1f.0 on #chip drivers/pc80/tpm # device pnp 0c31.0 on end diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d7706d16a0..cf67ca18d0 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE + select HAVE_SPD_IN_CBFS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -40,10 +41,6 @@ config MAINBOARD_FAMILY string default "Intel_Kunimitsu" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ @@ -59,4 +56,8 @@ config INCLUDE_NHLT_BLOBS config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl deleted file mode 100644 index d9fdd023f1..0000000000 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index acd197bff4..85586cb137 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -17,34 +17,16 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -187,6 +169,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -256,7 +239,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 90a559471a..4bf179351b 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -33,7 +33,4 @@ DefinitionBlock( #include #include - - // Mainboard specific - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 3317f113e7..2cd0196137 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -51,138 +51,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -210,17 +210,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index b7c4d5551c..4136c368fd 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -44,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables( if (nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - /* 4 Channel DMIC array. */ if (nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 9ecf28d1fe..6a14c293a5 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0000 Dual Channel 4GB SPD_SOURCES += hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0001 Single Channel 2GB SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF-1G-1866 # 0b0010 Dual Channel 4GB @@ -20,18 +18,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index a1faf7e7e2..8674512ff4 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -49,7 +49,6 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) static const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 }; - if (mem_cfg_id == K4E6E304EE_MEM_ID) { memcpy(rcomp_strength_ptr, StrengthendRcompTarget, sizeof(StrengthendRcompTarget)); @@ -69,8 +68,7 @@ uintptr_t mainboard_get_spd_data(void) printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 6c872b186e..e2f2f8e559 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index bda108ed1b..0d6a863e44 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 6c872b186e..e2f2f8e559 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index bda108ed1b..0d6a863e44 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f94cd54fd5..e7aaae50c8 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -5,16 +5,14 @@ if BOARD_INTEL_SKLSDLBRK config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CONSOLE_SERIAL select DRIVERS_UART - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION @@ -34,10 +32,6 @@ config MAINBOARD_FAMILY string default "Intel_SaddleBrook" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index cc55ccfc71..5a92ae07c9 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -3,100 +3,54 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -#544 440 r 0 unused - # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7c2a7d7f35..0da097fa4a 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -14,23 +14,13 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -140,8 +130,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1" @@ -175,16 +163,6 @@ chip soc/intel/skylake # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0a" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -227,6 +205,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index f705b5488c..b5e9a0b076 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index 255f278db3..a574ac589d 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -75,7 +75,7 @@ static const struct pad_config gpio_table[] = { /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), /* GSPI0_CS# */ /* GPP_B15 */ /* WLAN_PCIE_WAKE */ /* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), @@ -84,11 +84,11 @@ static const struct pad_config gpio_table[] = { /* CODEC_SPI_CLK */ /* CODEC_SPI_MISO */ /* CODEC_SPI_MOSI */ -/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF1), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, DN_20K, DEEP, NF1), /* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0ALERT# */ /* GPP_C5 */ diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index f96add75b7..0d055ab0d2 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -8,7 +8,6 @@ #include "spd/spd.h" #include - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig new file mode 100644 index 0000000000..a822bcc350 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -0,0 +1,25 @@ +if BOARD_INTEL_SHADOWMOUNTAIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "intel/shadowmountain" + +config MAINBOARD_FAMILY + string + default "Intel_shadowmountain" + +config MAINBOARD_PART_NUMBER + string + default "shadowmountain" + +endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name new file mode 100644 index 0000000000..e489039400 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SHADOWMOUNTAIN + bool "shadowmountain" diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt new file mode 100644 index 0000000000..7e0cccf015 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake Pre-CEP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl new file mode 100644 index 0000000000..10d08e26e2 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..fbd7d72f9f --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index d2dacd5eaf..6965066ab0 100644 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 75 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 25d6a37a05..97795cd0ea 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -10,10 +10,8 @@ #include #include "onboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 8c2244fa55..80a4d218a4 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -3,108 +3,57 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index 0f4cdfaf6b..06229ede4b 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -12,8 +12,6 @@ * by pad number and which community it is in. */ - - /* family number in high byte and inner pad number in lowest byte */ void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 91337878c2..77b07d2e38 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -4,14 +4,9 @@ chip soc/intel/braswell # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ chip soc/intel/braswell register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ chip soc/intel/braswell register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index e059c8266d..309a21721f 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index fb82091b62..d3d6168d15 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -68,7 +68,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -135,7 +134,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -205,7 +203,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -235,7 +232,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index dd40848948..82f46294cb 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -20,7 +20,6 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 35bc012d17..bc2e7a278a 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -25,7 +25,6 @@ #define BOARD_TOUCH_IRQ 184 - /* Audio: Gpio index in SW bank */ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ @@ -43,8 +42,6 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 0 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ - - /* SD CARD gpio */ #define SDCARD_CD 81 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 867c88eb14..9df542dfa6 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -7,17 +7,23 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI - select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select HAVE_SPD_IN_CBFS + select SOC_INTEL_CSE_LITE_SKU + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS bool @@ -25,9 +31,9 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB + select VBOOT_EARLY_EC_SYNC config MAINBOARD_DIR string @@ -46,7 +52,8 @@ config GBB_HWID config MAINBOARD_PART_NUMBER string - default "tglrvp" + default "tglrvpu" if BOARD_INTEL_TGLRVP_UP3 + default "tglrvpy" if BOARD_INTEL_TGLRVP_UP4 config MAINBOARD_FAMILY string @@ -76,7 +83,7 @@ config DIMM_SPD_SIZE int default 512 -choice TGL_EC +choice prompt "ON BOARD EC" default TGL_CHROME_EC help @@ -98,9 +105,16 @@ endchoice config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA config UART_FOR_CONSOLE int default 2 + +config DRIVER_TPM_SPI_BUS + default 0x2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 54 # GPE0_DW1_22 (GPP_C22) + endif diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 065bd4c3a2..2ca32f3760 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -14,10 +14,10 @@ romstage-y += board_id.c smm-y += smihandler.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/tglrvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b053de..ffecfd2256 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -154,7 +154,7 @@ Scope (\_SB.PCI0.I2C3) Name (STA, Zero) Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(0,1) /* Clock 0, 19.2MHz */ @@ -170,12 +170,12 @@ Scope (\_SB.PCI0.I2C3) STXS(GPP_C15) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -187,7 +187,7 @@ Scope (\_SB.PCI0.I2C3) /* Pull PWREN low */ CTXS(GPP_B23) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -369,7 +369,7 @@ Scope (\_SB.PCI0.I2C5) Name (STA, Zero) Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(1,1) /* Clock 1, 19.2MHz */ @@ -389,12 +389,12 @@ Scope (\_SB.PCI0.I2C5) STXS(GPP_H12) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -410,7 +410,7 @@ Scope (\_SB.PCI0.I2C5) CTXS(GPP_R6) #endif - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index c8d6cd2c07..f3dee88627 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -3,7 +3,6 @@ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ - /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304d36..1e2e7920cf 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index e34fd58cc7..a93f008b08 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -7,13 +7,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -27,6 +27,7 @@ DefinitionBlock( #include #include #include + #include } } @@ -48,10 +49,6 @@ DefinitionBlock( #include - /* Mainboard specific */ - #include "acpi/mainboard.asl" - /* Camera */ - #include #include "acpi/mipi_camera.asl" } diff --git a/src/mainboard/intel/tglrvp/ec.c b/src/mainboard/intel/tglrvp/ec.c new file mode 100644 index 0000000000..14760017ef --- /dev/null +++ b/src/mainboard/intel/tglrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 7708b85188..82877ed28e 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,8 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + mainboard_ec_init(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c index 8c9444cb59..3d8107fed8 100644 --- a/src/mainboard/intel/tglrvp/smihandler.c +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex index 2ff9ed382e..4bf724e827 100644 --- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index 8dd1507544..df52042e07 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,21 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = Micron-MT53D1G64D8SQ-046 SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex index 40fccaa76d..946bcc0015 100644 --- a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -1,11 +1,13 @@ -23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +20,6 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex index 945b2e8e06..946bcc0015 100644 --- a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -1,11 +1,13 @@ 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 -48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +20,6 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index 52db2afcf3..4303faf0d2 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -41,6 +41,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ @@ -54,6 +56,9 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index de0adf6cff..b61276c0c1 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,7 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a95a..57f36ab9d9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -9,15 +9,18 @@ chip soc/intel/tigerlake # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" + + # Enable heci1 communication + register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 @@ -29,11 +32,9 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector - # CPU replacement check - register "CpuReplacementCheck" = "1" + # CPU replacement check + register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -85,14 +86,14 @@ chip soc/intel/tigerlake register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -117,9 +118,23 @@ chip soc/intel/tigerlake # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" #HD Audio register "PchHdaDspEnable" = "1" @@ -134,6 +149,10 @@ chip soc/intel/tigerlake # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -142,7 +161,7 @@ chip soc/intel/tigerlake }, .i2c[2] = { .speed = I2C_SPEED_FAST, - }, + }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, @@ -155,7 +174,29 @@ chip soc/intel/tigerlake #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A04:U22/0x9A14:U42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 @@ -186,10 +227,12 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic @@ -254,9 +297,22 @@ chip soc/intel/tigerlake device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 off end # GSPI0 0xA0AA - device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1e.2 on end # GSPI0 0xA0AA + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" + device spi 0 on end + end + end # GSPI1 0xA0AB + device pci 1f.0 on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden # PMC 0xA0A1 # The pmc_mux chip driver is a placeholder for the @@ -268,14 +324,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "7" register "usb3_port_number" = "4" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 44575067dc..51b301d3cf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,6 +54,11 @@ static const struct pad_config gpio_table[] = { /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + + /* EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */ + + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* AUDIO_PWREN */ }; /* Early pad configuration in bootblock */ @@ -89,6 +94,25 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* TPM */ + /* B19 : GSPI1_CS0B */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c119..70833eefac 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -9,31 +9,33 @@ chip soc/intel/tigerlake # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" + + # Enable heci1 communication + register "HeciEnabled" = "1" # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector - # CPU replacement check - register "CpuReplacementCheck" = "1" + # CPU replacement check + register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -66,9 +68,16 @@ chip soc/intel/tigerlake # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + register "DdiPortCHpd" = "0" + register "DdiPortCDdc" = "0" register "DdiPort1Hpd" = "1" - register "DdiPort1Ddc" = "1" + register "DdiPort1Ddc" = "0" + register "DdiPort2Hpd" = "1" + register "DdiPort2Ddc" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -81,14 +90,14 @@ chip soc/intel/tigerlake register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -113,9 +122,23 @@ chip soc/intel/tigerlake # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" #HD Audio register "PchHdaDspEnable" = "1" @@ -130,6 +153,10 @@ chip soc/intel/tigerlake # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -151,13 +178,35 @@ chip soc/intel/tigerlake #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up4 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A02:Y22/0x9A12:Y42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D @@ -168,7 +217,7 @@ chip soc/intel/tigerlake device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 on # SensorHUB 0xA0FC @@ -182,10 +231,12 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic @@ -250,11 +301,45 @@ chip soc/intel/tigerlake device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 off end # GSPI0 0xA0AA - device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1e.2 on end # GSPI0 0xA0AA + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" + device spi 0 on end + end + end # GSPI1 0xA0AB + device pci 1f.0 on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 + device pci 1f.2 hidden # PMC 0xA0A1 + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "6" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end # PMC device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 679933a004..77da5cce5c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -51,6 +51,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */ + + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* AUDIO_PWREN */ }; /* Early pad configuration in bootblock */ @@ -86,6 +90,25 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* TPM */ + /* B19 : GSPI1_CS0B */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 2f6b21e9ce..7ac5f1c9aa 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -25,11 +25,6 @@ config MAINBOARD_PART_NUMBER string default "WHITETIP MOUNTAIN 2" - -config MAX_CPUS - int - default 16 - config VGA_BIOS_FILE string default "pci8086,0166.rom" diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 62eb09aff6..c6d4ce8a7b 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,16 +2,13 @@ #include #include -#include #include #include #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -23,18 +20,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tmax = MAX_TEMPERATURE; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index da1b185c7e..77ff74375e 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -4,85 +4,54 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04d54..29041aaeca 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,24 +9,6 @@ chip soc/intel/broadwell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -34,33 +16,45 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index f9d4fe8c3a..7d58eb6930 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include // CPU #include @@ -25,8 +25,8 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include - #include + #include + #include } } diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 69553cbaef..17462ac4f4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 1ef94778a3..e83c0874e5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index bacb7b11aa..9c8d0f6e47 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 006837aaf7..1a527d6178 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG - select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 52c2fbbec1..6970dfc45e 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index cf758b1c38..282c603fb8 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -4,153 +4,125 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 12 gfx_uma_size +411 3 e 12 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 11 cmos_defaults_loaded -#937 11 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 11 cmos_defaults_loaded # coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature -968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 -971 1 e 1 lpt - -#972 12 r 0 unused +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 +971 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed -#8 2 Thermal +8 0 Disabled +8 1 Speed +#8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (°C/°F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 -#10 10 60/140 -#10 11 63/145 -#10 12 66/150 -#10 13 69/156 -#10 14 72/161 -#10 15 75/167 -11 0 No -11 1 Yes -12 0 1M -12 1 4M -12 2 8M -12 3 16M -12 4 32M -12 5 48M -12 6 64M +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +11 0 No +11 1 Yes +12 0 1M +12 1 4M +12 2 8M +12 3 16M +12 4 32M +12 5 48M +12 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 9b5ba55018..4ea20e5be5 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 37bb96828f..90221981dd 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -63,7 +63,7 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ + pnp_write_config(dev, PNP_IDX_MSC5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); @@ -73,9 +73,10 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ - pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, PNP_IDX_MSC1, 0x00); /* GPIO bit 2 is 0 */ + /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_EN, 0x03); dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index a5062e45b4..26a800aa5a 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -16,10 +16,8 @@ static u16 hwm_base = 0xa00; #define FAN_CRUISE_CONTROL_DISABLED 0 #define FAN_CRUISE_CONTROL_SPEED 1 #define FAN_CRUISE_CONTROL_THERMAL 2 - #define FAN_SPEED_5625 0 - struct fan_speed { u8 fan_in; u16 fan_speed; diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig new file mode 100644 index 0000000000..dd8f4fac48 --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_KONTRON_BSL6_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select EXCLUDE_NATIVE_SD_INTERFACE + select NO_FADT_8042 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select EC_KONTRON_KEMPLD + select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_I2C_NCT7802Y + +config BOARD_KONTRON_BSL6_OPTIONS + bool + select BOARD_KONTRON_BSL6_COMMON + select HAVE_ACPI_RESUME + +config BOARD_KONTRON_BOXER26_OPTIONS + bool + select BOARD_KONTRON_BSL6_COMMON + select DRIVERS_I2C_LM96000 + select SECUNET_DMI + +if BOARD_KONTRON_BSL6_COMMON + +config MAINBOARD_DIR + string + default "kontron/bsl6" + +config MAINBOARD_VENDOR + string + default "Siemens" if BOARD_SIEMENS_BOXER26 + +config MAINBOARD_PART_NUMBER + string + default "bSL6" if BOARD_KONTRON_BSL6 + default "Boxer26" if BOARD_SIEMENS_BOXER26 + +config VARIANT_DIR + string + default "bsl6" if BOARD_KONTRON_BSL6 + default "boxer26" if BOARD_SIEMENS_BOXER26 + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config CBFS_SIZE + hex + default 0x600000 if BOARD_SIEMENS_BOXER26 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name new file mode 100644 index 0000000000..90bf1c474f --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -0,0 +1,7 @@ +config BOARD_KONTRON_BSL6 + bool "COMe-bSL6" + select BOARD_KONTRON_BSL6_OPTIONS + +config BOARD_SIEMENS_BOXER26 + bool "COMe-bSL6 on Siemens/Boxer26" + select BOARD_KONTRON_BOXER26_OPTIONS diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc new file mode 100644 index 0000000000..5164272950 --- /dev/null +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/kontron/bsl6/acpi/ec.asl b/src/mainboard/kontron/bsl6/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/kontron/bsl6/acpi/superio.asl b/src/mainboard/kontron/bsl6/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/kontron/bsl6/board_info.txt b/src/mainboard/kontron/bsl6/board_info.txt new file mode 100644 index 0000000000..b1c4635055 --- /dev/null +++ b/src/mainboard/kontron/bsl6/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Board name: COMe-bSL6 +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/kontron/bsl6/bootblock.c b/src/mainboard/kontron/bsl6/bootblock.c new file mode 100644 index 0000000000..7dacd4aa8c --- /dev/null +++ b/src/mainboard/kontron/bsl6/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + kempld_enable_uart_for_console(); +} diff --git a/src/mainboard/kontron/bsl6/cmos.default b/src/mainboard/kontron/bsl6/cmos.default new file mode 100644 index 0000000000..2b66561959 --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.default @@ -0,0 +1,10 @@ +debug_level=Debug + +hyper_threading=Enable + +power_on_after_fail=Enable + +boot_devices=(hd0,0);(hd1,0) +boot_default=0xff + +cmos_defaults_loaded=No diff --git a/src/mainboard/kontron/bsl6/cmos.layout b/src/mainboard/kontron/bsl6/cmos.layout new file mode 100644 index 0000000000..2ace8ae00f --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 +442 1 e 2 ethernet3 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb new file mode 100644 index 0000000000..910a49da75 --- /dev/null +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + # VR Settings Configuration for 2 Domains + #+----------------+-------+-------+ + #| Domain/Setting | VCC | VCCGT | + #+----------------+-------+-------+ + #| Psi1Threshold | 20A | 20A | + #| Psi2Threshold | 5A | 5A | + #| Psi3Threshold | 1A | 1A | + #| Psi3Enable | 1 | 1 | + #| Psi4Enable | 1 | 1 | + #| ImonSlope | 0 | 0 | + #| ImonOffset | 0 | 0 | + #| IccMax | 55A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | + #| AcLoadline | 2.1 | 3.1 | + #| DcLoadline | 2.1 | 3.1 | + #+----------------+-------+-------+ + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(55), + .voltage_limit = 1520, + .ac_loadline = 210, + .dc_loadline = 210, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Vendor set Psys Pmax to 30W + register "power_limits_config" = "{ + .psys_pmax = 30, + }" + + # TODO + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on # USB xHCI + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug + end + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + # SataPortsDevSlp not supported + end + device pci 1d.0 on # PCI Express Port 9 (COMe 0) + register "PcieRpEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 (COMe 1) + register "PcieRpEnable[9]" = "1" + end + device pci 1d.2 on # PCI Express Port 11 (COMe 2) + register "PcieRpEnable[10]" = "1" + end + device pci 1f.0 on # LPC Interface + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # EC/kempld at 0xa80/0xa81 + register "gen1_dec" = "0x00000a81" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/kontron/kempld + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + device generic 0.0 on end # UART #0 + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on # SMBus + chip drivers/i2c/nct7802y + device i2c 0x2e on end + end + end + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl new file mode 100644 index 0000000000..3be51152d6 --- /dev/null +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/kontron/bsl6/gpio.c b/src/mainboard/kontron/bsl6/gpio.c new file mode 100644 index 0000000000..c99a53d4b3 --- /dev/null +++ b/src/mainboard/kontron/bsl6/gpio.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A21, 1, DEEP), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B6, 1, DEEP), + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* XXX: C6 not readable */ + /* XXX: C7 not readable */ + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), + + PAD_CFG_GPO(GPP_D0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), + PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D19, 0, DEEP), + PAD_CFG_GPO(GPP_D20, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), + PAD_CFG_GPO(GPP_D22, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), + PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + PAD_CFG_GPO(GPP_G0, 1, PLTRST), + PAD_CFG_GPO(GPP_G1, 1, PLTRST), + PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), + PAD_CFG_GPO(GPP_G4, 1, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G7, 1, DEEP), + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G22, 1, PLTRST), + PAD_CFG_GPO(GPP_G23, 1, PLTRST), + + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO(GPP_H1, 1, DEEP), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), + PAD_CFG_GPO(GPP_H4, 1, DEEP), + PAD_CFG_GPO(GPP_H5, 1, DEEP), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 1, DEEP), + PAD_CFG_GPO(GPP_H8, 1, DEEP), + PAD_CFG_GPO(GPP_H9, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPD1, 0, PWROK), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/bsl6/include/mainboard/gpio.h b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h new file mode 100644 index 0000000000..ef2a21c418 --- /dev/null +++ b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/kontron/bsl6/include/variant.h b/src/mainboard/kontron/bsl6/include/variant.h new file mode 100644 index 0000000000..4f65da5fb1 --- /dev/null +++ b/src/mainboard/kontron/bsl6/include/variant.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include + +void variant_memory_init_params(FSPM_UPD *); + +#endif diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c new file mode 100644 index 0000000000..771c6aae7b --- /dev/null +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void init_mainboard(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c new file mode 100644 index 0000000000..0cb7b06375 --- /dev/null +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Rcomp resistor */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp target */ +static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; + + get_option(&memory_params->HyperThreading, "hyper_threading"); + + variant_memory_init_params(mupd); +} diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads new file mode 100644 index 0000000000..ea4750aa13 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP2, HDMI2, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb new file mode 100644 index 0000000000..88335ae285 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "SkipExtGfxScan" = "1" + + device domain 0 on + device pci 1f.0 on + chip ec/kontron/kempld + device generic 1.0 on # I2C + chip drivers/i2c/lm96000 + register "vin[1].low" = "1140*100/116" + register "vin[1].high" = "1260*100/116" + register "vin[0].low" = "1810" + register "vin[0].high" = "2000" + register "vin[2].low" = "3140" + register "vin[2].high" = "3470" + register "vin[3].low" = "4750" + register "vin[3].high" = "5250" + register "vin[4].low" = "11400" + register "vin[4].high" = "12600" + + register "fan_in[0].low" = "3240" + register "fan_in[1].low" = "3240" + + register "fan[0].mode" = "LM96000_FAN_MANUAL" + register "fan[0].spinup" = "LM96000_SPINUP_250MS" + register "fan[0].freq" = "LM96000_PWM_25_7KHZ" + register "fan[0].duty_cycle" = "100" + + register "fan[1].mode" = "LM96000_FAN_MANUAL" + register "fan[1].spinup" = "LM96000_SPINUP_250MS" + register "fan[1].freq" = "LM96000_PWM_25_7KHZ" + register "fan[1].duty_cycle" = "100" + + device i2c 0x2c on end + end + chip drivers/secunet/dmi + device i2c 0x57 on end # Serial EEPROM + end + end + end + end # LPC Interface + device pci 1f.4 on + chip drivers/i2c/nct7802y + register "fan[1].mode" = "FAN_MANUAL" + register "fan[1].duty_cycle" = "100" + end + end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE # Debug + end +end diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c new file mode 100644 index 0000000000..f1409e0b42 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ + char nvram_var[] = "ethernetx"; + unsigned int i; + + for (i = 0; i < 3; ++i) { + u8 eth_enable = 1; + nvram_var[sizeof(nvram_var) - 2] = '1' + i; + get_option(ð_enable, nvram_var); + if (!eth_enable) { + printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i); + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8)); + } + } +} diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads new file mode 100644 index 0000000000..0cf02cd3b2 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb new file mode 100644 index 0000000000..718eff7f00 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) + register "PcieRpEnable[ 0]" = "1" + register "PcieRpEnable[ 1]" = "1" + register "PcieRpEnable[ 2]" = "1" + register "PcieRpEnable[ 3]" = "1" + register "PcieRpEnable[11]" = "1" + + register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "SataPortsEnable[3]" = "1" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1f.4 on + chip drivers/i2c/nct7802y + register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_DUTY" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_PECI_0" + register "fan[1].smart.table" = "{ { 30, 40 }, + { 40, 48 }, + { 50, 60 }, + { 60, 76 } }" + register "fan[1].smart.critical_temp" = "80" + end + end # SMBus + end +end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c new file mode 100644 index 0000000000..c9122c1c24 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ +} diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 3012052a24..f22470cf9b 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -4,7 +4,7 @@ #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index d63c75deb1..914ad6df6a 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -4,128 +4,101 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -401 3 e 12 gfx_uma_size - -#404 3 r 0 unused +400 1 e 2 hyper_threading +401 3 e 12 gfx_uma_size # coreboot config options: southbridge -407 1 e 1 nmi -408 2 e 7 power_on_after_fail -410 2 e 11 sata_mode +407 1 e 1 nmi +408 2 e 7 power_on_after_fail +410 2 e 11 sata_mode # coreboot config options: additional mainboard options -412 4 e 10 systemp_type -416 7 h 0 fan1_min -424 7 h 0 fan1_max -432 7 h 0 fan2_min -440 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader -448 64 r 0 write_protected_by_bios -512 328 s 0 boot_devices -840 8 h 0 boot_default -848 1 e 9 cmos_defaults_loaded -849 1 e 2 ethernet1 -850 1 e 2 ethernet2 -#851 5 r 0 unused +448 64 r 0 write_protected_by_bios +512 328 s 0 boot_devices +840 8 h 0 boot_default +848 1 e 9 cmos_defaults_loaded +849 1 e 2 ethernet1 +850 1 e 2 ethernet2 # coreboot config options: mainboard specific options -856 2 e 8 fan1_mode -858 2 r 0 fan1_reserved -860 2 e 8 fan2_mode -862 2 r 0 fan2_reserved -864 16 h 0 fan1_target -880 16 h 0 fan2_target +856 2 e 8 fan1_mode +858 2 r 0 fan1_reserved +860 2 e 8 fan2_mode +862 2 r 0 fan2_reserved +864 16 h 0 fan1_target +880 16 h 0 fan2_target # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Auto -8 1 PWM -8 2 Speed -8 3 Thermal -9 0 No -9 1 Yes -10 0 None -10 1 AMD -10 2 LM75@90 -10 3 GPIO16 -10 4 LM75@9e -11 0 AHCI -11 1 Compatible -11 2 Legacy -12 0 32M -12 1 64M -12 2 96M -12 3 128M -12 4 160M -12 5 192M -12 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Auto +8 1 PWM +8 2 Speed +8 3 Thermal +9 0 No +9 1 Yes +10 0 None +10 1 AMD +10 2 LM75@90 +10 3 GPIO16 +10 4 LM75@9e +11 0 AHCI +11 1 Compatible +11 2 Legacy +12 0 32M +12 1 64M +12 2 96M +12 3 128M +12 4 160M +12 5 192M +12 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index db0c9e24f9..71c9611639 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -8,13 +8,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "0" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "0" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "0" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index f736688289..434a1de2c7 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 669577ef0d..d1aa9d5dc8 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -35,7 +36,7 @@ void bootblock_mainboard_early_init(void) const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_conf_state(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ + pnp_write_config(dev, PNP_IDX_EN, 0x03); /* Enable GPIO2+3 */ pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are GPIO27, 26, 25, 24 */ pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32, @@ -46,7 +47,8 @@ void bootblock_mainboard_early_init(void) /* Values can only be changed, when devices are enabled. */ pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */ pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ - pnp_write_config(dev, 0xf3, 0x40); /* Disable suspend LED during normal operation */ + /* Disable suspend LED during normal operation */ + pnp_write_config(dev, PNP_IDX_MSC3, 0x40); pnp_exit_conf_state(dev); } @@ -54,15 +56,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig new file mode 100644 index 0000000000..f53746d7a9 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig @@ -0,0 +1,58 @@ +if BOARD_KONTRON_COME_MAL10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_CRB_TPM + select MAINBOARD_HAS_LIBGFXINIT + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE + +config MAINBOARD_DIR + string + default "kontron/mal10" + +# TODO: Add a new carrier boards here +choice + prompt "Carrier board" + default BOARD_KONTRON_T10_TNI + help + This option sets the type of carrier board to be used with + the Kontron mAL10 COMe module. + +config BOARD_KONTRON_T10_TNI + bool "Kontron i-T10-TNIx" + help + By selecting this option, the target ROM image will be built for + the Kontron Ref.Carrier-i T10-TNI carrier board. + +endchoice + +config VARIANT_DIR + string + default "mal10" + +config CARRIER_DIR + string + default "t10-tni" if BOARD_KONTRON_T10_TNI + +config MAINBOARD_PART_NUMBER + string + default "COMe-mAL10" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "carriers/$(CONFIG_CARRIER_DIR)/overridetree.cb" + +endif diff --git a/src/mainboard/kontron/mal10/Kconfig.name b/src/mainboard/kontron/mal10/Kconfig.name new file mode 100644 index 0000000000..ac54165880 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_KONTRON_COME_MAL10 + bool "COMe-mAL10" diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc new file mode 100644 index 0000000000..7fbab00337 --- /dev/null +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += carriers/$(CARRIER_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/kontron/mal10/acpi/dptf.asl b/src/mainboard/kontron/mal10/acpi/dptf.asl new file mode 100644 index 0000000000..240da453bd --- /dev/null +++ b/src/mainboard/kontron/mal10/acpi/dptf.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/kontron/mal10/board_info.txt b/src/mainboard/kontron/mal10/board_info.txt new file mode 100644 index 0000000000..d93d125911 --- /dev/null +++ b/src/mainboard/kontron/mal10/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/bootblock.c b/src/mainboard/kontron/mal10/bootblock.c new file mode 100644 index 0000000000..5c40e2dc6c --- /dev/null +++ b/src/mainboard/kontron/mal10/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void init_cpld(void) +{ + /* Set up LPC decoding for CPLD I/O port ranges */ + lpc_open_pmio_window(0x0A80, 2); + + /* Enable console serial ports */ + lpc_io_setup_comm_a_b(); + kempld_enable_uart_for_console(); +} + +void bootblock_mainboard_early_init(void) +{ + variant_early_gpio_configure(); + init_cpld(); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc new file mode 100644 index 0000000000..c291d45ebd --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += gpio.c diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt new file mode 100644 index 0000000000..2902dc4b85 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-Ref-Carrier-i-T10-TNI +Board URL: https://www.kontron.com/products/boards-and-standard-form-factors/com-express/starterkits-and-evaluation-boards/come-ref.carrier-i-t10-tni.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c new file mode 100644 index 0000000000..674b209317 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_5, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_6, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_7, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_8, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_9, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_10, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_11, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_12, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_13, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_14, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_17, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_19, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_20, DN_20K, DEEP, OFF, TxDRxE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, DRIVER), + /* GPIO_22 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_22, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_23 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_23, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE : PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_23, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_24 - GPIO (DW0: 0x40800102, DW1: 0x00027100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, LEVEL, TxDRxE, DISPUPD, ACPI), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_24, + PAD_RESET(DEEP) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5), + PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), + PAD_CFG_GPIO_BIDIRECT(GPIO_28, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_29, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_30, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_31, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_32, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_33, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_34, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_35, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_36, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_37, DN_20K, DEEP, HIZCRx0, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_38, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_39, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_40, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_41, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_48, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_49, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPIO_62, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_63, 0, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_64, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_65, 0, NONE, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_66, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_67, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_68, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_69, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_70, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_71, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_72, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_73, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP), + PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, UP_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_189, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_190, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_191, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_192, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_193, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_194, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_195, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_197, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_198, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_199, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_PWRGOOD, NONE, DEEP, NF1), + PAD_CFG_NF(PMIC_RESET_B, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_213, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_214, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_215, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_STDBY, DN_20K, DEEP, NF1), + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_74, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_75, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_76, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_77, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_78, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_79, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_80, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_81, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_82, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_83, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2), + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_88, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_89, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_90, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_91, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_92, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_104, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_105, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_106, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_109, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_110, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_111, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_112, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_113, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_116, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_117, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_118, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_119, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_120, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_121, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_122, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_123, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_124, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_125, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_126, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_127, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_128, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_129, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_130, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_131, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_132, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_133, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_134, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_135, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_137, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_138, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_139, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_146, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_147, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_148, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_149, DN_20K, DEEP, NF3), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_150, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_151, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_152, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_153, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_154, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_155, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_209, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_AC_PRESENT, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S3_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S4_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SUSCLK, NONE, DEEP, NF1), + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUS_STAT_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUSPWRDNACK, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_205, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_206, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_207, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_208, NONE, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_166, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_167, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_168, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_169, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_170, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_171, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER), + PAD_CFG_NF_IOSSTATE(GPIO_178, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void carrier_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb new file mode 100644 index 0000000000..9248c0c21c --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC1)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "usb3_port[1]" = "PORT_EN(OC0)" + + device domain 0 on + device pci 0e.0 off end # TODO: Audio + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "0" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "0" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "0" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "0" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "1" + end + end +end diff --git a/src/mainboard/kontron/mal10/cmos.default b/src/mainboard/kontron/mal10/cmos.default new file mode 100644 index 0000000000..55cac796c6 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.default @@ -0,0 +1,6 @@ +baud_rate = 115200 +debug_level = Info +power_on_after_fail = Enable +boot_devices = (hd0,0);(hd1,0) +boot_default = 0xff +cmos_defaults_loaded = No diff --git a/src/mainboard/kontron/mal10/cmos.layout b/src/mainboard/kontron/mal10/cmos.layout new file mode 100644 index 0000000000..cc5359f4b7 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.layout @@ -0,0 +1,55 @@ +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/mal10/dsdt.asl b/src/mainboard/kontron/mal10/dsdt.asl new file mode 100644 index 0000000000..78d2c285a5 --- /dev/null +++ b/src/mainboard/kontron/mal10/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + #include + + Scope (\_SB) + { + Device(PCI0) + { + #include + #include + } + #include "acpi/dptf.asl" + #include + #include + } +} diff --git a/src/mainboard/kontron/mal10/include/carrier/gpio.h b/src/mainboard/kontron/mal10/include/carrier/gpio.h new file mode 100644 index 0000000000..9466b24dba --- /dev/null +++ b/src/mainboard/kontron/mal10/include/carrier/gpio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CARRIER_GPIO_H +#define CARRIER_GPIO_H + +#include + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void carrier_gpio_configure(void); + +#endif /* CARRIER_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/include/variant/gpio.h new file mode 100644 index 0000000000..a3ff7c0c31 --- /dev/null +++ b/src/mainboard/kontron/mal10/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +void variant_early_gpio_configure(void); + +#endif /* VARIANT_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/mal10.fmd b/src/mainboard/kontron/mal10/mal10.fmd new file mode 100644 index 0000000000..21d780a066 --- /dev/null +++ b/src/mainboard/kontron/mal10/mal10.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC 0x1000 + SI_BIOS 0xefe000 { + IFWI 0x2ff000 + OBB 0xbff000 { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + CONSOLE 0x20000 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 + } +} diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c new file mode 100644 index 0000000000..3d259d8ea7 --- /dev/null +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + carrier_gpio_configure(); + + /* + * CPU Power Management Configuration correspond to the BIOS Setup menu settings + * in the AMI UEFI v112. + * TODO: move these FSP options to device tree + */ + silconfig->EnableCx = 1; /* Enable CPU power states */ + silconfig->C1e = 1; /* enable Enhanced C-states */ + /* + * Attention! Do not change PkgCStateLimit! This causes spikes in the power + * consumption of the SoC when the system comes out of power saving mode, and + * voltage sagging at the output of DC-DC converters on the COMe module. In the + * AMI BIOS Setup shows this parameter, but does not allow changing it. + */ + silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */ + silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */ + silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */ + silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */ + silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */ + silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */ + silconfig->PmSupport = 1; /* GT PM Support */ + silconfig->EnableRenderStandby = 1; /* enable render standby */ + silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */ + silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */ + + /* Override High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* Override APIC options */ + silconfig->IoApicId = 1; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; +} diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c new file mode 100644 index 0000000000..dba78f7909 --- /dev/null +++ b/src/mainboard/kontron/mal10/romstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.Profile = 0x19; + mupd->FspmConfig.MemoryDown = 0; + mupd->FspmConfig.DDR3LPageSize = 2; + mupd->FspmConfig.DualRankSupportEnable = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.DIMM0SPDAddress = 0xA0; + mupd->FspmConfig.DIMM1SPDAddress = 0xA4; + + mupd->FspmConfig.RmtCheckRun = 1; + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0; + mupd->FspmConfig.EnhancePort8xhDecoding = 1; + + mupd->FspmConfig.MsgLevelMask = 0; + mupd->FspmConfig.MrcDataSaving = 0; + mupd->FspmConfig.MrcFastBoot = 1; + + mupd->FspmConfig.PrimaryVideoAdaptor = 2; +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc new file mode 100644 index 0000000000..4b48156a52 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += gpio.c diff --git a/src/mainboard/kontron/mal10/variants/mal10/board_info.txt b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt new file mode 100644 index 0000000000..ce668920f5 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-mAL10 +Board URL: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/variants/mal10/data.vbt b/src/mainboard/kontron/mal10/variants/mal10/data.vbt new file mode 100644 index 0000000000..25be675548 Binary files /dev/null and b/src/mainboard/kontron/mal10/variants/mal10/data.vbt differ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb new file mode 100644 index 0000000000..1421cb7905 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + register "enable_vtd" = "1" + register "dptf_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # iGPU + device pci 03.0 off end # Iunit + device pci 0d.0 on end # P2SB + device pci 0d.1 on end # PMC + device pci 0d.2 on end # SPI + device pci 0d.3 on end # Shared SRAM + device pci 0e.0 on end # Audio + device pci 0f.0 on end # TXE + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + end + device pci 14.1 off # PCIe-B 2 (Root Port 1) + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + end + device pci 15.0 on end # XHCI + device pci 15.1 off end # XDCI + device pci 16.0 off end # I2C 0 + device pci 16.1 off end # I2C 1 + device pci 16.2 off end # I2C 2 + device pci 16.3 off end # I2C 3 + device pci 17.0 off end # I2C 4 + device pci 17.1 off end # I2C 5 + device pci 17.2 off end # I2C 6 + device pci 17.3 off end # I2C 7 + device pci 18.0 off end # HSUART 0 + device pci 18.1 off end # HSUART 1 + device pci 18.2 off end # UART 2 + device pci 18.3 off end # UART 3 + device pci 19.0 off end # SPI 0 + device pci 19.1 off end # SPI 1 + device pci 19.2 off end # SPI 2 + device pci 1a.0 on end # PWM + device pci 1b.0 on end # SDCARD + device pci 1c.0 on end # eMMC + device pci 1d.0 off end # UFS + device pci 1e.0 off end # SDIO + device pci 1f.0 on # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip ec/kontron/kempld + device generic 0.0 on # UART #0 + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + end + device generic 0.1 on # UART #1 + register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" + end + device generic 1.0 on # I2C + register "i2c_frequency" = "KEMPLD_I2C_FREQ_FAST_MODE_400KHZ" + end + end + end # LPC + device pci 1f.1 on # SMBUS + chip drivers/i2c/nct7802y # Hardware Monitor + register "sensors" = "{ \ + .local_enable = 1, \ + .rtd[2] = RTD_VOLTAGE_MODE, \ + .rtd[1] = RTD_VOLTAGE_MODE, \ + .rtd[0] = RTD_THERMISTOR_MODE, \ + }" + # FAN0 + register "fan[0].mode" = "FAN_SMART" + register "fan[0].smart.mode" = "SMART_FAN_RPM" + register "fan[0].smart.tempsrc" = "TEMP_SOURCE_REMOTE_1" + register "fan[0].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[0].smart.critical_temp" = "95" + # FAN1 + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_RPM" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_LOCAL" + register "fan[1].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[1].smart.critical_temp" = "95" + device i2c 0x2e on end + end + end # SMBUS + end + chip drivers/crb + # Resource allocation reserves memory. + # This is required for correct use of TPM + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads new file mode 100644 index 0000000000..fee0ce85c0 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, eDP, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c new file mode 100644 index 0000000000..3986776870 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pad_config gpio_table[] = { + /* SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + + /* SMBUS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + + /* LPC */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void variant_early_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 2cca51e0a5..21a0941ccd 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -6,7 +6,6 @@ #include #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index 9ec85a07f0..910d2e66a8 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index bf6a881405..6f91672106 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -19,12 +19,6 @@ Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, @@ -37,20 +31,6 @@ Package(){0x0005FFFF, 2, INTD, 0 }, Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, @@ -75,12 +55,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, }) Name(APR0, Package(){ @@ -97,12 +71,6 @@ Package(){0x0002FFFF, 2, 0, 16 }, Package(){0x0002FFFF, 3, 0, 17 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, Package(){0x0004FFFF, 1, 0, 17 }, @@ -115,20 +83,6 @@ Package(){0x0005FFFF, 2, 0, 19 }, Package(){0x0005FFFF, 3, 0, 16 }, - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, @@ -153,12 +107,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, }) Name(PS2, Package(){ @@ -205,107 +153,13 @@ Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, }) - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, }) diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c0a87ddb21..19add3ac9b 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index fa4f10be44..04ffe7e52b 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -5,51 +5,50 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -#400 8 r 8 reserved for century byte -408 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +#400 8 r 8 reserved for century byte +408 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index fde51d906d..57b535afc5 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -5,9 +5,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index 8339626b9f..d900c94069 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -26,7 +26,6 @@ static void mainboard_enable(struct device *dev) if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); - } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a5c1..5d8eb4d3aa 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -124,43 +124,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 9028555c1e..40b9a535b6 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -1,5 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + Method(_WAK,1) { /* ME may not be up yet. */ @@ -12,10 +25,3 @@ Method(_WAK,1) /* Not implemented. */ Return(Package(){0,0}) } - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/l520/acpi/superio.asl +++ b/src/mainboard/lenovo/l520/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 6f69102dbc..9669ca219f 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index aecd7f3bca..e96915d2d1 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -4,116 +4,91 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused -440 8 h 0 volume +432 3 e 11 gfx_uma_size +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 93390c9112..6505d139c1 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "0" @@ -14,12 +14,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index df39d49f72..b0f258ec4d 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index 68e682fdbc..b5c6395f51 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -21,7 +21,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index f1e575f0a6..fde744ff4d 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 888feac2cc..20a9096395 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -12,7 +12,6 @@ Device (EC0) OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset(0x00), , 1, , 1, HKFA, 1, // FN lock (Hotkey / FN row toggle) diff --git a/src/mainboard/lenovo/s230u/acpi/superio.asl b/src/mainboard/lenovo/s230u/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/s230u/acpi/superio.asl +++ b/src/mainboard/lenovo/s230u/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e6082d5..eb92d78ae8 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" @@ -13,12 +13,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x041e041e" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 7633c91bf5..fb51412bd8 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 155b02eec1..434b58c6a3 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -70,8 +70,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) die("SPD data not found."); diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 5b3ecf1da6..809ea45d27 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 14b5a8bbe9..643c106aff 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -7,7 +7,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ @@ -46,6 +46,5 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 8d6b608cde..24038a7f87 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -4,119 +4,94 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 240 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 9 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 wlan -415 1 e 1 trackpoint -416 8 h 0 volume -424 1 e 1 fn_ctrl_swap -425 1 e 1 sticky_fn -426 1 e 1 power_management_beeps -427 1 e 1 low_battery_beep -428 1 e 1 uwb - +411 1 e 9 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan +415 1 e 1 trackpoint +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -432 512 s 0 boot_devices -944 8 h 0 boot_default +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -952 2 e 12 hybrid_graphics_mode -954 4 e 11 gfx_uma_size +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 unused +984 16 h 0 check_sum # RAM initialization internal data -1024 128 r 0 read_training_results +1024 128 r 0 read_training_results # VBOOT -1152 128 r 0 vbnv +1152 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -10 0 AHCI -10 1 Compatible -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +10 0 AHCI +10 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 5414f8b628..b8163e710b 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ static int poll_clk_stable(pnp_devfn_t dev, int timeout) { /* Enable 14.318MHz CLK on CLKIN */ pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) return 1; diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index a1325fb27a..3967a90536 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t410/acpi/superio.asl +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index f957656b51..45ae4d3e45 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout index f3e1559a01..71d65cee8d 100644 --- a/src/mainboard/lenovo/t410/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -4,111 +4,85 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on -#423 1 r 1 unused +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on # coreboot config options: northbridge -424 3 e 10 gfx_uma_size -#427 5 r 0 unused -432 2 e 12 hybrid_graphics_mode +424 3 e 10 gfx_uma_size +432 2 e 12 hybrid_graphics_mode # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only -12 0 Integrated Only -12 1 Discrete Only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d4b7..af770dc01c 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "1" register "gpu_panel_power_down_delay" = "600" diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index b794cb69a8..40a57cb578 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20130325 /* OEM revision */ @@ -20,7 +20,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 6856f5b3d9..445ef7afc0 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -32,7 +32,7 @@ static void hybrid_graphics_init(void) early_hybrid_graphics(&igd, &peg); /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); if (peg) @@ -42,9 +42,9 @@ static void hybrid_graphics_init(void) reg32 |= DEVEN_IGD; else /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } void mainboard_pre_raminit(void) diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index ade22ff980..08b5d2f909 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -23,7 +23,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { case 0x18: diff --git a/src/mainboard/lenovo/t420/acpi/superio.asl b/src/mainboard/lenovo/t420/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t420/acpi/superio.asl +++ b/src/mainboard/lenovo/t420/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index ce5f04d47f..e1d15be56b 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -4,124 +4,99 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 13 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5a96..ffd1d2491f 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index b04691dcc2..3df1e37f3e 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index b974f2a757..e72ef43617 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ b/src/mainboard/lenovo/t420s/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index ce5f04d47f..e1d15be56b 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -4,124 +4,99 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 13 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c32a3..4b9567579f 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index b974f2a757..e72ef43617 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index c9a48ad345..40b9a535b6 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -1,5 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + Method(_WAK,1) { /* ME may not be up yet. */ @@ -9,12 +22,6 @@ Method(_WAK,1) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + /* Not implemented. */ Return(Package(){0,0}) } - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t430/acpi/superio.asl +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index 5cb1fd38d5..29d8eba786 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index b38a91b189..dd51c36854 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -4,123 +4,98 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 95eaa99337..cafc2dffb2 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms @@ -16,12 +16,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 87eab8c120..0287cd9027 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads index b04691dcc2..3df1e37f3e 100644 --- a/src/mainboard/lenovo/t430/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 6b34105826..6f1568d16c 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S + select HAVE_SPD_IN_CBFS if BOARD_LENOVO_T431S # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/acpi/superio.asl b/src/mainboard/lenovo/t430s/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t430s/acpi/superio.asl +++ b/src/mainboard/lenovo/t430s/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 1697806aa3..02c1ea78df 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -4,121 +4,96 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 1 e 1 enable_dual_graphics -#436 4 r 0 unused -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 1 e 1 enable_dual_graphics +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706eb0c..d9ececa7a1 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms @@ -20,13 +20,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index ae95e6c8d6..41bef2f70e 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 923e379dcd..54236a1ffc 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -29,8 +28,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index 38d83d6be8..3926956fb7 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -1,18 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_4gb # 0b0010 4GiB -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 32dde6fdcc..b84576de5e 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -3,7 +3,6 @@ if BOARD_LENOVO_THINKPAD_T440P config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 - select CPU_INTEL_HASWELL select EC_LENOVO_H8 select H8_HAS_PRIMARY_FN_KEYS select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index c235d1228a..93016a8a85 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 222ab40fb8..464d24277b 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -4,102 +4,78 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: northbridge -435 1 e 1 enable_dual_graphics -#437 3 r 0 unused -440 8 h 0 volume +435 1 e 1 enable_dual_graphics +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible # Haswell ThinkPads have no Thinklight -#10 0 Both -10 1 Keyboard -#10 2 Thinklight only -10 3 None -13 0 Disable -13 1 AC and battery -13 2 AC only +#10 0 Both +10 1 Keyboard +#10 2 Thinklight only +10 3 None +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 58f0ca82a1..8db28cbfae 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,22 +4,17 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" - register "gpu_panel_power_backlight_off_delay" = "1" - register "gpu_panel_power_backlight_on_delay" = "1" - register "gpu_panel_power_cycle_delay" = "6" - register "gpu_panel_power_down_delay" = "500" - register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight_pwm_hz" = "220" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 220, + }" register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" device lapic 0x0 on end device lapic 0xacac off end end @@ -38,15 +33,6 @@ chip northbridge/intel/haswell register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8a" - register "pirqd_routing" = "0x89" - register "pirqe_routing" = "0x86" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x87" - register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" device pci 14.0 on end # xHCI Controller diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 8f89092d09..9a54673ec8 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision @@ -24,7 +24,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c index e0c19dc316..fac8400223 100644 --- a/src/mainboard/lenovo/t440p/hda_verb.c +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -5,8 +5,9 @@ const u32 cim_verb_data[] = { 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ 0x17aa220e, /* Subsystem ID */ - 12, /* Number of 4 dword sets */ + 32, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x17aa220e), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), @@ -18,6 +19,26 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x05350000, 0x0534601a, 0x05450000, 0x05442000, + 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, + 0x05350016, 0x05341ee1, 0x05450016, 0x05441ee1, + 0x05350023, 0x05341f7b, 0x05450023, 0x05441f7b, + 0x05350030, 0x05341fbd, 0x05450030, 0x05441fbd, + 0x05350000, 0x0534e01a, 0x05450030, 0x05441fbd, + 0x02050020, 0x02048014, 0x02050020, 0x02040014, + 0x05350000, 0x0534e01a, 0x05450000, 0x0544e01a, + 0x0205001c, 0x02046800, 0x0205006d, 0x0204aa10, + 0x02050076, 0x02040009, 0x0205006b, 0x02045029, + 0x0205006c, 0x0204a400, 0x02050018, 0x02047208, + 0x0205001a, 0x02049ad2, 0x02050014, 0x02040710, + 0x02050079, 0x02040b40, 0x02050070, 0x02048800, + 0x00b3f410, 0x00c3f11f, 0x00c3f001, 0x015707c0, + 0x0153b080, 0x01470740, 0x0143b000, 0x02050004, + 0x02040080, 0x01470c02, 0x000f0000, 0x000f0000, + 0x02050029, 0x02040050, 0x02050025, 0x0204ebc2, + 0x02050026, 0x02044028, 0x02050029, 0x02040250, + 0x000f0000, 0x000f0000, 0x02050005, 0x0204ff1f, }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index dce3ebd427..de48240e88 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include -#include #include #define GPE_EC_SCI 1 @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t520/acpi/superio.asl +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2dfd682c5a..dd51c36854 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -4,123 +4,98 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 5128d06e4b..296be73181 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t530/acpi/superio.asl +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 4130b5f806..6cd8ac066b 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -4,124 +4,99 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 1b16ca3b2c..7adc0f5c14 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 62fcfe95e6..4a9c6ae740 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 246d15d0c5..2af6365f6f 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -4,117 +4,90 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 7 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: cpu -#945 3 r 0 unused # coreboot config options: ec -948 1 e 1 touchpad -949 1 e 1 bluetooth -950 1 e 1 wwan -951 1 e 1 wlan -952 8 h 0 volume -960 1 e 9 first_battery -961 1 e 1 trackpoint -#962 1 r 0 unused -963 1 e 1 sticky_fn -964 1 e 1 power_management_beeps -965 1 e 1 low_battery_beep +948 1 e 1 touchpad +949 1 e 1 bluetooth +950 1 e 1 wwan +951 1 e 1 wlan +952 8 h 0 volume +960 1 e 9 first_battery +961 1 e 1 trackpoint +963 1 e 1 sticky_fn +964 1 e 1 power_management_beeps +965 1 e 1 low_battery_beep # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 378d673c25..363a43a8ba 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -75,7 +75,7 @@ int dlpc_init(void) /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -102,7 +102,7 @@ static int dock_superio_init(void) /* startup 14.318MHz Clock */ dock_write_register(0x29, 0xa0); /* wait until clock is settled */ - while(!(dock_read_register(0x29) & 0x10) && timeout--) + while (!(dock_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -147,7 +147,6 @@ static int dock_superio_init(void) dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP, 0x00); - /* no GPIO events enabled for PORT0 */ outb(0x00, 0x1622); /* clear GPIO events on PORT0 */ @@ -171,7 +170,7 @@ int dock_connect(void) timeout = 1000; - while(!(inb(DLPC_CONTROL) & 8) && timeout--) + while (!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index bddbb775b5..7875dc6374 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index ad2c58e26a..0a1ae53b72 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -25,7 +25,7 @@ static void early_superio_config(void) pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); /* Enable COM1 */ diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 013c9b0a9d..69ffe33209 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -16,24 +17,32 @@ static void mainboard_smi_brightness_down(void) { - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; - if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) - *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; - } + uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf; + u8 *bar = (void *)(uintptr_t)reg32; + + /* Validate pointer before using it */ + if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t))) + return; + + printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; + if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) + *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; } static void mainboard_smi_brightness_up(void) { - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; - if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) - *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; - } + uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf; + u8 *bar = (void *)(uintptr_t)reg32; + + /* Validate pointer before using it */ + if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t))) + return; + + printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; + if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) + *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; } int mainboard_io_trap_handler(int smif) @@ -90,7 +99,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { /* brightness up */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index 9eef15936a..7206526637 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->cmap = 0x01; /* Enable COM 1 port */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index 4905f1d133..11a078e35c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -4,85 +4,59 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 5 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 4 e 11 gfx_uma_size -#435 549 r 0 unused - +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x131e/acpi/superio.asl +++ b/src/mainboard/lenovo/x131e/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 32394de59a..b9da70dd08 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -4,113 +4,87 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -#421 3 r 0 unused +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea87d..18ed380428 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_up_delay" = "100" register "gpu_panel_power_down_delay" = "100" @@ -20,13 +20,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" - - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" end end diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 3affa49bd3..10dc4ceb0c 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index adb999430c..0bec670a2b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT + select HAVE_SPD_IN_CBFS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index a3d2a0fb64..90a08b081a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -4,120 +4,95 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b3c11ea450..b4d3800aa2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "3000" register "gpu_panel_power_cycle_delay" = "6" @@ -18,13 +18,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 85a9767d1e..a798424146 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index f49a59f8e8..6f18feee91 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -32,8 +32,7 @@ static uint8_t *get_spd_data(int spd_index) size_t spd_file_len; printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index e047c6ee58..d3244d1a9c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -1,20 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = elpida.hex # 0b0000 Single Channel 2GB -SPD_SOURCES += hynix.hex # 0b0001 2GiB -SPD_SOURCES += samsung.hex # 0b0010 4GiB -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +SPD_SOURCES = elpida # 0b0000 Single Channel 2GB +SPD_SOURCES += hynix # 0b0001 2GiB +SPD_SOURCES += samsung # 0b0010 4GiB diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 14b5a8bbe9..643c106aff 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -7,7 +7,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ @@ -46,6 +46,5 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 95c7930fd5..afd5461af5 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -4,115 +4,90 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 240 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 9 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 wlan -415 1 e 1 trackpoint -416 8 h 0 volume -424 1 e 1 fn_ctrl_swap -425 1 e 1 sticky_fn -426 1 e 1 power_management_beeps -427 1 e 1 low_battery_beep -428 1 e 1 uwb +411 1 e 9 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan +415 1 e 1 trackpoint +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -432 512 s 0 boot_devices -944 8 h 0 boot_default +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 unused +984 16 h 0 check_sum # RAM initialization internal data -1024 128 r 0 read_training_results +1024 128 r 0 read_training_results # VBOOT -1152 128 r 0 vbnv - +1152 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -10 0 AHCI -10 1 Compatible -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +10 0 AHCI +10 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 8ab71c8ca1..c05f138c89 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index f957656b51..45ae4d3e45 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 6dc55b24ec..4ca1ade9b4 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -4,109 +4,83 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on -#423 1 r 1 unused +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on # coreboot config options: northbridge -424 3 e 10 gfx_uma_size -#427 5 r 0 unused -432 8 h 0 volume +424 3 e 10 gfx_uma_size +432 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d374cec1a0..6b6543dee3 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "3" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_down_delay" = "250" diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index b794cb69a8..40a57cb578 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20130325 /* OEM revision */ @@ -20,7 +20,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 05a4cf21f4..d8e82fcb74 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index ade22ff980..08b5d2f909 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -23,7 +23,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { case 0x18: diff --git a/src/mainboard/lenovo/x220/acpi/superio.asl b/src/mainboard/lenovo/x220/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x220/acpi/superio.asl +++ b/src/mainboard/lenovo/x220/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 740f57a700..f152b2982a 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -4,120 +4,94 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 12 usb_always_on -#423 1 r 1 unused +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 12 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused -440 8 h 0 volume +432 3 e 11 gfx_uma_size +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da355d..667b280f0c 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index e4c854c734..bb120bfa0e 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,15 +12,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x230/acpi/superio.asl +++ b/src/mainboard/lenovo/x230/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 0f32e9f90c..9669ca219f 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 6a6cdd537b..89891bf0b0 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -4,121 +4,96 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 085b4e137b..de91bbacd5 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 6d37aabc01..b2d0cf20a5 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -5,10 +5,10 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms - register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_up_delay" = "2000" # 200ms device domain 0 on diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 62fcfe95e6..4a9c6ae740 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 70dcd35210..61ab465694 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -4,118 +4,91 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 6 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: cpu -#945 4 r 0 unused # coreboot config options: ec -949 1 e 9 first_battery -950 1 e 1 bluetooth -951 1 e 1 wwan -952 1 e 1 wlan -953 1 e 1 trackpoint -#954 1 r 0 unused -955 1 e 1 sticky_fn -956 1 e 1 power_management_beeps -959 1 e 1 low_battery_beep -960 8 h 0 volume -968 8 h 0 tft_brightness +949 1 e 9 first_battery +950 1 e 1 bluetooth +951 1 e 1 wwan +952 1 e 1 wlan +953 1 e 1 trackpoint +955 1 e 1 sticky_fn +956 1 e 1 power_management_beeps +959 1 e 1 low_battery_beep +960 8 h 0 volume +968 8 h 0 tft_brightness # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 -1056 128 r 0 vbnv +1056 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 25c1aace8e..3abe5c1151 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -72,7 +72,7 @@ int dlpc_init(void) /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -99,7 +99,7 @@ int dock_connect(void) timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while (!(inb(0x164c) & 8) && timeout--) udelay(1000); if (!timeout) { @@ -121,7 +121,7 @@ int dock_connect(void) dock_write_register(0x29, 0x06); /* wait until clock is settled */ timeout = 1000; - while(!(dock_read_register(0x29) & 0x08) && timeout--) + while (!(dock_read_register(0x29) & 0x08) && timeout--) udelay(1000); if (!timeout) diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 8919ead3d5..4d6f0840bb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index fc7394617b..3add1952cd 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -79,7 +79,6 @@ void mainboard_late_rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } - void mainboard_get_spd_map(u8 spd_map[4]) { spd_map[0] = 0x50; diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index f239b4cf1a..b5889db406 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -92,7 +92,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { /* brightness up */ diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index 9c4223ae4b..bfd532a85a 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -44,4 +44,7 @@ config CBFS_SIZE hex default 0x600000 +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 95874bb5fa..9fedde5db8 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -30,16 +30,10 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" @@ -49,34 +43,17 @@ chip soc/intel/skylake register "SataPortsDevSlp[1]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------------+-------+ @@ -189,9 +166,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -216,6 +195,7 @@ chip soc/intel/skylake device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 on end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl index 5b3a5dfc8d..3de4e26b22 100644 --- a/src/mainboard/libretrend/lt1000/dsdt.asl +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ ) { - #include + #include #include #include diff --git a/src/mainboard/libretrend/lt1000/gpio.h b/src/mainboard/libretrend/lt1000/gpio.h index fde917efd9..7e0e0a7348 100644 --- a/src/mainboard/libretrend/lt1000/gpio.h +++ b/src/mainboard/libretrend/lt1000/gpio.h @@ -17,46 +17,46 @@ static const struct pad_config gpio_table[] = { /* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP), /* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), @@ -65,100 +65,100 @@ static const struct pad_config gpio_table[] = { /* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), -/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ -/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* SML0ALERT# */ PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), +/* SML1CLK */ PAD_NC(GPP_C6, NONE), /* RESERVED */ +/* SML1DATA */ PAD_NC(GPP_C7, NONE), /* RESERVED */ /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_NC(GPP_C14, NONE), +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), /* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), /* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), -/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_NC(GPP_C23, NONE), -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), /* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), /* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), -/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), /* SATAXPCI0 */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), /* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -169,14 +169,14 @@ static const struct pad_config gpio_table[] = { /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), -/* BATLOW# */ PAD_CFG_NC(GPD0), +/* BATLOW# */ PAD_NC(GPD0, NONE), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NC(GPD2), +/* LAN_WAKE# */ PAD_NC(GPD2, NONE), /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 0021cfb668..55157eda52 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -1,13 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_LIPPERT_FRONTRUNNER_AF +if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_SMSC_SMSCSUPERIO + select SUPERIO_SMSC_SMSCSUPERIO if BOARD_LIPPERT_FRONTRUNNER_AF + # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. + # The ADLINK ExpressBase-6 baseboard happens to use this SIO: + select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -22,9 +25,19 @@ config MAINBOARD_DIR string default "lippert/frontrunner-af" +config VARIANT_DIR + string + default "frontrunner-af" if BOARD_LIPPERT_FRONTRUNNER_AF + default "toucan-af" if BOARD_LIPPERT_TOUCAN_AF + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "FrontRunner-AF" + default "FrontRunner-AF" if BOARD_LIPPERT_FRONTRUNNER_AF + default "Toucan-AF" if BOARD_LIPPERT_TOUCAN_AF config HW_MEM_HOLE_SIZEK hex @@ -54,4 +67,4 @@ config SB800_AHCI_ROM bool default n -endif # BOARD_LIPPERT_FRONTRUNNER_AF +endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 2a8cba52ab..caf65d1e65 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LIPPERT_FRONTRUNNER_AF bool "FrontRunner-AF aka ADLINK CoreModule2-GF" + +config BOARD_LIPPERT_TOUCAN_AF + bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 9b9e5aeb11..b05b4e8bcb 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -7,15 +7,16 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif -bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/bootblock.c romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c +romstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c +romstage-y += variants/$(VARIANT_DIR)/OemCustomize.c ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c +ramstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c +ramstage-y += variants/$(VARIANT_DIR)/OemCustomize.c +ramstage-y += variants/$(VARIANT_DIR)/mainboard.c # Minimal SEMA watchdog support romstage-y += sema.c diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index 7b73e5db9c..f8b62fa0be 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -365,6 +365,7 @@ Scope(\_SB) { }) Name(PCIB, Package(){ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) /* PCI slots: slot 0, slot 1, slot 2, slot 3 behind Dev14, Fun4. */ Package(){0x0004FFFF, 0, 0, 0x14 }, Package(){0x0004FFFF, 1, 0, 0x15 }, @@ -382,5 +383,20 @@ Scope(\_SB) { Package(){0x0007FFFF, 1, 0, 0x14 }, Package(){0x0007FFFF, 2, 0, 0x15 }, Package(){0x0007FFFF, 3, 0, 0x16 }, +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, +#endif }) } diff --git a/src/mainboard/lippert/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/board_info.txt index 9246cdbc34..4a443cdaf0 100644 --- a/src/mainboard/lippert/frontrunner-af/board_info.txt +++ b/src/mainboard/lippert/frontrunner-af/board_info.txt @@ -1,5 +1,4 @@ Category: half -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 ROM package: SOIC8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index beedaa7930..b076f0a776 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -5,52 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 2b7c11a871..e0804ed159 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ @@ -134,8 +134,7 @@ DefinitionBlock ( PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, + , 1, /* MiscControl */ T1EE, 1, T2EE, 1, Offset(0x01), /* MiscStatus */ @@ -1174,7 +1173,9 @@ DefinitionBlock ( ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) IO(Decode16, 0x0E00, 0x0E00, 1, 0x80) /* SIO runtime regs */ +#endif IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 7d4f1f944d..ba6f0bb0cf 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -37,15 +37,19 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define USB_CONFIG 0x3F +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define USB_CONFIG 0x0F +#endif /** * @def PCI_CLOCK_CTRL @@ -58,7 +62,11 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define PCI_CLOCK_CTRL 0x1F +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define PCI_CLOCK_CTRL 0x1E +#endif /** * @def SATA_CONTROLLER @@ -140,20 +148,28 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define AZALIA_SDIN_PIN 0x02 +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define AZALIA_SDIN_PIN 0x2A +#endif /** * @def GPP_CONTROLLER */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define GPP_CONTROLLER CIMX_OPTION_DISABLED +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define GPP_CONTROLLER CIMX_OPTION_ENABLED +#endif /** * @def GPP_CFGMODE diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/BiosCallOuts.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/OemCustomize.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt new file mode 100644 index 0000000000..00f3dcb22c --- /dev/null +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt @@ -0,0 +1,6 @@ +Category: half +Board URL: https://www.adlinktech.com/Products/PC104SBCs/PC_104_Plus_SBCs/CM2-GF +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lippert/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c similarity index 85% rename from src/mainboard/lippert/frontrunner-af/bootblock.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c index 070da4e7b5..4bb4c10550 100644 --- a/src/mainboard/lippert/frontrunner-af/bootblock.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/frontrunner-af/devicetree.cb rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c similarity index 99% rename from src/mainboard/lippert/frontrunner-af/mainboard.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c index 71d0f415df..e32e125cd2 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c @@ -79,6 +79,7 @@ static void init(struct device *dev) iomux_write8(190, 1); iomux_write8(191, 1); iomux_write8(192, 1); + /* just in case anyone cares */ if (!fch_gpio_state(197)) printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/toucan-af/BiosCallOuts.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/toucan-af/OemCustomize.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c diff --git a/src/mainboard/lippert/toucan-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt similarity index 100% rename from src/mainboard/lippert/toucan-af/board_info.txt rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt diff --git a/src/mainboard/lippert/toucan-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c similarity index 100% rename from src/mainboard/lippert/toucan-af/bootblock.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/toucan-af/devicetree.cb rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/toucan-af/mainboard.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig deleted file mode 100644 index 102b1d7bc7..0000000000 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_LIPPERT_TOUCAN_AF - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. - # The ADLINK ExpressBase-6 baseboard happens to use this SIO: - select SUPERIO_WINBOND_W83627DHG - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - # This erases 28 KB and writes 10 KB register dumps to SPI flash on every - # boot, wasting 3 s and causing wear! Therefore disable S3 for now. - #select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "lippert/toucan-af" - -config MAINBOARD_PART_NUMBER - string - default "Toucan-AF" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n - -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - -config VGA_BIOS_ID - string - default "1002,9802" - -config SB800_AHCI_ROM - bool - default n - -endif # BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name deleted file mode 100644 index 3481f92fba..0000000000 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc deleted file mode 100644 index caabc74565..0000000000 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c - -# Minimal SEMA watchdog support -romstage-y += ../frontrunner-af/sema.c -ramstage-y += ../frontrunner-af/sema.c diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl deleted file mode 100644 index 987ba225c9..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ /dev/null @@ -1,382 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 16 }, - Package(){0x0009FFFF, 2, 0, 17 }, - Package(){0x0009FFFF, 3, 0, 18 }, - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 16 }, - Package(){0x000AFFFF, 2, 0, 17 }, - Package(){0x000AFFFF, 3, 0, 18 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/lippert/toucan-af/acpi/sata.asl b/src/mainboard/lippert/toucan-af/acpi/sata.asl deleted file mode 100644 index 7f305fb17f..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/sata.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/lippert/toucan-af/acpi/superio.asl b/src/mainboard/lippert/toucan-af/acpi/superio.asl deleted file mode 100644 index 490d8c49d5..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/superio.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * SuperI/O devices - */ - -/* PS/2 Keyboard */ -Device(KBC) { - Name(_HID, EISAID("PNP0303")) - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0060, 0x0060, 1, 1) - IO(Decode16, 0x0064, 0x0064, 1, 1) - IRQNoFlags(){1} - }) -} - -/* PS/2 Mouse */ -Device(PS2M) { - Name(_HID, EISAID("PNP0F13")) - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){12} - }) -} diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl deleted file mode 100644 index ca9e002a36..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c deleted file mode 100644 index d8d46d499e..0000000000 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Select the CPU family */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE - -/* Agesa optional capabilities selection */ -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_WHEA FALSE - -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE - -/* Agesa configuration values selection */ -#include - -/* Include the files that instantiate the configuration definitions */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/* Instantiate all solution relevant data */ -#include diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout deleted file mode 100644 index beedaa7930..0000000000 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ /dev/null @@ -1,57 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl deleted file mode 100644 index 5b54b8c90e..0000000000 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ /dev/null @@ -1,1246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_SB) { /* define processor scope */ - Device (C000) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - } - Device (C001) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - } - Device (C002) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - } - Device (C003) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - } - } /* End _SB scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - } - - /* USB controller PME# */ - Method(_L0B) { - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method (_OSC, 4) - { - /* Check for PCI/PCI-X/PCIe GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } - } /* End _OSC */ - - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - #include "acpi/superio.asl" - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */ - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* Determine the OS we're running on */ - OSFL() - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c deleted file mode 100644 index 5196caf33f..0000000000 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h deleted file mode 100644 index b029efb069..0000000000 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x0F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1E - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 1 - -static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */ -{ - /* NID, PinConfig (Verbs 71F..C) */ - {0x11, 0x411111F0}, /* NPC */ - {0x12, 0x411111F0}, /* DMIC */ - {0x14, 0x01214110}, /* FRONT (Port-D) */ - {0x15, 0x01011112}, /* SURR (Port-A) */ - {0x16, 0x01016111}, /* CEN/LFE (Port-G) */ - {0x17, 0x411111F0}, /* SIDESURR (Port-H) */ - {0x18, 0x01A19930}, /* MIC1 (Port-B) */ - {0x19, 0x411111F0}, /* MIC2 (Port-F) */ - {0x1A, 0x0181313F}, /* LINE1 (Port-C) */ - {0x1B, 0x411111F0}, /* LINE2 (Port-E) */ - {0x1C, 0x411111F0}, /* CD-IN */ - {0x1D, 0x40132601}, /* BEEP-IN */ - {0x1E, 0x01441120}, /* S/PDIF-OUT */ - {0x1F, 0x01C46140}, /* S/PDIF-IN */ - {0xff, 0xffffffff} /* end of table */ -}; - -static const CODECTBLLIST codec_tablelist[] = -{ - {0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]}, - {0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL} -}; - -/** - * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific codec verb table list - */ -#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) - -#endif diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index e6095ba305..93a43f9517 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -33,12 +33,4 @@ config CBFS_SIZE hex default 0x200000 -config VGA_BIOS_FILE - string - default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vgabios.bin" - -config VGA_BIOS_ID - string - default "8086,0102" - endif diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c index 28c9d8ee6e..e68746c7b2 100644 --- a/src/mainboard/msi/ms7707/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -3,7 +3,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index db48656489..2ccf7c63ab 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,12 +1,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 0a57964b1f..3dfe2e35d3 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 1df5b8c7ba..ae7a945921 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -6,7 +6,6 @@ #include #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * @@ -170,7 +169,6 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { PSO_END }; - void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c index e60353c925..0de0c58f3d 100644 --- a/src/mainboard/msi/ms7721/bootblock.c +++ b/src/mainboard/msi/ms7721/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -20,7 +21,7 @@ static void gpio_init(pnp_devfn_t dev) pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0x60, 0x0a); //Base addr high + pnp_write_config(dev, PNP_IDX_IO0, 0x0a); //Base addr high pnp_write_config(dev, 0x61, 0x00); //Base addr low pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 5740382985..3a0ac1c3eb 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index ade4c04bf3..b076f0a776 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -5,50 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 7c8f6aa91f..25d5ef29ff 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -3,9 +3,9 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 8a1cc03a0e..6f96ed8f0f 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b4e88b51ed..bb907f1af7 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,7 +3,7 @@ if BOARD_OCP_DELTALAKE config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select FSP_CAR + select CONSOLE_OVERRIDE_LOGLEVEL select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP @@ -13,6 +13,16 @@ config BOARD_SPECIFIC_OPTIONS select OCP_DMI select VPD select VPD_SMBIOS_VERSION + select IPMI_OCP + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 1 + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + default n config IPMI_KCS_REGISTER_SPACING int @@ -36,6 +46,15 @@ config MAX_SOCKET config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +# Deltalake is single socket server, the platform design has 1 DIMM per channel +config DIMM_MAX + int + default 6 + +config CONSOLE_POST + bool + default y endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 4fb50b2e2c..e961a3423a 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -7,6 +7,6 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +all-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel_vpd.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl index e04bde5d19..286cc6cb99 100644 --- a/src/mainboard/ocp/deltalake/acpi/platform.asl +++ b/src/mainboard/ocp/deltalake/acpi/platform.asl @@ -329,9 +329,9 @@ Field (PSYS, ByteAcc, NoLock, Preserve) /* SMI I/O Trap */ Method (TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler } /* @@ -345,7 +345,7 @@ Method (TRAP, 1, Serialized) Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c index 8004170a5e..402b572873 100644 --- a/src/mainboard/ocp/deltalake/bootblock.c +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include #define ASPEED_SIO_PORT 0x2E @@ -52,6 +52,9 @@ static uint8_t com_to_ast_sio(uint8_t com) void bootblock_mainboard_early_init(void) { + /* pre-configure Lewisburg PCH GPIO pads */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + /* Open IO windows */ enable_espi_lpc_io_windows(); diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index cc17e06f6c..8b6e3aea6c 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -33,8 +33,9 @@ chip soc/intel/xeon_sp/cpx # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL register "pstate_req_ratio" = "0xa" - register "coherency_support" = "0" - register "ats_support" = "0" + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS @@ -50,6 +51,7 @@ chip soc/intel/xeon_sp/cpx end device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 on end # Host bridge device pci 04.0 on end # Intel SkyLake-E CBDMA Registers device pci 04.1 on end # Intel SkyLake-E CBDMA Registers @@ -62,6 +64,9 @@ chip soc/intel/xeon_sp/cpx device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers device pci 05.2 on end # Intel SkyLake-E RAS device pci 05.4 on end # Intel SkyLake-E IOAPIC + device pci 07.0 on end + device pci 07.4 on end + device pci 07.7 on end device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers @@ -82,8 +87,17 @@ chip soc/intel/xeon_sp/cpx device pci 1f.0 on chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + use pch_gpio as gpio_dev register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" + register "post_complete_gpio" = "GPP_B20" + register "post_complete_invert" = "1" + end + chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end end end # ISA bridge: Intel Device a245 device pci 1f.1 on end # p2sb diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c74b5fecb8..63aeb700c2 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision @@ -14,10 +14,16 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include #include // CPX-SP ACPI tables - #include + #include + + // LPC related entries + Scope (\_SB.PC00) + { + #include + } } diff --git a/src/mainboard/ocp/deltalake/fadt.c b/src/mainboard/ocp/deltalake/fadt.c index b9fcd582ef..6306e03e30 100644 --- a/src/mainboard/ocp/deltalake/fadt.c +++ b/src/mainboard/ocp/deltalake/fadt.c @@ -3,7 +3,7 @@ #include #include -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h new file mode 100644 index 0000000000..fad22aa1cf --- /dev/null +++ b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF3), /* ESPI_ALERT1# */ + PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, NONE, RSMRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, RSMRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, RSMRST, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A7, NONE, RSMRST, NF1), /* PIRQA# */ + PAD_CFG_NF(GPP_A8, NONE, RSMRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, NONE, RSMRST, NF1), /* CLKOUT_LPC0 */ + PAD_NC(GPP_A10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A11, NONE, RSMRST, NF1), /* PME# */ + PAD_CFG_GPI_SCI(GPP_A12, NONE, RSMRST, OFF, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1), /* SUS_ACK# */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_NC(GPP_A17, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_NC(GPP_A21, NONE), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_NC(GPP_A23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, NONE), /* GPIO */ + PAD_NC(GPP_B1, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_B11 - RESERVED */ + PAD_CFG_NF(GPP_B12, NONE, RSMRST, NF1), /* GLB_RST_WARN_N# */ + PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, RSMRST, NF1), /* SPKR */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* PCHHOT# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), /* GPIO */ + PAD_NC(GPP_F1, NONE), /* GPIO */ + PAD_NC(GPP_F2, NONE), /* GPIO */ + PAD_NC(GPP_F3, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_F6, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_F8, 0, RSMRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_F10, NONE), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_NC(GPP_F20, NONE), /* GPIO */ + PAD_NC(GPP_F21, NONE), /* GPIO */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, RSMRST, LEVEL, ACPI), /* GPIO */ + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_NF(GPP_C5, NONE, RSMRST, NF1), /* SML0ALERT# */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_C20 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_SMI(GPP_C22, NONE, RSMRST, LEVEL, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_NMI(GPP_D0, NONE, RSMRST, LEVEL, NONE), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D4, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_D5, NONE), /* GPIO */ + PAD_NC(GPP_D6, NONE), /* GPIO */ + PAD_NC(GPP_D7, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D9, NONE), /* GPIO */ + PAD_NC(GPP_D10, NONE), /* GPIO */ + PAD_NC(GPP_D11, NONE), /* GPIO */ + PAD_NC(GPP_D12, NONE), /* GPIO */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, RSMRST), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPIO */ + PAD_NC(GPP_D20, NONE), /* GPIO */ + PAD_NC(GPP_D21, NONE), /* GPIO */ + PAD_NC(GPP_D22, NONE), /* GPIO */ + PAD_NC(GPP_D23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* CPU_GP0 */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_NC(GPP_E6, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1), /* USB_OC0# */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + /* -------- GPIO Group GPD -------- */ + /* GPD0 - RESERVED */ + PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* ACPRESENT */ + PAD_NC(GPD2, NONE), /* GPIO */ + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ + PAD_NC(GPD6, NONE), /* GPIO */ + PAD_NC(GPD7, NONE), /* GPIO */ + PAD_NC(GPD8, NONE), /* GPIO */ + PAD_NC(GPD9, NONE), /* GPIO */ + PAD_NC(GPD10, NONE), /* GPIO */ + PAD_NC(GPD11, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_NC(GPP_I7, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I8, NONE, RSMRST, NF2), /* PCI_DIS */ + PAD_CFG_NF(GPP_I9, NONE, RSMRST, NF2), /* LAN_DIS */ + PAD_NC(GPP_I10, NONE), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_J ------- */ + PAD_NC(GPP_J0, NONE), /* GPIO */ + PAD_NC(GPP_J1, NONE), /* GPIO */ + PAD_NC(GPP_J2, NONE), /* GPIO */ + PAD_NC(GPP_J3, NONE), /* GPIO */ + PAD_NC(GPP_J4, NONE), /* GPIO */ + PAD_NC(GPP_J5, NONE), /* GPIO */ + PAD_NC(GPP_J6, NONE), /* GPIO */ + PAD_NC(GPP_J7, NONE), /* GPIO */ + PAD_NC(GPP_J8, NONE), /* GPIO */ + PAD_NC(GPP_J9, NONE), /* GPIO */ + PAD_NC(GPP_J10, NONE), /* GPIO */ + PAD_NC(GPP_J11, NONE), /* GPIO */ + PAD_NC(GPP_J12, NONE), /* GPIO */ + PAD_NC(GPP_J13, NONE), /* GPIO */ + PAD_NC(GPP_J14, NONE), /* GPIO */ + PAD_NC(GPP_J15, NONE), /* GPIO */ + PAD_NC(GPP_J16, NONE), /* GPIO */ + PAD_NC(GPP_J17, NONE), /* GPIO */ + PAD_NC(GPP_J18, NONE), /* GPIO */ + PAD_NC(GPP_J19, NONE), /* GPIO */ + PAD_NC(GPP_J20, NONE), /* GPIO */ + PAD_NC(GPP_J21, NONE), /* GPIO */ + PAD_NC(GPP_J22, NONE), /* GPIO */ + PAD_NC(GPP_J23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), /* GPIO */ + PAD_NC(GPP_K1, NONE), /* GPIO */ + PAD_NC(GPP_K2, NONE), /* GPIO */ + PAD_NC(GPP_K3, NONE), /* GPIO */ + PAD_NC(GPP_K4, NONE), /* GPIO */ + PAD_NC(GPP_K5, NONE), /* GPIO */ + PAD_NC(GPP_K6, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_K8, NONE, RSMRST, NF1), /* LAN_NCSI_ARB_IN */ + PAD_CFG_NF(GPP_K9, NONE, RSMRST, NF1), /* LAN_NCSI_ARB_OUT */ + PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1), /* PE_RST# */ + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), /* GPIO */ + PAD_NC(GPP_G1, NONE), /* GPIO */ + PAD_NC(GPP_G2, NONE), /* GPIO */ + PAD_NC(GPP_G3, NONE), /* GPIO */ + PAD_NC(GPP_G4, NONE), /* GPIO */ + PAD_NC(GPP_G5, NONE), /* GPIO */ + PAD_NC(GPP_G6, NONE), /* GPIO */ + PAD_NC(GPP_G7, NONE), /* GPIO */ + PAD_NC(GPP_G8, NONE), /* GPIO */ + PAD_NC(GPP_G9, NONE), /* GPIO */ + PAD_NC(GPP_G10, NONE), /* GPIO */ + PAD_NC(GPP_G11, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_G17, NONE, RSMRST, NF1), /* ADR_COMPLETE */ + PAD_CFG_NF(GPP_G18, NONE, RSMRST, NF1), /* NMI# */ + PAD_CFG_NF(GPP_G19, NONE, RSMRST, NF1), /* SMI# */ + /* GPP_G20 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_G22, NONE), /* GPIO */ + PAD_NC(GPP_G23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_H2, NONE), /* GPIO */ + PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2), /* SSATAXPCIE2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* CSME_INTR_OUT */ + PAD_CFG_NF(GPP_L2, NONE, RSMRST, NF1), /* TESTCH0_D0 */ + PAD_CFG_NF(GPP_L3, NONE, RSMRST, NF1), /* TESTCH0_D1 */ + PAD_CFG_NF(GPP_L4, NONE, RSMRST, NF1), /* TESTCH0_D2 */ + PAD_CFG_NF(GPP_L5, NONE, RSMRST, NF1), /* TESTCH0_D3 */ + PAD_CFG_NF(GPP_L6, NONE, RSMRST, NF1), /* TESTCH0_D4 */ + PAD_CFG_NF(GPP_L7, NONE, RSMRST, NF1), /* TESTCH0_D5 */ + PAD_CFG_NF(GPP_L8, NONE, RSMRST, NF1), /* TESTCH0_D6 */ + PAD_CFG_NF(GPP_L9, NONE, RSMRST, NF1), /* TESTCH0_D7 */ + PAD_CFG_NF(GPP_L10, NONE, RSMRST, NF1), /* TESTCH0_CLK */ + PAD_NC(GPP_L11, NONE), /* GPIO */ + PAD_NC(GPP_L12, NONE), /* GPIO */ + PAD_NC(GPP_L13, NONE), /* GPIO */ + PAD_NC(GPP_L14, NONE), /* GPIO */ + PAD_NC(GPP_L15, NONE), /* GPIO */ + PAD_NC(GPP_L16, NONE), /* GPIO */ + PAD_NC(GPP_L17, NONE), /* GPIO */ + PAD_NC(GPP_L18, NONE), /* GPIO */ + PAD_NC(GPP_L19, NONE), /* GPIO */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF3), /* ESPI_ALERT1# */ + PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, NONE, RSMRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, RSMRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, RSMRST, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A8, NONE, RSMRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, NONE, RSMRST, NF1), /* CLKOUT_LPC0 */ + PAD_NC(GPP_A10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1), /* SUS_ACK# */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index 19a85d567c..415b26d5d8 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -75,21 +75,43 @@ enum cb_err ipmi_get_slot_id(uint8_t *slot_id) return CB_SUCCESS; } +enum cb_err ipmi_set_post_start(const int port) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(port, IPMI_NETFN_OEM, 0x0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, + sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + if (ret != sizeof(rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return CB_ERR; + } + + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); + return CB_SUCCESS; +} + void init_frb2_wdt(void) { - char val[VPD_LEN]; - /* Enable FRB2 timer by default. */ - u8 enable = 1; + uint8_t enable, action; uint16_t countdown; if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { - if (!enable) { - printk(BIOS_DEBUG, "Disable FRB2 timer\n"); - ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); - return; - } + printk(BIOS_DEBUG, "Got VPD %s value: %d\n", FRB2_TIMER, enable); + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set to %d\n", FRB2_TIMER, + FRB2_TIMER_DEFAULT); + enable = FRB2_TIMER_DEFAULT; } + if (enable) { if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { countdown = (uint16_t)atol(val); @@ -97,10 +119,69 @@ void init_frb2_wdt(void) countdown * 100); } else { printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", - DEFAULT_COUNTDOWN * 100); - countdown = DEFAULT_COUNTDOWN; + FRB2_COUNTDOWN_DEFAULT * 100); + countdown = FRB2_COUNTDOWN_DEFAULT; } - ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, - TIMEOUT_HARD_RESET); + + if (vpd_gets(FRB2_ACTION, val, VPD_LEN, VPD_RW_THEN_RO)) { + action = (uint8_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer action set to: %d\n", action); + } else { + printk(BIOS_DEBUG, "FRB2 timer action use default value: %d\n", + FRB2_ACTION_DEFAULT); + action = FRB2_ACTION_DEFAULT; + } + ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, action); + } else { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); } } + +enum cb_err ipmi_set_cmos_clear(void) +{ + int ret; + + struct ipmi_oem_rsp { + struct ipmi_rsp resp; + struct boot_order data; + } __packed; + + struct ipmi_oem_rsp rsp; + struct boot_order req; + + /* IPMI OEM get bios boot order command to check if the valid bit and + the CMOS clear bit are both set from the response BootMode byte. */ + + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_GET_BIOS_BOOT_ORDER, + NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + if (!IS_CMOS_AND_VALID_BIT(rsp.data.boot_mode)) { + req = rsp.data; + SET_CMOS_AND_VALID_BIT(req.boot_mode); + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_SET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + printk(BIOS_INFO, "IPMI CMOS clear requested because CMOS data is invalid.\n"); + + return CB_SUCCESS; + } + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index 840f999990..440a5056ba 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -9,6 +9,15 @@ #define IPMI_OEM_SET_PPIN 0x77 #define IPMI_OEM_GET_PCIE_CONFIG 0xf4 #define IPMI_OEM_GET_BOARD_ID 0x37 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 +#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 + +#define CMOS_BIT (1 << 1) +#define VALID_BIT (1 << 7) +#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= ~(CMOS_BIT | VALID_BIT)) +#define SET_CMOS_AND_VALID_BIT(x) ((x) |= (CMOS_BIT | VALID_BIT)) +#define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) enum config_type { PCIE_CONFIG_UNKNOWN = 0x0, @@ -25,8 +34,19 @@ struct ppin_req { uint32_t cpu1_hi; } __packed; +struct boot_order { + uint8_t boot_mode; + uint8_t boot_dev0; + uint8_t boot_dev1; + uint8_t boot_dev2; + uint8_t boot_dev3; + uint8_t boot_dev4; +} __packed; + enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); enum cb_err ipmi_get_slot_id(uint8_t *slot_id); +enum cb_err ipmi_set_post_start(const int port); void init_frb2_wdt(void); +enum cb_err ipmi_set_cmos_clear(void); #endif diff --git a/src/mainboard/ocp/deltalake/loglevel_vpd.c b/src/mainboard/ocp/deltalake/loglevel_vpd.c new file mode 100644 index 0000000000..3faf37a0ea --- /dev/null +++ b/src/mainboard/ocp/deltalake/loglevel_vpd.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "vpd.h" + +int get_console_loglevel(void) +{ + int log_level = COREBOOT_LOG_LEVEL_DEFAULT; + char val_str[VPD_LEN]; + + if (vpd_gets(COREBOOT_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + log_level = (int)atol(val_str); + if (log_level < 0 || log_level >= BIOS_NEVER) + log_level = COREBOOT_LOG_LEVEL_DEFAULT; + } + return log_level; +} diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 88f89b5817..afc2b69cd4 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,13 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -#include -#include #include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include #include "ipmi.h" @@ -16,6 +24,46 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; +/* Override SMBIOS type 16 error correction type. */ +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + const struct SystemMemoryMapHob *hob; + + hob = get_system_memory_map(); + assert(hob != NULL); + + switch (hob->RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + +/* + * Update SMBIOS type 0 ec version. + * In deltalake, BMC version is used to represent ec version. + * In current version of OpenBMC, it follows IPMI v2.0 to define minor revision as BCD + * encoded, so the format of it must be transferred before send to SMBIOS. + */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + uint8_t bmc_major_revision, bmc_minor_revision; + + ipmi_bmc_version(&bmc_major_revision, &bmc_minor_revision); + *ec_major_revision = bmc_major_revision & 0x7f; /* bit[6:0] Major Firmware Revision */ + *ec_minor_revision = ((bmc_minor_revision / 16) * 10) + (bmc_minor_revision % 16); +} + /* Override SMBIOS 2 Location In Chassis from BMC */ const char *smbios_mainboard_location_in_chassis(void) { @@ -34,15 +82,75 @@ const char *smbios_mainboard_location_in_chassis(void) return slot_id_str; } +/* + * Override SMBIOS type 4 cpu voltage. + * BIT7 will set to 1 after value return. If BIT7 is set to 1, the remaining seven + * bits of this field are set to contain the processor's current voltage times 10. + */ +unsigned int smbios_cpu_get_voltage(void) +{ + /* This will return 1.6V which is expected value for Delta Lake + 10h = (1.6 * 10) = 16 */ + return 0x10; +} + +/* System Slot Socket, Stack, Type and Data bus width Information */ +typedef struct { + u8 stack; + u8 slot_type; + u8 slot_data_bus_width; + u8 dev_func; + const char *slot_designator; +} slot_info; + +slot_info slotinfo[] = { + {CSTACK, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "SSD1_M2_Data_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "SSD0_M2_Boot_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "BB_OCP_NIC"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1OU_JD2_M2_3"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1OU_JD1_M2_1"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD1_M2_1"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2OU_JD3_M2_4"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2OU_JD3_M2_5"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD2_M2_3"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "1OU_OCP_NIC"}, +}; + +#define SPD_REGVID_LEN 6 +/* A 4-digit long number plus a space */ +static void write_oem_word(uint16_t val, char *str) +{ + snprintf(str, SPD_REGVID_LEN, "%04x ", val); +} + static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { uint8_t pcie_config = 0; + const struct SystemMemoryMapHob *hob; + char spd_reg_vid[SPD_REGVID_LEN]; + char empty[1] = ""; + char *oem_str7 = empty; /* OEM string 1 to 6 */ ocp_oem_smbios_strings(dev, t); - /* TODO: Add real OEM string 7, add TBF for now */ - t->count = smbios_add_oem_string(t->eos, TBF); + /* OEM string 7 is the register vendor ID in SPD for each DIMM strung together */ + hob = get_system_memory_map(); + assert(hob != NULL); + /* There are at most 6 channels and 2 DIMMs per channel, but Delta Lake has 6 DIMMs, + e.g. b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + write_oem_word(hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm].SPDRegVen, + spd_reg_vid); + oem_str7 = strconcat(oem_str7, spd_reg_vid); + } + } + t->count = smbios_add_oem_string(t->eos, oem_str7); /* Add OEM string 8 */ if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { @@ -70,14 +178,176 @@ static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) } } +static const struct port_information smbios_type8_info[] = { + { + .internal_reference_designator = "JCN18 - CPU MIPI60", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN32 - TPM_CONN", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN7 - USB type C", + .internal_connector_type = CONN_USB_TYPE_C, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, +}; + +static int create_smbios_type9(int *handle, unsigned long *current) +{ + int index; + int length = 0; + uint8_t slot_length; + uint8_t sec_bus; + uint8_t slot_usage; + uint8_t pcie_config = 0; + uint8_t characteristics_1 = 0; + uint8_t characteristics_2 = 0; + uint32_t vendor_device_id; + uint32_t stack_busnos[6]; + pci_devfn_t pci_dev; + unsigned int cap; + uint16_t sltcap; + + if (ipmi_get_pcie_config(&pcie_config) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); + + get_stack_busnos(stack_busnos); + + for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { + if (pcie_config == PCIE_CONFIG_A) { + if (index == 0 || index == 1 || index == 2) + printk(BIOS_INFO, "Find Config-A slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_B) { + if (index == 0 || index == 1 || index == 2 || index == 3 || index == 4 + || index == 5 || index == 6) + printk(BIOS_INFO, "Find Config-B slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_C) { + if (index == 0 || index == 1 || index == 7 || index == 8 || index == 9 + || index == 10 || index == 11 || index == 12 || index == 13) + printk(BIOS_INFO, "Find Config-C slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_D) { + if (index != 13) + printk(BIOS_INFO, "Find Config-D slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + + if (slotinfo[index].slot_data_bus_width == SlotDataBusWidth16X) + slot_length = SlotLengthLong; + else + slot_length = SlotLengthShort; + + pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack], + slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7); + sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + + if (sec_bus == 0xFF) { + slot_usage = SlotUsageUnknown; + } else { + /* Checking for Slot device availability */ + pci_dev = PCI_DEV(sec_bus, 0, 0); + vendor_device_id = pci_s_read_config32(pci_dev, 0); + if (vendor_device_id == 0xFFFFFFFF) + slot_usage = SlotUsageAvailable; + else + slot_usage = SlotUsageInUse; + } + + characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts + characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported + + cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) + characteristics_2 |= SMBIOS_SLOT_HOTPLUG; + + length += smbios_write_type9(current, handle, + slotinfo[index].slot_designator, + slotinfo[index].slot_type, + slotinfo[index].slot_data_bus_width, + slot_usage, + slot_length, + characteristics_1, + characteristics_2, + stack_busnos[slotinfo[index].stack], + slotinfo[index].dev_func); + } + + return length; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + // add port information + len += smbios_write_type8( + current, handle, + smbios_type8_info, + ARRAY_SIZE(smbios_type8_info) + ); + + len += create_smbios_type9(handle, current); + + return len; +} + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char buf[40]; + + snprintf(buf, sizeof(buf), "DIMM %c0", 'A' + dimm->channel_num); + t->device_locator = smbios_add_string(t->eos, buf); + + snprintf(buf, sizeof(buf), "_Node0_Channel%d_Dimm0", dimm->channel_num); + t->bank_locator = smbios_add_string(t->eos, buf); +} + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return 0xb3; /* Xeon */ +} + +unsigned int smbios_processor_characteristics(void) +{ + /* 64-bit Capable, Multi-Core, Power/Performance Control */ + return 0x8c; /* BIT2 + BIT3 + BIT7 */ +} + static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings, read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); + dev->ops->get_smbios_data = mainboard_smbios_data; } void mainboard_silicon_init_params(FSPS_UPD *params) { + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } static void mainboard_final(void *chip_info) @@ -95,11 +365,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, }; - -static void pull_post_complete_pin(void *unused) -{ - /* Pull Low post complete pin */ - gpio_output(GPP_B20, 0); -} - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2c8dc5efa2..f0cdd3dbb7 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "chip.h" #include "ipmi.h" @@ -18,16 +19,62 @@ static void mainboard_config_upd(FSPM_UPD *mupd) { uint8_t val; + char val_str[VPD_LEN]; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) mupd->FspmConfig.SerialIoUartDebugEnable = val; else { printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to 1\n", FSP_LOG); - mupd->FspmConfig.SerialIoUartDebugEnable = 1; + "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + /* FSP debug log level */ + if (vpd_gets(FSP_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 0x0f) { + printk(BIOS_DEBUG, "Invalid DebugPrintLevel value from VPD: " + "%d\n", val); + val = FSP_LOG_LEVEL_DEFAULT; + } + printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val); + mupd->FspmConfig.DebugPrintLevel = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DebugPrintLevel to %d\n", FSP_LOG_LEVEL, + FSP_LOG_LEVEL_DEFAULT); + mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT; + } + } + + /* Enable DCI */ + if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) { + printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val); + mupd->FspmConfig.PchDciEn = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); + mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; + } + + /* + * UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark. + * Following code is effective when MemRefreshWaterMark patch is added to FSP + * and when corresponding VPD variable is set. + */ + if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 2) { + printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " + "%d\n", val); + val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); + mupd->FspmConfig.UnusedUpdSpace0[0] = val; + } } /* Update bifurcation settings according to different Configs */ @@ -96,10 +143,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ - if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { + ipmi_set_post_start(CONFIG_BMC_KCS_BASE); init_frb2_wdt(); + } mainboard_config_gpios(mupd); mainboard_config_iio(mupd); mainboard_config_upd(mupd); } + +void mainboard_rtc_failed(void) +{ + if (ipmi_set_cmos_clear() == CB_SUCCESS) + printk(BIOS_DEBUG, "%s: IPMI set cmos clear successful\n", __func__); + else + printk(BIOS_ERR, "%s: IPMI set cmos clear failed\n", __func__); +} diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 9e17bb9b80..71a3b09202 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -3,15 +3,41 @@ #ifndef DELTALAKE_VPD_H #define DELTALAKE_VPD_H -/* VPD variable for enabling/disabling FRB2 timer. */ -#define FRB2_TIMER "frb2_timer" +/* VPD variable maximum length */ +#define VPD_LEN 10 + +/* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */ +#define FRB2_TIMER "frb2_timer_enable" +#define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */ + /* VPD variable for setting FRB2 timer countdown value. */ #define FRB2_COUNTDOWN "frb2_countdown" -#define VPD_LEN 10 -/* Default countdown is 15 minutes. */ -#define DEFAULT_COUNTDOWN 9000 +/* Default countdown is 15 minutes when the VPD variable is not found */ +#define FRB2_COUNTDOWN_DEFAULT 9000 + +/* VPD variable for setting FRB2 timer action. + 0: No action, 1: hard reset, 2: power down, 3: power cycle */ +#define FRB2_ACTION "frb2_action" +#define FRB2_ACTION_DEFAULT 0 /* Default no action when the VPD variable is not found */ /* Define the VPD keys for UPD variables that can be overwritten */ #define FSP_LOG "fsp_log_enable" /* 1 or 0: enable or disable FSP SOL log */ +#define FSP_LOG_DEFAULT 1 /* Default value when the VPD variable is not found */ + +/* FSP debug print level: 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All */ +#define FSP_LOG_LEVEL "fsp_log_level" +#define FSP_LOG_LEVEL_DEFAULT 8 /* Default value when the VPD variable is not found */ + +/* DCI enable */ +#define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ +#define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ + +/* coreboot log level */ +#define COREBOOT_LOG_LEVEL "coreboot_log_level" +#define COREBOOT_LOG_LEVEL_DEFAULT 4 + +/* FSPM MemRefreshWatermark: 0:Auto, 1: high(default), 2: low */ +#define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" +#define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 #endif diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 421d4009ea..67c1fa9d52 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -6,10 +6,14 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select MAINBOARD_USES_FSP2_0 + select OCP_DMI + select PARALLEL_MP_AP_WORK select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 + select VPD config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index ca4e4637d2..2f7f327960 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c -ramstage-y += ramstage.c +romstage-y += ipmi.c +ramstage-y += ramstage.c ipmi.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index 3398568f1c..02c32f93b7 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -329,9 +329,9 @@ Field (PSYS, ByteAcc, NoLock, Preserve) /* SMI I/O Trap */ Method (TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler } /* @@ -345,7 +345,7 @@ Method (TRAP, 1, Serialized) Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index f6947a20b8..b6e3846f28 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,15 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include - -extern const unsigned char AmlCode[]; - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - acpi_init_gnvs(gnvs); -} +#include void mainboard_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd index 1e3fda7e8b..2ecce06570 100644 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ b/src/mainboard/ocp/tiogapass/board.fmd @@ -5,7 +5,15 @@ FLASH 32M { PLATFORM_DATA@0xa26000 0x10000 } SI_BIOS@0x1000000 0x1000000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x800 0xfff800 + MISC_RW@0x0 0x10000 { + RW_VPD(PRESERVE)@0x0 0x4000 + } + WP_RO@0x10000 0xff0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0xfec000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfeb800 + } + } } } diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 9fc34d77e8..b5c2aa1567 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 33f4090751..488f677a95 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -74,9 +74,10 @@ chip soc/intel/xeon_sp/skx chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" - register "bmc_boot_timeout" = "60" + register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251cf3..7fa518bd87 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -5,22 +5,18 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - // platform ACPI tables #include "acpi/platform.asl" - - // global NVS and variables - #include - + #include #include - - // Xeon-SP ACPI tables - Scope (\_SB) { - #include + #include + Scope (\_SB.PC00) + { + #include } } diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index 43b207e4d5..b66d7735d1 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -39,51 +39,48 @@ static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ }; +#define CFG_UPD_PORT(port, hide) \ + { \ + .PortIndex = port, \ + .HidePort = hide, \ + .DeEmphasis = 0x00, \ + .PortLinkSpeed = PcieAuto, \ + .MaxPayload = 0x00, \ + .DfxDnTxPreset = 0xFF, \ + .DfxRxPreset = 0xFF, \ + .DfxUpTxPreset = 0xFF, \ + .Sris = 0x00, \ + .PcieCommonClock = 0x00, \ + .NtbPpd = NTB_PORT_TRANSPARENT, \ + .NtbSplitBar = 0x00, \ + .NtbBarSizePBar23 = 0x16, \ + .NtbBarSizePBar4 = 0x16, \ + .NtbBarSizePBar5 = 0x16, \ + .NtbBarSizePBar45 = 0x16, \ + .NtbBarSizeSBar23 = 0x16, \ + .NtbBarSizeSBar4 = 0x16, \ + .NtbBarSizeSBar5 = 0x16, \ + .NtbBarSizeSBar45 = 0x16, \ + .NtbSBar01Prefetch = 0x00, \ + .NtbXlinkCtlOverride = 0x03, \ + } + /* * Standard Tioga Pass Iio PCIe Port Table */ static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, + CFG_UPD_PORT(PORT_1A, NOT_HIDE), + CFG_UPD_PORT(PORT_1B, HIDE), + CFG_UPD_PORT(PORT_1C, HIDE), + CFG_UPD_PORT(PORT_1D, HIDE), + CFG_UPD_PORT(PORT_2A, NOT_HIDE), + CFG_UPD_PORT(PORT_2B, HIDE), + CFG_UPD_PORT(PORT_2C, HIDE), + CFG_UPD_PORT(PORT_2D, HIDE), + CFG_UPD_PORT(PORT_3A, NOT_HIDE), + CFG_UPD_PORT(PORT_3B, HIDE), + CFG_UPD_PORT(PORT_3C, NOT_HIDE), + CFG_UPD_PORT(PORT_3D, HIDE), }; /* diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 1c26564e34..97ab7cb39e 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -12,23 +12,23 @@ static const struct pad_config gpio_table[] = { /* GPP_A0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - PIRQA# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* GPP_A10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ @@ -59,9 +59,9 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ @@ -83,11 +83,11 @@ static const struct pad_config gpio_table[] = { /* GPP_B11 - GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ @@ -105,7 +105,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ @@ -129,15 +129,15 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* GPP_F12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), /* GPP_F15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ @@ -147,22 +147,22 @@ static const struct pad_config gpio_table[] = { /* GPP_F18 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ @@ -233,7 +233,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D14 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ @@ -259,7 +259,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ @@ -269,9 +269,9 @@ static const struct pad_config gpio_table[] = { /* GPP_E7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ @@ -287,11 +287,11 @@ static const struct pad_config gpio_table[] = { /* GPD2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ @@ -303,18 +303,18 @@ static const struct pad_config gpio_table[] = { /* GPD10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), /* GPP_I4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ @@ -322,7 +322,7 @@ static const struct pad_config gpio_table[] = { /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), /* GPP_I8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ @@ -333,51 +333,51 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), /* GPP_J17 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), /* GPP_J19 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), /* GPP_J21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), /* GPP_J23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), @@ -397,13 +397,13 @@ static const struct pad_config gpio_table[] = { /* GPP_K6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -442,11 +442,11 @@ static const struct pad_config gpio_table[] = { /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), @@ -501,7 +501,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000000..0cdf110bd8 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "ipmi.h" +#include "vpd.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n"); +} + +void init_frb2_wdt(void) +{ + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); + return; + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", + countdown * 100); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", + DEFAULT_COUNTDOWN * 100); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000000..798f3125ef --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +void init_frb2_wdt(void); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 82b260d5b2..0e520f015d 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,9 +1,140 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + #include #include +#include +#include #include +#include #include +#include "ipmi.h" + +extern struct fru_info_str fru_strings; + +static const struct port_information SMBIOS_type8_info[] = { + /* + * Port Information fields: + * Internal Reference Designator, + * Internal Connector Type, + * External Reference Designator, + * External Connector_Type, + * Port Type + */ + { + "J7F5 - BMC JTAG HEADER", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8A1 - MINISAS1", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8A2 - MINISAS2", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8A3 - SATA CONBINE1", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8B1 - ME_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8D1 - VR_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8E1 - TPM_MODULE", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8F1 - M.2 CONNECTOR", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J9A1 - SATA RAID KEY", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9A2 - DEBUG 80 PORT", + CONN_OTHER, + TYPE_OTHER_PORT + }, + { + "J9A3 - CPU & PCH XDP", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9A5 - USB conn", + CONN_ACCESS_BUS_USB, + TYPE_USB + }, + { + "J9B1 - BMC_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9D1 - USB3.0 TYPE C", + CONN_ACCESS_BUS_USB, + TYPE_USB + }, + { + NULL, + CONN_NONE, + "J9E1 - VGA", + CONN_OTHER, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "JA9G1 - ETH0", + CONN_RJ_45, + TYPE_NETWORK_PORT + }, +}; + void mainboard_silicon_init_params(FSPS_UPD *params) { } @@ -14,4 +145,60 @@ static void pull_post_complete_pin(void *unused) gpio_output(GPP_B20, 0); } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + // add port information + len += smbios_write_type8( + current, handle, + SMBIOS_type8_info, + ARRAY_SIZE(SMBIOS_type8_info) + ); + + return len; +} +#endif + +static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + /* OEM string 1 to 6 */ + ocp_oem_smbios_strings(dev, t); + + /* OEM string 7 */ + if (fru_strings.board_info.custom_count > 1 && + *(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_oem_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_oem_string(t->eos, TBF); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = tp_oem_smbios_strings, + read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + req.cpu1_lo = xeon_sp_ppin[1].lo; + req.cpu1_hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index b728c3a5c5..fb2ce0217a 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -2,12 +2,15 @@ #include #include +#include #include #include #include #include #include +#include "ipmi.h" + static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; static void oem_update_iio(FSPM_UPD *mupd) @@ -49,6 +52,9 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* It's better to run get BMC selftest result first */ + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + init_frb2_wdt(); mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ diff --git a/src/mainboard/ocp/tiogapass/vpd.h b/src/mainboard/ocp/tiogapass/vpd.h new file mode 100644 index 0000000000..63a92f68b2 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/vpd.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef TIOGAPASS_VPD_H +#define TIOGAPASS_VPD_H + +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "frb2_timer" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "frb2_countdown" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 + +#endif /* TIOGAPASS_VPD_H */ diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 94d677bd27..06c2a49413 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -72,8 +72,4 @@ config MAINBOARD_PART_NUMBER string default "Elgon" -config MAINBOARD_FIT_DTS - string - default "gbcv2.dts" - endif diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index 2f46f571b2..1a775bb45e 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -8,35 +8,35 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) - Store(0, Local0) + Local0 = 0 - Store(0, PAGE) + PAGE = 0 - Store(BAPR, Local2) + Local2 = BAPR if (Arg2) // charging { - Or(2, Local0, Local0) + Local0 |= 2 - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) + If (Local2 == 0x8000) { + Local2 = 0 } } if (Arg3) // discharging { - Or(1, Local0, Local0) - Subtract(0x10000, Local2, Local2) + Local0 |= 1 + Local2 = 0x10000 - Local2 } - Store(Local0, Index(Arg1, 0x00)) + Arg1[0] = Local0 - Store(0, PAGE) - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) + PAGE = 0 + Arg1[2] = BARC + Arg1[1] = Local2 - Store(0, PAGE) - Store(BAVO, Index(Arg1, 3)) + PAGE = 0 + Arg1[3] = BAVO Release(ECLK) Return (Arg1) } @@ -44,37 +44,39 @@ Method(BSTA, 4, NotSerialized) Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) - Store(0, PAGE) - Store(BAFC, Local2) - Store(1, PAGE) - Store(BADC, Local1) + PAGE = 0 + Local2 = BAFC + PAGE = 1 + Local1 = BADC - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(1, PAGE) - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + Arg0[1] = Local1 // Design Capacity + Arg0[2] = Local2 // Last full charge capacity + PAGE = 1 + Arg0[4] = BADV // Design Voltage + Arg0[5] = Local2 / 20 // Warning capacity - Store(1, PAGE) - Store (BASN, Local0) + PAGE = 1 + Local0 = BASN Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) + Local1 = 4 While (Local0) { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) + Local2 = Local0 + Local0 /= 0x0A + Local2 -= (Local0 * 0x0A) + SERN[Local1] = Local2 + 48 + Local1-- } - Store (SERN, Index (Arg0, 10)) // Serial Number + Arg0[10] = SERN // Serial Number Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(4, PAGE) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - Store(5, PAGE) - Store(BAOE, Index (Arg0, 12)) // OEM information - Store(2, PAGE) - Store(BANA, Index (Arg0, 9)) // Model number + PAGE = 4 + TYPE = BATY + Arg0[11] = TYPE // Battery type + PAGE = 5 + Arg0[12] = BAOE // OEM information + PAGE = 2 + Arg0[9] = BANA // Model number Release(ECLK) Return (Arg0) } diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c deleted file mode 100644 index 17ed31edb4..0000000000 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index a3cd554cd2..aec434d55d 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -4,85 +4,61 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 9 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 9 sata_mode # coreboot config options: northbridge -424 3 e 10 gfx_uma_size +424 3 e 10 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f28f..b57b3feba8 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_up_delay" = "300" register "gpu_panel_power_down_delay" = "300" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index f175707cf0..f576551fd8 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20140108 /* OEM revision */ @@ -15,7 +15,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index ce8d504211..0ba7342178 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index f2f3b08d84..bbcef27b4d 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index dcc81c9f8a..d6edf03e8b 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/pcengines/apu1/acpi/mainboard.asl b/src/mainboard/pcengines/apu1/acpi/mainboard.asl index 9283191c95..5c0929a3f1 100644 --- a/src/mainboard/pcengines/apu1/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu1/acpi/mainboard.asl @@ -18,20 +18,20 @@ Name(PMOD, One) /* Assume APIC */ Scope(\_SB) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if(CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } Return(OSVR) diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl index 7f305fb17f..6d9ff03005 100644 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ b/src/mainboard/pcengines/apu1/acpi/sata.asl @@ -35,7 +35,7 @@ Device(PMRY) Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -48,7 +48,7 @@ Device(PMRY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -71,7 +71,7 @@ Device(SEDY) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -84,7 +84,7 @@ Device(SEDY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -98,35 +98,35 @@ Device(SEDY) Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl index 76b5f9edc6..3b6fd02055 100644 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu1/acpi/sleep.asl @@ -26,23 +26,23 @@ Method(\_PTS, 1) { /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) + if (Arg0 == 3){ + URRE = 0 } /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 } /* End Method(\_PTS) */ /* @@ -67,21 +67,21 @@ Method(\_WAK, 1) { /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,HPDE) + HPDE = 1 /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) + if (Arg0 == 3){ + URRE = 1 } /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) + Local1 = PWST + PWST = Local1 - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) + /* if (DeRefOf(WKST [0])) { + * WKST [1] = 0 * } else { - * Store(Arg0, Index(WKST,1)) + * WKST [1] = Arg0 * } */ Return(WKST) diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl index 4ecc52ade9..e4ed275617 100644 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl @@ -14,134 +14,134 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index f2c551f4bf..dd3cd91f30 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -1,35 +1,34 @@ entries # -0 384 r 0 reserved_memory -384 4 r 0 reboot_bits +0 384 r 0 reserved_memory +384 4 r 0 reboot_bits # leave 3 bits to make checksummed area start byte-aligned -392 1 e 2 boot_option -393 1 e 1 multi_core -#394 6 unused -400 4 e 4 debug_level +392 1 e 2 boot_option +393 1 e 1 multi_core +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned -408 16 h 0 check_sum +408 16 h 0 check_sum enumerations #