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soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h

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This enum is useful to have around for more than just the one file, so
move it to a common header file, and while we're there, also add an
option for UNKNOWN.

TEST=boot test on brya0

Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Tim Wawrzynczak
2021-12-02 16:16:48 -07:00
committed by Patrick Georgi
parent 1883106c73
commit 461ff1d3e6
2 changed files with 11 additions and 10 deletions
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15
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -23,11 +23,6 @@
#define CPU_PCIE_BASE 0x40 #define CPU_PCIE_BASE 0x40
enum pcie_rp_type {
PCH_PCIE_RP,
CPU_PCIE_RP,
};
enum vtd_base_index_type { enum vtd_base_index_type {
VTD_GFX, VTD_GFX,
VTD_IPU, VTD_IPU,
@ -40,11 +35,11 @@ enum vtd_base_index_type {
static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
{ {
assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU);
if (type == PCH_PCIE_RP) if (type == PCIE_RP_PCH)
return rp_number; return rp_number;
else // type == CPU_PCIE_RP else // type == PCIE_RP_CPU
return CPU_PCIE_BASE + rp_number; return CPU_PCIE_BASE + rp_number;
} }
@ -82,12 +77,12 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
/* Configure PCH PCIE ports */ /* Configure PCH PCIE ports */
m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp,
CONFIG_MAX_PCH_ROOT_PORTS); CONFIG_MAX_PCH_ROOT_PORTS);
/* Configure CPU PCIE ports */ /* Configure CPU PCIE ports */
m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp,
CONFIG_MAX_CPU_ROOT_PORTS); CONFIG_MAX_CPU_ROOT_PORTS);
} }

6
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@ -111,4 +111,10 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
*/ */
uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
enum pcie_rp_type {
PCIE_RP_UNKNOWN,
PCIE_RP_CPU,
PCIE_RP_PCH,
};
#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */