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Fix some cbmem.h includes

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Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2016-06-15 06:07:55 +03:00
parent bec853e9ad
commit 465eff61f4
7 changed files with 1 additions and 7 deletions
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1
src/cpu/intel/haswell/cache_as_ram.inc
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@@ -17,7 +17,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should * and the space used by the reference code. These 2 values combined should

2
src/cpu/intel/haswell/romstage.c
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@@ -28,7 +28,7 @@
#include <arch/stages.h> #include <arch/stages.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cbfs.h> #include <cbmem.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <reset.h> #include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/cpu/intel/model_2065x/cache_as_ram.inc
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@@ -17,7 +17,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

1
src/drivers/intel/fsp1_0/cache_as_ram.inc
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@@ -18,7 +18,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
cmp $0, %eax cmp $0, %eax
je cache_as_ram je cache_as_ram

1
src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
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@@ -17,7 +17,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
#define CACHE_AS_RAM_SIZE 0x10000 #define CACHE_AS_RAM_SIZE 0x10000
#define CACHE_AS_RAM_BASE 0xd0000 #define CACHE_AS_RAM_BASE 0xd0000

1
src/soc/intel/baytrail/romstage/cache_as_ram.inc
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@@ -17,7 +17,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
#include "fmap_config.h" #include "fmap_config.h"

1
src/soc/intel/broadwell/romstage/cache_as_ram.inc
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@@ -18,7 +18,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h>
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should * and the space used by the reference code. These 2 values combined should