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Sync addw2 and gaze15 with oryp6

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This commit is contained in:
Jeremy Soller
2020-07-01 12:44:59 -06:00
parent 9ba7399ee9
commit 46dacbd7c3
6 changed files with 42 additions and 22 deletions
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5
src/mainboard/system76/addw2/acpi/dgpu.asl
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@@ -29,6 +29,7 @@
Device (\_SB.PCI0.PEGP.DEV0)
{
Name(_ADR, 0x00000000)
Name (_STA, 0xF)
Name (LTRE, 0)
// Memory mapped PCI express registers
@@ -84,8 +85,6 @@ Device (\_SB.PCI0.PEGP.DEV0)
LREV, 1
}
Name (_STA, 0xF)
Method (_ON)
{
Debug = "PEGP.DEV0._ON"
@@ -139,8 +138,6 @@ Device (\_SB.PCI0.PEGP.DEV0)
Debug = " CMDR |= 7"
CMDR |= 7
//TODO: restore subsystem ID
Debug = " _STA = 0xF"
_STA = 0xF
}

13
src/mainboard/system76/addw2/ramstage.c
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@@ -38,10 +38,21 @@ static void dgpu_read_resources(struct device *dev) {
}
}
static void dgpu_enable_resources(struct device *dev) {
printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev));
dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
printk(BIOS_INFO, " subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device);
pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff));
pci_dev_enable_resources(dev);
}
static struct device_operations dgpu_pci_ops_dev = {
.read_resources = dgpu_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable_resources = dgpu_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,

2
src/mainboard/system76/addw2/romstage.c
View File

@@ -80,6 +80,8 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
// Allow memory clocks higher than 2933 MHz
memupd->FspmConfig.SaOcSupport = 1;
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);

5
src/mainboard/system76/gaze15/acpi/dgpu.asl
View File

@@ -29,6 +29,7 @@
Device (\_SB.PCI0.PEGP.DEV0)
{
Name(_ADR, 0x00000000)
Name (_STA, 0xF)
Name (LTRE, 0)
// Memory mapped PCI express registers
@@ -84,8 +85,6 @@ Device (\_SB.PCI0.PEGP.DEV0)
LREV, 1
}
Name (_STA, 0xF)
Method (_ON)
{
Debug = "PEGP.DEV0._ON"
@@ -139,8 +138,6 @@ Device (\_SB.PCI0.PEGP.DEV0)
Debug = " CMDR |= 7"
CMDR |= 7
//TODO: restore subsystem ID
Debug = " _STA = 0xF"
_STA = 0xF
}

13
src/mainboard/system76/gaze15/ramstage.c
View File

@@ -38,10 +38,21 @@ static void dgpu_read_resources(struct device *dev) {
}
}
static void dgpu_enable_resources(struct device *dev) {
printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev));
dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
printk(BIOS_INFO, " subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device);
pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff));
pci_dev_enable_resources(dev);
}
static struct device_operations dgpu_pci_ops_dev = {
.read_resources = dgpu_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable_resources = dgpu_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,

2
src/mainboard/system76/gaze15/romstage.c
View File

@@ -80,6 +80,8 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
// Allow memory clocks higher than 2933 MHz
memupd->FspmConfig.SaOcSupport = 1;
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);