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binaryPI: Drop BINARYPI_LEGACY_WRAPPER support

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Drop all the sources that were guarded with this.

Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Kyösti Mälkki
2017-09-06 15:42:23 +03:00
parent b81731d9db
commit 46f04cbb49
39 changed files with 9 additions and 2074 deletions
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4
src/cpu/amd/pi/Kconfig
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@@ -26,15 +26,11 @@ config CPU_AMD_PI
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
if CPU_AMD_PI
config BINARYPI_LEGACY_WRAPPER
def_bool n
config UDELAY_LAPIC_FIXED_FSB
int
default 200

6
src/cpu/amd/pi/Makefile.inc
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@@ -14,9 +14,3 @@
subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
romstage-y += romstage.c
ramstage-y += amd_late_init.c
endif

36
src/cpu/amd/pi/amd_late_init.c
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@@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <bootstate.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
static void agesawrapper_post_device(void *unused)
{
if (acpi_is_wakeup_s3())
return;
AGESAWRAPPER(amdinitlate);
if (!acpi_s3_resume_allowed())
return;
AGESAWRAPPER(amdS3Save);
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
agesawrapper_post_device, NULL);

55
src/cpu/amd/pi/romstage.c
View File

@@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <cbmem.h>
#include <cpu/amd/car.h>
#include <cpu/x86/mtrr.h>
#include <console/console.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
void asmlinkage early_all_cores(void)
{
amd_initmmio();
}
void *asmlinkage romstage_main(unsigned long bist)
{
int s3resume = 0;
u8 initial_apic_id = cpuid_ebx(1) >> 24;
/* Only BSP returns from here. */
cache_as_ram_main(bist, initial_apic_id);
cbmem_recovery(s3resume);
romstage_handoff_init(s3resume);
char *stack_top = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
stack_top += HIGH_ROMSTAGE_STACK_SIZE;
printk(BIOS_DEBUG, "Move CAR stack.\n");
return (void *)stack_top;
}
void asmlinkage romstage_after_car(void)
{
printk(BIOS_DEBUG, "CAR disabled.\n");
agesa_postcar(NULL);
run_ramstage();
}