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soc/intel/apollolake: Rename PWRMBASE macro and function

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This patch ensures PWRMBASE macro name and function to get PWRMBASE
address on APL SoC is aligned with other IA SoC.

PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS
read_pmc_mmio_bar() ->  pmc_mmio_regs()

Additionally, make `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.

BUG=None
TEST=None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
2022-02-01 19:01:36 +05:30
committed by Martin Roth
parent 1d886639ce
commit 480e7e5ac8
6 changed files with 12 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/apollolake/pmutil.c
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@ -24,14 +24,14 @@
#include "chip.h"
static uintptr_t read_pmc_mmio_bar(void)
uint8_t *pmc_mmio_regs(void)
{
return PMC_BAR0;
return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
}
uintptr_t soc_read_pmc_base(void)
{
return read_pmc_mmio_bar();
return (uintptr_t)pmc_mmio_regs();
}
uint32_t *soc_pmc_etr_addr(void)
@ -153,7 +153,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
void soc_fill_power_state(struct chipset_power_state *ps)
{
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
uintptr_t pmc_bar0 = soc_read_pmc_base();
ps->tco1_sts = tco_read_reg(TCO1_STS);
ps->tco2_sts = tco_read_reg(TCO2_STS);
@ -200,7 +200,7 @@ int soc_get_rtc_failed(void)
int vbnv_cmos_failed(void)
{
uintptr_t pmc_bar = read_pmc_mmio_bar();
uintptr_t pmc_bar = soc_read_pmc_base();
uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1));
int rtc_failure = rtc_failed(gen_pmcon1);