AGESA: Add amd_initcpuio() and amd_initmmio()
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki
@@ -27,6 +27,9 @@
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#
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#*****************************************************************************
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_12_init.c
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113
src/cpu/amd/agesa/family12/fixme.c
Normal file
113
src/cpu/amd/agesa/family12/fixme.c
Normal file
@@ -0,0 +1,113 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include "amdlib.h"
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable MMIO on AMD CPU Address Map Controller */
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/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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PciData = 0x00000B00;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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PciData = 0x00000A03;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set TOM-DFFFFFFF to Node0 Link0. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00DFFF00;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32) MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);
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PciData = 0x00FFFF00 | 0x80;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
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PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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//- PciData = 0x0000F000;
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PciData = 0x00FFF000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000013;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
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Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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/* Enable Non-Post Memory in CPU */
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PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
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PciData = (PciData >> 8) & ~0xff;
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PciData |= 0x80;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Enable memory access */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
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LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
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PciData |= BIT1;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
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LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
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LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
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}
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@@ -17,6 +17,9 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_14_init.c
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99
src/cpu/amd/agesa/family14/fixme.c
Normal file
99
src/cpu/amd/agesa/family14/fixme.c
Normal file
@@ -0,0 +1,99 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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||||
*/
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include "amdlib.h"
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/* Define AMD Ontario APPU SSID/SVID */
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#define AMD_APU_SVID 0x1022
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#define AMD_APU_SSID 0x1234
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
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PciData |= 1 << 7; // set NP (non-posted) bit
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; // last address before non-posted range
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32) MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
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Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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/* Set Ontario Link Data */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
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PciData = 0x01308002;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
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PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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@@ -25,5 +25,8 @@ subdirs-y += ../../../x86/mtrr
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subdirs-y += ../../../x86/pae
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subdirs-y += ../../../x86/smm
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_15_init.c
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281
src/cpu/amd/agesa/family15/fixme.c
Normal file
281
src/cpu/amd/agesa/family15/fixme.c
Normal file
@@ -0,0 +1,281 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
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|
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include "amdlib.h"
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#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
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void amd_initcpuio(void)
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{
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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UINT32 nodes;
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UINT32 node;
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UINT32 sblink;
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UINT32 i;
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UINT32 TOM;
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/* get the number of coherent nodes in the system */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
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LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
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nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
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/* Find out the Link ID of Node0 that connects to the
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* Southbridge (system IO hub). e.g. family10 MCM Processor,
|
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* sbLink is Processor0 Link2, internal Node0 Link3
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
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LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
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sblink = (PciData >> 8) & 3; //assume ganged
|
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|
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/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
|
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for (node = 0; node < nodes; node++) {
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/* clear all MMIO Mapped Base/Limit Registers */
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for (i = 0; i < 8; i++) {
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PciData = 0x00000000;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
|
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|
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/* clear all IO Space Base/Limit Registers */
|
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for (i = 0; i < 4; i++) {
|
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PciData = 0x00000000;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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}
|
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|
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/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
|
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
|
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PciData = 0x00000B00;
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PciData |= sblink << 4;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
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PciData = 0x00000A03;
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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|
||||
/* Set TOM1-FFFFFFFF to Node0 sbLink. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
|
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PciData = 0x00FFFF00;
|
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PciData |= sblink << 4;
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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TOM = (UINT32)MsrRead(TOP_MEM);
|
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PciData = (TOM >> 8) | 0x03;
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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|
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/* Set MMCONF space to Node0 sbLink with NP set.
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* default E0000000-EFFFFFFF
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* Just have all mmio set to non-posted,
|
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* coreboot not implemente the range by range setting yet.
|
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*/
|
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
|
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PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
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PciData = (PciData >> 8) & 0xFFFFFF00;
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PciData |= 0x80; //NP
|
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PciData |= sblink << 4;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
|
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PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03;
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
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|
||||
|
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/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/
|
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
|
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PciData = 0x00FFF000;
|
||||
PciData |= sblink << 4;
|
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
|
||||
PciData = 0x00000033;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
}
|
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#else
|
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|
||||
#define MMIO_NP_BIT BIT7
|
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|
||||
void amd_initcpuio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
UINT32 PciData;
|
||||
PCI_ADDR PciAddress;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
UINT32 TopMem;
|
||||
UINT32 nodes;
|
||||
UINT32 node;
|
||||
UINT32 SbLink;
|
||||
UINT32 i;
|
||||
|
||||
/* get the number of coherent nodes in the system */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60);
|
||||
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
nodes = ((PciData >> 4) & 7) + 1; //nodes[6:4]
|
||||
/* Find out the Link ID of Node0 that connects to the
|
||||
* Southbridge (system IO hub). e.g. family10 MCM Processor,
|
||||
* SbLink is Processor0 Link2, internal Node0 Link3
|
||||
*/
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64);
|
||||
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
SbLink = (PciData >> 8) & 3; //assume ganged
|
||||
/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
|
||||
for (node = 0; node < nodes; node++) {
|
||||
/* clear all MMIO Mapped Base/Limit Registers */
|
||||
for (i = 0; i < 8; i++) {
|
||||
PciData = 0x00000000;
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8);
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8);
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
/* clear all IO Space Base/Limit Registers */
|
||||
for (i = 0; i < 4; i++) {
|
||||
PciData = 0x00000000;
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8);
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8);
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
|
||||
/* Enable MMIO on AMD CPU Address Map Controller */
|
||||
|
||||
/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
|
||||
PciData = (0xA0000 >> 8) | 3;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
|
||||
PciData = 0xB0000 >> 8;
|
||||
PciData &= (~0xFF);
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Set UMA MMIO. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
|
||||
LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
|
||||
TopMem = (UINT32) MsrReg;
|
||||
MsrReg = (MsrReg >> 8) | 3;
|
||||
PciData = (UINT32) MsrReg;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c);
|
||||
if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) {
|
||||
PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8;
|
||||
} else {
|
||||
PciData = (0x100000000ull - 1) >> 8;
|
||||
}
|
||||
PciData &= (~0xFF);
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Set PCIE MMIO. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90);
|
||||
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94);
|
||||
PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF);
|
||||
PciData &= (~0xFF);
|
||||
PciData |= MMIO_NP_BIT;
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Set XAPIC MMIO. 24K */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98);
|
||||
PciData = (0xFEC00000 >> 8) | 3;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c);
|
||||
PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8);
|
||||
PciData &= (~0xFF);
|
||||
PciData |= MMIO_NP_BIT;
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0);
|
||||
PciData = (0xFEE00000 >> 8) | 3;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8);
|
||||
PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8;
|
||||
PciData &= (~0xFF);
|
||||
PciData |= MMIO_NP_BIT;
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
|
||||
PciData = 0x13;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
|
||||
PciData = 0x00FFF000;
|
||||
PciData &= (~0x7F);
|
||||
PciData |= SbLink << 4;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void amd_initmmio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/*
|
||||
* Set the MMIO Configuration Base Address and Bus Range onto
|
||||
* MMIO configuration base Address MSR register.
|
||||
*/
|
||||
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
|
||||
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
|
||||
|
||||
/*
|
||||
* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
|
||||
*/
|
||||
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
|
||||
MsrReg = MsrReg | (1ULL << 46);
|
||||
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
|
||||
|
||||
#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
|
||||
UINT32 PciData;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
/* Set PCIE MMIO. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x94);
|
||||
/* FIXME: LSB bits are not cleared for PciData. */
|
||||
PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) | MMIO_NP_BIT;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x90);
|
||||
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Enable memory access */
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
|
||||
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
|
||||
PciData |= BIT1;
|
||||
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
|
||||
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
|
||||
#endif
|
||||
|
||||
/* Set ROM cache onto WP to decrease post time */
|
||||
MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
|
||||
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
|
||||
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
|
||||
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
|
||||
}
|
||||
@@ -17,6 +17,9 @@
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
romstage-y += fixme.c
|
||||
|
||||
ramstage-y += fixme.c
|
||||
ramstage-y += chip_name.c
|
||||
ramstage-y += model_15_init.c
|
||||
|
||||
|
||||
91
src/cpu/amd/agesa/family15rl/fixme.c
Normal file
91
src/cpu/amd/agesa/family15rl/fixme.c
Normal file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include "amdlib.h"
|
||||
|
||||
void amd_initcpuio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
UINT32 PciData;
|
||||
PCI_ADDR PciAddress;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/* Enable legacy video routing: D18F1xF4 VGA Enable */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
|
||||
PciData = 1;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
|
||||
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
|
||||
* set to non-posted regions.
|
||||
*/
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
|
||||
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
|
||||
PciData |= 1 << 7; /* set NP (non-posted) bit */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
|
||||
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Map the remaining PCI hole as posted MMIO */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
|
||||
PciData = 0x00FECF00; /* last address before non-posted range */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
|
||||
MsrReg = (MsrReg >> 8) | 3;
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
|
||||
PciData = (UINT32)MsrReg;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Send all IO (0000-FFFF) to southbridge. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
|
||||
PciData = 0x0000F000;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
|
||||
PciData = 0x00000003;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
|
||||
void amd_initmmio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/*
|
||||
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
|
||||
Address MSR register.
|
||||
*/
|
||||
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
|
||||
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
|
||||
|
||||
/*
|
||||
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
|
||||
*/
|
||||
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
|
||||
MsrReg = MsrReg | 0x0000400000000000;
|
||||
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
|
||||
|
||||
/* Set ROM cache onto WP to decrease post time */
|
||||
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
|
||||
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
|
||||
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
|
||||
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
|
||||
}
|
||||
@@ -17,6 +17,9 @@
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
romstage-y += fixme.c
|
||||
|
||||
ramstage-y += fixme.c
|
||||
ramstage-y += chip_name.c
|
||||
ramstage-y += model_15_init.c
|
||||
|
||||
|
||||
91
src/cpu/amd/agesa/family15tn/fixme.c
Normal file
91
src/cpu/amd/agesa/family15tn/fixme.c
Normal file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include "amdlib.h"
|
||||
|
||||
void amd_initcpuio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
UINT32 PciData;
|
||||
PCI_ADDR PciAddress;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/* Enable legacy video routing: D18F1xF4 VGA Enable */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
|
||||
PciData = 1;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
|
||||
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
|
||||
* set to non-posted regions.
|
||||
*/
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
|
||||
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
|
||||
PciData |= 1 << 7; /* set NP (non-posted) bit */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
|
||||
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Map the remaining PCI hole as posted MMIO */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
|
||||
PciData = 0x00FECF00; /* last address before non-posted range */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
|
||||
MsrReg = (MsrReg >> 8) | 3;
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
|
||||
PciData = (UINT32)MsrReg;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Send all IO (0000-FFFF) to southbridge. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
|
||||
PciData = 0x0000F000;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
|
||||
PciData = 0x00000003;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
|
||||
void amd_initmmio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/*
|
||||
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
|
||||
Address MSR register.
|
||||
*/
|
||||
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
|
||||
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
|
||||
|
||||
/*
|
||||
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
|
||||
*/
|
||||
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
|
||||
MsrReg = MsrReg | 0x0000400000000000;
|
||||
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
|
||||
|
||||
/* Set ROM cache onto WP to decrease post time */
|
||||
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
|
||||
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
|
||||
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
|
||||
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
|
||||
}
|
||||
@@ -17,6 +17,9 @@
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
romstage-y += fixme.c
|
||||
|
||||
ramstage-y += fixme.c
|
||||
ramstage-y += chip_name.c
|
||||
ramstage-y += model_16_init.c
|
||||
|
||||
|
||||
91
src/cpu/amd/agesa/family16kb/fixme.c
Normal file
91
src/cpu/amd/agesa/family16kb/fixme.c
Normal file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include "amdlib.h"
|
||||
|
||||
void amd_initcpuio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
UINT32 PciData;
|
||||
PCI_ADDR PciAddress;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/* Enable legacy video routing: D18F1xF4 VGA Enable */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
|
||||
PciData = 1;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
|
||||
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
|
||||
* set to non-posted regions.
|
||||
*/
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
|
||||
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
|
||||
PciData |= 1 << 7; /* set NP (non-posted) bit */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
|
||||
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Map the remaining PCI hole as posted MMIO */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
|
||||
PciData = 0x00FECF00; /* last address before non-posted range */
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
|
||||
MsrReg = (MsrReg >> 8) | 3;
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
|
||||
PciData = (UINT32)MsrReg;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
|
||||
/* Send all IO (0000-FFFF) to southbridge. */
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
|
||||
PciData = 0x0000F000;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
|
||||
PciData = 0x00000003;
|
||||
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
|
||||
}
|
||||
|
||||
void amd_initmmio(void)
|
||||
{
|
||||
UINT64 MsrReg;
|
||||
AMD_CONFIG_PARAMS StdHeader;
|
||||
|
||||
/*
|
||||
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
|
||||
Address MSR register.
|
||||
*/
|
||||
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
|
||||
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
|
||||
|
||||
/*
|
||||
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
|
||||
*/
|
||||
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
|
||||
MsrReg = MsrReg | 0x0000400000000000;
|
||||
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
|
||||
|
||||
/* Set ROM cache onto WP to decrease post time */
|
||||
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
|
||||
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
|
||||
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
|
||||
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
|
||||
}
|
||||
Reference in New Issue
Block a user