src/mainboard: Remove unnecessary space after casts

Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>

src/mainboard/51nb/x210/romstage.c

@@ -38,6 +38,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mem_cfg->DqPinsInterleaved = TRUE;
 	mem_cfg->CaVrefConfig = 2;
 	mem_cfg->MemorySpdDataLen = blk.len;
-	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
-	mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
 }

src/mainboard/acer/aspire_vn7_572g/ec.c

@@ -53,15 +53,15 @@ uint8_t ec_cmd_94_query(void)
 
 uint8_t ec_idx_read(uint16_t addr)
 {
-	outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT);
+	outb((uint8_t)(addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT);
-	outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT);
+	outb((uint8_t)addr, EC_INDEX_IO_LOW_ADDR_PORT);
 	return inb(EC_INDEX_IO_DATA_PORT);
 }
 
 void ec_idx_write(uint16_t addr, uint8_t data)
 {
-	outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT);
+	outb((uint8_t)(addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT);
-	outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT);
+	outb((uint8_t)addr, EC_INDEX_IO_LOW_ADDR_PORT);
 	outb(data, EC_INDEX_IO_DATA_PORT);
 }
 

src/mainboard/acer/aspire_vn7_572g/mainboard.c

@@ -81,7 +81,7 @@ static void ec_send_time(void)
 	send_ec_command(0xE0);
 	for (int i = 0; i < 4; i++) {
 		/* Shift bytes */
-		ec_time_byte = (uint8_t) (ec_time >> (i * 8));
+		ec_time_byte = (uint8_t)(ec_time >> (i * 8));
 		printk(BIOS_DEBUG, "EC: Sending 0x%x (iteration %d)\n", ec_time_byte, i);
 		send_ec_data(ec_time_byte);
 	}

src/mainboard/acer/aspire_vn7_572g/romstage.c

@@ -30,8 +30,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mem_cfg->CaVrefConfig = 2;
 	mem_cfg->DqPinsInterleaved = 1;
 	mem_cfg->MemorySpdDataLen = blk.len;
-	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
-	mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
 
 	mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[1] = 1;
 	mem_cfg->PchSataHsioRxGen3EqBoostMag[1] = 1;

src/mainboard/emulation/qemu-armv7/mainboard.c

@@ -15,7 +15,7 @@ static void init_gfx(void)
 	/* height is at most 1024 */
 	int width = 800, height = 600;
 	uint32_t framebuffer = 0x4c000000;
-	pl111 = (uint32_t *) 0x10020000;
+	pl111 = (uint32_t *)0x10020000;
 	write32(pl111, (width / 4) - 4);
 	write32(pl111 + 1, height - 1);
 	/* registers 2, 3 and 5 are ignored by qemu. Set them correctly if

src/mainboard/emulation/qemu-i440fx/memmap.c

@@ -22,11 +22,11 @@ unsigned long qemu_get_high_memory_size(void)
 {
 	unsigned long high;
 	outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT);
-	high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22;
+	high = ((unsigned long)inb(CMOS_DATA_PORT)) << 22;
 	outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT);
-	high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
+	high |= ((unsigned long)inb(CMOS_DATA_PORT)) << 14;
 	outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT);
-	high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
+	high |= ((unsigned long)inb(CMOS_DATA_PORT)) << 6;
 	return high;
 }
 
@@ -34,9 +34,9 @@ unsigned long qemu_get_memory_size(void)
 {
 	unsigned long tomk;
 	outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT);
-	tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
+	tomk = ((unsigned long)inb(CMOS_DATA_PORT)) << 14;
 	outb(LOW_RAM_ADDR, CMOS_ADDR_PORT);
-	tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
+	tomk |= ((unsigned long)inb(CMOS_DATA_PORT)) << 6;
 	tomk += 16 * 1024;
 	return tomk;
 }

src/mainboard/emulation/qemu-power8/uart.c

@@ -7,7 +7,7 @@
 static uint8_t *buf = (void *)0;
 uintptr_t uart_platform_base(unsigned int idx)
 {
-	return (uintptr_t) buf;
+	return (uintptr_t)buf;
 }
 
 void uart_init(unsigned int idx)

src/mainboard/emulation/qemu-riscv/uart.c

@@ -6,5 +6,5 @@
 
 uintptr_t uart_platform_base(unsigned int idx)
 {
-	return (uintptr_t) QEMU_VIRT_UART0;
+	return (uintptr_t)QEMU_VIRT_UART0;
 }

src/mainboard/emulation/spike-riscv/uart.c

@@ -5,5 +5,5 @@
 
 uintptr_t uart_platform_base(unsigned int idx)
 {
-	return (uintptr_t) 0x02100000;
+	return (uintptr_t)0x02100000;
 }

src/mainboard/getac/p470/acpi_tables.c

@@ -17,7 +17,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 
 	acpi_header_t *header = &(ecdt->header);
 
-	memset((void *) ecdt, 0, ecdt_len);
+	memset((void *)ecdt, 0, ecdt_len);
 
 	/* fill out header fields */
 	memcpy(header->signature, "ECDT", 4);
@@ -48,7 +48,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 	memcpy(ecdt->ec_id, ec_id, sizeof(ec_id));
 
 	header->checksum =
-	    acpi_checksum((void *) ecdt, ecdt_len);
+	    acpi_checksum((void *)ecdt, ecdt_len);
 
 	return header->length;
 }

src/mainboard/google/brya/variants/moli/ramstage.c

@@ -23,7 +23,7 @@ static void devtree_update_emmc_rtd3(void)
 	if (board_ver <= 1)
 		return;
 
-	config->enable_gpio = (struct acpi_gpio) ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21);
+	config->enable_gpio = (struct acpi_gpio)ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21);
 }
 
 const struct cpu_power_limits limits[] = {

src/mainboard/google/storm/cdp.c

@@ -49,7 +49,7 @@ void board_nand_init(void)
 	if (board_id() != BOARD_ID_PROTO_0_2_NAND)
 		return;
 
-	ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
+	ebi2_regs = (struct ebi2cr_regs *)EBI2CR_BASE;
 
 	nand_clock_config();
 	configure_nand_gpio();

src/mainboard/ocp/deltalake/ipmi.c

@@ -20,7 +20,7 @@ enum cb_err ipmi_get_pcie_config(uint8_t *pcie_config)
 	struct ipmi_config_rsp rsp;
 
 	ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0,
-			IPMI_OEM_GET_PCIE_CONFIG, NULL, 0, (unsigned char *) &rsp,
+			IPMI_OEM_GET_PCIE_CONFIG, NULL, 0, (unsigned char *)&rsp,
 			sizeof(rsp));
 
 	if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) {
@@ -46,7 +46,7 @@ enum cb_err ipmi_get_slot_id(uint8_t *slot_id)
 	struct ipmi_config_rsp rsp;
 
 	ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID,
-			NULL, 0, (unsigned char *) &rsp, sizeof(rsp));
+			NULL, 0, (unsigned char *)&rsp, sizeof(rsp));
 
 	if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) {
 		printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",

src/mainboard/ocp/deltalake/romstage.c

@@ -105,7 +105,7 @@ static void mainboard_config_upd(FSPM_UPD *mupd)
 	}
 
 	/* Select DDR Frequency Limit */
-	if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const) &val_int)) {
+	if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const)&val_int)) {
 		printk(BIOS_INFO, "Setting DdrFreqLimit %d from VPD\n", val_int);
 		mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(val_int);
 	} else {

src/mainboard/ocp/tiogapass/romstage.c

@@ -32,17 +32,17 @@ static void mainboard_config_iio(FSPM_UPD *mupd)
 {
 	memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table));
 	mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
-		(UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf;
+		(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf;
 	mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
 		ARRAY_SIZE(tp_iio_bifur_table);
 
 	mupd->FspmConfig.IioPciConfig.ConfigurationTable =
-		(UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
+		(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0;
 	mupd->FspmConfig.IioPciConfig.NumberOfEntries =
 		ARRAY_SIZE(tp_iio_pci_port_skt0);
 
 	mupd->FspmConfig.PchPciConfig.PciPortConfig =
-		(UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
+		(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0;
 	mupd->FspmConfig.PchPciConfig.NumberOfEntries =
 		ARRAY_SIZE(tp_pch_pci_port_skt0);
 

src/mainboard/pcengines/apu2/irq_tables.c

@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

src/mainboard/protectli/vault_bsw/romstage.c

@@ -15,7 +15,7 @@ void mainboard_after_memory_init(void)
 	 * FSP enables internal UART. Disable it and re-enable Super I/O UART to
 	 * prevent loss of debug information on serial.
 	 */
-	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0);
+	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32)0);
 	ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
 }
 

src/mainboard/purism/librem_skl/romstage.c

@@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mem_cfg->DqPinsInterleaved = TRUE;
 	mem_cfg->CaVrefConfig = 2;
 	mem_cfg->MemorySpdDataLen = blk.len;
-	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
 
 	/* Enable and set SATA HSIO adjustments for ports 0 and 2 */
 	mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1;

src/mainboard/scaleway/tagada/bmcinfo.c

@@ -94,7 +94,7 @@ static bool bmcinfo_is_valid(size_t minsize)
 char *bmcinfo_serial(void)
 {
 	if (IS_BMC_INFO_FIELD_VALID(bmcSerial))
-		return (char *) BMC_INFO->bmcSerial;
+		return (char *)BMC_INFO->bmcSerial;
 	return NULL;
 }
 

src/mainboard/siemens/mc_apl1/mainboard.c

@@ -264,7 +264,7 @@ static void wait_for_legacy_dev(void *unused)
 		return;
 
 	/* Get legacy delay parameter from hwinfo. */
-	if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
+	if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay,
 			      sizeof(legacy_delay)) != sizeof(legacy_delay))
 		return;
 

src/mainboard/siemens/mc_ehl/mainboard.c

@@ -100,7 +100,7 @@ static void wait_for_legacy_dev(void *unused)
 		return;
 
 	/* Get legacy delay parameter from hwinfo. */
-	if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
+	if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay,
 			      sizeof(legacy_delay)) != sizeof(legacy_delay))
 		return;