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soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices

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This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.

Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Subrata Banik 2024-03-16 18:11:53 +05:30
parent aaacd5083a
commit 4866712b04
3 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/rex/Kconfig
View File

@ -43,7 +43,6 @@ config BOARD_GOOGLE_BASEBOARD_OVIS
select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE select RT8168_SET_LED_MODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@ -59,7 +58,6 @@ config BOARD_GOOGLE_BASEBOARD_REX
select HAVE_SLP_S0_GATE select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MEMORY_SOLDERDOWN select MEMORY_SOLDERDOWN
select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_METEORLAKE_U_H

1
src/mainboard/intel/mtlrvp/Kconfig
View File

@ -19,7 +19,6 @@ config BOARD_INTEL_MTLRVP_COMMON
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_METEORLAKE_U_H

2
src/soc/intel/meteorlake/Kconfig
View File

@ -84,7 +84,7 @@ config SOC_INTEL_METEORLAKE
select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET