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nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>

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Also replace 'reg' with 'reg32'.

Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2021-01-31 08:23:00 +01:00
committed by Patrick Georgi
parent 875c21f491
commit 487c1a24f5
1 changed files with 4 additions and 3 deletions
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7
src/northbridge/intel/i945/bootblock.c
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@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <arch/pci_io_cfg.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "i945.h"
static uint32_t encode_pciexbar_length(void)
@@ -27,6 +28,6 @@ void bootblock_early_northbridge_init(void)
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}