Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
3187d0267d
commit
4885daadb3
@@ -2,9 +2,16 @@ menu "Console"
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# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
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config CONSOLE_SERIAL8250
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bool "Serial port console output"
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depends on HAVE_UART_IO_MAPPED
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default y
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help
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Send coreboot debug output to a serial port console.
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Send coreboot debug output to an I/O mapped serial port console.
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config CONSOLE_SERIAL8250MEM
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bool "Serial port console output (memory mapped)"
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depends on HAVE_UART_MEMORY_MAPPED
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help
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Send coreboot debug output to a memory mapped serial port console.
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choice
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prompt "Serial port"
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@@ -43,7 +50,7 @@ config TTYS0_BASE
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choice
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prompt "Baud rate"
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default CONSOLE_SERIAL_115200
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depends on CONSOLE_SERIAL8250
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depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
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config CONSOLE_SERIAL_115200
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bool "115200"
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@@ -82,7 +89,7 @@ config TTYS0_BAUD
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config TTYS0_LCS
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int
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default 3
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depends on CONSOLE_SERIAL8250
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depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
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# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
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config HAVE_USBDEBUG
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