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mb/google/brya/var/agah: Update Aux settings

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Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.

Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Tony Huang
2022-02-10 16:19:03 +08:00
committed by Felix Held
parent b2e9193231
commit 4893003581
1 changed files with 4 additions and 1 deletions
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5
src/mainboard/google/brya/variants/agah/overridetree.cb
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@@ -1,5 +1,4 @@
chip soc/intel/alderlake chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |
@@ -31,6 +30,10 @@ chip soc/intel/alderlake
}, },
}" }"
register "SaGv" = "SaGv_Enabled"
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # register "usb2_ports[4]" = "USB2_PORT_EMPTY" #