Refactor GC6 support for all boards

Change-Id: Id9191c76e0055d5f02a1de8c25a35cf05718c092

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (\_SB.PCI0.PEGP) {
-	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
-
-	PowerResource (PWRR, 0, 0) {
-		Name (_STA, 1)
-
-		Method (_ON) {
-			Debug = "PEGP.PWRR._ON"
-			If (_STA != 1) {
-				\_SB.PCI0.PEGP.DEV0._ON ()
-				_STA = 1
-			}
-		}
-
-		Method (_OFF) {
-			Debug = "PEGP.PWRR._OFF"
-			If (_STA != 0) {
-				\_SB.PCI0.PEGP.DEV0._OFF ()
-				_STA = 0
-			}
-		}
-	}
-
-	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
-	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
-	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
-}
-
-Device (\_SB.PCI0.PEGP.DEV0) {
-	Name(_ADR, 0x00000000)
-	Name (_STA, 0xF)
-	Name (LTRE, 0)
-
-	// Memory mapped PCI express registers
-	// Not sure what this stuff is, but it is used to get into GC6
-        // TODO: use GPU config to generate address
-	OperationRegion (RPCX, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
-	Field (RPCX, ByteAcc, NoLock, Preserve) {
-		PVID,   16,
-		PDID,   16,
-		CMDR,   8,
-		Offset (0x19),
-		PRBN,   8,
-		Offset (0x84),
-		D0ST,   2,
-		Offset (0xAA),
-		CEDR,   1,
-		Offset (0xAC),
-			,   4,
-		CMLW,   6,
-		Offset (0xB0),
-		ASPM,   2,
-			,   2,
-		P0LD,   1,
-		RTLK,   1,
-		Offset (0xC9),
-			,   2,
-		LREN,   1,
-		Offset (0x11A),
-			,   1,
-		VCNP,   1,
-		Offset (0x214),
-		Offset (0x216),
-		P0LS,   4,
-		Offset (0x248),
-			,   7,
-		Q0L2,   1,
-		Q0L0,   1,
-		Offset (0x504),
-		Offset (0x506),
-		PCFG,   2,
-		Offset (0x508),
-		TREN,   1,
-		Offset (0xC20),
-			,   4,
-		P0AP,   2,
-		Offset (0xC38),
-			,   3,
-		P0RM,   1,
-		Offset (0xC74),
-		P0LT,   4,
-		Offset (0xD0C),
-			,   20,
-		LREV,   1
-	}
-
-	Method (_ON) {
-		Debug = "PEGP.DEV0._ON"
-
-		If (_STA != 0xF) {
-			Debug = "  If DGPU_PWR_EN low"
-			If (! GTXS (DGPU_PWR_EN)) {
-				Debug = "    DGPU_PWR_EN high"
-				STXS (DGPU_PWR_EN)
-
-				Debug = "    Sleep 16"
-				Sleep (16)
-			}
-
-			Debug = "  DGPU_RST_N high"
-			STXS(DGPU_RST_N)
-
-			Debug = "  Sleep 10"
-			Sleep (10)
-
-			Debug = "  Q0L0 = 1"
-			Q0L0 = 1
-
-			Debug = "  Sleep 16"
-			Sleep (16)
-
-			Debug = "  While Q0L0"
-			Local0 = 0
-			While (Q0L0) {
-				If ((Local0 > 4)) {
-					Debug = "    While Q0L0 timeout"
-					Break
-				}
-
-				Sleep (16)
-				Local0++
-			}
-
-			Debug = "  P0RM = 0"
-			P0RM = 0
-
-			Debug = "  P0AP = 0"
-			P0AP = 0
-
-			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
-			LREN = LTRE
-
-			Debug = "  CEDR = 1"
-			CEDR = 1
-
-			Debug = "  CMDR |= 7"
-			CMDR |= 7
-
-			Debug = "  _STA = 0xF"
-			_STA = 0xF
-		}
-	}
-
-	Method (_OFF) {
-		Debug = "PEGP.DEV0._OFF"
-
-		If (_STA != 0x5) {
-			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
-			LTRE = LREN
-
-			Debug = "  Q0L2 = 1"
-			Q0L2 = 1
-
-			Debug = "  Sleep 16"
-			Sleep (16)
-
-			Debug = "  While Q0L2"
-			Local0 = Zero
-			While (Q0L2) {
-				If ((Local0 > 4)) {
-					Debug = "    While Q0L2 timeout"
-					Break
-				}
-
-				Sleep (16)
-				Local0++
-			}
-
-			Debug = "  P0RM = 1"
-			P0RM = 1
-
-			Debug = "  P0AP = 3"
-			P0AP = 3
-
-			Debug = "  Sleep 10"
-			Sleep (10)
-
-			Debug = "  DGPU_RST_N low"
-			CTXS(DGPU_RST_N)
-
-			Debug = "  While DGPU_GC6 low"
-			Local0 = Zero
-			While (! GRXS(DGPU_GC6)) {
-				If ((Local0 > 4)) {
-					Debug = "    While DGPU_GC6 low timeout"
-
-					Debug = "    DGPU_PWR_EN low"
-					CTXS (DGPU_PWR_EN)
-					Break
-				}
-
-				Sleep (16)
-				Local0++
-			}
-
-			Debug = "  _STA = 0x5"
-			_STA = 0x5
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/mainboard/system76/addw1/Makefile.inc

@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variant/gpio.h>
-#include <drivers/gfx/nvidia/acpi/gpu.asl>
 
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
@@ -9,6 +8,12 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F22
 #define DGPU_PWR_EN	GPP_F23
 #define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
 
 #ifndef __ACPI__
 void variant_configure_early_gpios(void);

src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/galp5/acpi/dgpu.asl

@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB.PCI0.RP05)
-{
-	Device (DEV0)
-	{
-		Name(_ADR, 0x00000000)
-
-		// Fix SSID being lost across sleep by saving it
-		Name(NVSS, 0x00000000)
-
-		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
-		Field (PCIC, DwordAcc, NoLock, Preserve)
-		{
-			Offset (0x40),
-			SSID, 32,
-		}
-
-		Name (_PR0, Package () { PWRR })
-		Name (_PR3, Package () { PWRR })
-		PowerResource (PWRR, 0, 0)
-		{
-			Name (_STA, 1)
-
-			Method (_ON)
-			{
-				^^SSID = ^^NVSS
-				Printf("GPU _ON %o", ToHexString(^^SSID))
-				_STA = 1
-			}
-
-			Method (_OFF)
-			{
-				^^NVSS = ^^SSID
-				Printf("GPU _OFF %o", ToHexString(^^SSID))
-				_STA = 0
-			}
-		}
-	}
-}

src/mainboard/system76/galp5/acpi/mainboard.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "dgpu.asl"
+#include "../gpio.h"
 
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
@@ -10,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (RP01) { // Remapped from RP05
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }

src/mainboard/system76/galp5/devicetree.cb

@@ -263,17 +263,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[4]" = "1"
 			register "PcieClkSrcUsage[2]" = "4"
 			register "PcieClkSrcClkReq[2]" = "2"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "2" # PEG_CLKREQ#
-				device generic 0 on end
-			end
-
 			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device

src/mainboard/system76/galp5/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_U4
 #define DGPU_PWR_EN	GPP_U5
 #define DGPU_GC6	GPP_D2
+#define DGPU_SSID	0x40181558
 
 #ifndef __ACPI__
 

src/mainboard/system76/gaze15/Makefile.inc

@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variant/gpio.h>
-#include <drivers/gfx/nvidia/acpi/gpu.asl>
 
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
@@ -11,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F22
 #define DGPU_PWR_EN	GPP_F23
 #define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85501558
 
 #ifndef __ACPI__
 void variant_configure_early_gpios(void);

src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F22
 #define DGPU_PWR_EN	GPP_F23
 #define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85201558
 
 #ifndef __ACPI__
 void variant_configure_early_gpios(void);

src/mainboard/system76/gaze16/acpi/dgpu.asl

@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB.PCI0.PEG1)
-{
-	Device (DEV0)
-	{
-		Name(_ADR, 0x00000000)
-
-		// Fix SSID being lost across sleep by saving it
-		Name(NVSS, 0x00000000)
-
-		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
-		Field (PCIC, DwordAcc, NoLock, Preserve)
-		{
-			Offset (0x40),
-			SSID, 32,
-		}
-
-		Name (_PR0, Package () { PWRR })
-		Name (_PR3, Package () { PWRR })
-		PowerResource (PWRR, 0, 0)
-		{
-			Name (_STA, 1)
-
-			Method (_ON)
-			{
-				^^SSID = ^^NVSS
-				Printf("GPU _ON %o", ToHexString(^^SSID))
-				_STA = 1
-			}
-
-			Method (_OFF)
-			{
-				^^NVSS = ^^SSID
-				Printf("GPU _OFF %o", ToHexString(^^SSID))
-				_STA = 0
-			}
-		}
-	}
-}

src/mainboard/system76/gaze16/acpi/mainboard.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "dgpu.asl"
+#include <variant/gpio.h>
 
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
@@ -10,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }

src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F8
 #define DGPU_PWR_EN	GPP_F9
 #define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50151558
 
 #ifndef __ACPI__
 

src/mainboard/system76/gaze16/variants/3050/overridetree.cb

@@ -6,17 +6,6 @@ chip soc/intel/tigerlake
 			# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
 			register "PcieClkSrcUsage[0]" = "0x42"
 			register "PcieClkSrcClkReq[0]" = "0"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "0" # GFX_CLKREQ0#
-				device generic 0 on end
-			end
-
 			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device

src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F8
 #define DGPU_PWR_EN	GPP_F9
 #define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50e11558
 
 #ifndef __ACPI__
 

src/mainboard/system76/gaze16/variants/3060/overridetree.cb

@@ -6,17 +6,6 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
-			end
-
 			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/gpio.h>
-#include <drivers/gfx/nvidia/acpi/gpu.asl>
 
 #define EC_GPE_SCI 0x17 /* GPP_B23 */
 #define EC_GPE_SWI 0x26 /* GPP_G6 */
@@ -12,6 +11,10 @@ Scope (\_SB)
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/oryp5/include/mainboard/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F22
 #define DGPU_PWR_EN	GPP_F23
 #define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x95e61558
 
 #ifndef __ACPI__
 void mainboard_configure_early_gpios(void);

src/mainboard/system76/oryp6/Makefile.inc

@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/oryp6/acpi/mainboard.asl

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variant/gpio.h>
-#include <drivers/gfx/nvidia/acpi/gpu.asl>
 
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
@@ -11,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x50d31558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x65e51558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/oryp6/variants/oryp7/include/variant/romstage.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_ROMSTAGE_H
+#define VARIANT_ROMSTAGE_H
+
+#include <fsp/soc_binding.h>
+
+void variant_configure_fspm(FSPM_UPD *memupd);
+
+#endif

src/mainboard/system76/oryp8/acpi/mainboard.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "dgpu.asl"
+#include <mainboard/gpio.h>
 
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
@@ -10,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }

src/mainboard/system76/oryp8/devicetree.cb

@@ -92,17 +92,6 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
-			end
-
 			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device

src/mainboard/system76/oryp8/include/mainboard/gpio.h

@@ -8,6 +8,7 @@
 #define DGPU_RST_N	GPP_F8
 #define DGPU_PWR_EN	GPP_F9
 #define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x65f11558
 
 #ifndef __ACPI__
 void mainboard_configure_early_gpios(void);