From 48f69da67b7db193bc1cacfd6c7f1a97553980a0 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Wed, 8 Jun 2022 21:30:26 +0100 Subject: [PATCH] soc/intel/apollolake: Enable SATA Power Optimisation Enable PwrOptEnable FSP S UPD and hook it to the inverted value of SataPwrOptimizeDisable to allow it to be disabled from the devicetree. Signed-off-by: Sean Rhodes Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Lean Sheng Tan --- src/soc/intel/apollolake/chip.c | 3 +++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ac8dfdf568..bbf0564906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -734,6 +734,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) sizeof(silconfig->SataPortsEnable)); } + /* Sata Power Optimisation */ + silconfig->SataPwrOptEnable = !(cfg->SataPwrOptimizeDisable); + /* 8254 Timer */ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); silconfig->Timer8254ClkSetting = use_8254; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c220453595..9352dcbab5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -212,6 +212,9 @@ struct soc_intel_apollolake_config { /* SATA Aggressive Link Power Management */ uint8_t DisableSataSalpSupport; + + /* Sata Power Optimisation */ + uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_apollolake_config config_t;