sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/xeon_sp: Share unlock_pam_regions()

Browse Source 
unlock_pam_regions() is needed for SKX and CPX. Put the codes into
chip_gen1.c so that it could be shared among SoC generations.

After shared, unlock_pam_regions() is still called from SKX and
CPX SoC specific codes. SPR will also use chip_gen1.c, but it will
not call unlock_pam_regions().

TEST=Build and boot on intel/archercity CRB

Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Shuo Liu
2024-04-02 03:28:34 +08:00
committed by Lean Sheng Tan
parent d57d5e3b37
commit 49437a6945
4 changed files with 30 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/soc/intel/xeon_sp/chip_gen1.c
View File

@@ -4,6 +4,9 @@
#include <assert.h> #include <assert.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
#include <intelblocks/acpi.h> #include <intelblocks/acpi.h>
#include <post.h> #include <post.h>
#include <soc/acpi.h> #include <soc/acpi.h>
@@ -199,3 +202,28 @@ void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus,
else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(sr)) else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(sr))
create_ioat_domains(dp, bus, sr, pci_segment_group); create_ioat_domains(dp, bus, sr, pci_segment_group);
} }
/*
* Route PAM segment access to DRAM
* Only call this code from socket0!
*/
void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}

22
src/soc/intel/xeon_sp/cpx/chip.c
View File

@@ -161,28 +161,6 @@ static void chip_final(void *data)
set_bios_init_completion(); set_bios_init_completion();
} }
/* Only call this code from socket0! */
static void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}
static void chip_init(void *data) static void chip_init(void *data)
{ {
unlock_pam_regions(); unlock_pam_regions();

2
src/soc/intel/xeon_sp/include/soc/chip_common.h
View File

@@ -89,4 +89,6 @@ bool is_cxl_domain(struct device *dev);
#define is_dev_on_domain0(dev) (is_domain0(dev_get_pci_domain(dev))) #define is_dev_on_domain0(dev) (is_domain0(dev_get_pci_domain(dev)))
#define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) #define is_stack0(socket, stack) (socket == 0 && stack == IioStack0)
void unlock_pam_regions(void);
#endif /* _CHIP_COMMON_H_ */ #endif /* _CHIP_COMMON_H_ */

25
src/soc/intel/xeon_sp/skx/chip.c
View File

@@ -3,9 +3,6 @@
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
#include <gpio.h> #include <gpio.h>
#include <intelblocks/acpi.h> #include <intelblocks/acpi.h>
#include <soc/acpi.h> #include <soc/acpi.h>
@@ -38,28 +35,6 @@ static void soc_enable_dev(struct device *dev)
} }
} }
/* Only call this code from socket0! */
static void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}
static void soc_init(void *data) static void soc_init(void *data)
{ {
unlock_pam_regions(); unlock_pam_regions();