{cpu/nb}/amd/family16: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
@@ -2,7 +2,6 @@
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config CPU_AMD_AGESA
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bool
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default n
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select ARCH_X86
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select DRIVERS_AMD_PI
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@@ -44,5 +43,3 @@ config ENABLE_MRC_CACHE
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from non-volatile memory.
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endif # CPU_AMD_AGESA
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source "src/cpu/amd/agesa/family16kb/Kconfig"
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@@ -1,7 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
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postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
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ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
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@@ -1,21 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config CPU_AMD_AGESA_FAMILY16_KB
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bool
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select SMM_ASEG
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_AGESA_FAMILY16_KB
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config FORCE_AM1_SOCKET_SUPPORT
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bool
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default n
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help
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Force AGESA to ignore package type mismatch between CPU and northbridge
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in memory code. This enables Socket AM1 support with current AGESA
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version for Kabini platform.
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Enable this option only if you have Socket AM1 board.
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Note that the AGESA release shipped with coreboot does not officially
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support the AM1 socket. Selecting this option might damage your hardware.
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endif
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@@ -1,9 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_16_init.c
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subdirs-y += ../../mtrr
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@@ -1,47 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Processor Object
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*
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*/
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Scope (\_SB) {/* define processor scope */
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Device (P000) {
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Name(_HID, "ACPI0007")
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Name(_UID, 0)
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}
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Device (P001) {
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Name(_HID, "ACPI0007")
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Name(_UID, 1)
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}
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Device (P002) {
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Name(_HID, "ACPI0007")
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Name(_UID, 2)
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}
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Device (P003) {
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Name(_HID, "ACPI0007")
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Name(_UID, 3)
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}
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Device (P004) {
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Name(_HID, "ACPI0007")
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Name(_UID, 4)
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}
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Device (P005) {
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Name(_HID, "ACPI0007")
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Name(_UID, 5)
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}
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Device (P006) {
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Name(_HID, "ACPI0007")
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Name(_UID, 6)
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}
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Device (P007) {
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Name(_HID, "ACPI0007")
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Name(_UID, 7)
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}
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} /* End _SB scope */
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@@ -1,7 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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struct chip_operations cpu_amd_agesa_family16kb_ops = {
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CHIP_NAME("AMD CPU Family 16h Model 00h-0Fh")
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};
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@@ -1,51 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/hpet.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include <amdlib.h>
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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@@ -1,96 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <device/device.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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static void model_16_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Model 16 Init.\n");
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msr_t msr;
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int msrno;
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#if CONFIG(LOGICAL_CPUS)
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u32 siblings;
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#endif
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/*
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* AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
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* by coreboot.
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*/
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disable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
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msr.lo = msr.hi = 0;
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wrmsr(MTRR_FIX_16K_A0000, msr);
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msr.lo = msr.hi = 0x1e1e1e1e;
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wrmsr(MTRR_FIX_64K_00000, msr);
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wrmsr(MTRR_FIX_16K_80000, msr);
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for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
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wrmsr(msrno, msr);
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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if (acpi_is_wakeup_s3())
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restore_mtrr();
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x86_mtrr_check();
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enable_cache();
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/* zero the machine check error status registers */
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mca_clear_status();
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#if CONFIG(LOGICAL_CPUS)
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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#endif
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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/* Write protect SMM space with SMMLOCK. */
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lock_smm();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_16_init,
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};
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static const struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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