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AMD NB: Limit the device field to 5 bits. (Propagation)

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Apply the change
http://review.coreboot.org/1264
to all the AMD northbridge.

Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1403
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
zbao
2012-08-03 15:44:42 +08:00
committed by Alexandru Gagniuc
parent 9bf356fc53
commit 49bb26a469
5 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/amd/agesa/family10/northbridge.c
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@@ -361,8 +361,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static device_t get_node_pci(u32 nodeid, u32 fn) static device_t get_node_pci(u32 nodeid, u32 fn)
{ {
#if NODE_NUMS == 64 #if NODE_NUMS + CONFIG_CDB >= 32
if (nodeid < 32) { if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else { } else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));

4
src/northbridge/amd/agesa/family12/northbridge.c
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@@ -50,7 +50,11 @@ static unsigned fx_devs=0;
device_t get_node_pci(u32 nodeid, u32 fn) device_t get_node_pci(u32 nodeid, u32 fn)
{ {
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
} }

4
src/northbridge/amd/agesa/family14/northbridge.c
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@@ -51,7 +51,11 @@ static unsigned fx_devs = 0;
device_t get_node_pci(u32 nodeid, u32 fn) device_t get_node_pci(u32 nodeid, u32 fn)
{ {
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
} }
static void get_fx_devs(void) static void get_fx_devs(void)

4
src/northbridge/amd/agesa/family15/northbridge.c
View File

@@ -122,8 +122,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static device_t get_node_pci(u32 nodeid, u32 fn) static device_t get_node_pci(u32 nodeid, u32 fn)
{ {
#if MAX_NODE_NUMS == 64 #if MAX_NODE_NUMS + CONFIG_CDB >= 32
if (nodeid < 32) { if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else { } else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));

4
src/northbridge/amd/amdfam10/northbridge.c
View File

@@ -63,8 +63,8 @@ static unsigned fx_devs=0;
device_t get_node_pci(u32 nodeid, u32 fn) device_t get_node_pci(u32 nodeid, u32 fn)
{ {
#if NODE_NUMS == 64 #if NODE_NUMS + CONFIG_CDB >= 32
if(nodeid<32) { if((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else { } else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));