From 49c455b353e9ab6a43a9a8c528d608c5934e71b6 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 30 Dec 2022 12:56:40 -0700 Subject: [PATCH] mb/system76/tgl-u: galp5: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: I7491c4ffd62b284ba47fded70793830f63cb9c5f Signed-off-by: Tim Crawford --- src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 445c41dbe1..ce3ecc3a66 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -21,6 +21,12 @@ chip soc/intel/tigerlake # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" register "PcieClkSrcClkReq[0]" = "0" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end end device ref north_xhci on # J_TYPEC2 register "UsbTcPortEn" = "1"