mediatek/mt8173: Add display driver
BRANCH=none BUG=none TEST=saw bootloader screen on rev4 and rev5 with CL:331813 Change-Id: Ibb01cf251276d2c059739f10e166fefd0de35460 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d52a4c486b75b99dc25657ccb6ed90f671c26d6 Original-Change-Id: I4efe439d52b5a5516145960bcffb340152bfba53 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331812 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jitao Shi
committed by
Patrick Georgi
Patrick Georgi
parent
866cc3d662
commit
4a04a7bf10
300
src/soc/mediatek/mt8173/dsi.c
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300
src/soc/mediatek/mt8173/dsi.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#include <soc/dsi.h>
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static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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const struct edid *edid)
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{
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u32 txdiv0, txdiv1;
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u64 pcw;
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u32 reg;
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u32 bit_per_pixel;
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int i, data_rate;
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reg = read32(&mipi_tx0->dsi_bg_con);
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reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20);
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reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17);
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reg = (reg & (~RG_DSI_V04_SEL)) | (4 << 14);
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reg = (reg & (~RG_DSI_V072_SEL)) | (4 << 11);
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reg = (reg & (~RG_DSI_V10_SEL)) | (4 << 8);
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reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5);
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reg |= RG_DSI_BG_CKEN;
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reg |= RG_DSI_BG_CORE_EN;
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write32(&mipi_tx0->dsi_bg_con, reg);
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udelay(30);
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clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
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8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
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setbits_le32(&mipi_tx0->dsi_con,
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RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
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clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
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RG_DSI_MPPLL_SDM_PWR_ON);
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clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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switch (format) {
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case MIPI_DSI_FMT_RGB565:
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bit_per_pixel = 16;
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break;
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case MIPI_DSI_FMT_RGB666:
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case MIPI_DSI_FMT_RGB666_PACKED:
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bit_per_pixel = 18;
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break;
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case MIPI_DSI_FMT_RGB888:
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default:
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bit_per_pixel = 24;
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break;
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}
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/**
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* data_rate = (pixel_clock / 1000) * bit_per_pixel * mipi_ratio / lane_num
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* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
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* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
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* we set mipi_ratio is 1.02.
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* lane_num
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*/
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data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel /
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(lanes * 1000 * 100);
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if (data_rate > 500) {
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txdiv0 = 0;
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txdiv1 = 0;
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} else if (data_rate >= 250) {
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txdiv0 = 1;
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txdiv1 = 0;
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} else if (data_rate >= 125) {
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txdiv0 = 2;
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txdiv1 = 0;
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} else if (data_rate >= 62) {
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txdiv0 = 2;
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txdiv1 = 1;
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} else if (data_rate >= 50) {
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txdiv0 = 2;
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txdiv1 = 2;
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} else {
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printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "
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"pixel clock (%u), bpp (%u), and number of lanes (%u)\n",
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data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes);
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return -1;
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}
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clrsetbits_le32(&mipi_tx0->dsi_pll_con0,
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RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
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RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
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/**
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* PLL PCW config
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* PCW bit 24~30 = integer part of pcw
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* PCW bit 0~23 = fractional part of pcw
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* pcw = data_Rate*4*txdiv/(Ref_clk*2);
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* Post DIV =4, so need data_Rate*4
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* Ref_clk is 26MHz
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*/
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pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
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pcw /= 13;
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write32(&mipi_tx0->dsi_pll_con2, pcw);
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setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
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setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
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for (i = 0; i < lanes; i++)
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setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
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setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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udelay(40);
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clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
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clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
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return data_rate;
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}
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static void mtk_dsi_phy_timconfig(u32 data_rate)
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{
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u32 timcon0, timcon1, timcon2, timcon3;
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u32 cycle_time, ui, lpx;
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ui = 1000 / data_rate + 0x01;
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cycle_time = 8000 / data_rate + 0x01;
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lpx = 5;
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timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
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timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
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(4 * lpx);
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timcon2 = ((div_round_up(0x64, cycle_time) + 0xa) << 24) |
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(div_round_up(0x150, cycle_time) << 16);
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timcon3 = (2 * lpx) << 16 |
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div_round_up(80 + 52 * ui, cycle_time) << 8 |
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div_round_up(0x40, cycle_time);
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write32(&dsi0->dsi_phy_timecon0, timcon0);
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write32(&dsi0->dsi_phy_timecon1, timcon1);
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write32(&dsi0->dsi_phy_timecon2, timcon2);
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write32(&dsi0->dsi_phy_timecon3, timcon3);
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}
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static void mtk_dsi_reset(void)
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{
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setbits_le32(&dsi0->dsi_con_ctrl, 3);
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clrbits_le32(&dsi0->dsi_con_ctrl, 1);
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}
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static void mtk_dsi_clk_hs_mode_enable(void)
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{
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setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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}
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static void mtk_dsi_clk_hs_mode_disable(void)
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{
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clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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}
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static void mtk_dsi_set_mode(u32 mode_flags)
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{
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u32 tmp_reg1 = 0;
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if (mode_flags & MIPI_DSI_MODE_VIDEO) {
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tmp_reg1 = SYNC_PULSE_MODE;
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if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
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tmp_reg1 = BURST_MODE;
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if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
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tmp_reg1 = SYNC_PULSE_MODE;
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}
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write32(&dsi0->dsi_mode_ctrl, tmp_reg1);
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}
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static void mtk_dsi_rxtx_control(u32 lanes)
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{
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u32 tmp_reg = 0;
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switch (lanes) {
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case 1:
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tmp_reg = 1 << 2;
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break;
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case 2:
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tmp_reg = 3 << 2;
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break;
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case 3:
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tmp_reg = 7 << 2;
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break;
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case 4:
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default:
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tmp_reg = 0xf << 2;
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break;
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}
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write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
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}
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static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
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const struct edid *edid)
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{
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u32 hsync_active_byte;
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u32 hbp_byte;
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u32 hfp_byte;
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u32 vbp_byte;
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u32 vfp_byte;
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u32 bpp;
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u32 packet_fmt;
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if (format == MIPI_DSI_FMT_RGB565)
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bpp = 2;
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else
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bpp = 3;
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vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
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edid->mode.vborder;
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vfp_byte = edid->mode.vso - edid->mode.vborder;
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write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
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write32(&dsi0->dsi_vbp_nl, vbp_byte);
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write32(&dsi0->dsi_vfp_nl, vfp_byte);
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write32(&dsi0->dsi_vact_nl, edid->mode.va);
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if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
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hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
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edid->mode.hborder) * bpp - 10;
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else
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hbp_byte = (edid->mode.hbl - edid->mode.hso -
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edid->mode.hborder) * bpp - 10;
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hsync_active_byte = edid->mode.hspw * bpp - 10;
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hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12;
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write32(&dsi0->dsi_hsa_wc, hsync_active_byte);
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write32(&dsi0->dsi_hbp_wc, hbp_byte);
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write32(&dsi0->dsi_hfp_wc, hfp_byte);
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switch (format) {
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case MIPI_DSI_FMT_RGB888:
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packet_fmt = PACKED_PS_24BIT_RGB888;
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break;
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case MIPI_DSI_FMT_RGB666:
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packet_fmt = LOOSELY_PS_18BIT_RGB666;
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break;
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case MIPI_DSI_FMT_RGB666_PACKED:
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packet_fmt = PACKED_PS_18BIT_RGB666;
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break;
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case MIPI_DSI_FMT_RGB565:
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packet_fmt = PACKED_PS_16BIT_RGB565;
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break;
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default:
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packet_fmt = PACKED_PS_24BIT_RGB888;
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break;
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}
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packet_fmt |= edid->mode.ha * bpp & DSI_PS_WC;
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write32(&dsi0->dsi_psctrl, packet_fmt);
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}
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static void mtk_dsi_start(void)
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{
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write32(&dsi0->dsi_start, 0);
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write32(&dsi0->dsi_start, 1);
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}
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int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes,
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const struct edid *edid)
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{
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int data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid);
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if (data_rate < 0)
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return -1;
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mtk_dsi_reset();
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mtk_dsi_phy_timconfig(data_rate);
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mtk_dsi_rxtx_control(lanes);
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mtk_dsi_clk_hs_mode_disable();
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mtk_dsi_config_vdo_timing(mode_flags, format, edid);
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mtk_dsi_set_mode(mode_flags);
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mtk_dsi_clk_hs_mode_enable();
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mtk_dsi_start();
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return 0;
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}
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