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cpu/amd: remove .intel_syntax

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Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.

Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2016-01-22 12:26:52 +01:00 committed by Patrick Georgi
parent 0302b060b6
commit 4a30ab9096
2 changed files with 60 additions and 66 deletions
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63
src/cpu/amd/agesa/cache_as_ram.inc
View File

@ -63,62 +63,59 @@ cache_as_ram_setup:
#ifdef __x86_64__ #ifdef __x86_64__
/* switch to 64 bit long mode */ /* switch to 64 bit long mode */
.intel_syntax noprefix mov %esi, %ecx
add $0, %ecx # core number
xor %eax, %eax
lea (0x1000+0x23)(%ecx), %edi
mov %edi, (%ecx)
mov %eax, 4(%ecx)
mov ecx, esi lea 0x1000(%ecx), %edi
add ecx, 0 # core number movl $0x000000e3, 0x00(%edi)
xor eax, eax movl %eax, 0x04(%edi)
lea edi, [ecx+0x1000+0x23] movl $0x400000e3, 0x08(%edi)
mov dword ptr [ecx+0], edi movl %eax, 0x0c(%edi)
mov dword ptr [ecx+4], eax movl $0x800000e3, 0x10(%edi)
movl %eax, 0x14(%edi)
lea edi, [ecx+0x1000] movl $0xc00000e3, 0x18(%edi)
mov dword ptr [edi+0x00], 0x000000e3 movl %eax, 0x1c(%edi)
mov dword ptr [edi+0x04], eax
mov dword ptr [edi+0x08], 0x400000e3
mov dword ptr [edi+0x0c], eax
mov dword ptr [edi+0x10], 0x800000e3
mov dword ptr [edi+0x14], eax
mov dword ptr [edi+0x18], 0xc00000e3
mov dword ptr [edi+0x1c], eax
# load rom based identity mapped page tables # load rom based identity mapped page tables
mov eax, ecx mov %ecx, %eax
mov cr3,eax mov %eax, %cr3
# enable PAE # enable PAE
mov eax, cr4 mov %cr4, %eax
bts eax, 5 bts $5, %eax
mov cr4, eax mov %eax, %cr4
# enable long mode # enable long mode
mov ecx, 0xC0000080 mov $0xC0000080, %ecx
rdmsr rdmsr
bts eax, 8 bts $8, %eax
wrmsr wrmsr
# enable paging # enable paging
mov eax, cr0 mov %cr0, %eax
bts eax, 31 bts $31, %eax
mov cr0, eax mov %eax, %cr0
# use call far to switch to 64-bit code segment # use call far to switch to 64-bit code segment
jmp 0x18,.+7 ljmp $0x18, $1f
1:
/* Pass the BIST result */ /* Pass the BIST result */
cvtsd2si esi, xmm1 cvtsd2si %xmm1, %esi
/* Pass the cpu_init_detected */ /* Pass the cpu_init_detected */
cvtsd2si edi, xmm0 cvtsd2si %xmm0, %edi
/* align the stack */ /* align the stack */
and esp, 0xFFFFFFF0 and $0xFFFFFFF0, %esp
.code64 .code64
call cache_as_ram_main call cache_as_ram_main
.code32 .code32
.att_syntax prefix
#else #else
AMD_ENABLE_STACK AMD_ENABLE_STACK

63
src/cpu/amd/pi/cache_as_ram.inc
View File

@ -64,62 +64,59 @@ cache_as_ram_setup:
AMD_ENABLE_STACK AMD_ENABLE_STACK
#ifdef __x86_64__ #ifdef __x86_64__
/* switch to 64 bit long mode */ /* switch to 64 bit long mode */
.intel_syntax noprefix mov %esi, %ecx
add $0, %ecx # core number
xor %eax, %eax
lea (0x1000+0x23)(%ecx), %edi
mov %edi, (%ecx)
mov %eax, 4(%ecx)
mov ecx, esi lea 0x1000(%ecx), %edi
add ecx, 0 # core number movl $0x000000e3, 0x00(%edi)
xor eax, eax movl %eax, 0x04(%edi)
lea edi, [ecx+0x1000+0x23] movl $0x400000e3, 0x08(%edi)
mov dword ptr [ecx+0], edi movl %eax, 0x0c(%edi)
mov dword ptr [ecx+4], eax movl $0x800000e3, 0x10(%edi)
movl %eax, 0x14(%edi)
lea edi, [ecx+0x1000] movl $0xc00000e3, 0x18(%edi)
mov dword ptr [edi+0x00], 0x000000e3 movl %eax, 0x1c(%edi)
mov dword ptr [edi+0x04], eax
mov dword ptr [edi+0x08], 0x400000e3
mov dword ptr [edi+0x0c], eax
mov dword ptr [edi+0x10], 0x800000e3
mov dword ptr [edi+0x14], eax
mov dword ptr [edi+0x18], 0xc00000e3
mov dword ptr [edi+0x1c], eax
# load rom based identity mapped page tables # load rom based identity mapped page tables
mov eax, ecx mov %ecx, %eax
mov cr3,eax mov %eax, %cr3
# enable PAE # enable PAE
mov eax, cr4 mov %cr4, %eax
bts eax, 5 bts $5, %eax
mov cr4, eax mov %eax, %cr4
# enable long mode # enable long mode
mov ecx, 0xC0000080 mov $0xC0000080, %ecx
rdmsr rdmsr
bts eax, 8 bts $8, %eax
wrmsr wrmsr
# enable paging # enable paging
mov eax, cr0 mov %cr0, %eax
bts eax, 31 bts $31, %eax
mov cr0, eax mov %eax, %cr0
# use call far to switch to 64-bit code segment # use call far to switch to 64-bit code segment
jmp 0x18,.+7 ljmp $0x18, $1f
1:
/* Pass the BIST result */ /* Pass the BIST result */
cvtsd2si esi, xmm1 cvtsd2si %xmm1, %esi
/* Pass the cpu_init_detected */ /* Pass the cpu_init_detected */
cvtsd2si edi, xmm0 cvtsd2si %xmm0, %edi
/* align the stack */ /* align the stack */
and esp, 0xFFFFFFF0 and $0xFFFFFFF0, %esp
.code64 .code64
call cache_as_ram_main call cache_as_ram_main
.code32 .code32
.att_syntax prefix
#else #else
/* Restore the BIST result */ /* Restore the BIST result */
cvtsd2si %xmm0, %edx cvtsd2si %xmm0, %edx