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x86: Drop -Wa,--divide

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Fix up all the code that is using / to use >> for divisions instead.

Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10819
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Stefan Reinauer
2015-07-07 00:54:05 +02:00
parent cfa9b99b23
commit 4a45ec43fe
19 changed files with 44 additions and 47 deletions
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8
src/cpu/amd/car/cache_as_ram.inc
View File

@@ -240,15 +240,15 @@ clear_fixed_var_mtrr_out:
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
extractmask gas_bug_workaround, %eax
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
extractmask gas_bug_workaround, %edx
/*
* Without the gas bug workaround, the entire macro would consist
* only of the two lines below:
* extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
* extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
* extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
* extractmask (((\carsize - \windowoffset) >> 12)), %edx
*/
.endm

2
src/cpu/amd/geode_gx2/cache_as_ram.inc
View File

@@ -166,7 +166,7 @@ done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
push %edi
mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi

2
src/cpu/amd/geode_lx/cache_as_ram.inc
View File

@@ -192,7 +192,7 @@ done_cache_as_ram_main:
* copying it back to itself to invalidate the cache */
push %edi
mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi

8
src/cpu/intel/car/cache_as_ram.inc
View File

@@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out:
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
extractmask gas_bug_workaround, %eax
.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
extractmask gas_bug_workaround, %edx
/*
* Without the gas bug workaround, the entire macro would consist
* only of the two lines below:
* extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
* extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
* extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
* extractmask (((\carsize - \windowoffset) >> 12)), %edx
*/
.endm

4
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@@ -47,7 +47,7 @@ cache_as_ram:
* For hyper-threaded CPUs these are shared.
*/
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -296,7 +296,7 @@ no_msr_11e:
cld
xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */

4
src/cpu/intel/haswell/cache_as_ram.inc
View File

@@ -60,7 +60,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -116,7 +116,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl

4
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@@ -57,7 +57,7 @@ wait_for_sipi:
post_code(0x22)
/* Zero out all fixed range MTRRs. */
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -121,7 +121,7 @@ clear_var_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl

6
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@@ -55,7 +55,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -111,7 +111,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
@@ -298,7 +298,7 @@ before_romstage:
cld
movl $CONFIG_RAMBASE, %esi
movl CBMEM_RESUME_BACKUP, %edi
movl $HIGH_MEMORY_SAVE / 4, %ecx
movl $HIGH_MEMORY_SAVE >> 2, %ecx
rep movsl
__acpi_resume_backup_done:

4
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@@ -40,7 +40,7 @@ cache_as_ram:
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
movl $((mtrr_table_end - mtrr_table) / 2), %edi
movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -90,7 +90,7 @@ clear_mtrrs:
/* Clear the cache memory reagion. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl