src/soc: Add required space before opening parenthesis '('

Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/baytrail/pcie.c

@@ -197,7 +197,7 @@ static void check_device_present(device_t dev)
 			reg_script_run_on_dev(dev, no_dev_behind_port);
 			dev->enabled = 0;
 		}
-	} else if(!dev->enabled) {
+	} else if (!dev->enabled) {
 		/* Port is disabled, but device present. Disable link. */
 		pci_write_config32(dev, LCTL,
 			pci_read_config32(dev, LCTL) | LD);

src/soc/intel/baytrail/romstage/early_spi.c

@@ -45,7 +45,7 @@ int early_spi_read_wpsr(u8 *sr)
 	SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
 
 	/* Wait for error / complete status */
-	while(timeout--) {
+	while (timeout--) {
 		u16 status = SPI16(SSFS);
 		if (status & FLASH_CYCLE_ERROR) {
 			printk(BIOS_ERR, "SPI rdsr failed\n");

src/soc/intel/baytrail/sata.c

@@ -170,7 +170,7 @@ static void sata_enable(device_t dev)
 	reg16 = pci_read_config16(dev, 0x90);
 	reg16 &= ~0x03e0;
 	reg16 |= (config->sata_port_map ^ 0x3) << 8;
-	if(config->sata_ahci)
+	if (config->sata_ahci)
 		reg16 |= 0x60;
 	pci_write_config16(dev, 0x90, reg16);
 

src/soc/intel/braswell/gpio_support.c

@@ -109,7 +109,7 @@ static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg)
 	int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
 			+ GP_SOUTHEAST_COUNT;
 
-	if(gpio_num > max_gpio_cnt)
+	if (gpio_num > max_gpio_cnt)
 		return;
 	/* Get GPIO Community based on GPIO_NUMBER */
 	comm = gpio_get_community_num(gpio_num, &pad_num);
@@ -149,7 +149,7 @@ int gpio_get(gpio_t gpio_num)
 	int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
 				+ GP_SOUTHEAST_COUNT;
 
-	if(gpio_num > max_gpio_cnt)
+	if (gpio_num > max_gpio_cnt)
 		return -1;
 
 	/* Get GPIO Community based on GPIO_NUMBER */

src/soc/intel/braswell/tsc_freq.c

@@ -41,7 +41,7 @@ static const unsigned int cpu_bus_clk_freq_table[] = {
 unsigned int cpu_bus_freq_khz(void)
 {
 	msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
-	if((clk_info.lo & 0xF)  < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
+	if ((clk_info.lo & 0xF)  < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
 	{
 		return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
 	}

src/soc/intel/broadwell/lpc.c

@@ -105,7 +105,7 @@ static void pch_pirq_init(device_t dev)
 	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
 	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/soc/intel/broadwell/smihandler.c

@@ -505,7 +505,7 @@ static void southbridge_smi_monitor(void)
 	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
 	       trap_cycle & 0xfffc);
 	for (i=0; i < 4; i++)
-		if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+		if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
 	printk(BIOS_DEBUG, "  read/write: %s\n",

src/soc/intel/common/hda_verb.c

@@ -106,7 +106,7 @@ static int hda_wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base +  HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -134,7 +134,7 @@ static int hda_wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/soc/intel/fsp_baytrail/southcluster.c

@@ -190,7 +190,7 @@ static void write_pci_config_irqs(void)
 	 * the Interrupt Route registers in the ILB
 	 */
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 
 		if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 			(!irq_dev->enabled))
@@ -287,7 +287,7 @@ static void sc_pirq_init(device_t dev)
 		write16(ir_base + i, ir->pcidev[i]);
 
 		/* If the entry is more than just 0, print it out */
-		if(ir->pcidev[i]) {
+		if (ir->pcidev[i]) {
 			printk(BIOS_SPEW, " %d: ", i);
 			for (j = 0; j < 4; j++) {
 				pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;

src/soc/intel/quark/i2c.c

@@ -162,7 +162,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
 		}
 		timeout--;
 		udelay(1);
-	} while(1);
+	} while (1);
 
 	/* Finish reading the data bytes */
 	while (read_length > 0) {

src/soc/intel/skylake/chip.c

@@ -464,17 +464,17 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	}
 	memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
 	/* GPIO IRQ Route  The valid values is 14 or 15*/
-	if(config->GpioIrqSelect == 0)
+	if (config->GpioIrqSelect == 0)
 		params->GpioIrqRoute = GPIO_IRQ14;
 	else
 		params->GpioIrqRoute = config->GpioIrqSelect;
 	/* SCI IRQ Select  The valid values is 9, 10, 11 and 20 21, 22, 23*/
-	if(config->SciIrqSelect == 0)
+	if (config->SciIrqSelect == 0)
 		params->SciIrqSelect = SCI_IRQ9;
 	else
 		params->SciIrqSelect = config->SciIrqSelect;
 	/* TCO IRQ Select  The valid values is 9, 10, 11, 20 21, 22, 23*/
-	if(config->TcoIrqSelect == 0)
+	if (config->TcoIrqSelect == 0)
 		params->TcoIrqSelect = TCO_IRQ9;
 	else
 		params->TcoIrqSelect = config->TcoIrqSelect;