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nb/intel/x4x: Use PCI bitwise ops

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Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.

Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42155
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-06-08 01:39:25 +02:00
committed by Felix Held
parent 26886076f4
commit 4a9569a123
3 changed files with 10 additions and 18 deletions
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14
src/northbridge/intel/x4x/raminit.c
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@@ -597,10 +597,9 @@ static void checkreset_ddr2(int boot_path)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
/* do magic 0xf0 thing. */
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
full_reset();
}
@@ -690,11 +689,10 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
do_raminit(&s, fast_boot);
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1);
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);