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skl mainboards/dt: Move serirq setting into LPC device scope

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Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2024-06-23 20:32:15 +02:00
parent df7de392ef
commit 4b72203989
11 changed files with 25 additions and 27 deletions
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4
src/mainboard/51nb/x210/devicetree.cb
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@ -39,8 +39,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enable Root Ports 3, 4 and 9
register "PcieRpEnable[2]" = "1" # Ethernet controller
register "PcieRpClkReqSupport[2]" = "1"
@ -116,6 +114,8 @@ chip soc/intel/skylake
device ref pcie_rp4 on end
device ref pcie_rp9 on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"

5
src/mainboard/facebook/monolith/devicetree.cb
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@ -18,9 +18,6 @@ chip soc/intel/skylake
register "lpc_iod" = "0x0070"
register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
# LPC serial IRQ
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# "Intel SpeedStep Technology"
register "eist_enable" = "1"
@ -214,6 +211,8 @@ chip soc/intel/skylake
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# CPLD host command ranges are in 0x280-0x2BF
# EC PNP registers are at 0x6e and 0x6f
register "gen1_dec" = "0x003c0281"

5
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
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@ -4,8 +4,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enable PCIE slot
register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "1"
@ -119,5 +117,8 @@ chip soc/intel/skylake
device ref sdxc off end
device ref hda on end
device ref gbe on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
end
end
end

4
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
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@ -7,8 +7,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
@ -173,6 +171,8 @@ chip soc/intel/skylake
device ref emmc off end
device ref sdxc off end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
#chip drivers/pc80/tpm
# device pnp 0c31.0 on end
#end

5
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -32,8 +32,6 @@ chip soc/intel/skylake
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 4 Domains
#+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT |
@ -217,6 +215,9 @@ chip soc/intel/skylake
device ref gspi1 on end
device ref hda on end
device ref smbus on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
end
device ref fast_spi on end
device ref gbe on end
end

4
src/mainboard/libretrend/lt1000/devicetree.cb
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@ -9,8 +9,6 @@ chip soc/intel/skylake
register "eist_enable" = "1"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Set the Thermal Control Circuit (TCC) activation value to 95C
# even though FSP integration guide says to set it to 100C for SKL-U
# (offset at 0), because when the TCC activates at 100C, the CPU
@ -170,6 +168,8 @@ chip soc/intel/skylake
device ref pcie_rp11 on end
device ref pcie_rp12 on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff

5
src/mainboard/protectli/vault_kbl/devicetree.cb
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@ -17,9 +17,6 @@ chip soc/intel/skylake
# Disable DPTF
register "dptf_enable" = "0"
# Enable SERIRQ continuous
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "tcc_offset" = "5" # TCC of 95C
# FSP Configuration
@ -198,6 +195,8 @@ chip soc/intel/skylake
"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0a01"
register "gen3_dec" = "0x000c03e1"

6
src/mainboard/purism/librem_skl/devicetree.cb
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@ -47,9 +47,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
# EC/KBC requires continuous mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 4 Domains
#+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT |
@ -153,6 +150,9 @@ chip soc/intel/skylake
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
# EC/KBC requires continuous mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
chip drivers/pc80/tpm

4
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
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@ -28,8 +28,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 4 Domains
#+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT |
@ -172,6 +170,8 @@ chip soc/intel/skylake
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"

5
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
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@ -4,9 +4,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
# LPC
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
register "s0ix_enable" = true
register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
@ -33,6 +30,8 @@ chip soc/intel/skylake
}"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
chip superio/common
device pnp 2e.0 on end
end

5
src/mainboard/system76/kbl-u/devicetree.cb
View File

@ -18,9 +18,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
}"
# Serial IRQ
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Power
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
@ -172,6 +169,8 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[8]" = "1"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x00040069"