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mainboard: Get rid of device_t

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Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.

Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-06-08 19:00:44 +02:00
committed by Nico Huber
parent 5cb876cc1f
commit 4b73fa97ce
16 changed files with 29 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/compulab/intense_pc/romstage.c
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@@ -24,7 +24,7 @@
void pch_enable_lpc(void)
{
device_t dev = PCH_LPC_DEV;
pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);

6
src/mainboard/google/beltino/chromeos.c
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@@ -48,10 +48,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -59,10 +60,11 @@ int get_write_protect_state(void)
int get_recovery_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;

2
src/mainboard/google/butterfly/chromeos.c
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@@ -37,7 +37,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
int lidswitch = 0;

6
src/mainboard/google/jecht/chromeos.c
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@@ -51,10 +51,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -62,10 +63,11 @@ int get_write_protect_state(void)
int get_recovery_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;

2
src/mainboard/google/parrot/chromeos.c
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@@ -34,7 +34,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);

4
src/mainboard/google/stout/chromeos.c
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@@ -97,11 +97,11 @@ int get_lid_switch(void)
int get_recovery_mode_switch(void)
{
#ifdef __PRE_RAM__
device_t dev = PCI_DEV(0, 0x1f, 0);
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
#else
static int ec_in_rec_mode = 0;
static int ec_rec_flag_good = 0;
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
u8 ec_status = ec_read(EC_STATUS_REG);

2
src/mainboard/intel/baskingridge/chromeos.c
View File

@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)

2
src/mainboard/intel/cougar_canyon2/romstage.c
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@@ -51,7 +51,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
device_t dev = PCH_LPC_DEV;
pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);

2
src/mainboard/intel/d510mo/romstage.c
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@@ -42,7 +42,7 @@
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
device_t dev;
pci_devfn_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);

2
src/mainboard/intel/emeraldlake2/chromeos.c
View File

@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)

2
src/mainboard/intel/emeraldlake2/romstage.c
View File

@@ -42,7 +42,7 @@
void pch_enable_lpc(void)
{
device_t dev = PCH_LPC_DEV;
pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);

2
src/mainboard/intel/galileo/gpio.c
View File

@@ -45,7 +45,7 @@ void car_mainboard_pre_console_init(void)
}
}
void mainboard_gpio_i2c_init(device_t dev)
void mainboard_gpio_i2c_init(struct device *dev)
{
const struct reg_script *script;

8
src/mainboard/samsung/lumpy/chromeos.c
View File

@@ -40,7 +40,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
u8 lid = ec_read(0x83);
@@ -91,7 +91,7 @@ int get_write_protect_state(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -103,7 +103,7 @@ int get_developer_mode_switch(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@@ -115,7 +115,7 @@ int get_recovery_mode_switch(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;

8
src/mainboard/samsung/stumpy/chromeos.c
View File

@@ -37,7 +37,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
@@ -88,7 +88,7 @@ int get_write_protect_state(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -100,7 +100,7 @@ int get_developer_mode_switch(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@@ -112,7 +112,7 @@ int get_recovery_mode_switch(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;

2
src/mainboard/tyan/s2912_fam10/get_bus_conf.c
View File

@@ -65,7 +65,7 @@ void get_bus_conf(void)
unsigned apicid_base;
struct mb_sysconf_t *m;
device_t dev;
struct device *dev;
int i;
if(get_bus_conf_done == 1) return; //do it only once

2
src/soc/intel/quark/include/soc/ramstage.h
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@@ -24,7 +24,7 @@
#endif
#include <soc/QuarkNcSocId.h>
void mainboard_gpio_i2c_init(device_t dev);
void mainboard_gpio_i2c_init(struct device *dev);
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
void fsp_silicon_init(bool s3wake);
#endif