more breakage, thanks to Ron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
@@ -1,127 +1,3 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=524288
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=4
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default HARD_RESET_FUNCTION=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="HDAMA"
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default MAINBOARD_VENDOR="ARIMA"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 32K heap
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##
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default HEAP_SIZE=0x8000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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@@ -157,203 +33,72 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h "
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
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pnp cf8.0
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northbridge amd/amdk8 "mc1" link 0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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pci 1:18.0
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southbridge amd/amd8131 "amd8131" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 1
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pci 0:0.0
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pci 0:1.0 on
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superio NSC/pc87360 link 1
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pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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pnp 2e.4 off # SWC
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pnp 2e.5 off # Mouse
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pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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pnp 2e.7 off # GPIO
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pnp 2e.8 off # ACB
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pnp 2e.9 off # FSCM
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pnp 2e.a off # WDT
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end
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on # ACPI/SMBUS
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chip drivers/generic/generic link 4
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#phillips pca9545 smbus mux
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i2c 70
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# analog_devices adm1026
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chip drivers/generic/generic link 0
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i2c 2c
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# sample config for arima/hdama
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chip northbridge/amd/amdk8
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print "HI MOM!\n"
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device pnp cf8.0 on # cf8 config
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print "HI MOM!\n"
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device pci 18.0 on # northbridge
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print "HI MOM!\n"
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# devices on link 0, link 0 == LDT 0
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chip southbridge/amd/amd8131
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print "SOUTH\n"
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# the on/off keyword is mandatory
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device pci 0.0 on end
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print "SOUTH2\n"
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device pci 0.1 on end
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print "SOUTH3\n"
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device pci 1.0 on end
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print "SOUTH4\n"
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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print "NEXT SOUTH\n"
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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# this "device pci 0.0" is a child of the
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# previous one
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# devices behind the bridge
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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# the device statement can span across multiple
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# lines too
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device pci 1.0
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off
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end
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i2c 70
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i2c 70
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i2c 70
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end
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device pci 1.0 on
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chip superio/NSC/pc87360
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device pnp 2e.3 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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end
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end
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device pci 1.1 on end
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device pci 1.2 off end
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device pci 1.3 off end
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device pci 1.5 on end
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device pci 1.6 on end
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end
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chip drivers/generic/generic link 4 #dimm 0-0-0
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i2c 50
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end
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chip drivers/generic/generic link 4 #dimm 0-0-1
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i2c 51
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end
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chip drivers/generic/generic link 4 #dimm 0-1-0
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i2c 52
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end
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chip drivers/generic/generic link 4 #dimm 0-1-1
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i2c 53
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end
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chip drivers/generic/generic link 4 #dimm 1-0-0
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i2c 54
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end
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chip drivers/generic/generic link 4 #dimm 1-0-1
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i2c 55
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end
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chip drivers/generic/generic link 4 #dimm 1-1-0
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i2c 56
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end
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chip drivers/generic/generic link 4 #dimm 1-1-1
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i2c 57
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end
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pci 0:1.5 off
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pci 0:1.6 off
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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end
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pci 1:18.0
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pci 1:18.0
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pci 1:18.1
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pci 1:18.2
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pci 1:18.3
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end
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cpu amd/socket_940 "cpu0" link 1
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apic 0
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end
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cpu amd/socket_940 "cpu1" link 1
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apic 1
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end # device pci 18.0
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device pci 18.0 on
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# some non-existence devices on link 1
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end
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device pci 18.0 on
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# some non-existence devices on link 2
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end
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device pci 18.1
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# empty
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end
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device pci 18.2
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# empty
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end
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device pci 18.3
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# empty
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end
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end # device pnp
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end
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124
src/mainboard/arima/hdama/Options.lb
Normal file
124
src/mainboard/arima/hdama/Options.lb
Normal file
@@ -0,0 +1,124 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=524288
|
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|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="HDAMA"
|
||||
default MAINBOARD_VENDOR="ARIMA"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
default _RAMBASE=0x00004000
|
||||
end
|
||||
Reference in New Issue
Block a user