soc/intel/apollolake: Add PrmrrSize and SGX enable config

Add PrmrrSize and sgx_enable config option. PrmrrSize gets
configured in romstage so that FSP can allocate memory for SGX.
Also, adjust cbmem_top() calculation.

Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/apollolake/memmap.c

@@ -26,6 +26,7 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <cbmem.h>
+#include "chip.h"
 #include <device/pci.h>
 #include <fsp/memmap.h>
 #include <intelblocks/smm.h>
@@ -34,7 +35,25 @@
 
 void *cbmem_top(void)
 {
-	return (void *)sa_get_tseg_base();
+	const struct device *dev;
+	const config_t *config;
+	void *tolum = (void *)sa_get_tseg_base();
+
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+		return tolum;
+
+	dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	config = dev->chip_info;
+
+	if (!config)
+		die("Failed to get chip_info\n");
+
+	/* FSP allocates 2x PRMRR Size Memory for alignment */
+	if (config->sgx_enable)
+		tolum -= config->PrmrrSize * 2;
+
+	return tolum;
 }
 
 int smm_subregion(int sub, void **start, size_t *size)